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Commit 3335786a982578abf9a25e4d6ce67d3416ebe15e

Authored by Stefan Roese
1 parent c6cfcc91ea
Exists in v2017.01-smarct4x and in 25 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2017.01-smarct3x, v2017.01-smarct3x-emmc

drivers/phy: Add Marvell SerDes / PHY drivers used on Armada 3k 

This version is based on the Marvell U-Boot version with this patch
applied as latest patch:

Git ID 7f408573: "fix: comphy: cp110: add comphy initialization for usb
device mode" from 2016-07-05.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Wilson Ding <dingwei@marvell.com>
Cc: Victor Gu <xigu@marvell.com>
Cc: Hua Jing <jinghua@marvell.com>
Cc: Terry Zhou <bjzhou@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Cc: Haim Boot <hayim@marvell.com>

Showing 11 changed files with 2153 additions and 0 deletions Side-by-side Diff

... ... @@ -48,6 +48,8 @@
48 48  
49 49 source "drivers/pcmcia/Kconfig"
50 50  
  51 +source "drivers/phy/marvell/Kconfig"
  52 +
51 53 source "drivers/pinctrl/Kconfig"
52 54  
53 55 source "drivers/power/Kconfig"
... ... @@ -70,6 +70,7 @@
70 70 obj-y += pcmcia/
71 71 obj-y += dfu/
72 72 obj-$(CONFIG_X86) += pch/
  73 +obj-y += phy/marvell/
73 74 obj-y += rtc/
74 75 obj-y += sound/
75 76 obj-y += spmi/
drivers/phy/marvell/Kconfig
Diff comments   View file @ 3335786
  1 +config MVEBU_COMPHY_SUPPORT
  2 + bool "ComPhy SerDes driver"
  3 + default n
  4 + help
  5 + Choose this option to add support
  6 + for Comphy driver.
  7 + This driver passes over the lanes
  8 + and initialize the lane depends on the
  9 + type and speed.
drivers/phy/marvell/Makefile
Diff comments   View file @ 3335786
  1 +#
  2 +# SPDX-License-Identifier: GPL-2.0+
  3 +#
  4 +
  5 +obj-$(CONFIG_MVEBU_COMPHY_SUPPORT) += comphy_core.o
  6 +obj-$(CONFIG_MVEBU_COMPHY_SUPPORT) += comphy_mux.o
  7 +obj-$(CONFIG_ARMADA_3700) += comphy_a3700.o
drivers/phy/marvell/comphy.h
Diff comments   View file @ 3335786
  1 +/*
  2 + * Copyright (C) 2015-2016 Marvell International Ltd.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef _COMPHY_H_
  8 +#define _COMPHY_H_
  9 +
  10 +#include <dt-bindings/comphy/comphy_data.h>
  11 +#include <fdtdec.h>
  12 +
  13 +#if defined(DEBUG)
  14 +#define debug_enter() printf("----> Enter %s\n", __func__);
  15 +#define debug_exit() printf("<---- Exit %s\n", __func__);
  16 +#else
  17 +#define debug_enter()
  18 +#define debug_exit()
  19 +#endif
  20 +
  21 +/* COMPHY registers */
  22 +#define COMMON_PHY_CFG1_REG 0x0
  23 +#define COMMON_PHY_CFG1_PWR_UP_OFFSET 1
  24 +#define COMMON_PHY_CFG1_PWR_UP_MASK \
  25 + (0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET)
  26 +#define COMMON_PHY_CFG1_PIPE_SELECT_OFFSET 2
  27 +#define COMMON_PHY_CFG1_PIPE_SELECT_MASK \
  28 + (0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET)
  29 +#define COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET 13
  30 +#define COMMON_PHY_CFG1_PWR_ON_RESET_MASK \
  31 + (0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET)
  32 +#define COMMON_PHY_CFG1_CORE_RSTN_OFFSET 14
  33 +#define COMMON_PHY_CFG1_CORE_RSTN_MASK \
  34 + (0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET)
  35 +#define COMMON_PHY_PHY_MODE_OFFSET 15
  36 +#define COMMON_PHY_PHY_MODE_MASK \
  37 + (0x1 << COMMON_PHY_PHY_MODE_OFFSET)
  38 +
  39 +#define COMMON_PHY_CFG6_REG 0x14
  40 +#define COMMON_PHY_CFG6_IF_40_SEL_OFFSET 18
  41 +#define COMMON_PHY_CFG6_IF_40_SEL_MASK \
  42 + (0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET)
  43 +
  44 +#define COMMON_SELECTOR_PHY_OFFSET 0x140
  45 +#define COMMON_SELECTOR_PIPE_OFFSET 0x144
  46 +
  47 +#define COMMON_PHY_SD_CTRL1 0x148
  48 +#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET 0
  49 +#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK 0xFFFF
  50 +#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET 24
  51 +#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK \
  52 + (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET)
  53 +#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET 25
  54 +#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK \
  55 + (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET)
  56 +#define COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET 26
  57 +#define COMMON_PHY_SD_CTRL1_RXAUI1_MASK \
  58 + (0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET)
  59 +#define COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET 27
  60 +#define COMMON_PHY_SD_CTRL1_RXAUI0_MASK \
  61 + (0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET)
  62 +
  63 +#define DFX_DEV_GEN_CTRL12 (MVEBU_CP0_REGS_BASE + 0x400280)
  64 +#define DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET 7
  65 +#define DFX_DEV_GEN_PCIE_CLK_SRC_MASK \
  66 + (0x3 << DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET)
  67 +
  68 +#define MAX_LANE_OPTIONS 10
  69 +#define MAX_UTMI_PHY_COUNT 2
  70 +
  71 +struct comphy_mux_options {
  72 + u32 type;
  73 + u32 mux_value;
  74 +};
  75 +
  76 +struct comphy_mux_data {
  77 + u32 max_lane_values;
  78 + struct comphy_mux_options mux_values[MAX_LANE_OPTIONS];
  79 +};
  80 +
  81 +struct comphy_map {
  82 + u32 type;
  83 + u32 speed;
  84 + u32 invert;
  85 + bool clk_src;
  86 +};
  87 +
  88 +struct chip_serdes_phy_config {
  89 + struct comphy_mux_data *mux_data;
  90 + int (*ptr_comphy_chip_init)(struct chip_serdes_phy_config *,
  91 + struct comphy_map *);
  92 + void __iomem *comphy_base_addr;
  93 + void __iomem *hpipe3_base_addr;
  94 + u32 comphy_lanes_count;
  95 + u32 comphy_mux_bitcount;
  96 + u32 comphy_index;
  97 +};
  98 +
  99 +/* Register helper functions */
  100 +void reg_set(void __iomem *addr, u32 data, u32 mask);
  101 +void reg_set_silent(void __iomem *addr, u32 data, u32 mask);
  102 +void reg_set16(void __iomem *addr, u16 data, u16 mask);
  103 +void reg_set_silent16(void __iomem *addr, u16 data, u16 mask);
  104 +
  105 +/* SoC specific init functions */
  106 +#ifdef CONFIG_ARMADA_3700
  107 +int comphy_a3700_init(struct chip_serdes_phy_config *ptr_chip_cfg,
  108 + struct comphy_map *serdes_map);
  109 +#else
  110 +static inline int comphy_a3700_init(struct chip_serdes_phy_config *ptr_chip_cfg,
  111 + struct comphy_map *serdes_map)
  112 +{
  113 + /*
  114 + * This function should never be called in this configuration, so
  115 + * lets return an error here.
  116 + */
  117 + return -1;
  118 +}
  119 +#endif
  120 +int comphy_ap806_init(struct chip_serdes_phy_config *ptr_chip_cfg,
  121 + struct comphy_map *serdes_map);
  122 +int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
  123 + struct comphy_map *serdes_map);
  124 +
  125 +void comphy_dedicated_phys_init(void);
  126 +
  127 +/* MUX function */
  128 +void comphy_mux_init(struct chip_serdes_phy_config *ptr_chip_cfg,
  129 + struct comphy_map *comphy_map_data,
  130 + void __iomem *selector_base);
  131 +
  132 +void comphy_pcie_config_set(u32 comphy_max_count,
  133 + struct comphy_map *serdes_map);
  134 +void comphy_pcie_config_detect(u32 comphy_max_count,
  135 + struct comphy_map *serdes_map);
  136 +void comphy_pcie_unit_general_config(u32 pex_index);
  137 +
  138 +#endif /* _COMPHY_H_ */
drivers/phy/marvell/comphy_a3700.c
Diff comments   View file @ 3335786
  1 +/*
  2 + * Copyright (C) 2015-2016 Marvell International Ltd.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <fdtdec.h>
  9 +#include <asm/io.h>
  10 +#include <asm/arch/cpu.h>
  11 +#include <asm/arch/soc.h>
  12 +
  13 +#include "comphy_a3700.h"
  14 +
  15 +DECLARE_GLOBAL_DATA_PTR;
  16 +
  17 +struct sgmii_phy_init_data_fix {
  18 + u16 addr;
  19 + u16 value;
  20 +};
  21 +
  22 +/* Changes to 40M1G25 mode data required for running 40M3G125 init mode */
  23 +static struct sgmii_phy_init_data_fix sgmii_phy_init_fix[] = {
  24 + {0x005, 0x07CC}, {0x015, 0x0000}, {0x01B, 0x0000}, {0x01D, 0x0000},
  25 + {0x01E, 0x0000}, {0x01F, 0x0000}, {0x020, 0x0000}, {0x021, 0x0030},
  26 + {0x026, 0x0888}, {0x04D, 0x0152}, {0x04F, 0xA020}, {0x050, 0x07CC},
  27 + {0x053, 0xE9CA}, {0x055, 0xBD97}, {0x071, 0x3015}, {0x076, 0x03AA},
  28 + {0x07C, 0x0FDF}, {0x0C2, 0x3030}, {0x0C3, 0x8000}, {0x0E2, 0x5550},
  29 + {0x0E3, 0x12A4}, {0x0E4, 0x7D00}, {0x0E6, 0x0C83}, {0x101, 0xFCC0},
  30 + {0x104, 0x0C10}
  31 +};
  32 +
  33 +/* 40M1G25 mode init data */
  34 +static u16 sgmii_phy_init[512] = {
  35 + /* 0 1 2 3 4 5 6 7 */
  36 + /*-----------------------------------------------------------*/
  37 + /* 8 9 A B C D E F */
  38 + 0x3110, 0xFD83, 0x6430, 0x412F, 0x82C0, 0x06FA, 0x4500, 0x6D26, /* 00 */
  39 + 0xAFC0, 0x8000, 0xC000, 0x0000, 0x2000, 0x49CC, 0x0BC9, 0x2A52, /* 08 */
  40 + 0x0BD2, 0x0CDE, 0x13D2, 0x0CE8, 0x1149, 0x10E0, 0x0000, 0x0000, /* 10 */
  41 + 0x0000, 0x0000, 0x0000, 0x0001, 0x0000, 0x4134, 0x0D2D, 0xFFFF, /* 18 */
  42 + 0xFFE0, 0x4030, 0x1016, 0x0030, 0x0000, 0x0800, 0x0866, 0x0000, /* 20 */
  43 + 0x0000, 0x0000, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, /* 28 */
  44 + 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */
  45 + 0x0000, 0x0000, 0x000F, 0x6A62, 0x1988, 0x3100, 0x3100, 0x3100, /* 38 */
  46 + 0x3100, 0xA708, 0x2430, 0x0830, 0x1030, 0x4610, 0xFF00, 0xFF00, /* 40 */
  47 + 0x0060, 0x1000, 0x0400, 0x0040, 0x00F0, 0x0155, 0x1100, 0xA02A, /* 48 */
  48 + 0x06FA, 0x0080, 0xB008, 0xE3ED, 0x5002, 0xB592, 0x7A80, 0x0001, /* 50 */
  49 + 0x020A, 0x8820, 0x6014, 0x8054, 0xACAA, 0xFC88, 0x2A02, 0x45CF, /* 58 */
  50 + 0x000F, 0x1817, 0x2860, 0x064F, 0x0000, 0x0204, 0x1800, 0x6000, /* 60 */
  51 + 0x810F, 0x4F23, 0x4000, 0x4498, 0x0850, 0x0000, 0x000E, 0x1002, /* 68 */
  52 + 0x9D3A, 0x3009, 0xD066, 0x0491, 0x0001, 0x6AB0, 0x0399, 0x3780, /* 70 */
  53 + 0x0040, 0x5AC0, 0x4A80, 0x0000, 0x01DF, 0x0000, 0x0007, 0x0000, /* 78 */
  54 + 0x2D54, 0x00A1, 0x4000, 0x0100, 0xA20A, 0x0000, 0x0000, 0x0000, /* 80 */
  55 + 0x0000, 0x0000, 0x0000, 0x7400, 0x0E81, 0x1000, 0x1242, 0x0210, /* 88 */
  56 + 0x80DF, 0x0F1F, 0x2F3F, 0x4F5F, 0x6F7F, 0x0F1F, 0x2F3F, 0x4F5F, /* 90 */
  57 + 0x6F7F, 0x4BAD, 0x0000, 0x0000, 0x0800, 0x0000, 0x2400, 0xB651, /* 98 */
  58 + 0xC9E0, 0x4247, 0x0A24, 0x0000, 0xAF19, 0x1004, 0x0000, 0x0000, /* A0 */
  59 + 0x0000, 0x0013, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* A8 */
  60 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* B0 */
  61 + 0x0000, 0x0000, 0x0000, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, /* B8 */
  62 + 0x0000, 0x0000, 0x3010, 0xFA00, 0x0000, 0x0000, 0x0000, 0x0003, /* C0 */
  63 + 0x1618, 0x8200, 0x8000, 0x0400, 0x050F, 0x0000, 0x0000, 0x0000, /* C8 */
  64 + 0x4C93, 0x0000, 0x1000, 0x1120, 0x0010, 0x1242, 0x1242, 0x1E00, /* D0 */
  65 + 0x0000, 0x0000, 0x0000, 0x00F8, 0x0000, 0x0041, 0x0800, 0x0000, /* D8 */
  66 + 0x82A0, 0x572E, 0x2490, 0x14A9, 0x4E00, 0x0000, 0x0803, 0x0541, /* E0 */
  67 + 0x0C15, 0x0000, 0x0000, 0x0400, 0x2626, 0x0000, 0x0000, 0x4200, /* E8 */
  68 + 0x0000, 0xAA55, 0x1020, 0x0000, 0x0000, 0x5010, 0x0000, 0x0000, /* F0 */
  69 + 0x0000, 0x0000, 0x5000, 0x0000, 0x0000, 0x0000, 0x02F2, 0x0000, /* F8 */
  70 + 0x101F, 0xFDC0, 0x4000, 0x8010, 0x0110, 0x0006, 0x0000, 0x0000, /*100 */
  71 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*108 */
  72 + 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04C6, 0x0000, /*110 */
  73 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*118 */
  74 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*120 */
  75 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*128 */
  76 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*130 */
  77 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*138 */
  78 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*140 */
  79 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*148 */
  80 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*150 */
  81 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*158 */
  82 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*160 */
  83 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*168 */
  84 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*170 */
  85 + 0x0000, 0x0000, 0x0000, 0x00F0, 0x08A2, 0x3112, 0x0A14, 0x0000, /*178 */
  86 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*180 */
  87 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*188 */
  88 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*190 */
  89 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*198 */
  90 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A0 */
  91 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A8 */
  92 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B0 */
  93 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B8 */
  94 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C0 */
  95 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C8 */
  96 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D0 */
  97 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D8 */
  98 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E0 */
  99 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E8 */
  100 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1F0 */
  101 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 /*1F8 */
  102 +};
  103 +
  104 +/*
  105 + * comphy_poll_reg
  106 + *
  107 + * return: 1 on success, 0 on timeout
  108 + */
  109 +static u32 comphy_poll_reg(void *addr, u32 val, u32 mask, u32 timeout,
  110 + u8 op_type)
  111 +{
  112 + u32 rval = 0xDEAD;
  113 +
  114 + for (; timeout > 0; timeout--) {
  115 + if (op_type == POLL_16B_REG)
  116 + rval = readw(addr); /* 16 bit */
  117 + else
  118 + rval = readl(addr) ; /* 32 bit */
  119 +
  120 + if ((rval & mask) == val)
  121 + return 1;
  122 +
  123 + udelay(10000);
  124 + }
  125 +
  126 + debug("Time out waiting (%p = %#010x)\n", addr, rval);
  127 + return 0;
  128 +}
  129 +
  130 +/*
  131 + * comphy_pcie_power_up
  132 + *
  133 + * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
  134 + */
  135 +static int comphy_pcie_power_up(u32 speed, u32 invert)
  136 +{
  137 + int ret;
  138 +
  139 + debug_enter();
  140 +
  141 + /*
  142 + * 1. Enable max PLL.
  143 + */
  144 + reg_set16((void __iomem *)LANE_CFG1_ADDR(PCIE),
  145 + bf_use_max_pll_rate, 0);
  146 +
  147 + /*
  148 + * 2. Select 20 bit SERDES interface.
  149 + */
  150 + reg_set16((void __iomem *)GLOB_CLK_SRC_LO_ADDR(PCIE),
  151 + bf_cfg_sel_20b, 0);
  152 +
  153 + /*
  154 + * 3. Force to use reg setting for PCIe mode
  155 + */
  156 + reg_set16((void __iomem *)MISC_REG1_ADDR(PCIE),
  157 + bf_sel_bits_pcie_force, 0);
  158 +
  159 + /*
  160 + * 4. Change RX wait
  161 + */
  162 + reg_set16((void __iomem *)PWR_MGM_TIM1_ADDR(PCIE), 0x10C, 0xFFFF);
  163 +
  164 + /*
  165 + * 5. Enable idle sync
  166 + */
  167 + reg_set16((void __iomem *)UNIT_CTRL_ADDR(PCIE),
  168 + 0x60 | rb_idle_sync_en, 0xFFFF);
  169 +
  170 + /*
  171 + * 6. Enable the output of 100M/125M/500M clock
  172 + */
  173 + reg_set16((void __iomem *)MISC_REG0_ADDR(PCIE),
  174 + 0xA00D | rb_clk500m_en | rb_clk100m_125m_en, 0xFFFF);
  175 +
  176 + /*
  177 + * 7. Enable TX
  178 + */
  179 + reg_set((void __iomem *)PHY_REF_CLK_ADDR, 0x1342, 0xFFFFFFFF);
  180 +
  181 + /*
  182 + * 8. Check crystal jumper setting and program the Power and PLL
  183 + * Control accordingly
  184 + */
  185 + if (get_ref_clk() == 40) {
  186 + reg_set16((void __iomem *)PWR_PLL_CTRL_ADDR(PCIE),
  187 + 0xFC63, 0xFFFF); /* 40 MHz */
  188 + } else {
  189 + reg_set16((void __iomem *)PWR_PLL_CTRL_ADDR(PCIE),
  190 + 0xFC62, 0xFFFF); /* 25 MHz */
  191 + }
  192 +
  193 + /*
  194 + * 9. Override Speed_PLL value and use MAC PLL
  195 + */
  196 + reg_set16((void __iomem *)KVCO_CAL_CTRL_ADDR(PCIE),
  197 + 0x0040 | rb_use_max_pll_rate, 0xFFFF);
  198 +
  199 + /*
  200 + * 10. Check the Polarity invert bit
  201 + */
  202 + if (invert & PHY_POLARITY_TXD_INVERT) {
  203 + reg_set16((void __iomem *)SYNC_PATTERN_ADDR(PCIE),
  204 + phy_txd_inv, 0);
  205 + }
  206 +
  207 + if (invert & PHY_POLARITY_RXD_INVERT) {
  208 + reg_set16((void __iomem *)SYNC_PATTERN_ADDR(PCIE),
  209 + phy_rxd_inv, 0);
  210 + }
  211 +
  212 + /*
  213 + * 11. Release SW reset
  214 + */
  215 + reg_set16((void __iomem *)GLOB_PHY_CTRL0_ADDR(PCIE),
  216 + rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32,
  217 + bf_soft_rst | bf_mode_refdiv);
  218 +
  219 + /* Wait for > 55 us to allow PCLK be enabled */
  220 + udelay(PLL_SET_DELAY_US);
  221 +
  222 + /* Assert PCLK enabled */
  223 + ret = comphy_poll_reg((void *)LANE_STAT1_ADDR(PCIE), /* address */
  224 + rb_txdclk_pclk_en, /* value */
  225 + rb_txdclk_pclk_en, /* mask */
  226 + PLL_LOCK_TIMEOUT, /* timeout */
  227 + POLL_16B_REG); /* 16bit */
  228 + if (ret == 0)
  229 + printf("Failed to lock PCIe PLL\n");
  230 +
  231 + debug_exit();
  232 +
  233 + /* Return the status of the PLL */
  234 + return ret;
  235 +}
  236 +
  237 +/*
  238 + * comphy_sata_power_up
  239 + *
  240 + * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
  241 + */
  242 +static int comphy_sata_power_up(void)
  243 +{
  244 + int ret;
  245 +
  246 + debug_enter();
  247 +
  248 + /*
  249 + * 0. Swap SATA TX lines
  250 + */
  251 + reg_set((void __iomem *)rh_vsreg_addr,
  252 + vphy_sync_pattern_reg, 0xFFFFFFFF);
  253 + reg_set((void __iomem *)rh_vsreg_data, bs_txd_inv, bs_txd_inv);
  254 +
  255 + /*
  256 + * 1. Select 40-bit data width width
  257 + */
  258 + reg_set((void __iomem *)rh_vsreg_addr, vphy_loopback_reg0, 0xFFFFFFFF);
  259 + reg_set((void __iomem *)rh_vsreg_data, 0x800, bs_phyintf_40bit);
  260 +
  261 + /*
  262 + * 2. Select reference clock and PHY mode (SATA)
  263 + */
  264 + reg_set((void __iomem *)rh_vsreg_addr, vphy_power_reg0, 0xFFFFFFFF);
  265 + if (get_ref_clk() == 40) {
  266 + reg_set((void __iomem *)rh_vsreg_data,
  267 + 0x3, 0x00FF); /* 40 MHz */
  268 + } else {
  269 + reg_set((void __iomem *)rh_vsreg_data,
  270 + 0x1, 0x00FF); /* 25 MHz */
  271 + }
  272 +
  273 + /*
  274 + * 3. Use maximum PLL rate (no power save)
  275 + */
  276 + reg_set((void __iomem *)rh_vsreg_addr, vphy_calctl_reg, 0xFFFFFFFF);
  277 + reg_set((void __iomem *)rh_vsreg_data,
  278 + bs_max_pll_rate, bs_max_pll_rate);
  279 +
  280 + /*
  281 + * 4. Reset reserved bit (??)
  282 + */
  283 + reg_set((void __iomem *)rh_vsreg_addr, vphy_reserve_reg, 0xFFFFFFFF);
  284 + reg_set((void __iomem *)rh_vsreg_data, 0, bs_phyctrl_frm_pin);
  285 +
  286 + /*
  287 + * 5. Set vendor-specific configuration (??)
  288 + */
  289 + reg_set((void __iomem *)rh_vs0_a, vsata_ctrl_reg, 0xFFFFFFFF);
  290 + reg_set((void __iomem *)rh_vs0_d, bs_phy_pu_pll, bs_phy_pu_pll);
  291 +
  292 + /* Wait for > 55 us to allow PLL be enabled */
  293 + udelay(PLL_SET_DELAY_US);
  294 +
  295 + /* Assert SATA PLL enabled */
  296 + reg_set((void __iomem *)rh_vsreg_addr, vphy_loopback_reg0, 0xFFFFFFFF);
  297 + ret = comphy_poll_reg((void *)rh_vsreg_data, /* address */
  298 + bs_pll_ready_tx, /* value */
  299 + bs_pll_ready_tx, /* mask */
  300 + PLL_LOCK_TIMEOUT, /* timeout */
  301 + POLL_32B_REG); /* 32bit */
  302 + if (ret == 0)
  303 + printf("Failed to lock SATA PLL\n");
  304 +
  305 + debug_exit();
  306 +
  307 + return ret;
  308 +}
  309 +
  310 +/*
  311 + * comphy_usb3_power_up
  312 + *
  313 + * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
  314 + */
  315 +static int comphy_usb3_power_up(u32 type, u32 speed, u32 invert)
  316 +{
  317 + int ret;
  318 +
  319 + debug_enter();
  320 +
  321 + /*
  322 + * 1. Power up OTG module
  323 + */
  324 + reg_set((void __iomem *)USB2_PHY_OTG_CTRL_ADDR, rb_pu_otg, 0);
  325 +
  326 + /*
  327 + * 2. Set counter for 100us pulse in USB3 Host and Device
  328 + * restore default burst size limit (Reference Clock 31:24)
  329 + */
  330 + reg_set((void __iomem *)USB3_CTRPUL_VAL_REG,
  331 + 0x8 << 24, rb_usb3_ctr_100ns);
  332 +
  333 +
  334 + /* 0xd005c300 = 0x1001 */
  335 + /* set PRD_TXDEEMPH (3.5db de-emph) */
  336 + reg_set16((void __iomem *)LANE_CFG0_ADDR(USB3), 0x1, 0xFF);
  337 +
  338 + /*
  339 + * unset BIT0: set Tx Electrical Idle Mode: Transmitter is in
  340 + * low impedance mode during electrical idle
  341 + */
  342 + /* unset BIT4: set G2 Tx Datapath with no Delayed Latency */
  343 + /* unset BIT6: set Tx Detect Rx Mode at LoZ mode */
  344 + reg_set16((void __iomem *)LANE_CFG1_ADDR(USB3), 0x0, 0xFFFF);
  345 +
  346 +
  347 + /* 0xd005c310 = 0x93: set Spread Spectrum Clock Enabled */
  348 + reg_set16((void __iomem *)LANE_CFG4_ADDR(USB3),
  349 + bf_spread_spectrum_clock_en, 0x80);
  350 +
  351 + /*
  352 + * set Override Margining Controls From the MAC: Use margining signals
  353 + * from lane configuration
  354 + */
  355 + reg_set16((void __iomem *)TEST_MODE_CTRL_ADDR(USB3),
  356 + rb_mode_margin_override, 0xFFFF);
  357 +
  358 + /* set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles */
  359 + /* set Mode Clock Source = PCLK is generated from REFCLK */
  360 + reg_set16((void __iomem *)GLOB_CLK_SRC_LO_ADDR(USB3), 0x0, 0xFF);
  361 +
  362 + /* set G2 Spread Spectrum Clock Amplitude at 4K */
  363 + reg_set16((void __iomem *)GEN2_SETTING_2_ADDR(USB3), g2_tx_ssc_amp,
  364 + 0xF000);
  365 +
  366 + /*
  367 + * unset G3 Spread Spectrum Clock Amplitude & set G3 TX and RX Register
  368 + * Master Current Select
  369 + */
  370 + reg_set16((void __iomem *)GEN2_SETTING_3_ADDR(USB3), 0x0, 0xFFFF);
  371 +
  372 + /*
  373 + * 3. Check crystal jumper setting and program the Power and PLL
  374 + * Control accordingly
  375 + */
  376 + if (get_ref_clk() == 40) {
  377 + reg_set16((void __iomem *)PWR_PLL_CTRL_ADDR(USB3), 0xFCA3,
  378 + 0xFFFF); /* 40 MHz */
  379 + } else {
  380 + reg_set16((void __iomem *)PWR_PLL_CTRL_ADDR(USB3), 0xFCA2,
  381 + 0xFFFF); /* 25 MHz */
  382 + }
  383 +
  384 + /*
  385 + * 4. Change RX wait
  386 + */
  387 + reg_set16((void __iomem *)PWR_MGM_TIM1_ADDR(USB3), 0x10C, 0xFFFF);
  388 +
  389 + /*
  390 + * 5. Enable idle sync
  391 + */
  392 + reg_set16((void __iomem *)UNIT_CTRL_ADDR(USB3), 0x60 | rb_idle_sync_en,
  393 + 0xFFFF);
  394 +
  395 + /*
  396 + * 6. Enable the output of 500M clock
  397 + */
  398 + reg_set16((void __iomem *)MISC_REG0_ADDR(USB3), 0xA00D | rb_clk500m_en,
  399 + 0xFFFF);
  400 +
  401 + /*
  402 + * 7. Set 20-bit data width
  403 + */
  404 + reg_set16((void __iomem *)DIG_LB_EN_ADDR(USB3), 0x0400, 0xFFFF);
  405 +
  406 + /*
  407 + * 8. Override Speed_PLL value and use MAC PLL
  408 + */
  409 + reg_set16((void __iomem *)KVCO_CAL_CTRL_ADDR(USB3),
  410 + 0x0040 | rb_use_max_pll_rate, 0xFFFF);
  411 +
  412 + /*
  413 + * 9. Check the Polarity invert bit
  414 + */
  415 + if (invert & PHY_POLARITY_TXD_INVERT) {
  416 + reg_set16((void __iomem *)SYNC_PATTERN_ADDR(USB3),
  417 + phy_txd_inv, 0);
  418 + }
  419 +
  420 + if (invert & PHY_POLARITY_RXD_INVERT) {
  421 + reg_set16((void __iomem *)SYNC_PATTERN_ADDR(USB3),
  422 + phy_rxd_inv, 0);
  423 + }
  424 +
  425 + /*
  426 + * 10. Release SW reset
  427 + */
  428 + reg_set16((void __iomem *)GLOB_PHY_CTRL0_ADDR(USB3),
  429 + rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32 | 0x20,
  430 + 0xFFFF);
  431 +
  432 + /* Wait for > 55 us to allow PCLK be enabled */
  433 + udelay(PLL_SET_DELAY_US);
  434 +
  435 + /* Assert PCLK enabled */
  436 + ret = comphy_poll_reg((void *)LANE_STAT1_ADDR(USB3), /* address */
  437 + rb_txdclk_pclk_en, /* value */
  438 + rb_txdclk_pclk_en, /* mask */
  439 + PLL_LOCK_TIMEOUT, /* timeout */
  440 + POLL_16B_REG); /* 16bit */
  441 + if (ret == 0)
  442 + printf("Failed to lock USB3 PLL\n");
  443 +
  444 + /*
  445 + * Set Soft ID for Host mode (Device mode works with Hard ID
  446 + * detection)
  447 + */
  448 + if (type == PHY_TYPE_USB3_HOST0) {
  449 + /*
  450 + * set BIT0: set ID_MODE of Host/Device = "Soft ID" (BIT1)
  451 + * clear BIT1: set SOFT_ID = Host
  452 + * set BIT4: set INT_MODE = ID. Interrupt Mode: enable
  453 + * interrupt by ID instead of using both interrupts
  454 + * of HOST and Device ORed simultaneously
  455 + * INT_MODE=ID in order to avoid unexpected
  456 + * behaviour or both interrupts together
  457 + */
  458 + reg_set((void __iomem *)USB32_CTRL_BASE,
  459 + usb32_ctrl_id_mode | usb32_ctrl_int_mode,
  460 + usb32_ctrl_id_mode | usb32_ctrl_soft_id |
  461 + usb32_ctrl_int_mode);
  462 + }
  463 +
  464 + debug_exit();
  465 +
  466 + return ret;
  467 +}
  468 +
  469 +/*
  470 + * comphy_usb2_power_up
  471 + *
  472 + * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
  473 + */
  474 +static int comphy_usb2_power_up(u8 usb32)
  475 +{
  476 + int ret;
  477 +
  478 + debug_enter();
  479 +
  480 + if (usb32 != 0 && usb32 != 1) {
  481 + printf("invalid usb32 value: (%d), should be either 0 or 1\n",
  482 + usb32);
  483 + debug_exit();
  484 + return 0;
  485 + }
  486 +
  487 + /*
  488 + * 0. Setup PLL. 40MHz clock uses defaults.
  489 + * See "PLL Settings for Typical REFCLK" table
  490 + */
  491 + if (get_ref_clk() == 25) {
  492 + reg_set((void __iomem *)USB2_PHY_BASE(usb32),
  493 + 5 | (96 << 16), 0x3F | (0xFF << 16) | (0x3 << 28));
  494 + }
  495 +
  496 + /*
  497 + * 1. PHY pull up and disable USB2 suspend
  498 + */
  499 + reg_set((void __iomem *)USB2_PHY_CTRL_ADDR(usb32),
  500 + RB_USB2PHY_SUSPM(usb32) | RB_USB2PHY_PU(usb32), 0);
  501 +
  502 + if (usb32 != 0) {
  503 + /*
  504 + * 2. Power up OTG module
  505 + */
  506 + reg_set((void __iomem *)USB2_PHY_OTG_CTRL_ADDR, rb_pu_otg, 0);
  507 +
  508 + /*
  509 + * 3. Configure PHY charger detection
  510 + */
  511 + reg_set((void __iomem *)USB2_PHY_CHRGR_DET_ADDR, 0,
  512 + rb_cdp_en | rb_dcp_en | rb_pd_en | rb_cdp_dm_auto |
  513 + rb_enswitch_dp | rb_enswitch_dm | rb_pu_chrg_dtc);
  514 + }
  515 +
  516 + /* Assert PLL calibration done */
  517 + ret = comphy_poll_reg((void *)USB2_PHY_CAL_CTRL_ADDR(usb32),
  518 + rb_usb2phy_pllcal_done, /* value */
  519 + rb_usb2phy_pllcal_done, /* mask */
  520 + PLL_LOCK_TIMEOUT, /* timeout */
  521 + POLL_32B_REG); /* 32bit */
  522 + if (ret == 0)
  523 + printf("Failed to end USB2 PLL calibration\n");
  524 +
  525 + /* Assert impedance calibration done */
  526 + ret = comphy_poll_reg((void *)USB2_PHY_CAL_CTRL_ADDR(usb32),
  527 + rb_usb2phy_impcal_done, /* value */
  528 + rb_usb2phy_impcal_done, /* mask */
  529 + PLL_LOCK_TIMEOUT, /* timeout */
  530 + POLL_32B_REG); /* 32bit */
  531 + if (ret == 0)
  532 + printf("Failed to end USB2 impedance calibration\n");
  533 +
  534 + /* Assert squetch calibration done */
  535 + ret = comphy_poll_reg((void *)USB2_PHY_RX_CHAN_CTRL1_ADDR(usb32),
  536 + rb_usb2phy_sqcal_done, /* value */
  537 + rb_usb2phy_sqcal_done, /* mask */
  538 + PLL_LOCK_TIMEOUT, /* timeout */
  539 + POLL_32B_REG); /* 32bit */
  540 + if (ret == 0)
  541 + printf("Failed to end USB2 unknown calibration\n");
  542 +
  543 + /* Assert PLL is ready */
  544 + ret = comphy_poll_reg((void *)USB2_PHY_PLL_CTRL0_ADDR(usb32),
  545 + rb_usb2phy_pll_ready, /* value */
  546 + rb_usb2phy_pll_ready, /* mask */
  547 + PLL_LOCK_TIMEOUT, /* timeout */
  548 + POLL_32B_REG); /* 32bit */
  549 +
  550 + if (ret == 0)
  551 + printf("Failed to lock USB2 PLL\n");
  552 +
  553 + debug_exit();
  554 +
  555 + return ret;
  556 +}
  557 +
  558 +/*
  559 + * comphy_emmc_power_up
  560 + *
  561 + * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
  562 + */
  563 +static int comphy_emmc_power_up(void)
  564 +{
  565 + debug_enter();
  566 +
  567 + /*
  568 + * 1. Bus power ON, Bus voltage 1.8V
  569 + */
  570 + reg_set((void __iomem *)SDIO_HOST_CTRL1_ADDR, 0xB00, 0xF00);
  571 +
  572 + /*
  573 + * 2. Set FIFO parameters
  574 + */
  575 + reg_set((void __iomem *)SDIO_SDHC_FIFO_ADDR, 0x315, 0xFFFFFFFF);
  576 +
  577 + /*
  578 + * 3. Set Capabilities 1_2
  579 + */
  580 + reg_set((void __iomem *)SDIO_CAP_12_ADDR, 0x25FAC8B2, 0xFFFFFFFF);
  581 +
  582 + /*
  583 + * 4. Set Endian
  584 + */
  585 + reg_set((void __iomem *)SDIO_ENDIAN_ADDR, 0x00c00000, 0);
  586 +
  587 + /*
  588 + * 4. Init PHY
  589 + */
  590 + reg_set((void __iomem *)SDIO_PHY_TIMING_ADDR, 0x80000000, 0x80000000);
  591 + reg_set((void __iomem *)SDIO_PHY_PAD_CTRL0_ADDR, 0x50000000,
  592 + 0xF0000000);
  593 +
  594 + /*
  595 + * 5. DLL reset
  596 + */
  597 + reg_set((void __iomem *)SDIO_DLL_RST_ADDR, 0xFFFEFFFF, 0);
  598 + reg_set((void __iomem *)SDIO_DLL_RST_ADDR, 0x00010000, 0);
  599 +
  600 + debug_exit();
  601 +
  602 + return 1;
  603 +}
  604 +
  605 +/*
  606 + * comphy_sgmii_power_up
  607 + *
  608 + * return:
  609 + */
  610 +static void comphy_sgmii_phy_init(u32 lane, u32 speed)
  611 +{
  612 + const int fix_arr_sz = ARRAY_SIZE(sgmii_phy_init_fix);
  613 + int addr, fix_idx;
  614 + u16 val;
  615 +
  616 + fix_idx = 0;
  617 + for (addr = 0; addr < 512; addr++) {
  618 + /*
  619 + * All PHY register values are defined in full for 3.125Gbps
  620 + * SERDES speed. The values required for 1.25 Gbps are almost
  621 + * the same and only few registers should be "fixed" in
  622 + * comparison to 3.125 Gbps values. These register values are
  623 + * stored in "sgmii_phy_init_fix" array.
  624 + */
  625 + if ((speed != PHY_SPEED_1_25G) &&
  626 + (sgmii_phy_init_fix[fix_idx].addr == addr)) {
  627 + /* Use new value */
  628 + val = sgmii_phy_init_fix[fix_idx].value;
  629 + if (fix_idx < fix_arr_sz)
  630 + fix_idx++;
  631 + } else {
  632 + val = sgmii_phy_init[addr];
  633 + }
  634 +
  635 + phy_write16(lane, addr, val, 0xFFFF);
  636 + }
  637 +}
  638 +
  639 +/*
  640 + * comphy_sgmii_power_up
  641 + *
  642 + * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
  643 + */
  644 +static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert)
  645 +{
  646 + int ret;
  647 +
  648 + debug_enter();
  649 +
  650 + /*
  651 + * 1. Configure PHY to SATA/SAS mode by setting pin PIN_PIPE_SEL=0
  652 + */
  653 + reg_set((void __iomem *)COMPHY_SEL_ADDR, 0, rf_compy_select(lane));
  654 +
  655 + /*
  656 + * 2. Reset PHY by setting PHY input port PIN_RESET=1.
  657 + * 3. Set PHY input port PIN_TX_IDLE=1, PIN_PU_IVREF=1 to keep
  658 + * PHY TXP/TXN output to idle state during PHY initialization
  659 + * 4. Set PHY input port PIN_PU_PLL=0, PIN_PU_RX=0, PIN_PU_TX=0.
  660 + */
  661 + reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane),
  662 + rb_pin_reset_comphy | rb_pin_tx_idle | rb_pin_pu_iveref,
  663 + rb_pin_reset_core | rb_pin_pu_pll |
  664 + rb_pin_pu_rx | rb_pin_pu_tx);
  665 +
  666 + /*
  667 + * 5. Release reset to the PHY by setting PIN_RESET=0.
  668 + */
  669 + reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane),
  670 + 0, rb_pin_reset_comphy);
  671 +
  672 + /*
  673 + * 7. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide
  674 + * COMPHY bit rate
  675 + */
  676 + if (speed == PHY_SPEED_3_125G) { /* 3.125 GHz */
  677 + reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane),
  678 + (0x8 << rf_gen_rx_sel_shift) |
  679 + (0x8 << rf_gen_tx_sel_shift),
  680 + rf_gen_rx_select | rf_gen_tx_select);
  681 +
  682 + } else if (speed == PHY_SPEED_1_25G) { /* 1.25 GHz */
  683 + reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane),
  684 + (0x6 << rf_gen_rx_sel_shift) |
  685 + (0x6 << rf_gen_tx_sel_shift),
  686 + rf_gen_rx_select | rf_gen_tx_select);
  687 + } else {
  688 + printf("Unsupported COMPHY speed!\n");
  689 + return 0;
  690 + }
  691 +
  692 + /*
  693 + * 8. Wait 1mS for bandgap and reference clocks to stabilize;
  694 + * then start SW programming.
  695 + */
  696 + mdelay(10);
  697 +
  698 + /* 9. Program COMPHY register PHY_MODE */
  699 + phy_write16(lane, PHY_PWR_PLL_CTRL_ADDR,
  700 + PHY_MODE_SGMII << rf_phy_mode_shift, rf_phy_mode_mask);
  701 +
  702 + /*
  703 + * 10. Set COMPHY register REFCLK_SEL to select the correct REFCLK
  704 + * source
  705 + */
  706 + phy_write16(lane, PHY_MISC_REG0_ADDR, 0, rb_ref_clk_sel);
  707 +
  708 + /*
  709 + * 11. Set correct reference clock frequency in COMPHY register
  710 + * REF_FREF_SEL.
  711 + */
  712 + if (get_ref_clk() == 40) {
  713 + phy_write16(lane, PHY_PWR_PLL_CTRL_ADDR,
  714 + 0x4 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask);
  715 + } else {
  716 + /* 25MHz */
  717 + phy_write16(lane, PHY_PWR_PLL_CTRL_ADDR,
  718 + 0x1 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask);
  719 + }
  720 +
  721 + /* 12. Program COMPHY register PHY_GEN_MAX[1:0] */
  722 + /*
  723 + * This step is mentioned in the flow received from verification team.
  724 + * However the PHY_GEN_MAX value is only meaningful for other
  725 + * interfaces (not SGMII). For instance, it selects SATA speed
  726 + * 1.5/3/6 Gbps or PCIe speed 2.5/5 Gbps
  727 + */
  728 +
  729 + /*
  730 + * 13. Program COMPHY register SEL_BITS to set correct parallel data
  731 + * bus width
  732 + */
  733 + /* 10bit */
  734 + phy_write16(lane, PHY_DIG_LB_EN_ADDR, 0, rf_data_width_mask);
  735 +
  736 + /*
  737 + * 14. As long as DFE function needs to be enabled in any mode,
  738 + * COMPHY register DFE_UPDATE_EN[5:0] shall be programmed to 0x3F
  739 + * for real chip during COMPHY power on.
  740 + */
  741 + /*
  742 + * The step 14 exists (and empty) in the original initialization flow
  743 + * obtained from the verification team. According to the functional
  744 + * specification DFE_UPDATE_EN already has the default value 0x3F
  745 + */
  746 +
  747 + /*
  748 + * 15. Program COMPHY GEN registers.
  749 + * These registers should be programmed based on the lab testing
  750 + * result to achieve optimal performance. Please contact the CEA
  751 + * group to get the related GEN table during real chip bring-up.
  752 + * We only requred to run though the entire registers programming
  753 + * flow defined by "comphy_sgmii_phy_init" when the REF clock is
  754 + * 40 MHz. For REF clock 25 MHz the default values stored in PHY
  755 + * registers are OK.
  756 + */
  757 + debug("Running C-DPI phy init %s mode\n",
  758 + speed == PHY_SPEED_3_125G ? "2G5" : "1G");
  759 + if (get_ref_clk() == 40)
  760 + comphy_sgmii_phy_init(lane, speed);
  761 +
  762 + /*
  763 + * 16. [Simulation Only] should not be used for real chip.
  764 + * By pass power up calibration by programming EXT_FORCE_CAL_DONE
  765 + * (R02h[9]) to 1 to shorten COMPHY simulation time.
  766 + */
  767 + /*
  768 + * 17. [Simulation Only: should not be used for real chip]
  769 + * Program COMPHY register FAST_DFE_TIMER_EN=1 to shorten RX
  770 + * training simulation time.
  771 + */
  772 +
  773 + /*
  774 + * 18. Check the PHY Polarity invert bit
  775 + */
  776 + if (invert & PHY_POLARITY_TXD_INVERT)
  777 + phy_write16(lane, PHY_SYNC_PATTERN_ADDR, phy_txd_inv, 0);
  778 +
  779 + if (invert & PHY_POLARITY_RXD_INVERT)
  780 + phy_write16(lane, PHY_SYNC_PATTERN_ADDR, phy_rxd_inv, 0);
  781 +
  782 + /*
  783 + * 19. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1
  784 + * to start PHY power up sequence. All the PHY register
  785 + * programming should be done before PIN_PU_PLL=1. There should be
  786 + * no register programming for normal PHY operation from this point.
  787 + */
  788 + reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane),
  789 + rb_pin_pu_pll | rb_pin_pu_rx | rb_pin_pu_tx,
  790 + rb_pin_pu_pll | rb_pin_pu_rx | rb_pin_pu_tx);
  791 +
  792 + /*
  793 + * 20. Wait for PHY power up sequence to finish by checking output ports
  794 + * PIN_PLL_READY_TX=1 and PIN_PLL_READY_RX=1.
  795 + */
  796 + ret = comphy_poll_reg((void *)COMPHY_PHY_STAT1_ADDR(lane), /* address */
  797 + rb_pll_ready_tx | rb_pll_ready_rx, /* value */
  798 + rb_pll_ready_tx | rb_pll_ready_rx, /* mask */
  799 + PLL_LOCK_TIMEOUT, /* timeout */
  800 + POLL_32B_REG); /* 32bit */
  801 + if (ret == 0)
  802 + printf("Failed to lock PLL for SGMII PHY %d\n", lane);
  803 +
  804 + /*
  805 + * 21. Set COMPHY input port PIN_TX_IDLE=0
  806 + */
  807 + reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane),
  808 + 0x0, rb_pin_tx_idle);
  809 +
  810 + /*
  811 + * 22. After valid data appear on PIN_RXDATA bus, set PIN_RX_INIT=1.
  812 + * to start RX initialization. PIN_RX_INIT_DONE will be cleared to
  813 + * 0 by the PHY. After RX initialization is done, PIN_RX_INIT_DONE
  814 + * will be set to 1 by COMPHY. Set PIN_RX_INIT=0 after
  815 + * PIN_RX_INIT_DONE= 1.
  816 + * Please refer to RX initialization part for details.
  817 + */
  818 + reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane), rb_phy_rx_init,
  819 + 0x0);
  820 +
  821 + ret = comphy_poll_reg((void *)COMPHY_PHY_STAT1_ADDR(lane), /* address */
  822 + rb_rx_init_done, /* value */
  823 + rb_rx_init_done, /* mask */
  824 + PLL_LOCK_TIMEOUT, /* timeout */
  825 + POLL_32B_REG); /* 32bit */
  826 + if (ret == 0)
  827 + printf("Failed to init RX of SGMII PHY %d\n", lane);
  828 +
  829 + debug_exit();
  830 +
  831 + return ret;
  832 +}
  833 +
  834 +void comphy_dedicated_phys_init(void)
  835 +{
  836 + int node, usb32, ret = 1;
  837 + const void *blob = gd->fdt_blob;
  838 +
  839 + debug_enter();
  840 +
  841 + for (usb32 = 0; usb32 <= 1; usb32++) {
  842 + /*
  843 + * There are 2 UTMI PHYs in this SOC.
  844 + * One is independendent and one is paired with USB3 port (OTG)
  845 + */
  846 + if (usb32 == 0) {
  847 + node = fdt_node_offset_by_compatible(
  848 + blob, -1, "marvell,armada-3700-ehci");
  849 + } else {
  850 + node = fdt_node_offset_by_compatible(
  851 + blob, -1, "marvell,armada3700-xhci");
  852 + }
  853 +
  854 + if (node > 0) {
  855 + if (fdtdec_get_is_enabled(blob, node)) {
  856 + ret = comphy_usb2_power_up(usb32);
  857 + if (ret == 0)
  858 + printf("Failed to initialize UTMI PHY\n");
  859 + else
  860 + debug("UTMI PHY init succeed\n");
  861 + } else {
  862 + debug("USB%d node is disabled\n",
  863 + usb32 == 0 ? 2 : 3);
  864 + }
  865 + } else {
  866 + debug("No USB%d node in DT\n", usb32 == 0 ? 2 : 3);
  867 + }
  868 + }
  869 +
  870 + node = fdt_node_offset_by_compatible(blob, -1,
  871 + "marvell,armada-3700-ahci");
  872 + if (node > 0) {
  873 + if (fdtdec_get_is_enabled(blob, node)) {
  874 + ret = comphy_sata_power_up();
  875 + if (ret == 0)
  876 + printf("Failed to initialize SATA PHY\n");
  877 + else
  878 + debug("SATA PHY init succeed\n");
  879 + } else {
  880 + debug("SATA node is disabled\n");
  881 + }
  882 + } else {
  883 + debug("No SATA node in DT\n");
  884 + }
  885 +
  886 + node = fdt_node_offset_by_compatible(blob, -1,
  887 + "marvell,armada-3700-sdio");
  888 + if (node <= 0) {
  889 + debug("No SDIO node in DT, looking for MMC one\n");
  890 + node = fdt_node_offset_by_compatible(blob, -1,
  891 + "marvell,xenon-sdhci");
  892 + }
  893 +
  894 + if (node > 0) {
  895 + if (fdtdec_get_is_enabled(blob, node)) {
  896 + ret = comphy_emmc_power_up();
  897 + if (ret == 0)
  898 + printf("Failed to initialize SDIO/eMMC PHY\n");
  899 + else
  900 + debug("SDIO/eMMC PHY init succeed\n");
  901 + } else {
  902 + debug("SDIO/eMMC node is disabled\n");
  903 + }
  904 + } else {
  905 + debug("No SDIO/eMMC node in DT\n");
  906 + }
  907 +
  908 + debug_exit();
  909 +}
  910 +
  911 +int comphy_a3700_init(struct chip_serdes_phy_config *chip_cfg,
  912 + struct comphy_map *serdes_map)
  913 +{
  914 + struct comphy_map *comphy_map;
  915 + u32 comphy_max_count = chip_cfg->comphy_lanes_count;
  916 + u32 lane, ret = 0;
  917 +
  918 + debug_enter();
  919 +
  920 + for (lane = 0, comphy_map = serdes_map; lane < comphy_max_count;
  921 + lane++, comphy_map++) {
  922 + debug("Initialize serdes number %d\n", lane);
  923 + debug("Serdes type = 0x%x invert=%d\n",
  924 + comphy_map->type, comphy_map->invert);
  925 +
  926 + switch (comphy_map->type) {
  927 + case PHY_TYPE_UNCONNECTED:
  928 + continue;
  929 + break;
  930 +
  931 + case PHY_TYPE_PEX0:
  932 + ret = comphy_pcie_power_up(comphy_map->speed,
  933 + comphy_map->invert);
  934 + break;
  935 +
  936 + case PHY_TYPE_USB3_HOST0:
  937 + case PHY_TYPE_USB3_DEVICE:
  938 + ret = comphy_usb3_power_up(comphy_map->type,
  939 + comphy_map->speed,
  940 + comphy_map->invert);
  941 + break;
  942 +
  943 + case PHY_TYPE_SGMII0:
  944 + case PHY_TYPE_SGMII1:
  945 + ret = comphy_sgmii_power_up(lane, comphy_map->speed,
  946 + comphy_map->invert);
  947 + break;
  948 +
  949 + default:
  950 + debug("Unknown SerDes type, skip initialize SerDes %d\n",
  951 + lane);
  952 + ret = 1;
  953 + break;
  954 + }
  955 + if (ret == 0)
  956 + printf("PLL is not locked - Failed to initialize lane %d\n",
  957 + lane);
  958 + }
  959 +
  960 + debug_exit();
  961 + return ret;
  962 +}
drivers/phy/marvell/comphy_a3700.h
Diff comments   View file @ 3335786
  1 +/*
  2 + * Copyright (C) 2015-2016 Marvell International Ltd.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef _COMPHY_A3700_H_
  8 +#define _COMPHY_A3700_H_
  9 +
  10 +#include "comphy.h"
  11 +#include "comphy_hpipe.h"
  12 +
  13 +#define MVEBU_REG(offs) ((uintptr_t)MVEBU_REGISTER(offs))
  14 +
  15 +#define DEFAULT_REFCLK_MHZ 25
  16 +#define PLL_SET_DELAY_US 600
  17 +#define PLL_LOCK_TIMEOUT 1000
  18 +#define POLL_16B_REG 1
  19 +#define POLL_32B_REG 0
  20 +
  21 +/*
  22 + * COMPHY SB definitions
  23 + */
  24 +#define COMPHY_SEL_ADDR MVEBU_REG(0x0183FC)
  25 +#define rf_compy_select(lane) (0x1 << (((lane) == 1) ? 4 : 0))
  26 +
  27 +#define COMPHY_PHY_CFG1_ADDR(lane) MVEBU_REG(0x018300 + (lane) * 0x28)
  28 +#define rb_pin_pu_iveref BIT(1)
  29 +#define rb_pin_reset_core BIT(11)
  30 +#define rb_pin_reset_comphy BIT(12)
  31 +#define rb_pin_pu_pll BIT(16)
  32 +#define rb_pin_pu_rx BIT(17)
  33 +#define rb_pin_pu_tx BIT(18)
  34 +#define rb_pin_tx_idle BIT(19)
  35 +#define rf_gen_rx_sel_shift 22
  36 +#define rf_gen_rx_select (0xFF << rf_gen_rx_sel_shift)
  37 +#define rf_gen_tx_sel_shift 26
  38 +#define rf_gen_tx_select (0xFF << rf_gen_tx_sel_shift)
  39 +#define rb_phy_rx_init BIT(30)
  40 +
  41 +#define COMPHY_PHY_STAT1_ADDR(lane) MVEBU_REG(0x018318 + (lane) * 0x28)
  42 +#define rb_rx_init_done BIT(0)
  43 +#define rb_pll_ready_rx BIT(2)
  44 +#define rb_pll_ready_tx BIT(3)
  45 +
  46 +/*
  47 + * PCIe/USB/SGMII definitions
  48 + */
  49 +#define PCIE_BASE MVEBU_REG(0x070000)
  50 +#define PCIETOP_BASE MVEBU_REG(0x080000)
  51 +#define PCIE_RAMBASE MVEBU_REG(0x08C000)
  52 +#define PCIEPHY_BASE MVEBU_REG(0x01F000)
  53 +#define PCIEPHY_SHFT 2
  54 +
  55 +#define USB32_BASE MVEBU_REG(0x050000) /* usb3 device */
  56 +#define USB32H_BASE MVEBU_REG(0x058000) /* usb3 host */
  57 +#define USB3PHY_BASE MVEBU_REG(0x05C000)
  58 +#define USB2PHY_BASE MVEBU_REG(0x05D000)
  59 +#define USB2PHY2_BASE MVEBU_REG(0x05F000)
  60 +#define USB32_CTRL_BASE MVEBU_REG(0x05D800)
  61 +#define USB3PHY_SHFT 2
  62 +
  63 +#define SGMIIPHY_BASE(l) (l == 1 ? USB3PHY_BASE : PCIEPHY_BASE)
  64 +#define SGMIIPHY_ADDR(l, a) (((a & 0x00007FF) * 2) | SGMIIPHY_BASE(l))
  65 +
  66 +#define phy_read16(l, a) read16((void __iomem *)SGMIIPHY_ADDR(l, a))
  67 +#define phy_write16(l, a, data, mask) \
  68 + reg_set16((void __iomem *)SGMIIPHY_ADDR(l, a), data, mask)
  69 +
  70 +/* units */
  71 +#define PCIE 1
  72 +#define USB3 2
  73 +
  74 +#define PHY_BASE(unit) ((unit == PCIE) ? PCIEPHY_BASE : USB3PHY_BASE)
  75 +#define PHY_SHFT(unit) ((unit == PCIE) ? PCIEPHY_SHFT : USB3PHY_SHFT)
  76 +
  77 +/* bit definition for USB32_CTRL_BASE (USB32 Control Mode) */
  78 +#define usb32_ctrl_id_mode BIT(0)
  79 +#define usb32_ctrl_soft_id BIT(1)
  80 +#define usb32_ctrl_int_mode BIT(4)
  81 +
  82 +
  83 +#define PHY_PWR_PLL_CTRL_ADDR 0x01 /* for phy_read16 and phy_write16 */
  84 +#define PWR_PLL_CTRL_ADDR(unit) \
  85 + (PHY_PWR_PLL_CTRL_ADDR * PHY_SHFT(unit) + PHY_BASE(unit))
  86 +#define rf_phy_mode_shift 5
  87 +#define rf_phy_mode_mask (0x7 << rf_phy_mode_shift)
  88 +#define rf_ref_freq_sel_shift 0
  89 +#define rf_ref_freq_sel_mask (0x1F << rf_ref_freq_sel_shift)
  90 +#define PHY_MODE_SGMII 0x4
  91 +
  92 +/* for phy_read16 and phy_write16 */
  93 +#define PHY_REG_KVCO_CAL_CTRL_ADDR 0x02
  94 +#define KVCO_CAL_CTRL_ADDR(unit) \
  95 + (PHY_REG_KVCO_CAL_CTRL_ADDR * PHY_SHFT(unit) + PHY_BASE(unit))
  96 +#define rb_use_max_pll_rate BIT(12)
  97 +#define rb_force_calibration_done BIT(9)
  98 +
  99 +/* for phy_read16 and phy_write16 */
  100 +#define PHY_DIG_LB_EN_ADDR 0x23
  101 +#define DIG_LB_EN_ADDR(unit) \
  102 + (PHY_DIG_LB_EN_ADDR * PHY_SHFT(unit) + PHY_BASE(unit))
  103 +#define rf_data_width_shift 10
  104 +#define rf_data_width_mask (0x3 << rf_data_width_shift)
  105 +
  106 +/* for phy_read16 and phy_write16 */
  107 +#define PHY_SYNC_PATTERN_ADDR 0x24
  108 +#define SYNC_PATTERN_ADDR(unit) \
  109 + (PHY_SYNC_PATTERN_ADDR * PHY_SHFT(unit) + PHY_BASE(unit))
  110 +#define phy_txd_inv BIT(10)
  111 +#define phy_rxd_inv BIT(11)
  112 +
  113 +/* for phy_read16 and phy_write16 */
  114 +#define PHY_REG_UNIT_CTRL_ADDR 0x48
  115 +#define UNIT_CTRL_ADDR(unit) \
  116 + (PHY_REG_UNIT_CTRL_ADDR * PHY_SHFT(unit) + PHY_BASE(unit))
  117 +#define rb_idle_sync_en BIT(12)
  118 +
  119 +/* for phy_read16 and phy_write16 */
  120 +#define PHY_REG_GEN2_SETTINGS_2 0x3e
  121 +#define GEN2_SETTING_2_ADDR(unit) \
  122 + (PHY_REG_GEN2_SETTINGS_2 * PHY_SHFT(unit) + PHY_BASE(unit))
  123 +#define g2_tx_ssc_amp BIT(14)
  124 +
  125 +/* for phy_read16 and phy_write16 */
  126 +#define PHY_REG_GEN2_SETTINGS_3 0x3f
  127 +#define GEN2_SETTING_3_ADDR(unit) \
  128 + (PHY_REG_GEN2_SETTINGS_3 * PHY_SHFT(unit) + PHY_BASE(unit))
  129 +
  130 +/* for phy_read16 and phy_write16 */
  131 +#define PHY_MISC_REG0_ADDR 0x4f
  132 +#define MISC_REG0_ADDR(unit) \
  133 + (PHY_MISC_REG0_ADDR * PHY_SHFT(unit) + PHY_BASE(unit))
  134 +#define rb_clk100m_125m_en BIT(4)
  135 +#define rb_clk500m_en BIT(7)
  136 +#define rb_ref_clk_sel BIT(10)
  137 +
  138 +/* for phy_read16 and phy_write16 */
  139 +#define PHY_REG_IFACE_REF_CLK_CTRL_ADDR 0x51
  140 +#define UNIT_IFACE_REF_CLK_CTRL_ADDR(unit) \
  141 + (PHY_REG_IFACE_REF_CLK_CTRL_ADDR * PHY_SHFT(unit) + PHY_BASE(unit))
  142 +#define rb_ref1m_gen_div_force BIT(8)
  143 +#define rf_ref1m_gen_div_value_shift 0
  144 +#define rf_ref1m_gen_div_value_mask (0xFF << rf_ref1m_gen_div_value_shift)
  145 +
  146 +/* for phy_read16 and phy_write16 */
  147 +#define PHY_REG_ERR_CNT_CONST_CTRL_ADDR 0x6A
  148 +#define UNIT_ERR_CNT_CONST_CTRL_ADDR(unit) \
  149 + (PHY_REG_ERR_CNT_CONST_CTRL_ADDR * PHY_SHFT(unit) + PHY_BASE(unit))
  150 +#define rb_fast_dfe_enable BIT(13)
  151 +
  152 +#define MISC_REG1_ADDR(u) (0x73 * PHY_SHFT(u) + PHY_BASE(u))
  153 +#define bf_sel_bits_pcie_force BIT(15)
  154 +
  155 +#define LANE_CFG0_ADDR(u) (0x180 * PHY_SHFT(u) + PHY_BASE(u))
  156 +#define bf_use_max_pll_rate BIT(9)
  157 +#define LANE_CFG1_ADDR(u) (0x181 * PHY_SHFT(u) + PHY_BASE(u))
  158 +#define bf_use_max_pll_rate BIT(9)
  159 +/* 0x5c310 = 0x93 (set BIT7) */
  160 +#define LANE_CFG4_ADDR(u) (0x188 * PHY_SHFT(u) + PHY_BASE(u))
  161 +#define bf_spread_spectrum_clock_en BIT(7)
  162 +
  163 +#define LANE_STAT1_ADDR(u) (0x183 * PHY_SHFT(u) + PHY_BASE(u))
  164 +#define rb_txdclk_pclk_en BIT(0)
  165 +
  166 +#define GLOB_PHY_CTRL0_ADDR(u) (0x1c1 * PHY_SHFT(u) + PHY_BASE(u))
  167 +#define bf_soft_rst BIT(0)
  168 +#define bf_mode_refdiv 0x30
  169 +#define rb_mode_core_clk_freq_sel BIT(9)
  170 +#define rb_mode_pipe_width_32 BIT(3)
  171 +
  172 +#define TEST_MODE_CTRL_ADDR(u) (0x1c2 * PHY_SHFT(u) + PHY_BASE(u))
  173 +#define rb_mode_margin_override BIT(2)
  174 +
  175 +#define GLOB_CLK_SRC_LO_ADDR(u) (0x1c3 * PHY_SHFT(u) + PHY_BASE(u))
  176 +#define bf_cfg_sel_20b BIT(15)
  177 +
  178 +#define PWR_MGM_TIM1_ADDR(u) (0x1d0 * PHY_SHFT(u) + PHY_BASE(u))
  179 +
  180 +#define PHY_REF_CLK_ADDR (0x4814 + PCIE_BASE)
  181 +
  182 +#define USB3_CTRPUL_VAL_REG (0x20 + USB32_BASE)
  183 +#define USB3H_CTRPUL_VAL_REG (0x3454 + USB32H_BASE)
  184 +#define rb_usb3_ctr_100ns 0xff000000
  185 +
  186 +#define USB2_OTG_PHY_CTRL_ADDR (0x820 + USB2PHY_BASE)
  187 +#define rb_usb2phy_suspm BIT(14)
  188 +#define rb_usb2phy_pu BIT(0)
  189 +
  190 +#define USB2_PHY_OTG_CTRL_ADDR (0x34 + USB2PHY_BASE)
  191 +#define rb_pu_otg BIT(4)
  192 +
  193 +#define USB2_PHY_CHRGR_DET_ADDR (0x38 + USB2PHY_BASE)
  194 +#define rb_cdp_en BIT(2)
  195 +#define rb_dcp_en BIT(3)
  196 +#define rb_pd_en BIT(4)
  197 +#define rb_pu_chrg_dtc BIT(5)
  198 +#define rb_cdp_dm_auto BIT(7)
  199 +#define rb_enswitch_dp BIT(12)
  200 +#define rb_enswitch_dm BIT(13)
  201 +
  202 +#define USB2_CAL_CTRL_ADDR (0x8 + USB2PHY_BASE)
  203 +#define rb_usb2phy_pllcal_done BIT(31)
  204 +#define rb_usb2phy_impcal_done BIT(23)
  205 +
  206 +#define USB2_PLL_CTRL0_ADDR (0x0 + USB2PHY_BASE)
  207 +#define rb_usb2phy_pll_ready BIT(31)
  208 +
  209 +#define USB2_RX_CHAN_CTRL1_ADDR (0x18 + USB2PHY_BASE)
  210 +#define rb_usb2phy_sqcal_done BIT(31)
  211 +
  212 +#define USB2_PHY2_CTRL_ADDR (0x804 + USB2PHY2_BASE)
  213 +#define rb_usb2phy2_suspm BIT(7)
  214 +#define rb_usb2phy2_pu BIT(0)
  215 +#define USB2_PHY2_CAL_CTRL_ADDR (0x8 + USB2PHY2_BASE)
  216 +#define USB2_PHY2_PLL_CTRL0_ADDR (0x0 + USB2PHY2_BASE)
  217 +#define USB2_PHY2_RX_CHAN_CTRL1_ADDR (0x18 + USB2PHY2_BASE)
  218 +
  219 +#define USB2_PHY_BASE(usb32) (usb32 == 0 ? USB2PHY2_BASE : USB2PHY_BASE)
  220 +#define USB2_PHY_CTRL_ADDR(usb32) \
  221 + (usb32 == 0 ? USB2_PHY2_CTRL_ADDR : USB2_OTG_PHY_CTRL_ADDR)
  222 +#define RB_USB2PHY_SUSPM(usb32) \
  223 + (usb32 == 0 ? rb_usb2phy2_suspm : rb_usb2phy_suspm)
  224 +#define RB_USB2PHY_PU(usb32) \
  225 + (usb32 == 0 ? rb_usb2phy2_pu : rb_usb2phy_pu)
  226 +#define USB2_PHY_CAL_CTRL_ADDR(usb32) \
  227 + (usb32 == 0 ? USB2_PHY2_CAL_CTRL_ADDR : USB2_CAL_CTRL_ADDR)
  228 +#define USB2_PHY_RX_CHAN_CTRL1_ADDR(usb32) \
  229 + (usb32 == 0 ? USB2_PHY2_RX_CHAN_CTRL1_ADDR : USB2_RX_CHAN_CTRL1_ADDR)
  230 +#define USB2_PHY_PLL_CTRL0_ADDR(usb32) \
  231 + (usb32 == 0 ? USB2_PHY2_PLL_CTRL0_ADDR : USB2_PLL_CTRL0_ADDR)
  232 +
  233 +/*
  234 + * SATA definitions
  235 + */
  236 +#define AHCI_BASE MVEBU_REG(0xE0000)
  237 +
  238 +#define rh_vsreg_addr (AHCI_BASE + 0x178)
  239 +#define rh_vsreg_data (AHCI_BASE + 0x17C)
  240 +#define rh_vs0_a (AHCI_BASE + 0xA0)
  241 +#define rh_vs0_d (AHCI_BASE + 0xA4)
  242 +
  243 +#define vphy_sync_pattern_reg 0x224
  244 +#define bs_txd_inv BIT(10)
  245 +#define bs_rxd_inv BIT(11)
  246 +
  247 +#define vphy_loopback_reg0 0x223
  248 +#define bs_phyintf_40bit 0x0C00
  249 +#define bs_pll_ready_tx 0x10
  250 +
  251 +#define vphy_power_reg0 0x201
  252 +
  253 +#define vphy_calctl_reg 0x202
  254 +#define bs_max_pll_rate BIT(12)
  255 +
  256 +#define vphy_reserve_reg 0x0e
  257 +#define bs_phyctrl_frm_pin BIT(13)
  258 +
  259 +#define vsata_ctrl_reg 0x00
  260 +#define bs_phy_pu_pll BIT(6)
  261 +
  262 +/*
  263 + * SDIO/eMMC definitions
  264 + */
  265 +#define SDIO_BASE MVEBU_REG(0xD8000)
  266 +
  267 +#define SDIO_HOST_CTRL1_ADDR (SDIO_BASE + 0x28)
  268 +#define SDIO_SDHC_FIFO_ADDR (SDIO_BASE + 0x12C)
  269 +#define SDIO_CAP_12_ADDR (SDIO_BASE + 0x40)
  270 +#define SDIO_ENDIAN_ADDR (SDIO_BASE + 0x1A4)
  271 +#define SDIO_PHY_TIMING_ADDR (SDIO_BASE + 0x170)
  272 +#define SDIO_PHY_PAD_CTRL0_ADDR (SDIO_BASE + 0x178)
  273 +#define SDIO_DLL_RST_ADDR (SDIO_BASE + 0x148)
  274 +
  275 +#endif /* _COMPHY_A3700_H_ */
drivers/phy/marvell/comphy_core.c
Diff comments   View file @ 3335786
  1 +/*
  2 + * Copyright (C) 2015-2016 Marvell International Ltd.
  3 + *
  4 + * Copyright (C) 2016 Stefan Roese <sr@denx.de>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#include <common.h>
  10 +#include <dm.h>
  11 +#include <fdtdec.h>
  12 +#include <linux/errno.h>
  13 +#include <asm/io.h>
  14 +
  15 +#include "comphy.h"
  16 +
  17 +#define COMPHY_MAX_CHIP 4
  18 +
  19 +DECLARE_GLOBAL_DATA_PTR;
  20 +
  21 +static char *get_speed_string(u32 speed)
  22 +{
  23 + char *speed_strings[] = {"1.25 Gbps", "1.5 Gbps", "2.5 Gbps",
  24 + "3.0 Gbps", "3.125 Gbps", "5 Gbps", "6 Gbps",
  25 + "6.25 Gbps", "10.31 Gbps" };
  26 +
  27 + if (speed < 0 || speed > PHY_SPEED_MAX)
  28 + return "invalid";
  29 +
  30 + return speed_strings[speed];
  31 +}
  32 +
  33 +static char *get_type_string(u32 type)
  34 +{
  35 + char *type_strings[] = {"UNCONNECTED", "PEX0", "PEX1", "PEX2", "PEX3",
  36 + "SATA0", "SATA1", "SATA2", "SATA3", "SGMII0",
  37 + "SGMII1", "SGMII2", "SGMII3", "QSGMII",
  38 + "USB3_HOST0", "USB3_HOST1", "USB3_DEVICE",
  39 + "XAUI0", "XAUI1", "XAUI2", "XAUI3",
  40 + "RXAUI0", "RXAUI1", "KR"};
  41 +
  42 + if (type < 0 || type > PHY_TYPE_MAX)
  43 + return "invalid";
  44 +
  45 + return type_strings[type];
  46 +}
  47 +
  48 +void reg_set(void __iomem *addr, u32 data, u32 mask)
  49 +{
  50 + debug("Write to address = %#010lx, data = %#010x (mask = %#010x) - ",
  51 + (unsigned long)addr, data, mask);
  52 + debug("old value = %#010x ==> ", readl(addr));
  53 + reg_set_silent(addr, data, mask);
  54 + debug("new value %#010x\n", readl(addr));
  55 +}
  56 +
  57 +void reg_set_silent(void __iomem *addr, u32 data, u32 mask)
  58 +{
  59 + u32 reg_data;
  60 +
  61 + reg_data = readl(addr);
  62 + reg_data &= ~mask;
  63 + reg_data |= data;
  64 + writel(reg_data, addr);
  65 +}
  66 +
  67 +void reg_set16(void __iomem *addr, u16 data, u16 mask)
  68 +{
  69 + debug("Write to address = %#010lx, data = %#06x (mask = %#06x) - ",
  70 + (unsigned long)addr, data, mask);
  71 + debug("old value = %#06x ==> ", readw(addr));
  72 + reg_set_silent16(addr, data, mask);
  73 + debug("new value %#06x\n", readw(addr));
  74 +}
  75 +
  76 +void reg_set_silent16(void __iomem *addr, u16 data, u16 mask)
  77 +{
  78 + u16 reg_data;
  79 +
  80 + reg_data = readw(addr);
  81 + reg_data &= ~mask;
  82 + reg_data |= data;
  83 + writew(reg_data, addr);
  84 +}
  85 +
  86 +void comphy_print(struct chip_serdes_phy_config *chip_cfg,
  87 + struct comphy_map *comphy_map_data)
  88 +{
  89 + u32 lane;
  90 +
  91 + for (lane = 0; lane < chip_cfg->comphy_lanes_count;
  92 + lane++, comphy_map_data++) {
  93 + if (comphy_map_data->type == PHY_TYPE_UNCONNECTED)
  94 + continue;
  95 +
  96 + if (comphy_map_data->speed == PHY_SPEED_INVALID) {
  97 + printf("Comphy-%d: %-13s\n", lane,
  98 + get_type_string(comphy_map_data->type));
  99 + } else {
  100 + printf("Comphy-%d: %-13s %-10s\n", lane,
  101 + get_type_string(comphy_map_data->type),
  102 + get_speed_string(comphy_map_data->speed));
  103 + }
  104 + }
  105 +}
  106 +
  107 +static int comphy_probe(struct udevice *dev)
  108 +{
  109 + const void *blob = gd->fdt_blob;
  110 + int node = dev->of_offset;
  111 + struct chip_serdes_phy_config *chip_cfg = dev_get_priv(dev);
  112 + struct comphy_map comphy_map_data[MAX_LANE_OPTIONS];
  113 + int subnode;
  114 + int lane;
  115 +
  116 + /* Save base addresses for later use */
  117 + chip_cfg->comphy_base_addr = (void *)dev_get_addr_index(dev, 0);
  118 + if (IS_ERR(chip_cfg->comphy_base_addr))
  119 + return PTR_ERR(chip_cfg->comphy_base_addr);
  120 +
  121 + chip_cfg->hpipe3_base_addr = (void *)dev_get_addr_index(dev, 1);
  122 + if (IS_ERR(chip_cfg->hpipe3_base_addr))
  123 + return PTR_ERR(chip_cfg->hpipe3_base_addr);
  124 +
  125 + chip_cfg->comphy_lanes_count = fdtdec_get_int(blob, node,
  126 + "max-lanes", 0);
  127 + if (chip_cfg->comphy_lanes_count <= 0) {
  128 + dev_err(&dev->dev, "comphy max lanes is wrong\n");
  129 + return -EINVAL;
  130 + }
  131 +
  132 + chip_cfg->comphy_mux_bitcount = fdtdec_get_int(blob, node,
  133 + "mux-bitcount", 0);
  134 + if (chip_cfg->comphy_mux_bitcount <= 0) {
  135 + dev_err(&dev->dev, "comphy mux bit count is wrong\n");
  136 + return -EINVAL;
  137 + }
  138 +
  139 + if (of_device_is_compatible(dev, "marvell,comphy-armada-3700"))
  140 + chip_cfg->ptr_comphy_chip_init = comphy_a3700_init;
  141 +
  142 + /*
  143 + * Bail out if no chip_init function is defined, e.g. no
  144 + * compatible node is found
  145 + */
  146 + if (!chip_cfg->ptr_comphy_chip_init) {
  147 + dev_err(&dev->dev, "comphy: No compatible DT node found\n");
  148 + return -ENODEV;
  149 + }
  150 +
  151 + lane = 0;
  152 + fdt_for_each_subnode(blob, subnode, node) {
  153 + /* Skip disabled ports */
  154 + if (!fdtdec_get_is_enabled(blob, subnode))
  155 + continue;
  156 +
  157 + comphy_map_data[lane].speed = fdtdec_get_int(
  158 + blob, subnode, "phy-speed", PHY_TYPE_INVALID);
  159 + comphy_map_data[lane].type = fdtdec_get_int(
  160 + blob, subnode, "phy-type", PHY_SPEED_INVALID);
  161 + comphy_map_data[lane].invert = fdtdec_get_int(
  162 + blob, subnode, "phy-invert", PHY_POLARITY_NO_INVERT);
  163 + comphy_map_data[lane].clk_src = fdtdec_get_bool(blob, subnode,
  164 + "clk-src");
  165 + if (comphy_map_data[lane].type == PHY_TYPE_INVALID) {
  166 + printf("no phy type for lane %d, setting lane as unconnected\n",
  167 + lane + 1);
  168 + }
  169 +
  170 + lane++;
  171 + }
  172 +
  173 + /* Save comphy index for MultiCP devices (A8K) */
  174 + chip_cfg->comphy_index = dev->seq;
  175 + /* PHY power UP sequence */
  176 + chip_cfg->ptr_comphy_chip_init(chip_cfg, comphy_map_data);
  177 + /* PHY print SerDes status */
  178 + comphy_print(chip_cfg, comphy_map_data);
  179 +
  180 + /* Initialize dedicated PHYs (not muxed SerDes lanes) */
  181 + comphy_dedicated_phys_init();
  182 +
  183 + return 0;
  184 +}
  185 +
  186 +static const struct udevice_id comphy_ids[] = {
  187 + { .compatible = "marvell,mvebu-comphy" },
  188 + { }
  189 +};
  190 +
  191 +U_BOOT_DRIVER(mvebu_comphy) = {
  192 + .name = "mvebu_comphy",
  193 + .id = UCLASS_MISC,
  194 + .of_match = comphy_ids,
  195 + .probe = comphy_probe,
  196 + .priv_auto_alloc_size = sizeof(struct chip_serdes_phy_config),
  197 +};
drivers/phy/marvell/comphy_hpipe.h
Diff comments   View file @ 3335786
  1 +/*
  2 + * Copyright (C) 2015-2016 Marvell International Ltd.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef _COMPHY_HPIPE_H_
  8 +#define _COMPHY_HPIPE_H_
  9 +
  10 +/* SerDes IP register */
  11 +#define SD_EXTERNAL_CONFIG0_REG 0
  12 +#define SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET 1
  13 +#define SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK \
  14 + (1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET)
  15 +#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET 3
  16 +#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK \
  17 + (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET)
  18 +#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET 7
  19 +#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK \
  20 + (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET)
  21 +#define SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET 11
  22 +#define SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK \
  23 + (1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET)
  24 +#define SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET 12
  25 +#define SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK \
  26 + (1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET)
  27 +#define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET 14
  28 +#define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK \
  29 + (1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET)
  30 +#define SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET 15
  31 +#define SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK \
  32 + (0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET)
  33 +
  34 +#define SD_EXTERNAL_CONFIG1_REG 0x4
  35 +#define SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET 3
  36 +#define SD_EXTERNAL_CONFIG1_RESET_IN_MASK \
  37 + (0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET)
  38 +#define SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET 4
  39 +#define SD_EXTERNAL_CONFIG1_RX_INIT_MASK \
  40 + (0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET)
  41 +#define SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET 5
  42 +#define SD_EXTERNAL_CONFIG1_RESET_CORE_MASK \
  43 + (0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET)
  44 +#define SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET 6
  45 +#define SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK \
  46 + (0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET)
  47 +
  48 +#define SD_EXTERNAL_CONFIG2_REG 0x8
  49 +#define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET 4
  50 +#define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK \
  51 + (0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET)
  52 +
  53 +#define SD_EXTERNAL_STATUS0_REG 0x18
  54 +#define SD_EXTERNAL_STATUS0_PLL_TX_OFFSET 2
  55 +#define SD_EXTERNAL_STATUS0_PLL_TX_MASK \
  56 + (0x1 << SD_EXTERNAL_STATUS0_PLL_TX_OFFSET)
  57 +#define SD_EXTERNAL_STATUS0_PLL_RX_OFFSET 3
  58 +#define SD_EXTERNAL_STATUS0_PLL_RX_MASK \
  59 + (0x1 << SD_EXTERNAL_STATUS0_PLL_RX_OFFSET)
  60 +#define SD_EXTERNAL_STATUS0_RX_INIT_OFFSET 4
  61 +#define SD_EXTERNAL_STATUS0_RX_INIT_MASK \
  62 + (0x1 << SD_EXTERNAL_STATUS0_RX_INIT_OFFSET)
  63 +#define SD_EXTERNAL_STATUS0_RF_RESET_IN_OFFSET 6
  64 +#define SD_EXTERNAL_STATUS0_RF_RESET_IN_MASK \
  65 + (0x1 << SD_EXTERNAL_STATUS0_RF_RESET_IN_OFFSET)
  66 +
  67 +/* HPIPE register */
  68 +#define HPIPE_PWR_PLL_REG 0x4
  69 +#define HPIPE_PWR_PLL_REF_FREQ_OFFSET 0
  70 +#define HPIPE_PWR_PLL_REF_FREQ_MASK \
  71 + (0x1f << HPIPE_PWR_PLL_REF_FREQ_OFFSET)
  72 +#define HPIPE_PWR_PLL_PHY_MODE_OFFSET 5
  73 +#define HPIPE_PWR_PLL_PHY_MODE_MASK \
  74 + (0x7 << HPIPE_PWR_PLL_PHY_MODE_OFFSET)
  75 +
  76 +#define HPIPE_KVCO_CALIB_CTRL_REG 0x8
  77 +#define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET 12
  78 +#define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_MASK \
  79 + (0x1 << HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET)
  80 +
  81 +#define HPIPE_SQUELCH_FFE_SETTING_REG 0x018
  82 +
  83 +#define HPIPE_DFE_REG0 0x01C
  84 +#define HPIPE_DFE_RES_FORCE_OFFSET 15
  85 +#define HPIPE_DFE_RES_FORCE_MASK \
  86 + (0x1 << HPIPE_DFE_RES_FORCE_OFFSET)
  87 +
  88 +#define HPIPE_DFE_F3_F5_REG 0x028
  89 +#define HPIPE_DFE_F3_F5_DFE_EN_OFFSET 14
  90 +#define HPIPE_DFE_F3_F5_DFE_EN_MASK \
  91 + (0x1 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET)
  92 +#define HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET 15
  93 +#define HPIPE_DFE_F3_F5_DFE_CTRL_MASK \
  94 + (0x1 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET)
  95 +
  96 +#define HPIPE_G1_SET_0_REG 0x034
  97 +#define HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET 7
  98 +#define HPIPE_G1_SET_0_G1_TX_EMPH1_MASK \
  99 + (0xf << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET)
  100 +
  101 +#define HPIPE_G1_SET_1_REG 0x038
  102 +#define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET 0
  103 +#define HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK \
  104 + (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET)
  105 +#define HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET 3
  106 +#define HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK \
  107 + (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET)
  108 +#define HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET 10
  109 +#define HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK \
  110 + (0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET)
  111 +
  112 +#define HPIPE_G2_SETTINGS_1_REG 0x040
  113 +
  114 +#define HPIPE_G3_SETTINGS_1_REG 0x048
  115 +#define HPIPE_G3_RX_SELMUPI_OFFSET 0
  116 +#define HPIPE_G3_RX_SELMUPI_MASK \
  117 + (0x7 << HPIPE_G3_RX_SELMUPI_OFFSET)
  118 +#define HPIPE_G3_RX_SELMUPF_OFFSET 3
  119 +#define HPIPE_G3_RX_SELMUPF_MASK \
  120 + (0x7 << HPIPE_G3_RX_SELMUPF_OFFSET)
  121 +#define HPIPE_G3_SETTING_BIT_OFFSET 13
  122 +#define HPIPE_G3_SETTING_BIT_MASK \
  123 + (0x1 << HPIPE_G3_SETTING_BIT_OFFSET)
  124 +
  125 +#define HPIPE_LOOPBACK_REG 0x08c
  126 +#define HPIPE_LOOPBACK_SEL_OFFSET 1
  127 +#define HPIPE_LOOPBACK_SEL_MASK \
  128 + (0x7 << HPIPE_LOOPBACK_SEL_OFFSET)
  129 +
  130 +#define HPIPE_SYNC_PATTERN_REG 0x090
  131 +
  132 +#define HPIPE_INTERFACE_REG 0x94
  133 +#define HPIPE_INTERFACE_GEN_MAX_OFFSET 10
  134 +#define HPIPE_INTERFACE_GEN_MAX_MASK \
  135 + (0x3 << HPIPE_INTERFACE_GEN_MAX_OFFSET)
  136 +#define HPIPE_INTERFACE_LINK_TRAIN_OFFSET 14
  137 +#define HPIPE_INTERFACE_LINK_TRAIN_MASK \
  138 + (0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET)
  139 +
  140 +#define HPIPE_ISOLATE_MODE_REG 0x98
  141 +#define HPIPE_ISOLATE_MODE_GEN_RX_OFFSET 0
  142 +#define HPIPE_ISOLATE_MODE_GEN_RX_MASK \
  143 + (0xf << HPIPE_ISOLATE_MODE_GEN_RX_OFFSET)
  144 +#define HPIPE_ISOLATE_MODE_GEN_TX_OFFSET 4
  145 +#define HPIPE_ISOLATE_MODE_GEN_TX_MASK \
  146 + (0xf << HPIPE_ISOLATE_MODE_GEN_TX_OFFSET)
  147 +
  148 +#define HPIPE_VTHIMPCAL_CTRL_REG 0x104
  149 +
  150 +#define HPIPE_PCIE_REG0 0x120
  151 +#define HPIPE_PCIE_IDLE_SYNC_OFFSET 12
  152 +#define HPIPE_PCIE_IDLE_SYNC_MASK \
  153 + (0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET)
  154 +#define HPIPE_PCIE_SEL_BITS_OFFSET 13
  155 +#define HPIPE_PCIE_SEL_BITS_MASK \
  156 + (0x3 << HPIPE_PCIE_SEL_BITS_OFFSET)
  157 +
  158 +#define HPIPE_LANE_ALIGN_REG 0x124
  159 +#define HPIPE_LANE_ALIGN_OFF_OFFSET 12
  160 +#define HPIPE_LANE_ALIGN_OFF_MASK \
  161 + (0x1 << HPIPE_LANE_ALIGN_OFF_OFFSET)
  162 +
  163 +#define HPIPE_MISC_REG 0x13C
  164 +#define HPIPE_MISC_CLK100M_125M_OFFSET 4
  165 +#define HPIPE_MISC_CLK100M_125M_MASK \
  166 + (0x1 << HPIPE_MISC_CLK100M_125M_OFFSET)
  167 +#define HPIPE_MISC_TXDCLK_2X_OFFSET 6
  168 +#define HPIPE_MISC_TXDCLK_2X_MASK \
  169 + (0x1 << HPIPE_MISC_TXDCLK_2X_OFFSET)
  170 +#define HPIPE_MISC_CLK500_EN_OFFSET 7
  171 +#define HPIPE_MISC_CLK500_EN_MASK \
  172 + (0x1 << HPIPE_MISC_CLK500_EN_OFFSET)
  173 +#define HPIPE_MISC_REFCLK_SEL_OFFSET 10
  174 +#define HPIPE_MISC_REFCLK_SEL_MASK \
  175 + (0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET)
  176 +
  177 +#define HPIPE_RX_CONTROL_1_REG 0x140
  178 +#define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET 11
  179 +#define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK \
  180 + (0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET)
  181 +#define HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET 12
  182 +#define HPIPE_RX_CONTROL_1_CLK8T_EN_MASK \
  183 + (0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET)
  184 +
  185 +#define HPIPE_PWR_CTR_REG 0x148
  186 +#define HPIPE_PWR_CTR_RST_DFE_OFFSET 0
  187 +#define HPIPE_PWR_CTR_RST_DFE_MASK \
  188 + (0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET)
  189 +#define HPIPE_PWR_CTR_SFT_RST_OFFSET 10
  190 +#define HPIPE_PWR_CTR_SFT_RST_MASK \
  191 + (0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET)
  192 +
  193 +#define HPIPE_PLLINTP_REG1 0x150
  194 +
  195 +#define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG 0x16C
  196 +#define HPIPE_SMAPLER_OFFSET 12
  197 +#define HPIPE_SMAPLER_MASK \
  198 + (0x1 << HPIPE_SMAPLER_OFFSET)
  199 +
  200 +#define HPIPE_PWR_CTR_DTL_REG 0x184
  201 +#define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 2
  202 +#define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK \
  203 + (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET)
  204 +
  205 +#define HPIPE_RX_REG3 0x188
  206 +
  207 +#define HPIPE_TX_TRAIN_CTRL_0_REG 0x268
  208 +#define HPIPE_TX_TRAIN_P2P_HOLD_OFFSET 15
  209 +#define HPIPE_TX_TRAIN_P2P_HOLD_MASK \
  210 + (0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET)
  211 +
  212 +#define HPIPE_TX_TRAIN_CTRL_REG 0x26C
  213 +#define HPIPE_TX_TRAIN_CTRL_G1_OFFSET 0
  214 +#define HPIPE_TX_TRAIN_CTRL_G1_MASK \
  215 + (0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET)
  216 +#define HPIPE_TX_TRAIN_CTRL_GN1_OFFSET 1
  217 +#define HPIPE_TX_TRAIN_CTRL_GN1_MASK \
  218 + (0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET)
  219 +#define HPIPE_TX_TRAIN_CTRL_G0_OFFSET 2
  220 +#define HPIPE_TX_TRAIN_CTRL_G0_MASK \
  221 + (0x1 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET)
  222 +
  223 +#define HPIPE_TX_TRAIN_CTRL_4_REG 0x278
  224 +#define HPIPE_TRX_TRAIN_TIMER_OFFSET 0
  225 +#define HPIPE_TRX_TRAIN_TIMER_MASK \
  226 + (0x3FF << HPIPE_TRX_TRAIN_TIMER_OFFSET)
  227 +
  228 +#define HPIPE_PCIE_REG1 0x288
  229 +#define HPIPE_PCIE_REG3 0x290
  230 +
  231 +#define HPIPE_TX_TRAIN_CTRL_5_REG 0x2A4
  232 +#define HPIPE_TX_TRAIN_START_SQ_EN_OFFSET 11
  233 +#define HPIPE_TX_TRAIN_START_SQ_EN_MASK \
  234 + (0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET)
  235 +#define HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET 12
  236 +#define HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK \
  237 + (0x1 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET)
  238 +#define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET 13
  239 +#define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK \
  240 + (0x1 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET)
  241 +#define HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET 14
  242 +#define HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK \
  243 + (0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET)
  244 +
  245 +#define HPIPE_TX_TRAIN_REG 0x31C
  246 +#define HPIPE_TX_TRAIN_CHK_INIT_OFFSET 4
  247 +#define HPIPE_TX_TRAIN_CHK_INIT_MASK \
  248 + (0x1 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET)
  249 +#define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET 7
  250 +#define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK \
  251 + (0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET)
  252 +
  253 +#define HPIPE_TX_TRAIN_CTRL_11_REG 0x438
  254 +#define HPIPE_TX_STATUS_CHECK_MODE_OFFSET 6
  255 +#define HPIPE_TX_TX_STATUS_CHECK_MODE_MASK \
  256 + (0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET)
  257 +#define HPIPE_TX_NUM_OF_PRESET_OFFSET 10
  258 +#define HPIPE_TX_NUM_OF_PRESET_MASK \
  259 + (0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET)
  260 +#define HPIPE_TX_SWEEP_PRESET_EN_OFFSET 15
  261 +#define HPIPE_TX_SWEEP_PRESET_EN_MASK \
  262 + (0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET)
  263 +
  264 +#define HPIPE_G1_SETTINGS_3_REG 0x440
  265 +
  266 +#define HPIPE_G1_SETTINGS_4_REG 0x444
  267 +#define HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET 8
  268 +#define HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK \
  269 + (0x3 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET)
  270 +
  271 +#define HPIPE_G2_SETTINGS_3_REG 0x448
  272 +#define HPIPE_G2_SETTINGS_4_REG 0x44C
  273 +
  274 +#define HPIPE_G3_SETTING_3_REG 0x450
  275 +#define HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET 12
  276 +#define HPIPE_G3_FFE_DEG_RES_LEVEL_MASK \
  277 + (0x3 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET)
  278 +#define HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET 14
  279 +#define HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK \
  280 + (0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET)
  281 +
  282 +#define HPIPE_G3_SETTING_4_REG 0x454
  283 +#define HPIPE_G3_DFE_RES_OFFSET 8
  284 +#define HPIPE_G3_DFE_RES_MASK \
  285 + (0x3 << HPIPE_G3_DFE_RES_OFFSET)
  286 +
  287 +#define HPIPE_DFE_CTRL_28_REG 0x49C
  288 +#define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7
  289 +#define HPIPE_DFE_CTRL_28_PIPE4_MASK \
  290 + (0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET)
  291 +
  292 +#define HPIPE_LANE_CONFIG0_REG 0x600
  293 +#define HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET 0
  294 +#define HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK \
  295 + (0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET)
  296 +
  297 +#define HPIPE_LANE_CONFIG1_REG 0x604
  298 +#define HPIPE_LANE_CONFIG1_MAX_PLL_OFFSET 9
  299 +#define HPIPE_LANE_CONFIG1_MAX_PLL_MASK \
  300 + (0x1 << HPIPE_LANE_CONFIG1_MAX_PLL_OFFSET)
  301 +#define HPIPE_LANE_CONFIG1_GEN2_PLL_OFFSET 10
  302 +#define HPIPE_LANE_CONFIG1_GEN2_PLL_MASK \
  303 + (0x1 << HPIPE_LANE_CONFIG1_GEN2_PLL_OFFSET)
  304 +
  305 +#define HPIPE_LANE_STATUS1_REG 0x60C
  306 +#define HPIPE_LANE_STATUS1_PCLK_EN_OFFSET 0
  307 +#define HPIPE_LANE_STATUS1_PCLK_EN_MASK \
  308 + (0x1 << HPIPE_LANE_STATUS1_PCLK_EN_OFFSET)
  309 +
  310 +#define HPIPE_LANE_CFG4_REG 0x620
  311 +#define HPIPE_LANE_CFG4_DFE_CTRL_OFFSET 0
  312 +#define HPIPE_LANE_CFG4_DFE_CTRL_MASK \
  313 + (0x7 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET)
  314 +#define HPIPE_LANE_CFG4_DFE_OVER_OFFSET 6
  315 +#define HPIPE_LANE_CFG4_DFE_OVER_MASK \
  316 + (0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET)
  317 +#define HPIPE_LANE_CFG4_SSC_CTRL_OFFSET 7
  318 +#define HPIPE_LANE_CFG4_SSC_CTRL_MASK \
  319 + (0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET)
  320 +
  321 +#define HPIPE_LANE_EQU_CONFIG_0_REG 0x69C
  322 +#define HPIPE_CFG_PHY_RC_EP_OFFSET 12
  323 +#define HPIPE_CFG_PHY_RC_EP_MASK \
  324 + (0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET)
  325 +
  326 +#define HPIPE_LANE_EQ_CFG1_REG 0x6a0
  327 +#define HPIPE_CFG_UPDATE_POLARITY_OFFSET 12
  328 +#define HPIPE_CFG_UPDATE_POLARITY_MASK \
  329 + (0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET)
  330 +
  331 +#define HPIPE_RST_CLK_CTRL_REG 0x704
  332 +#define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET 0
  333 +#define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK \
  334 + (0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET)
  335 +#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET 2
  336 +#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK \
  337 + (0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET)
  338 +#define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET 3
  339 +#define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK \
  340 + (0x1 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET)
  341 +#define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET 9
  342 +#define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK \
  343 + (0x1 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET)
  344 +
  345 +#define HPIPE_TST_MODE_CTRL_REG 0x708
  346 +#define HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET 2
  347 +#define HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK \
  348 + (0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET)
  349 +
  350 +#define HPIPE_CLK_SRC_LO_REG 0x70c
  351 +#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET 1
  352 +#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK \
  353 + (0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET)
  354 +#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET 2
  355 +#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK \
  356 + (0x3 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET)
  357 +#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET 5
  358 +#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK \
  359 + (0x7 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET)
  360 +
  361 +#define HPIPE_CLK_SRC_HI_REG 0x710
  362 +#define HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET 0
  363 +#define HPIPE_CLK_SRC_HI_LANE_STRT_MASK \
  364 + (0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET)
  365 +#define HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET 1
  366 +#define HPIPE_CLK_SRC_HI_LANE_BREAK_MASK \
  367 + (0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET)
  368 +#define HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET 2
  369 +#define HPIPE_CLK_SRC_HI_LANE_MASTER_MASK \
  370 + (0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET)
  371 +#define HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET 7
  372 +#define HPIPE_CLK_SRC_HI_MODE_PIPE_MASK \
  373 + (0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET)
  374 +
  375 +#define HPIPE_GLOBAL_MISC_CTRL 0x718
  376 +#define HPIPE_GLOBAL_PM_CTRL 0x740
  377 +#define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET 0
  378 +#define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK \
  379 + (0xFF << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET)
  380 +
  381 +#endif /* _COMPHY_HPIPE_H_ */
drivers/phy/marvell/comphy_mux.c
Diff comments   View file @ 3335786
  1 +/*
  2 + * Copyright (C) 2015-2016 Marvell International Ltd.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <asm/io.h>
  9 +
  10 +#include "comphy.h"
  11 +#include "comphy_hpipe.h"
  12 +
  13 +/*
  14 + * comphy_mux_check_config()
  15 + * description: this function passes over the COMPHY lanes and check if the type
  16 + * is valid for specific lane. If the type is not valid,
  17 + * the function update the struct and set the type of the lane as
  18 + * PHY_TYPE_UNCONNECTED
  19 + */
  20 +static void comphy_mux_check_config(struct comphy_mux_data *mux_data,
  21 + struct comphy_map *comphy_map_data, int comphy_max_lanes)
  22 +{
  23 + struct comphy_mux_options *mux_opt;
  24 + int lane, opt, valid;
  25 +
  26 + debug_enter();
  27 +
  28 + for (lane = 0; lane < comphy_max_lanes;
  29 + lane++, comphy_map_data++, mux_data++) {
  30 + mux_opt = mux_data->mux_values;
  31 + for (opt = 0, valid = 0; opt < mux_data->max_lane_values;
  32 + opt++, mux_opt++) {
  33 + if (mux_opt->type == comphy_map_data->type) {
  34 + valid = 1;
  35 + break;
  36 + }
  37 + }
  38 + if (valid == 0) {
  39 + debug("lane number %d, had invalid type %d\n",
  40 + lane, comphy_map_data->type);
  41 + debug("set lane %d as type %d\n", lane,
  42 + PHY_TYPE_UNCONNECTED);
  43 + comphy_map_data->type = PHY_TYPE_UNCONNECTED;
  44 + } else {
  45 + debug("lane number %d, has type %d\n",
  46 + lane, comphy_map_data->type);
  47 + }
  48 + }
  49 +
  50 + debug_exit();
  51 +}
  52 +
  53 +static u32 comphy_mux_get_mux_value(struct comphy_mux_data *mux_data,
  54 + u32 type, int lane)
  55 +{
  56 + struct comphy_mux_options *mux_opt;
  57 + int opt;
  58 + u32 value = 0;
  59 +
  60 + debug_enter();
  61 +
  62 + mux_opt = mux_data->mux_values;
  63 + for (opt = 0 ; opt < mux_data->max_lane_values; opt++, mux_opt++) {
  64 + if (mux_opt->type == type) {
  65 + value = mux_opt->mux_value;
  66 + break;
  67 + }
  68 + }
  69 +
  70 + debug_exit();
  71 +
  72 + return value;
  73 +}
  74 +
  75 +static void comphy_mux_reg_write(struct comphy_mux_data *mux_data,
  76 + struct comphy_map *comphy_map_data,
  77 + int comphy_max_lanes,
  78 + void __iomem *selector_base, u32 bitcount)
  79 +{
  80 + u32 lane, value, offset, mask;
  81 +
  82 + debug_enter();
  83 +
  84 + for (lane = 0; lane < comphy_max_lanes;
  85 + lane++, comphy_map_data++, mux_data++) {
  86 + offset = lane * bitcount;
  87 + mask = (((1 << bitcount) - 1) << offset);
  88 + value = (comphy_mux_get_mux_value(mux_data,
  89 + comphy_map_data->type,
  90 + lane) << offset);
  91 + reg_set(selector_base, value, mask);
  92 + }
  93 +
  94 + debug_exit();
  95 +}
  96 +
  97 +void comphy_mux_init(struct chip_serdes_phy_config *chip_cfg,
  98 + struct comphy_map *comphy_map_data,
  99 + void __iomem *selector_base)
  100 +{
  101 + struct comphy_mux_data *mux_data;
  102 + u32 mux_bitcount;
  103 + u32 comphy_max_lanes;
  104 +
  105 + debug_enter();
  106 +
  107 + comphy_max_lanes = chip_cfg->comphy_lanes_count;
  108 + mux_data = chip_cfg->mux_data;
  109 + mux_bitcount = chip_cfg->comphy_mux_bitcount;
  110 +
  111 + /* check if the configuration is valid */
  112 + comphy_mux_check_config(mux_data, comphy_map_data, comphy_max_lanes);
  113 + /* Init COMPHY selectors */
  114 + comphy_mux_reg_write(mux_data, comphy_map_data, comphy_max_lanes,
  115 + selector_base, mux_bitcount);
  116 +
  117 + debug_exit();
  118 +}
include/dt-bindings/comphy/comphy_data.h
Diff comments   View file @ 3335786
  1 +/*
  2 + * Copyright (C) 2015-2016 Marvell International Ltd.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef _COMPHY_DATA_H_
  8 +#define _COMPHY_DATA_H_
  9 +
  10 +#define PHY_SPEED_1_25G 0
  11 +#define PHY_SPEED_1_5G 1
  12 +#define PHY_SPEED_2_5G 2
  13 +#define PHY_SPEED_3G 3
  14 +#define PHY_SPEED_3_125G 4
  15 +#define PHY_SPEED_5G 5
  16 +#define PHY_SPEED_6G 6
  17 +#define PHY_SPEED_6_25G 7
  18 +#define PHY_SPEED_10_3125G 8
  19 +#define PHY_SPEED_MAX 9
  20 +#define PHY_SPEED_INVALID 0xff
  21 +
  22 +#define PHY_TYPE_UNCONNECTED 0
  23 +#define PHY_TYPE_PEX0 1
  24 +#define PHY_TYPE_PEX1 2
  25 +#define PHY_TYPE_PEX2 3
  26 +#define PHY_TYPE_PEX3 4
  27 +#define PHY_TYPE_SATA0 5
  28 +#define PHY_TYPE_SATA1 6
  29 +#define PHY_TYPE_SATA2 7
  30 +#define PHY_TYPE_SATA3 8
  31 +#define PHY_TYPE_SGMII0 9
  32 +#define PHY_TYPE_SGMII1 10
  33 +#define PHY_TYPE_SGMII2 11
  34 +#define PHY_TYPE_SGMII3 12
  35 +#define PHY_TYPE_QSGMII 13
  36 +#define PHY_TYPE_USB3_HOST0 14
  37 +#define PHY_TYPE_USB3_HOST1 15
  38 +#define PHY_TYPE_USB3_DEVICE 16
  39 +#define PHY_TYPE_XAUI0 17
  40 +#define PHY_TYPE_XAUI1 18
  41 +#define PHY_TYPE_XAUI2 19
  42 +#define PHY_TYPE_XAUI3 20
  43 +#define PHY_TYPE_RXAUI0 21
  44 +#define PHY_TYPE_RXAUI1 22
  45 +#define PHY_TYPE_KR 23
  46 +#define PHY_TYPE_MAX 24
  47 +#define PHY_TYPE_INVALID 0xff
  48 +
  49 +#define PHY_POLARITY_NO_INVERT 0
  50 +#define PHY_POLARITY_TXD_INVERT 1
  51 +#define PHY_POLARITY_RXD_INVERT 2
  52 +#define PHY_POLARITY_ALL_INVERT \
  53 + (PHY_POLARITY_TXD_INVERT | PHY_POLARITY_RXD_INVERT)
  54 +
  55 +#define UTMI_PHY_TO_USB_HOST0 0
  56 +#define UTMI_PHY_TO_USB_HOST1 1
  57 +#define UTMI_PHY_TO_USB_DEVICE0 2
  58 +#define UTMI_PHY_INVALID 0xff
  59 +
  60 +#endif /* _COMPHY_DATA_H_ */