Eric Lee / smarc-uboot

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Commit 335f7b1290ce24a729a9689a1db834c743226ca8

Authored by Tom Rini
2 parents 48f0e6bb37 316f0d0f8f
Exists in smarc_8mq_lf_v2020.04 and in 20 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf-6.6.52-2.2.0, emb_lf_v2022.04, emb_lf_v2023.04, emb_lf_v2024.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

Merge git://git.denx.de/u-boot-mpc85xx

Showing 24 changed files Side-by-side Diff

board/Arcturus/ucp1020/tlb.c
Diff comments   View file @ 335f7b1
... ... @@ -79,7 +79,7 @@
79 79 (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
80 80 /* *I*G - eSDHC/eSPI/NAND boot */
81 81 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
82   - MAS3_SX | MAS3_SW | MAS3_SR, 0,
  82 + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_M,
83 83 0, 8, BOOKE_PAGESZ_1G, 1),
84 84  
85 85 #endif /* RAMBOOT/SPL */
board/freescale/b4860qds/tlb.c
Diff comments   View file @ 335f7b1
... ... @@ -147,7 +147,7 @@
147 147  
148 148 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
149 149 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
150   - MAS3_SX|MAS3_SW|MAS3_SR, 0,
  150 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
151 151 0, 17, BOOKE_PAGESZ_2G, 1)
152 152 #endif
153 153 };
board/freescale/bsc9131rdb/tlb.c
Diff comments   View file @ 335f7b1
... ... @@ -49,7 +49,7 @@
49 49  
50 50 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
51 51 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
52   - MAS3_SX|MAS3_SW|MAS3_SR, 0,
  52 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
53 53 0, 8, BOOKE_PAGESZ_1G, 1),
54 54 #endif
55 55  
board/freescale/bsc9132qds/tlb.c
Diff comments   View file @ 335f7b1
... ... @@ -71,7 +71,7 @@
71 71  
72 72 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
73 73 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
74   - MAS3_SX|MAS3_SW|MAS3_SR, 0,
  74 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
75 75 0, 8, BOOKE_PAGESZ_1G, 1),
76 76 #endif
77 77  
board/freescale/c29xpcie/tlb.c
Diff comments   View file @ 335f7b1
... ... @@ -67,11 +67,11 @@
67 67 (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
68 68 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
69 69 CONFIG_SYS_DDR_SDRAM_BASE,
70   - MAS3_SX|MAS3_SW|MAS3_SR, 0,
  70 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
71 71 0, 8, BOOKE_PAGESZ_256M, 1),
72 72 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
73 73 CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
74   - MAS3_SX|MAS3_SW|MAS3_SR, 0,
  74 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
75 75 0, 9, BOOKE_PAGESZ_256M, 1),
76 76 #endif
77 77  
board/freescale/mpc8541cds/tlb.c
Diff comments   View file @ 335f7b1
... ... @@ -81,7 +81,7 @@
81 81 * 0xf000_0000 64M LBC SDRAM
82 82 */
83 83 SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
84   - MAS3_SX|MAS3_SW|MAS3_SR, 0,
  84 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
85 85 0, 6, BOOKE_PAGESZ_64M, 1),
86 86  
87 87 /*
board/freescale/mpc8548cds/tlb.c
Diff comments   View file @ 335f7b1
... ... @@ -48,7 +48,7 @@
48 48 */
49 49 SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE,
50 50 CONFIG_SYS_LBC_SDRAM_BASE_PHYS,
51   - MAS3_SX|MAS3_SW|MAS3_SR, 0,
  51 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
52 52 0, 2, BOOKE_PAGESZ_64M, 1),
53 53  
54 54 /*
board/freescale/mpc8568mds/tlb.c
Diff comments   View file @ 335f7b1
... ... @@ -67,7 +67,7 @@
67 67 * 0xf000_0000 64M LBC SDRAM
68 68 */
69 69 SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
70   - MAS3_SX|MAS3_SW|MAS3_SR, 0,
  70 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
71 71 0, 4, BOOKE_PAGESZ_64M, 1),
72 72  
73 73 /*
board/freescale/p1010rdb/tlb.c
Diff comments   View file @ 335f7b1
... ... @@ -76,7 +76,7 @@
76 76 #if defined(CONFIG_SYS_RAMBOOT) || \
77 77 (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
78 78 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
79   - MAS3_SX|MAS3_SW|MAS3_SR, 0,
  79 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
80 80 0, 8, BOOKE_PAGESZ_1G, 1),
81 81 #endif
82 82  
board/freescale/p1022ds/tlb.c
Diff comments   View file @ 335f7b1
... ... @@ -75,12 +75,12 @@
75 75 (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
76 76 /* **** - eSDHC/eSPI/NAND boot */
77 77 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
78   - MAS3_SX|MAS3_SW|MAS3_SR, 0,
  78 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
79 79 0, 8, BOOKE_PAGESZ_1G, 1),
80 80 /* **** - eSDHC/eSPI/NAND boot - second 1GB of memory */
81 81 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
82 82 CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
83   - MAS3_SX|MAS3_SW|MAS3_SR, 0,
  83 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
84 84 0, 9, BOOKE_PAGESZ_1G, 1),
85 85 #endif
86 86  
board/freescale/p1023rdb/tlb.c
Diff comments   View file @ 335f7b1
... ... @@ -86,12 +86,12 @@
86 86 #ifdef CONFIG_SYS_RAMBOOT
87 87 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
88 88 CONFIG_SYS_DDR_SDRAM_BASE,
89   - MAS3_SX|MAS3_SW|MAS3_SR, 0,
  89 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
90 90 0, 12, BOOKE_PAGESZ_256M, 1),
91 91  
92 92 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
93 93 CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
94   - MAS3_SX|MAS3_SW|MAS3_SR, 0,
  94 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
95 95 0, 13, BOOKE_PAGESZ_256M, 1),
96 96 #endif
97 97 };
board/freescale/p1_p2_rdb_pc/tlb.c
Diff comments   View file @ 335f7b1
... ... @@ -82,7 +82,7 @@
82 82 (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
83 83 /* *I*G - eSDHC/eSPI/NAND boot */
84 84 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
85   - MAS3_SX|MAS3_SW|MAS3_SR, 0,
  85 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
86 86 0, 8, BOOKE_PAGESZ_1G, 1),
87 87  
88 88 #if defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)
board/freescale/p1_twr/tlb.c
Diff comments   View file @ 335f7b1
... ... @@ -67,7 +67,7 @@
67 67 #ifdef CONFIG_SYS_RAMBOOT
68 68 /* *I*G - eSDHC boot */
69 69 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
70   - MAS3_SX|MAS3_SW|MAS3_SR, 0,
  70 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
71 71 0, 8, BOOKE_PAGESZ_1G, 1),
72 72 #endif
73 73  
board/freescale/t102xqds/tlb.c
Diff comments   View file @ 335f7b1
... ... @@ -102,11 +102,11 @@
102 102  
103 103 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
104 104 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
105   - MAS3_SX|MAS3_SW|MAS3_SR, 0,
  105 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
106 106 0, 12, BOOKE_PAGESZ_1G, 1),
107 107 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
108 108 CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
109   - MAS3_SX|MAS3_SW|MAS3_SR, 0,
  109 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
110 110 0, 13, BOOKE_PAGESZ_1G, 1)
111 111 #endif
112 112 /* entry 14 and 15 has been used hard coded, they will be disabled
board/freescale/t102xrdb/tlb.c
Diff comments   View file @ 335f7b1
... ... @@ -102,11 +102,11 @@
102 102  
103 103 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
104 104 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
105   - MAS3_SX|MAS3_SW|MAS3_SR, 0,
  105 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
106 106 0, 12, BOOKE_PAGESZ_1G, 1),
107 107 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
108 108 CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
109   - MAS3_SX|MAS3_SW|MAS3_SR, 0,
  109 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
110 110 0, 13, BOOKE_PAGESZ_1G, 1)
111 111 #endif
112 112 /* entry 14 and 15 has been used hard coded, they will be disabled
board/freescale/t104xrdb/tlb.c
Diff comments   View file @ 335f7b1
... ... @@ -120,11 +120,11 @@
120 120  
121 121 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
122 122 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
123   - MAS3_SX|MAS3_SW|MAS3_SR, 0,
  123 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
124 124 0, 12, BOOKE_PAGESZ_1G, 1),
125 125 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
126 126 CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
127   - MAS3_SX|MAS3_SW|MAS3_SR, 0,
  127 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
128 128 0, 13, BOOKE_PAGESZ_1G, 1)
129 129 #endif
130 130 };
board/freescale/t208xqds/tlb.c
Diff comments   View file @ 335f7b1
... ... @@ -145,7 +145,7 @@
145 145  
146 146 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
147 147 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
148   - MAS3_SX|MAS3_SW|MAS3_SR, 0,
  148 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
149 149 0, 19, BOOKE_PAGESZ_2G, 1)
150 150 #endif
151 151 };
board/freescale/t208xrdb/tlb.c
Diff comments   View file @ 335f7b1
... ... @@ -144,7 +144,7 @@
144 144 #endif
145 145 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
146 146 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
147   - MAS3_SX|MAS3_SW|MAS3_SR, 0,
  147 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
148 148 0, 19, BOOKE_PAGESZ_2G, 1)
149 149 #endif
150 150  
board/freescale/t4qds/tlb.c
Diff comments   View file @ 335f7b1
... ... @@ -139,7 +139,7 @@
139 139  
140 140 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
141 141 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
142   - MAS3_SX|MAS3_SW|MAS3_SR, 0,
  142 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
143 143 0, 19, BOOKE_PAGESZ_2G, 1)
144 144 #endif
145 145 };
board/freescale/t4rdb/tlb.c
Diff comments   View file @ 335f7b1
... ... @@ -116,7 +116,7 @@
116 116 #endif
117 117 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
118 118 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
119   - MAS3_SX|MAS3_SW|MAS3_SR, 0,
  119 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
120 120 0, 18, BOOKE_PAGESZ_2G, 1)
121 121 #endif
122 122 };
board/gdsys/p1022/tlb.c
Diff comments   View file @ 335f7b1
... ... @@ -65,7 +65,7 @@
65 65  
66 66 #ifdef CONFIG_SYS_RAMBOOT
67 67 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
68   - MAS3_SX|MAS3_SW|MAS3_SR, 0,
  68 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
69 69 0, 6, BOOKE_PAGESZ_1G, 1),
70 70 #endif
71 71 #endif
... ... @@ -66,7 +66,7 @@
66 66 * 0xf0000000 64M LBC SDRAM First half
67 67 */
68 68 SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
69   - MAS3_SX|MAS3_SW|MAS3_SR, 0,
  69 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
70 70 0, 3, BOOKE_PAGESZ_64M, 1),
71 71  
72 72 /*
... ... @@ -75,7 +75,7 @@
75 75 */
76 76 SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
77 77 CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
78   - MAS3_SX|MAS3_SW|MAS3_SR, 0,
  78 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
79 79 0, 4, BOOKE_PAGESZ_64M, 1),
80 80 #endif
81 81  
include/configs/T104xRDB.h
Diff comments   View file @ 335f7b1
... ... @@ -634,6 +634,7 @@
634 634 #ifdef CONFIG_USB_EHCI_HCD
635 635 #define CONFIG_USB_EHCI_FSL
636 636 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  637 +#define CONFIG_EHCI_DESC_BIG_ENDIAN
637 638 #endif
638 639 #endif
639 640  
include/configs/p1_p2_rdb_pc.h
Diff comments   View file @ 335f7b1
... ... @@ -782,6 +782,7 @@
782 782 #ifdef CONFIG_USB_EHCI_HCD
783 783 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
784 784 #define CONFIG_USB_EHCI_FSL
  785 +#define CONFIG_EHCI_DESC_BIG_ENDIAN
785 786 #endif
786 787 #endif
787 788