Eric Lee / smarc-uboot

Download as
Browse Code »

Commit 33a999590869bb33d0f4e2b27b2270f6e12c9953

Authored by Álvaro Fernández Rojas
Committed by Daniel Schwierzeck
1 parent 6ffc18cd04
Exists in smarc_8mq_lf_v2020.04 and in 17 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

dm: cpu: bmips: add BCM6348 support 

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

Showing 1 changed file with 34 additions and 0 deletions Inline Diff

drivers/cpu/bmips_cpu.c
Diff comments   View file @ 33a9995
1 /* 1 /*
2 * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> 2 * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
3 * 3 *
4 * Derived from linux/arch/mips/bcm63xx/cpu.c: 4 * Derived from linux/arch/mips/bcm63xx/cpu.c:
5 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> 5 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
6 * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org> 6 * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
7 * 7 *
8 * SPDX-License-Identifier: GPL-2.0+ 8 * SPDX-License-Identifier: GPL-2.0+
9 */ 9 */
10 10
11 #include <common.h> 11 #include <common.h>
12 #include <cpu.h> 12 #include <cpu.h>
13 #include <dm.h> 13 #include <dm.h>
14 #include <errno.h> 14 #include <errno.h>
15 #include <asm/io.h> 15 #include <asm/io.h>
16 16
17 DECLARE_GLOBAL_DATA_PTR; 17 DECLARE_GLOBAL_DATA_PTR;
18 18
19 #define REV_CHIPID_SHIFT 16 19 #define REV_CHIPID_SHIFT 16
20 #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT) 20 #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT)
21 #define REV_LONG_CHIPID_SHIFT 12 21 #define REV_LONG_CHIPID_SHIFT 12
22 #define REV_LONG_CHIPID_MASK (0xfffff << REV_LONG_CHIPID_SHIFT) 22 #define REV_LONG_CHIPID_MASK (0xfffff << REV_LONG_CHIPID_SHIFT)
23 #define REV_REVID_SHIFT 0 23 #define REV_REVID_SHIFT 0
24 #define REV_REVID_MASK (0xff << REV_REVID_SHIFT) 24 #define REV_REVID_MASK (0xff << REV_REVID_SHIFT)
25 25
26 #define REG_BCM6328_OTP 0x62c 26 #define REG_BCM6328_OTP 0x62c
27 #define BCM6328_TP1_DISABLED BIT(9) 27 #define BCM6328_TP1_DISABLED BIT(9)
28 28
29 #define REG_BCM6328_MISC_STRAPBUS 0x1a40 29 #define REG_BCM6328_MISC_STRAPBUS 0x1a40
30 #define STRAPBUS_6328_FCVO_SHIFT 7 30 #define STRAPBUS_6328_FCVO_SHIFT 7
31 #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT) 31 #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
32 32
33 #define REG_BCM6348_PERF_MIPSPLLCFG 0x34
34 #define MIPSPLLCFG_6348_M1CPU_SHIFT 6
35 #define MIPSPLLCFG_6348_M1CPU_MASK (0x7 << MIPSPLLCFG_6348_M1CPU_SHIFT)
36 #define MIPSPLLCFG_6348_N2_SHIFT 15
37 #define MIPSPLLCFG_6348_N2_MASK (0x1F << MIPSPLLCFG_6348_N2_SHIFT)
38 #define MIPSPLLCFG_6348_N1_SHIFT 20
39 #define MIPSPLLCFG_6348_N1_MASK (0x7 << MIPSPLLCFG_6348_N1_SHIFT)
40
33 #define REG_BCM6358_DDR_DMIPSPLLCFG 0x12b8 41 #define REG_BCM6358_DDR_DMIPSPLLCFG 0x12b8
34 #define DMIPSPLLCFG_6358_M1_SHIFT 0 42 #define DMIPSPLLCFG_6358_M1_SHIFT 0
35 #define DMIPSPLLCFG_6358_M1_MASK (0xff << DMIPSPLLCFG_6358_M1_SHIFT) 43 #define DMIPSPLLCFG_6358_M1_MASK (0xff << DMIPSPLLCFG_6358_M1_SHIFT)
36 #define DMIPSPLLCFG_6358_N1_SHIFT 23 44 #define DMIPSPLLCFG_6358_N1_SHIFT 23
37 #define DMIPSPLLCFG_6358_N1_MASK (0x3f << DMIPSPLLCFG_6358_N1_SHIFT) 45 #define DMIPSPLLCFG_6358_N1_MASK (0x3f << DMIPSPLLCFG_6358_N1_SHIFT)
38 #define DMIPSPLLCFG_6358_N2_SHIFT 29 46 #define DMIPSPLLCFG_6358_N2_SHIFT 29
39 #define DMIPSPLLCFG_6358_N2_MASK (0x7 << DMIPSPLLCFG_6358_N2_SHIFT) 47 #define DMIPSPLLCFG_6358_N2_MASK (0x7 << DMIPSPLLCFG_6358_N2_SHIFT)
40 48
41 #define REG_BCM63268_MISC_STRAPBUS 0x1814 49 #define REG_BCM63268_MISC_STRAPBUS 0x1814
42 #define STRAPBUS_63268_FCVO_SHIFT 21 50 #define STRAPBUS_63268_FCVO_SHIFT 21
43 #define STRAPBUS_63268_FCVO_MASK (0xf << STRAPBUS_63268_FCVO_SHIFT) 51 #define STRAPBUS_63268_FCVO_MASK (0xf << STRAPBUS_63268_FCVO_SHIFT)
44 52
45 struct bmips_cpu_priv; 53 struct bmips_cpu_priv;
46 54
47 struct bmips_cpu_hw { 55 struct bmips_cpu_hw {
48 int (*get_cpu_desc)(struct bmips_cpu_priv *priv, char *buf, int size); 56 int (*get_cpu_desc)(struct bmips_cpu_priv *priv, char *buf, int size);
49 ulong (*get_cpu_freq)(struct bmips_cpu_priv *); 57 ulong (*get_cpu_freq)(struct bmips_cpu_priv *);
50 int (*get_cpu_count)(struct bmips_cpu_priv *); 58 int (*get_cpu_count)(struct bmips_cpu_priv *);
51 }; 59 };
52 60
53 struct bmips_cpu_priv { 61 struct bmips_cpu_priv {
54 void __iomem *regs; 62 void __iomem *regs;
55 const struct bmips_cpu_hw *hw; 63 const struct bmips_cpu_hw *hw;
56 }; 64 };
57 65
58 /* Specific CPU Ops */ 66 /* Specific CPU Ops */
59 static int bmips_short_cpu_desc(struct bmips_cpu_priv *priv, char *buf, 67 static int bmips_short_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
60 int size) 68 int size)
61 { 69 {
62 unsigned short cpu_id; 70 unsigned short cpu_id;
63 unsigned char cpu_rev; 71 unsigned char cpu_rev;
64 u32 val; 72 u32 val;
65 73
66 val = readl_be(priv->regs); 74 val = readl_be(priv->regs);
67 cpu_id = (val & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT; 75 cpu_id = (val & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
68 cpu_rev = (val & REV_REVID_MASK) >> REV_REVID_SHIFT; 76 cpu_rev = (val & REV_REVID_MASK) >> REV_REVID_SHIFT;
69 77
70 snprintf(buf, size, "BCM%04X%02X", cpu_id, cpu_rev); 78 snprintf(buf, size, "BCM%04X%02X", cpu_id, cpu_rev);
71 79
72 return 0; 80 return 0;
73 } 81 }
74 82
75 static int bmips_long_cpu_desc(struct bmips_cpu_priv *priv, char *buf, 83 static int bmips_long_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
76 int size) 84 int size)
77 { 85 {
78 unsigned int cpu_id; 86 unsigned int cpu_id;
79 unsigned char cpu_rev; 87 unsigned char cpu_rev;
80 u32 val; 88 u32 val;
81 89
82 val = readl_be(priv->regs); 90 val = readl_be(priv->regs);
83 cpu_id = (val & REV_LONG_CHIPID_MASK) >> REV_LONG_CHIPID_SHIFT; 91 cpu_id = (val & REV_LONG_CHIPID_MASK) >> REV_LONG_CHIPID_SHIFT;
84 cpu_rev = (val & REV_REVID_MASK) >> REV_REVID_SHIFT; 92 cpu_rev = (val & REV_REVID_MASK) >> REV_REVID_SHIFT;
85 93
86 snprintf(buf, size, "BCM%05X%02X", cpu_id, cpu_rev); 94 snprintf(buf, size, "BCM%05X%02X", cpu_id, cpu_rev);
87 95
88 return 0; 96 return 0;
89 } 97 }
90 98
91 static ulong bcm6328_get_cpu_freq(struct bmips_cpu_priv *priv) 99 static ulong bcm6328_get_cpu_freq(struct bmips_cpu_priv *priv)
92 { 100 {
93 unsigned int mips_pll_fcvo; 101 unsigned int mips_pll_fcvo;
94 102
95 mips_pll_fcvo = readl_be(priv->regs + REG_BCM6328_MISC_STRAPBUS); 103 mips_pll_fcvo = readl_be(priv->regs + REG_BCM6328_MISC_STRAPBUS);
96 mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_6328_FCVO_MASK) 104 mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_6328_FCVO_MASK)
97 >> STRAPBUS_6328_FCVO_SHIFT; 105 >> STRAPBUS_6328_FCVO_SHIFT;
98 106
99 switch (mips_pll_fcvo) { 107 switch (mips_pll_fcvo) {
100 case 0x12: 108 case 0x12:
101 case 0x14: 109 case 0x14:
102 case 0x19: 110 case 0x19:
103 return 160000000; 111 return 160000000;
104 case 0x1c: 112 case 0x1c:
105 return 192000000; 113 return 192000000;
106 case 0x13: 114 case 0x13:
107 case 0x15: 115 case 0x15:
108 return 200000000; 116 return 200000000;
109 case 0x1a: 117 case 0x1a:
110 return 384000000; 118 return 384000000;
111 case 0x16: 119 case 0x16:
112 return 400000000; 120 return 400000000;
113 default: 121 default:
114 return 320000000; 122 return 320000000;
115 } 123 }
116 } 124 }
117 125
126 static ulong bcm6348_get_cpu_freq(struct bmips_cpu_priv *priv)
127 {
128 unsigned int tmp, n1, n2, m1;
129
130 tmp = readl_be(priv->regs + REG_BCM6348_PERF_MIPSPLLCFG);
131 n1 = (tmp & MIPSPLLCFG_6348_N1_MASK) >> MIPSPLLCFG_6348_N1_SHIFT;
132 n2 = (tmp & MIPSPLLCFG_6348_N2_MASK) >> MIPSPLLCFG_6348_N2_SHIFT;
133 m1 = (tmp & MIPSPLLCFG_6348_M1CPU_MASK) >> MIPSPLLCFG_6348_M1CPU_SHIFT;
134
135 return (16 * 1000000 * (n1 + 1) * (n2 + 2)) / (m1 + 1);
136 }
137
118 static ulong bcm6358_get_cpu_freq(struct bmips_cpu_priv *priv) 138 static ulong bcm6358_get_cpu_freq(struct bmips_cpu_priv *priv)
119 { 139 {
120 unsigned int tmp, n1, n2, m1; 140 unsigned int tmp, n1, n2, m1;
121 141
122 tmp = readl_be(priv->regs + REG_BCM6358_DDR_DMIPSPLLCFG); 142 tmp = readl_be(priv->regs + REG_BCM6358_DDR_DMIPSPLLCFG);
123 n1 = (tmp & DMIPSPLLCFG_6358_N1_MASK) >> DMIPSPLLCFG_6358_N1_SHIFT; 143 n1 = (tmp & DMIPSPLLCFG_6358_N1_MASK) >> DMIPSPLLCFG_6358_N1_SHIFT;
124 n2 = (tmp & DMIPSPLLCFG_6358_N2_MASK) >> DMIPSPLLCFG_6358_N2_SHIFT; 144 n2 = (tmp & DMIPSPLLCFG_6358_N2_MASK) >> DMIPSPLLCFG_6358_N2_SHIFT;
125 m1 = (tmp & DMIPSPLLCFG_6358_M1_MASK) >> DMIPSPLLCFG_6358_M1_SHIFT; 145 m1 = (tmp & DMIPSPLLCFG_6358_M1_MASK) >> DMIPSPLLCFG_6358_M1_SHIFT;
126 146
127 return (16 * 1000000 * n1 * n2) / m1; 147 return (16 * 1000000 * n1 * n2) / m1;
128 } 148 }
129 149
130 static ulong bcm63268_get_cpu_freq(struct bmips_cpu_priv *priv) 150 static ulong bcm63268_get_cpu_freq(struct bmips_cpu_priv *priv)
131 { 151 {
132 unsigned int mips_pll_fcvo; 152 unsigned int mips_pll_fcvo;
133 153
134 mips_pll_fcvo = readl_be(priv->regs + REG_BCM63268_MISC_STRAPBUS); 154 mips_pll_fcvo = readl_be(priv->regs + REG_BCM63268_MISC_STRAPBUS);
135 mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_63268_FCVO_MASK) 155 mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_63268_FCVO_MASK)
136 >> STRAPBUS_63268_FCVO_SHIFT; 156 >> STRAPBUS_63268_FCVO_SHIFT;
137 157
138 switch (mips_pll_fcvo) { 158 switch (mips_pll_fcvo) {
139 case 0x3: 159 case 0x3:
140 case 0xe: 160 case 0xe:
141 return 320000000; 161 return 320000000;
142 case 0xa: 162 case 0xa:
143 return 333000000; 163 return 333000000;
144 case 0x2: 164 case 0x2:
145 case 0xb: 165 case 0xb:
146 case 0xf: 166 case 0xf:
147 return 400000000; 167 return 400000000;
148 default: 168 default:
149 return 0; 169 return 0;
150 } 170 }
151 } 171 }
152 172
153 static int bcm6328_get_cpu_count(struct bmips_cpu_priv *priv) 173 static int bcm6328_get_cpu_count(struct bmips_cpu_priv *priv)
154 { 174 {
155 u32 val = readl_be(priv->regs + REG_BCM6328_OTP); 175 u32 val = readl_be(priv->regs + REG_BCM6328_OTP);
156 176
157 if (val & BCM6328_TP1_DISABLED) 177 if (val & BCM6328_TP1_DISABLED)
158 return 1; 178 return 1;
159 else 179 else
160 return 2; 180 return 2;
161 } 181 }
162 182
183 static int bcm6345_get_cpu_count(struct bmips_cpu_priv *priv)
184 {
185 return 1;
186 }
187
163 static int bcm6358_get_cpu_count(struct bmips_cpu_priv *priv) 188 static int bcm6358_get_cpu_count(struct bmips_cpu_priv *priv)
164 { 189 {
165 return 2; 190 return 2;
166 } 191 }
167 192
168 static const struct bmips_cpu_hw bmips_cpu_bcm6328 = { 193 static const struct bmips_cpu_hw bmips_cpu_bcm6328 = {
169 .get_cpu_desc = bmips_long_cpu_desc, 194 .get_cpu_desc = bmips_long_cpu_desc,
170 .get_cpu_freq = bcm6328_get_cpu_freq, 195 .get_cpu_freq = bcm6328_get_cpu_freq,
171 .get_cpu_count = bcm6328_get_cpu_count, 196 .get_cpu_count = bcm6328_get_cpu_count,
172 }; 197 };
173 198
199 static const struct bmips_cpu_hw bmips_cpu_bcm6348 = {
200 .get_cpu_desc = bmips_short_cpu_desc,
201 .get_cpu_freq = bcm6348_get_cpu_freq,
202 .get_cpu_count = bcm6345_get_cpu_count,
203 };
204
174 static const struct bmips_cpu_hw bmips_cpu_bcm6358 = { 205 static const struct bmips_cpu_hw bmips_cpu_bcm6358 = {
175 .get_cpu_desc = bmips_short_cpu_desc, 206 .get_cpu_desc = bmips_short_cpu_desc,
176 .get_cpu_freq = bcm6358_get_cpu_freq, 207 .get_cpu_freq = bcm6358_get_cpu_freq,
177 .get_cpu_count = bcm6358_get_cpu_count, 208 .get_cpu_count = bcm6358_get_cpu_count,
178 }; 209 };
179 210
180 static const struct bmips_cpu_hw bmips_cpu_bcm63268 = { 211 static const struct bmips_cpu_hw bmips_cpu_bcm63268 = {
181 .get_cpu_desc = bmips_long_cpu_desc, 212 .get_cpu_desc = bmips_long_cpu_desc,
182 .get_cpu_freq = bcm63268_get_cpu_freq, 213 .get_cpu_freq = bcm63268_get_cpu_freq,
183 .get_cpu_count = bcm6358_get_cpu_count, 214 .get_cpu_count = bcm6358_get_cpu_count,
184 }; 215 };
185 216
186 /* Generic CPU Ops */ 217 /* Generic CPU Ops */
187 static int bmips_cpu_get_desc(struct udevice *dev, char *buf, int size) 218 static int bmips_cpu_get_desc(struct udevice *dev, char *buf, int size)
188 { 219 {
189 struct bmips_cpu_priv *priv = dev_get_priv(dev); 220 struct bmips_cpu_priv *priv = dev_get_priv(dev);
190 const struct bmips_cpu_hw *hw = priv->hw; 221 const struct bmips_cpu_hw *hw = priv->hw;
191 222
192 return hw->get_cpu_desc(priv, buf, size); 223 return hw->get_cpu_desc(priv, buf, size);
193 } 224 }
194 225
195 static int bmips_cpu_get_info(struct udevice *dev, struct cpu_info *info) 226 static int bmips_cpu_get_info(struct udevice *dev, struct cpu_info *info)
196 { 227 {
197 struct bmips_cpu_priv *priv = dev_get_priv(dev); 228 struct bmips_cpu_priv *priv = dev_get_priv(dev);
198 const struct bmips_cpu_hw *hw = priv->hw; 229 const struct bmips_cpu_hw *hw = priv->hw;
199 230
200 info->cpu_freq = hw->get_cpu_freq(priv); 231 info->cpu_freq = hw->get_cpu_freq(priv);
201 info->features = BIT(CPU_FEAT_L1_CACHE); 232 info->features = BIT(CPU_FEAT_L1_CACHE);
202 info->features |= BIT(CPU_FEAT_MMU); 233 info->features |= BIT(CPU_FEAT_MMU);
203 info->features |= BIT(CPU_FEAT_DEVICE_ID); 234 info->features |= BIT(CPU_FEAT_DEVICE_ID);
204 235
205 return 0; 236 return 0;
206 } 237 }
207 238
208 static int bmips_cpu_get_count(struct udevice *dev) 239 static int bmips_cpu_get_count(struct udevice *dev)
209 { 240 {
210 struct bmips_cpu_priv *priv = dev_get_priv(dev); 241 struct bmips_cpu_priv *priv = dev_get_priv(dev);
211 const struct bmips_cpu_hw *hw = priv->hw; 242 const struct bmips_cpu_hw *hw = priv->hw;
212 243
213 return hw->get_cpu_count(priv); 244 return hw->get_cpu_count(priv);
214 } 245 }
215 246
216 static int bmips_cpu_get_vendor(struct udevice *dev, char *buf, int size) 247 static int bmips_cpu_get_vendor(struct udevice *dev, char *buf, int size)
217 { 248 {
218 snprintf(buf, size, "Broadcom"); 249 snprintf(buf, size, "Broadcom");
219 250
220 return 0; 251 return 0;
221 } 252 }
222 253
223 static const struct cpu_ops bmips_cpu_ops = { 254 static const struct cpu_ops bmips_cpu_ops = {
224 .get_desc = bmips_cpu_get_desc, 255 .get_desc = bmips_cpu_get_desc,
225 .get_info = bmips_cpu_get_info, 256 .get_info = bmips_cpu_get_info,
226 .get_count = bmips_cpu_get_count, 257 .get_count = bmips_cpu_get_count,
227 .get_vendor = bmips_cpu_get_vendor, 258 .get_vendor = bmips_cpu_get_vendor,
228 }; 259 };
229 260
230 /* BMIPS CPU driver */ 261 /* BMIPS CPU driver */
231 int bmips_cpu_bind(struct udevice *dev) 262 int bmips_cpu_bind(struct udevice *dev)
232 { 263 {
233 struct cpu_platdata *plat = dev_get_parent_platdata(dev); 264 struct cpu_platdata *plat = dev_get_parent_platdata(dev);
234 265
235 plat->cpu_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), 266 plat->cpu_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
236 "reg", -1); 267 "reg", -1);
237 plat->device_id = read_c0_prid(); 268 plat->device_id = read_c0_prid();
238 269
239 return 0; 270 return 0;
240 } 271 }
241 272
242 int bmips_cpu_probe(struct udevice *dev) 273 int bmips_cpu_probe(struct udevice *dev)
243 { 274 {
244 struct bmips_cpu_priv *priv = dev_get_priv(dev); 275 struct bmips_cpu_priv *priv = dev_get_priv(dev);
245 const struct bmips_cpu_hw *hw = 276 const struct bmips_cpu_hw *hw =
246 (const struct bmips_cpu_hw *)dev_get_driver_data(dev); 277 (const struct bmips_cpu_hw *)dev_get_driver_data(dev);
247 fdt_addr_t addr; 278 fdt_addr_t addr;
248 fdt_size_t size; 279 fdt_size_t size;
249 280
250 addr = dev_get_addr_size_index(dev_get_parent(dev), 0, &size); 281 addr = dev_get_addr_size_index(dev_get_parent(dev), 0, &size);
251 if (addr == FDT_ADDR_T_NONE) 282 if (addr == FDT_ADDR_T_NONE)
252 return -EINVAL; 283 return -EINVAL;
253 284
254 priv->regs = ioremap(addr, size); 285 priv->regs = ioremap(addr, size);
255 priv->hw = hw; 286 priv->hw = hw;
256 287
257 return 0; 288 return 0;
258 } 289 }
259 290
260 static const struct udevice_id bmips_cpu_ids[] = { 291 static const struct udevice_id bmips_cpu_ids[] = {
261 { 292 {
262 .compatible = "brcm,bcm6328-cpu", 293 .compatible = "brcm,bcm6328-cpu",
263 .data = (ulong)&bmips_cpu_bcm6328, 294 .data = (ulong)&bmips_cpu_bcm6328,
295 }, {
296 .compatible = "brcm,bcm6348-cpu",
297 .data = (ulong)&bmips_cpu_bcm6348,
264 }, { 298 }, {
265 .compatible = "brcm,bcm6358-cpu", 299 .compatible = "brcm,bcm6358-cpu",
266 .data = (ulong)&bmips_cpu_bcm6358, 300 .data = (ulong)&bmips_cpu_bcm6358,
267 }, { 301 }, {
268 .compatible = "brcm,bcm63268-cpu", 302 .compatible = "brcm,bcm63268-cpu",
269 .data = (ulong)&bmips_cpu_bcm63268, 303 .data = (ulong)&bmips_cpu_bcm63268,
270 }, 304 },
271 { /* sentinel */ } 305 { /* sentinel */ }
272 }; 306 };
273 307
274 U_BOOT_DRIVER(bmips_cpu_drv) = { 308 U_BOOT_DRIVER(bmips_cpu_drv) = {
275 .name = "bmips_cpu", 309 .name = "bmips_cpu",
276 .id = UCLASS_CPU, 310 .id = UCLASS_CPU,
277 .of_match = bmips_cpu_ids, 311 .of_match = bmips_cpu_ids,
278 .bind = bmips_cpu_bind, 312 .bind = bmips_cpu_bind,
279 .probe = bmips_cpu_probe, 313 .probe = bmips_cpu_probe,
280 .priv_auto_alloc_size = sizeof(struct bmips_cpu_priv), 314 .priv_auto_alloc_size = sizeof(struct bmips_cpu_priv),
281 .ops = &bmips_cpu_ops, 315 .ops = &bmips_cpu_ops,
282 .flags = DM_FLAG_PRE_RELOC, 316 .flags = DM_FLAG_PRE_RELOC,
283 }; 317 };
284 318
285 #ifdef CONFIG_DISPLAY_CPUINFO 319 #ifdef CONFIG_DISPLAY_CPUINFO
286 int print_cpuinfo(void) 320 int print_cpuinfo(void)
287 { 321 {
288 struct cpu_info cpu; 322 struct cpu_info cpu;
289 struct udevice *dev; 323 struct udevice *dev;
290 int err; 324 int err;
291 char desc[100]; 325 char desc[100];
292 326
293 err = uclass_get_device(UCLASS_CPU, 0, &dev); 327 err = uclass_get_device(UCLASS_CPU, 0, &dev);
294 if (err) 328 if (err)
295 return 0; 329 return 0;
296 330
297 err = cpu_get_info(dev, &cpu); 331 err = cpu_get_info(dev, &cpu);
298 if (err) 332 if (err)
299 return 0; 333 return 0;
300 334
301 err = cpu_get_desc(dev, desc, sizeof(desc)); 335 err = cpu_get_desc(dev, desc, sizeof(desc));
302 if (err) 336 if (err)
303 return 0; 337 return 0;
304 338
305 printf("Chip ID: %s, MIPS: ", desc); 339 printf("Chip ID: %s, MIPS: ", desc);
306 print_freq(cpu.cpu_freq, "\n"); 340 print_freq(cpu.cpu_freq, "\n");
307 341
308 return 0; 342 return 0;
309 } 343 }
310 #endif 344 #endif
311 345