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Commit 33a999590869bb33d0f4e2b27b2270f6e12c9953

Authored by Álvaro Fernández Rojas
Committed by Daniel Schwierzeck
1 parent 6ffc18cd04
Exists in smarc_8mq_lf_v2020.04 and in 17 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

dm: cpu: bmips: add BCM6348 support 

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

Showing 1 changed file with 34 additions and 0 deletions Side-by-side Diff

drivers/cpu/bmips_cpu.c
Diff comments   View file @ 33a9995
... ... @@ -30,6 +30,14 @@
30 30 #define STRAPBUS_6328_FCVO_SHIFT 7
31 31 #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
32 32  
  33 +#define REG_BCM6348_PERF_MIPSPLLCFG 0x34
  34 +#define MIPSPLLCFG_6348_M1CPU_SHIFT 6
  35 +#define MIPSPLLCFG_6348_M1CPU_MASK (0x7 << MIPSPLLCFG_6348_M1CPU_SHIFT)
  36 +#define MIPSPLLCFG_6348_N2_SHIFT 15
  37 +#define MIPSPLLCFG_6348_N2_MASK (0x1F << MIPSPLLCFG_6348_N2_SHIFT)
  38 +#define MIPSPLLCFG_6348_N1_SHIFT 20
  39 +#define MIPSPLLCFG_6348_N1_MASK (0x7 << MIPSPLLCFG_6348_N1_SHIFT)
  40 +
33 41 #define REG_BCM6358_DDR_DMIPSPLLCFG 0x12b8
34 42 #define DMIPSPLLCFG_6358_M1_SHIFT 0
35 43 #define DMIPSPLLCFG_6358_M1_MASK (0xff << DMIPSPLLCFG_6358_M1_SHIFT)
... ... @@ -115,6 +123,18 @@
115 123 }
116 124 }
117 125  
  126 +static ulong bcm6348_get_cpu_freq(struct bmips_cpu_priv *priv)
  127 +{
  128 + unsigned int tmp, n1, n2, m1;
  129 +
  130 + tmp = readl_be(priv->regs + REG_BCM6348_PERF_MIPSPLLCFG);
  131 + n1 = (tmp & MIPSPLLCFG_6348_N1_MASK) >> MIPSPLLCFG_6348_N1_SHIFT;
  132 + n2 = (tmp & MIPSPLLCFG_6348_N2_MASK) >> MIPSPLLCFG_6348_N2_SHIFT;
  133 + m1 = (tmp & MIPSPLLCFG_6348_M1CPU_MASK) >> MIPSPLLCFG_6348_M1CPU_SHIFT;
  134 +
  135 + return (16 * 1000000 * (n1 + 1) * (n2 + 2)) / (m1 + 1);
  136 +}
  137 +
118 138 static ulong bcm6358_get_cpu_freq(struct bmips_cpu_priv *priv)
119 139 {
120 140 unsigned int tmp, n1, n2, m1;
... ... @@ -160,6 +180,11 @@
160 180 return 2;
161 181 }
162 182  
  183 +static int bcm6345_get_cpu_count(struct bmips_cpu_priv *priv)
  184 +{
  185 + return 1;
  186 +}
  187 +
163 188 static int bcm6358_get_cpu_count(struct bmips_cpu_priv *priv)
164 189 {
165 190 return 2;
... ... @@ -171,6 +196,12 @@
171 196 .get_cpu_count = bcm6328_get_cpu_count,
172 197 };
173 198  
  199 +static const struct bmips_cpu_hw bmips_cpu_bcm6348 = {
  200 + .get_cpu_desc = bmips_short_cpu_desc,
  201 + .get_cpu_freq = bcm6348_get_cpu_freq,
  202 + .get_cpu_count = bcm6345_get_cpu_count,
  203 +};
  204 +
174 205 static const struct bmips_cpu_hw bmips_cpu_bcm6358 = {
175 206 .get_cpu_desc = bmips_short_cpu_desc,
176 207 .get_cpu_freq = bcm6358_get_cpu_freq,
... ... @@ -261,6 +292,9 @@
261 292 {
262 293 .compatible = "brcm,bcm6328-cpu",
263 294 .data = (ulong)&bmips_cpu_bcm6328,
  295 + }, {
  296 + .compatible = "brcm,bcm6348-cpu",
  297 + .data = (ulong)&bmips_cpu_bcm6348,
264 298 }, {
265 299 .compatible = "brcm,bcm6358-cpu",
266 300 .data = (ulong)&bmips_cpu_bcm6358,