Eric Lee / smarc-uboot

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Commit 33daf5b7858807cb4ce4158c2c56524671c14c08

Authored by Jean-Christophe PLAGNIOL-VILLARD
1 parent 0c698dcaa7
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

drivers/block : move block drivers to drivers/block 

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Showing 13 changed files with 2131 additions and 2085 deletions Side-by-side Diff

... ... @@ -207,6 +207,7 @@
207 207 LIBS += disk/libdisk.a
208 208 LIBS += drivers/libdrivers.a
209 209 LIBS += drivers/bios_emulator/libatibiosemu.a
  210 +LIBS += drivers/block/libblock.a
210 211 LIBS += drivers/hwmon/libhwmon.a
211 212 LIBS += drivers/i2c/libi2c.a
212 213 LIBS += drivers/input/libinput.a
... ... @@ -34,15 +34,10 @@
34 34 #
35 35 # Block and Flash Drivers
36 36 #
37   -COBJS-y += ahci.o
38 37 COBJS-y += at45.o
39   -COBJS-y += ata_piix.o
40 38 COBJS-y += cfi_flash.o
41 39 COBJS-y += dataflash.o
42 40 COBJS-y += mw_eeprom.o
43   -COBJS-y += sil680.o
44   -COBJS-y += sym53c8xx.o
45   -COBJS-y += systemace.o
46 41  
47 42 #
48 43 # Miscellaneous Drivers
drivers/ahci.c
View file @ 33daf5b
1   -/*
2   - * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
3   - * Author: Jason Jin<Jason.jin@freescale.com>
4   - * Zhang Wei<wei.zhang@freescale.com>
5   - *
6   - * See file CREDITS for list of people who contributed to this
7   - * project.
8   - *
9   - * This program is free software; you can redistribute it and/or
10   - * modify it under the terms of the GNU General Public License as
11   - * published by the Free Software Foundation; either version 2 of
12   - * the License, or (at your option) any later version.
13   - *
14   - * This program is distributed in the hope that it will be useful,
15   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
16   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17   - * GNU General Public License for more details.
18   - *
19   - * You should have received a copy of the GNU General Public License
20   - * along with this program; if not, write to the Free Software
21   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22   - * MA 02111-1307 USA
23   - *
24   - * with the reference on libata and ahci drvier in kernel
25   - *
26   - */
27   -#include <common.h>
28   -
29   -#ifdef CONFIG_SCSI_AHCI
30   -
31   -#include <command.h>
32   -#include <pci.h>
33   -#include <asm/processor.h>
34   -#include <asm/errno.h>
35   -#include <asm/io.h>
36   -#include <malloc.h>
37   -#include <scsi.h>
38   -#include <ata.h>
39   -#include <linux/ctype.h>
40   -#include <ahci.h>
41   -
42   -struct ahci_probe_ent *probe_ent = NULL;
43   -hd_driveid_t *ataid[AHCI_MAX_PORTS];
44   -
45   -#define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
46   -
47   -
48   -static inline u32 ahci_port_base(u32 base, u32 port)
49   -{
50   - return base + 0x100 + (port * 0x80);
51   -}
52   -
53   -
54   -static void ahci_setup_port(struct ahci_ioports *port, unsigned long base,
55   - unsigned int port_idx)
56   -{
57   - base = ahci_port_base(base, port_idx);
58   -
59   - port->cmd_addr = base;
60   - port->scr_addr = base + PORT_SCR;
61   -}
62   -
63   -
64   -#define msleep(a) udelay(a * 1000)
65   -#define ssleep(a) msleep(a * 1000)
66   -
67   -static int waiting_for_cmd_completed(volatile u8 *offset,
68   - int timeout_msec,
69   - u32 sign)
70   -{
71   - int i;
72   - u32 status;
73   -
74   - for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
75   - msleep(1);
76   -
77   - return (i < timeout_msec) ? 0 : -1;
78   -}
79   -
80   -
81   -static int ahci_host_init(struct ahci_probe_ent *probe_ent)
82   -{
83   - pci_dev_t pdev = probe_ent->dev;
84   - volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
85   - u32 tmp, cap_save;
86   - u16 tmp16;
87   - int i, j;
88   - volatile u8 *port_mmio;
89   - unsigned short vendor;
90   -
91   - cap_save = readl(mmio + HOST_CAP);
92   - cap_save &= ((1 << 28) | (1 << 17));
93   - cap_save |= (1 << 27);
94   -
95   - /* global controller reset */
96   - tmp = readl(mmio + HOST_CTL);
97   - if ((tmp & HOST_RESET) == 0)
98   - writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL);
99   -
100   - /* reset must complete within 1 second, or
101   - * the hardware should be considered fried.
102   - */
103   - ssleep(1);
104   -
105   - tmp = readl(mmio + HOST_CTL);
106   - if (tmp & HOST_RESET) {
107   - debug("controller reset failed (0x%x)\n", tmp);
108   - return -1;
109   - }
110   -
111   - writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
112   - writel(cap_save, mmio + HOST_CAP);
113   - writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
114   -
115   - pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
116   -
117   - if (vendor == PCI_VENDOR_ID_INTEL) {
118   - u16 tmp16;
119   - pci_read_config_word(pdev, 0x92, &tmp16);
120   - tmp16 |= 0xf;
121   - pci_write_config_word(pdev, 0x92, tmp16);
122   - }
123   -
124   - probe_ent->cap = readl(mmio + HOST_CAP);
125   - probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL);
126   - probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1;
127   -
128   - debug("cap 0x%x port_map 0x%x n_ports %d\n",
129   - probe_ent->cap, probe_ent->port_map, probe_ent->n_ports);
130   -
131   - for (i = 0; i < probe_ent->n_ports; i++) {
132   - probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i);
133   - port_mmio = (u8 *) probe_ent->port[i].port_mmio;
134   - ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i);
135   -
136   - /* make sure port is not active */
137   - tmp = readl(port_mmio + PORT_CMD);
138   - if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
139   - PORT_CMD_FIS_RX | PORT_CMD_START)) {
140   - tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
141   - PORT_CMD_FIS_RX | PORT_CMD_START);
142   - writel_with_flush(tmp, port_mmio + PORT_CMD);
143   -
144   - /* spec says 500 msecs for each bit, so
145   - * this is slightly incorrect.
146   - */
147   - msleep(500);
148   - }
149   -
150   - writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
151   -
152   - j = 0;
153   - while (j < 100) {
154   - msleep(10);
155   - tmp = readl(port_mmio + PORT_SCR_STAT);
156   - if ((tmp & 0xf) == 0x3)
157   - break;
158   - j++;
159   - }
160   -
161   - tmp = readl(port_mmio + PORT_SCR_ERR);
162   - debug("PORT_SCR_ERR 0x%x\n", tmp);
163   - writel(tmp, port_mmio + PORT_SCR_ERR);
164   -
165   - /* ack any pending irq events for this port */
166   - tmp = readl(port_mmio + PORT_IRQ_STAT);
167   - debug("PORT_IRQ_STAT 0x%x\n", tmp);
168   - if (tmp)
169   - writel(tmp, port_mmio + PORT_IRQ_STAT);
170   -
171   - writel(1 << i, mmio + HOST_IRQ_STAT);
172   -
173   - /* set irq mask (enables interrupts) */
174   - writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
175   -
176   - /*register linkup ports */
177   - tmp = readl(port_mmio + PORT_SCR_STAT);
178   - debug("Port %d status: 0x%x\n", i, tmp);
179   - if ((tmp & 0xf) == 0x03)
180   - probe_ent->link_port_map |= (0x01 << i);
181   - }
182   -
183   - tmp = readl(mmio + HOST_CTL);
184   - debug("HOST_CTL 0x%x\n", tmp);
185   - writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
186   - tmp = readl(mmio + HOST_CTL);
187   - debug("HOST_CTL 0x%x\n", tmp);
188   -
189   - pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
190   - tmp |= PCI_COMMAND_MASTER;
191   - pci_write_config_word(pdev, PCI_COMMAND, tmp16);
192   -
193   - return 0;
194   -}
195   -
196   -
197   -static void ahci_print_info(struct ahci_probe_ent *probe_ent)
198   -{
199   - pci_dev_t pdev = probe_ent->dev;
200   - volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
201   - u32 vers, cap, impl, speed;
202   - const char *speed_s;
203   - u16 cc;
204   - const char *scc_s;
205   -
206   - vers = readl(mmio + HOST_VERSION);
207   - cap = probe_ent->cap;
208   - impl = probe_ent->port_map;
209   -
210   - speed = (cap >> 20) & 0xf;
211   - if (speed == 1)
212   - speed_s = "1.5";
213   - else if (speed == 2)
214   - speed_s = "3";
215   - else
216   - speed_s = "?";
217   -
218   - pci_read_config_word(pdev, 0x0a, &cc);
219   - if (cc == 0x0101)
220   - scc_s = "IDE";
221   - else if (cc == 0x0106)
222   - scc_s = "SATA";
223   - else if (cc == 0x0104)
224   - scc_s = "RAID";
225   - else
226   - scc_s = "unknown";
227   -
228   - printf("AHCI %02x%02x.%02x%02x "
229   - "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
230   - (vers >> 24) & 0xff,
231   - (vers >> 16) & 0xff,
232   - (vers >> 8) & 0xff,
233   - vers & 0xff,
234   - ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
235   -
236   - printf("flags: "
237   - "%s%s%s%s%s%s"
238   - "%s%s%s%s%s%s%s\n",
239   - cap & (1 << 31) ? "64bit " : "",
240   - cap & (1 << 30) ? "ncq " : "",
241   - cap & (1 << 28) ? "ilck " : "",
242   - cap & (1 << 27) ? "stag " : "",
243   - cap & (1 << 26) ? "pm " : "",
244   - cap & (1 << 25) ? "led " : "",
245   - cap & (1 << 24) ? "clo " : "",
246   - cap & (1 << 19) ? "nz " : "",
247   - cap & (1 << 18) ? "only " : "",
248   - cap & (1 << 17) ? "pmp " : "",
249   - cap & (1 << 15) ? "pio " : "",
250   - cap & (1 << 14) ? "slum " : "",
251   - cap & (1 << 13) ? "part " : "");
252   -}
253   -
254   -static int ahci_init_one(pci_dev_t pdev)
255   -{
256   - u32 iobase;
257   - u16 vendor;
258   - int rc;
259   -
260   - memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS);
261   -
262   - probe_ent = malloc(sizeof(struct ahci_probe_ent));
263   - memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
264   - probe_ent->dev = pdev;
265   -
266   - pci_read_config_dword(pdev, AHCI_PCI_BAR, &iobase);
267   - iobase &= ~0xf;
268   -
269   - probe_ent->host_flags = ATA_FLAG_SATA
270   - | ATA_FLAG_NO_LEGACY
271   - | ATA_FLAG_MMIO
272   - | ATA_FLAG_PIO_DMA
273   - | ATA_FLAG_NO_ATAPI;
274   - probe_ent->pio_mask = 0x1f;
275   - probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
276   -
277   - probe_ent->mmio_base = iobase;
278   -
279   - /* Take from kernel:
280   - * JMicron-specific fixup:
281   - * make sure we're in AHCI mode
282   - */
283   - pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
284   - if (vendor == 0x197b)
285   - pci_write_config_byte(pdev, 0x41, 0xa1);
286   -
287   - /* initialize adapter */
288   - rc = ahci_host_init(probe_ent);
289   - if (rc)
290   - goto err_out;
291   -
292   - ahci_print_info(probe_ent);
293   -
294   - return 0;
295   -
296   - err_out:
297   - return rc;
298   -}
299   -
300   -
301   -#define MAX_DATA_BYTE_COUNT (4*1024*1024)
302   -
303   -static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len)
304   -{
305   - struct ahci_ioports *pp = &(probe_ent->port[port]);
306   - struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
307   - u32 sg_count;
308   - int i;
309   -
310   - sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
311   - if (sg_count > AHCI_MAX_SG) {
312   - printf("Error:Too much sg!\n");
313   - return -1;
314   - }
315   -
316   - for (i = 0; i < sg_count; i++) {
317   - ahci_sg->addr =
318   - cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT);
319   - ahci_sg->addr_hi = 0;
320   - ahci_sg->flags_size = cpu_to_le32(0x3fffff &
321   - (buf_len < MAX_DATA_BYTE_COUNT
322   - ? (buf_len - 1)
323   - : (MAX_DATA_BYTE_COUNT - 1)));
324   - ahci_sg++;
325   - buf_len -= MAX_DATA_BYTE_COUNT;
326   - }
327   -
328   - return sg_count;
329   -}
330   -
331   -
332   -static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
333   -{
334   - pp->cmd_slot->opts = cpu_to_le32(opts);
335   - pp->cmd_slot->status = 0;
336   - pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff);
337   - pp->cmd_slot->tbl_addr_hi = 0;
338   -}
339   -
340   -
341   -static void ahci_set_feature(u8 port)
342   -{
343   - struct ahci_ioports *pp = &(probe_ent->port[port]);
344   - volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
345   - u32 cmd_fis_len = 5; /* five dwords */
346   - u8 fis[20];
347   -
348   - /*set feature */
349   - memset(fis, 0, 20);
350   - fis[0] = 0x27;
351   - fis[1] = 1 << 7;
352   - fis[2] = ATA_CMD_SETF;
353   - fis[3] = SETFEATURES_XFER;
354   - fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01;
355   -
356   - memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
357   - ahci_fill_cmd_slot(pp, cmd_fis_len);
358   - writel(1, port_mmio + PORT_CMD_ISSUE);
359   - readl(port_mmio + PORT_CMD_ISSUE);
360   -
361   - if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) {
362   - printf("set feature error!\n");
363   - }
364   -}
365   -
366   -
367   -static int ahci_port_start(u8 port)
368   -{
369   - struct ahci_ioports *pp = &(probe_ent->port[port]);
370   - volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
371   - u32 port_status;
372   - u32 mem;
373   -
374   - debug("Enter start port: %d\n", port);
375   - port_status = readl(port_mmio + PORT_SCR_STAT);
376   - debug("Port %d status: %x\n", port, port_status);
377   - if ((port_status & 0xf) != 0x03) {
378   - printf("No Link on this port!\n");
379   - return -1;
380   - }
381   -
382   - mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);
383   - if (!mem) {
384   - free(pp);
385   - printf("No mem for table!\n");
386   - return -ENOMEM;
387   - }
388   -
389   - mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */
390   - memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ);
391   -
392   - /*
393   - * First item in chunk of DMA memory: 32-slot command table,
394   - * 32 bytes each in size
395   - */
396   - pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
397   - debug("cmd_slot = 0x%x\n", pp->cmd_slot);
398   - mem += (AHCI_CMD_SLOT_SZ + 224);
399   -
400   - /*
401   - * Second item: Received-FIS area
402   - */
403   - pp->rx_fis = mem;
404   - mem += AHCI_RX_FIS_SZ;
405   -
406   - /*
407   - * Third item: data area for storing a single command
408   - * and its scatter-gather table
409   - */
410   - pp->cmd_tbl = mem;
411   - debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl);
412   -
413   - mem += AHCI_CMD_TBL_HDR;
414   - pp->cmd_tbl_sg = (struct ahci_sg *)mem;
415   -
416   - writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR);
417   -
418   - writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
419   -
420   - writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
421   - PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
422   - PORT_CMD_START, port_mmio + PORT_CMD);
423   -
424   - debug("Exit start port %d\n", port);
425   -
426   - return 0;
427   -}
428   -
429   -
430   -static int get_ahci_device_data(u8 port, u8 *fis, int fis_len, u8 *buf,
431   - int buf_len)
432   -{
433   -
434   - struct ahci_ioports *pp = &(probe_ent->port[port]);
435   - volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
436   - u32 opts;
437   - u32 port_status;
438   - int sg_count;
439   -
440   - debug("Enter get_ahci_device_data: for port %d\n", port);
441   -
442   - if (port > probe_ent->n_ports) {
443   - printf("Invaild port number %d\n", port);
444   - return -1;
445   - }
446   -
447   - port_status = readl(port_mmio + PORT_SCR_STAT);
448   - if ((port_status & 0xf) != 0x03) {
449   - debug("No Link on port %d!\n", port);
450   - return -1;
451   - }
452   -
453   - memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
454   -
455   - sg_count = ahci_fill_sg(port, buf, buf_len);
456   - opts = (fis_len >> 2) | (sg_count << 16);
457   - ahci_fill_cmd_slot(pp, opts);
458   -
459   - writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
460   -
461   - if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) {
462   - printf("timeout exit!\n");
463   - return -1;
464   - }
465   - debug("get_ahci_device_data: %d byte transferred.\n",
466   - pp->cmd_slot->status);
467   -
468   - return 0;
469   -}
470   -
471   -
472   -static char *ata_id_strcpy(u16 *target, u16 *src, int len)
473   -{
474   - int i;
475   - for (i = 0; i < len / 2; i++)
476   - target[i] = le16_to_cpu(src[i]);
477   - return (char *)target;
478   -}
479   -
480   -
481   -static void dump_ataid(hd_driveid_t *ataid)
482   -{
483   - debug("(49)ataid->capability = 0x%x\n", ataid->capability);
484   - debug("(53)ataid->field_valid =0x%x\n", ataid->field_valid);
485   - debug("(63)ataid->dma_mword = 0x%x\n", ataid->dma_mword);
486   - debug("(64)ataid->eide_pio_modes = 0x%x\n", ataid->eide_pio_modes);
487   - debug("(75)ataid->queue_depth = 0x%x\n", ataid->queue_depth);
488   - debug("(80)ataid->major_rev_num = 0x%x\n", ataid->major_rev_num);
489   - debug("(81)ataid->minor_rev_num = 0x%x\n", ataid->minor_rev_num);
490   - debug("(82)ataid->command_set_1 = 0x%x\n", ataid->command_set_1);
491   - debug("(83)ataid->command_set_2 = 0x%x\n", ataid->command_set_2);
492   - debug("(84)ataid->cfsse = 0x%x\n", ataid->cfsse);
493   - debug("(85)ataid->cfs_enable_1 = 0x%x\n", ataid->cfs_enable_1);
494   - debug("(86)ataid->cfs_enable_2 = 0x%x\n", ataid->cfs_enable_2);
495   - debug("(87)ataid->csf_default = 0x%x\n", ataid->csf_default);
496   - debug("(88)ataid->dma_ultra = 0x%x\n", ataid->dma_ultra);
497   - debug("(93)ataid->hw_config = 0x%x\n", ataid->hw_config);
498   -}
499   -
500   -
501   -/*
502   - * SCSI INQUIRY command operation.
503   - */
504   -static int ata_scsiop_inquiry(ccb *pccb)
505   -{
506   - u8 hdr[] = {
507   - 0,
508   - 0,
509   - 0x5, /* claim SPC-3 version compatibility */
510   - 2,
511   - 95 - 4,
512   - };
513   - u8 fis[20];
514   - u8 *tmpid;
515   - u8 port;
516   -
517   - /* Clean ccb data buffer */
518   - memset(pccb->pdata, 0, pccb->datalen);
519   -
520   - memcpy(pccb->pdata, hdr, sizeof(hdr));
521   -
522   - if (pccb->datalen <= 35)
523   - return 0;
524   -
525   - memset(fis, 0, 20);
526   - /* Construct the FIS */
527   - fis[0] = 0x27; /* Host to device FIS. */
528   - fis[1] = 1 << 7; /* Command FIS. */
529   - fis[2] = ATA_CMD_IDENT; /* Command byte. */
530   -
531   - /* Read id from sata */
532   - port = pccb->target;
533   - if (!(tmpid = malloc(sizeof(hd_driveid_t))))
534   - return -ENOMEM;
535   -
536   - if (get_ahci_device_data(port, (u8 *) & fis, 20,
537   - tmpid, sizeof(hd_driveid_t))) {
538   - debug("scsi_ahci: SCSI inquiry command failure.\n");
539   - return -EIO;
540   - }
541   -
542   - if (ataid[port])
543   - free(ataid[port]);
544   - ataid[port] = (hd_driveid_t *) tmpid;
545   -
546   - memcpy(&pccb->pdata[8], "ATA ", 8);
547   - ata_id_strcpy((u16 *) &pccb->pdata[16], (u16 *)ataid[port]->model, 16);
548   - ata_id_strcpy((u16 *) &pccb->pdata[32], (u16 *)ataid[port]->fw_rev, 4);
549   -
550   - dump_ataid(ataid[port]);
551   - return 0;
552   -}
553   -
554   -
555   -/*
556   - * SCSI READ10 command operation.
557   - */
558   -static int ata_scsiop_read10(ccb * pccb)
559   -{
560   - u64 lba = 0;
561   - u32 len = 0;
562   - u8 fis[20];
563   -
564   - lba = (((u64) pccb->cmd[2]) << 24) | (((u64) pccb->cmd[3]) << 16)
565   - | (((u64) pccb->cmd[4]) << 8) | ((u64) pccb->cmd[5]);
566   - len = (((u32) pccb->cmd[7]) << 8) | ((u32) pccb->cmd[8]);
567   -
568   - /* For 10-byte and 16-byte SCSI R/W commands, transfer
569   - * length 0 means transfer 0 block of data.
570   - * However, for ATA R/W commands, sector count 0 means
571   - * 256 or 65536 sectors, not 0 sectors as in SCSI.
572   - *
573   - * WARNING: one or two older ATA drives treat 0 as 0...
574   - */
575   - if (!len)
576   - return 0;
577   - memset(fis, 0, 20);
578   -
579   - /* Construct the FIS */
580   - fis[0] = 0x27; /* Host to device FIS. */
581   - fis[1] = 1 << 7; /* Command FIS. */
582   - fis[2] = ATA_CMD_RD_DMA; /* Command byte. */
583   -
584   - /* LBA address, only support LBA28 in this driver */
585   - fis[4] = pccb->cmd[5];
586   - fis[5] = pccb->cmd[4];
587   - fis[6] = pccb->cmd[3];
588   - fis[7] = (pccb->cmd[2] & 0x0f) | 0xe0;
589   -
590   - /* Sector Count */
591   - fis[12] = pccb->cmd[8];
592   - fis[13] = pccb->cmd[7];
593   -
594   - /* Read from ahci */
595   - if (get_ahci_device_data(pccb->target, (u8 *) & fis, 20,
596   - pccb->pdata, pccb->datalen)) {
597   - debug("scsi_ahci: SCSI READ10 command failure.\n");
598   - return -EIO;
599   - }
600   -
601   - return 0;
602   -}
603   -
604   -
605   -/*
606   - * SCSI READ CAPACITY10 command operation.
607   - */
608   -static int ata_scsiop_read_capacity10(ccb *pccb)
609   -{
610   - u8 buf[8];
611   -
612   - if (!ataid[pccb->target]) {
613   - printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
614   - "\tNo ATA info!\n"
615   - "\tPlease run SCSI commmand INQUIRY firstly!\n");
616   - return -EPERM;
617   - }
618   -
619   - memset(buf, 0, 8);
620   -
621   - *(u32 *) buf = le32_to_cpu(ataid[pccb->target]->lba_capacity);
622   -
623   - buf[6] = 512 >> 8;
624   - buf[7] = 512 & 0xff;
625   -
626   - memcpy(pccb->pdata, buf, 8);
627   -
628   - return 0;
629   -}
630   -
631   -
632   -/*
633   - * SCSI TEST UNIT READY command operation.
634   - */
635   -static int ata_scsiop_test_unit_ready(ccb *pccb)
636   -{
637   - return (ataid[pccb->target]) ? 0 : -EPERM;
638   -}
639   -
640   -
641   -int scsi_exec(ccb *pccb)
642   -{
643   - int ret;
644   -
645   - switch (pccb->cmd[0]) {
646   - case SCSI_READ10:
647   - ret = ata_scsiop_read10(pccb);
648   - break;
649   - case SCSI_RD_CAPAC:
650   - ret = ata_scsiop_read_capacity10(pccb);
651   - break;
652   - case SCSI_TST_U_RDY:
653   - ret = ata_scsiop_test_unit_ready(pccb);
654   - break;
655   - case SCSI_INQUIRY:
656   - ret = ata_scsiop_inquiry(pccb);
657   - break;
658   - default:
659   - printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
660   - return FALSE;
661   - }
662   -
663   - if (ret) {
664   - debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
665   - return FALSE;
666   - }
667   - return TRUE;
668   -
669   -}
670   -
671   -
672   -void scsi_low_level_init(int busdevfunc)
673   -{
674   - int i;
675   - u32 linkmap;
676   -
677   - ahci_init_one(busdevfunc);
678   -
679   - linkmap = probe_ent->link_port_map;
680   -
681   - for (i = 0; i < CFG_SCSI_MAX_SCSI_ID; i++) {
682   - if (((linkmap >> i) & 0x01)) {
683   - if (ahci_port_start((u8) i)) {
684   - printf("Can not start port %d\n", i);
685   - continue;
686   - }
687   - ahci_set_feature((u8) i);
688   - }
689   - }
690   -}
691   -
692   -
693   -void scsi_bus_reset(void)
694   -{
695   - /*Not implement*/
696   -}
697   -
698   -
699   -void scsi_print_error(ccb * pccb)
700   -{
701   - /*The ahci error info can be read in the ahci driver*/
702   -}
703   -#endif
drivers/ata_piix.c
View file @ 33daf5b
1   -/*
2   - * Copyright (C) Procsys. All rights reserved.
3   - * Author: Mushtaq Khan <mushtaq_k@procsys.com>
4   - * <mushtaqk_921@yahoo.co.in>
5   - *
6   - * This program is free software; you can redistribute it and/or
7   - * modify it under the terms of the GNU General Public License as
8   - * published by the Free Software Foundation; either version 2 of
9   - * the License, or (at your option) any later version.
10   - *
11   - * This program is distributed in the hope that it will be useful,
12   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
13   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14   - * GNU General Public License for more details.
15   - *
16   - * You should have received a copy of the GNU General Public License
17   - * along with this program; if not, write to the Free Software
18   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19   - * MA 02111-1307 USA
20   - *
21   - * with the reference to ata_piix driver in kernel 2.4.32
22   - */
23   -
24   -/*
25   - * This file contains SATA controller and SATA drive initialization functions
26   - */
27   -
28   -#include <common.h>
29   -#include <pci.h>
30   -#include <command.h>
31   -#include <config.h>
32   -#include <asm/byteorder.h>
33   -#include <ide.h>
34   -#include <ata.h>
35   -
36   -#ifdef CFG_ATA_PIIX /*ata_piix driver */
37   -
38   -#define DEBUG_SATA 0 /*For debug prints set DEBUG_SATA to 1 */
39   -
40   -#define DRV_DECL /*For file specific declarations */
41   -#include <sata.h>
42   -#undef DRV_DECL
43   -
44   -/*Macros realted to PCI*/
45   -#define PCI_SATA_BUS 0x00
46   -#define PCI_SATA_DEV 0x1f
47   -#define PCI_SATA_FUNC 0x02
48   -
49   -#define PCI_SATA_BASE1 0x10
50   -#define PCI_SATA_BASE2 0x14
51   -#define PCI_SATA_BASE3 0x18
52   -#define PCI_SATA_BASE4 0x1c
53   -#define PCI_SATA_BASE5 0x20
54   -#define PCI_PMR 0x90
55   -#define PCI_PI 0x09
56   -#define PCI_PCS 0x92
57   -#define PCI_DMA_CTL 0x48
58   -
59   -#define PORT_PRESENT (1<<0)
60   -#define PORT_ENABLED (1<<4)
61   -
62   -u32 bdf;
63   -u32 iobase1 = 0; /*Primary cmd block */
64   -u32 iobase2 = 0; /*Primary ctl block */
65   -u32 iobase3 = 0; /*Sec cmd block */
66   -u32 iobase4 = 0; /*sec ctl block */
67   -u32 iobase5 = 0; /*BMDMA*/
68   -int
69   -pci_sata_init (void)
70   -{
71   - u32 bus = PCI_SATA_BUS;
72   - u32 dev = PCI_SATA_DEV;
73   - u32 fun = PCI_SATA_FUNC;
74   - u16 cmd = 0;
75   - u8 lat = 0, pcibios_max_latency = 0xff;
76   - u8 pmr; /*Port mapping reg */
77   - u8 pi; /*Prgming Interface reg */
78   -
79   - bdf = PCI_BDF (bus, dev, fun);
80   - pci_read_config_dword (bdf, PCI_SATA_BASE1, &iobase1);
81   - pci_read_config_dword (bdf, PCI_SATA_BASE2, &iobase2);
82   - pci_read_config_dword (bdf, PCI_SATA_BASE3, &iobase3);
83   - pci_read_config_dword (bdf, PCI_SATA_BASE4, &iobase4);
84   - pci_read_config_dword (bdf, PCI_SATA_BASE5, &iobase5);
85   -
86   - if ((iobase1 == 0xFFFFFFFF) || (iobase2 == 0xFFFFFFFF) ||
87   - (iobase3 == 0xFFFFFFFF) || (iobase4 == 0xFFFFFFFF) ||
88   - (iobase5 == 0xFFFFFFFF)) {
89   - printf ("error no base addr for SATA controller\n");
90   - return 1;
91   - /*ERROR*/}
92   -
93   - iobase1 &= 0xFFFFFFFE;
94   - iobase2 &= 0xFFFFFFFE;
95   - iobase3 &= 0xFFFFFFFE;
96   - iobase4 &= 0xFFFFFFFE;
97   - iobase5 &= 0xFFFFFFFE;
98   -
99   - /*check for mode */
100   - pci_read_config_byte (bdf, PCI_PMR, &pmr);
101   - if (pmr > 1) {
102   - printf ("combined mode not supported\n");
103   - return 1;
104   - }
105   -
106   - pci_read_config_byte (bdf, PCI_PI, &pi);
107   - if ((pi & 0x05) != 0x05) {
108   - printf ("Sata is in Legacy mode\n");
109   - return 1;
110   - } else {
111   - printf ("sata is in Native mode\n");
112   - }
113   -
114   - /*MASTER CFG AND IO CFG */
115   - pci_read_config_word (bdf, PCI_COMMAND, &cmd);
116   - cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
117   - pci_write_config_word (bdf, PCI_COMMAND, cmd);
118   - pci_read_config_byte (dev, PCI_LATENCY_TIMER, &lat);
119   -
120   - if (lat < 16)
121   - lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
122   - else if (lat > pcibios_max_latency)
123   - lat = pcibios_max_latency;
124   - pci_write_config_byte (dev, PCI_LATENCY_TIMER, lat);
125   -
126   - return 0;
127   -}
128   -
129   -int
130   -sata_bus_probe (int port_no)
131   -{
132   - int orig_mask, mask;
133   - u16 pcs;
134   -
135   - mask = (PORT_PRESENT << port_no);
136   - pci_read_config_word (bdf, PCI_PCS, &pcs);
137   - orig_mask = (int) pcs & 0xff;
138   - if ((orig_mask & mask) != mask)
139   - return 0;
140   - else
141   - return 1;
142   -}
143   -
144   -int
145   -init_sata (void)
146   -{
147   - u8 i, rv = 0;
148   -
149   - for (i = 0; i < CFG_SATA_MAXDEVICES; i++) {
150   - sata_dev_desc[i].type = DEV_TYPE_UNKNOWN;
151   - sata_dev_desc[i].if_type = IF_TYPE_IDE;
152   - sata_dev_desc[i].dev = i;
153   - sata_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
154   - sata_dev_desc[i].blksz = 0;
155   - sata_dev_desc[i].lba = 0;
156   - sata_dev_desc[i].block_read = sata_read;
157   - }
158   -
159   - rv = pci_sata_init ();
160   - if (rv == 1) {
161   - printf ("pci initialization failed\n");
162   - return 1;
163   - }
164   -
165   - port[0].port_no = 0;
166   - port[0].ioaddr.cmd_addr = iobase1;
167   - port[0].ioaddr.altstatus_addr = port[0].ioaddr.ctl_addr =
168   - iobase2 | ATA_PCI_CTL_OFS;
169   - port[0].ioaddr.bmdma_addr = iobase5;
170   -
171   - port[1].port_no = 1;
172   - port[1].ioaddr.cmd_addr = iobase3;
173   - port[1].ioaddr.altstatus_addr = port[1].ioaddr.ctl_addr =
174   - iobase4 | ATA_PCI_CTL_OFS;
175   - port[1].ioaddr.bmdma_addr = iobase5 + 0x8;
176   -
177   - for (i = 0; i < CFG_SATA_MAXBUS; i++)
178   - sata_port (&port[i].ioaddr);
179   -
180   - for (i = 0; i < CFG_SATA_MAXBUS; i++) {
181   - if (!(sata_bus_probe (i))) {
182   - port[i].port_state = 0;
183   - printf ("SATA#%d port is not present \n", i);
184   - } else {
185   - printf ("SATA#%d port is present\n", i);
186   - if (sata_bus_softreset (i)) {
187   - port[i].port_state = 0;
188   - } else {
189   - port[i].port_state = 1;
190   - }
191   - }
192   - }
193   -
194   - for (i = 0; i < CFG_SATA_MAXBUS; i++) {
195   - u8 j, devno;
196   -
197   - if (port[i].port_state == 0)
198   - continue;
199   - for (j = 0; j < CFG_SATA_DEVS_PER_BUS; j++) {
200   - sata_identify (i, j);
201   - set_Feature_cmd (i, j);
202   - devno = i * CFG_SATA_DEVS_PER_BUS + j;
203   - if ((sata_dev_desc[devno].lba > 0) &&
204   - (sata_dev_desc[devno].blksz > 0)) {
205   - dev_print (&sata_dev_desc[devno]);
206   - /* initialize partition type */
207   - init_part (&sata_dev_desc[devno]);
208   - if (curr_dev < 0)
209   - curr_dev =
210   - i * CFG_SATA_DEVS_PER_BUS + j;
211   - }
212   - }
213   - }
214   - return 0;
215   -}
216   -#endif
drivers/block/Makefile
Diff comments   View file @ 33daf5b
  1 +#
  2 +# (C) Copyright 2000-2007
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +#
  5 +# See file CREDITS for list of people who contributed to this
  6 +# project.
  7 +#
  8 +# This program is free software; you can redistribute it and/or
  9 +# modify it under the terms of the GNU General Public License as
  10 +# published by the Free Software Foundation; either version 2 of
  11 +# the License, or (at your option) any later version.
  12 +#
  13 +# This program is distributed in the hope that it will be useful,
  14 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 +# GNU General Public License for more details.
  17 +#
  18 +# You should have received a copy of the GNU General Public License
  19 +# along with this program; if not, write to the Free Software
  20 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 +# MA 02111-1307 USA
  22 +#
  23 +
  24 +include $(TOPDIR)/config.mk
  25 +
  26 +LIB := $(obj)libblock.a
  27 +
  28 +COBJS-y += ahci.o
  29 +COBJS-y += ata_piix.o
  30 +COBJS-y += sil680.o
  31 +COBJS-y += sym53c8xx.o
  32 +COBJS-y += systemace.o
  33 +
  34 +COBJS := $(COBJS-y)
  35 +SRCS := $(COBJS:.o=.c)
  36 +OBJS := $(addprefix $(obj),$(COBJS))
  37 +
  38 +all: $(LIB)
  39 +
  40 +$(LIB): $(obj).depend $(OBJS)
  41 + $(AR) $(ARFLAGS) $@ $(OBJS)
  42 +
  43 +#########################################################################
  44 +
  45 +# defines $(obj).depend target
  46 +include $(SRCTREE)/rules.mk
  47 +
  48 +sinclude $(obj).depend
  49 +
  50 +#########################################################################
drivers/block/ahci.c
Diff comments   View file @ 33daf5b
  1 +/*
  2 + * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
  3 + * Author: Jason Jin<Jason.jin@freescale.com>
  4 + * Zhang Wei<wei.zhang@freescale.com>
  5 + *
  6 + * See file CREDITS for list of people who contributed to this
  7 + * project.
  8 + *
  9 + * This program is free software; you can redistribute it and/or
  10 + * modify it under the terms of the GNU General Public License as
  11 + * published by the Free Software Foundation; either version 2 of
  12 + * the License, or (at your option) any later version.
  13 + *
  14 + * This program is distributed in the hope that it will be useful,
  15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17 + * GNU General Public License for more details.
  18 + *
  19 + * You should have received a copy of the GNU General Public License
  20 + * along with this program; if not, write to the Free Software
  21 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 + * MA 02111-1307 USA
  23 + *
  24 + * with the reference on libata and ahci drvier in kernel
  25 + *
  26 + */
  27 +#include <common.h>
  28 +
  29 +#ifdef CONFIG_SCSI_AHCI
  30 +
  31 +#include <command.h>
  32 +#include <pci.h>
  33 +#include <asm/processor.h>
  34 +#include <asm/errno.h>
  35 +#include <asm/io.h>
  36 +#include <malloc.h>
  37 +#include <scsi.h>
  38 +#include <ata.h>
  39 +#include <linux/ctype.h>
  40 +#include <ahci.h>
  41 +
  42 +struct ahci_probe_ent *probe_ent = NULL;
  43 +hd_driveid_t *ataid[AHCI_MAX_PORTS];
  44 +
  45 +#define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
  46 +
  47 +
  48 +static inline u32 ahci_port_base(u32 base, u32 port)
  49 +{
  50 + return base + 0x100 + (port * 0x80);
  51 +}
  52 +
  53 +
  54 +static void ahci_setup_port(struct ahci_ioports *port, unsigned long base,
  55 + unsigned int port_idx)
  56 +{
  57 + base = ahci_port_base(base, port_idx);
  58 +
  59 + port->cmd_addr = base;
  60 + port->scr_addr = base + PORT_SCR;
  61 +}
  62 +
  63 +
  64 +#define msleep(a) udelay(a * 1000)
  65 +#define ssleep(a) msleep(a * 1000)
  66 +
  67 +static int waiting_for_cmd_completed(volatile u8 *offset,
  68 + int timeout_msec,
  69 + u32 sign)
  70 +{
  71 + int i;
  72 + u32 status;
  73 +
  74 + for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
  75 + msleep(1);
  76 +
  77 + return (i < timeout_msec) ? 0 : -1;
  78 +}
  79 +
  80 +
  81 +static int ahci_host_init(struct ahci_probe_ent *probe_ent)
  82 +{
  83 + pci_dev_t pdev = probe_ent->dev;
  84 + volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
  85 + u32 tmp, cap_save;
  86 + u16 tmp16;
  87 + int i, j;
  88 + volatile u8 *port_mmio;
  89 + unsigned short vendor;
  90 +
  91 + cap_save = readl(mmio + HOST_CAP);
  92 + cap_save &= ((1 << 28) | (1 << 17));
  93 + cap_save |= (1 << 27);
  94 +
  95 + /* global controller reset */
  96 + tmp = readl(mmio + HOST_CTL);
  97 + if ((tmp & HOST_RESET) == 0)
  98 + writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL);
  99 +
  100 + /* reset must complete within 1 second, or
  101 + * the hardware should be considered fried.
  102 + */
  103 + ssleep(1);
  104 +
  105 + tmp = readl(mmio + HOST_CTL);
  106 + if (tmp & HOST_RESET) {
  107 + debug("controller reset failed (0x%x)\n", tmp);
  108 + return -1;
  109 + }
  110 +
  111 + writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
  112 + writel(cap_save, mmio + HOST_CAP);
  113 + writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
  114 +
  115 + pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
  116 +
  117 + if (vendor == PCI_VENDOR_ID_INTEL) {
  118 + u16 tmp16;
  119 + pci_read_config_word(pdev, 0x92, &tmp16);
  120 + tmp16 |= 0xf;
  121 + pci_write_config_word(pdev, 0x92, tmp16);
  122 + }
  123 +
  124 + probe_ent->cap = readl(mmio + HOST_CAP);
  125 + probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL);
  126 + probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1;
  127 +
  128 + debug("cap 0x%x port_map 0x%x n_ports %d\n",
  129 + probe_ent->cap, probe_ent->port_map, probe_ent->n_ports);
  130 +
  131 + for (i = 0; i < probe_ent->n_ports; i++) {
  132 + probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i);
  133 + port_mmio = (u8 *) probe_ent->port[i].port_mmio;
  134 + ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i);
  135 +
  136 + /* make sure port is not active */
  137 + tmp = readl(port_mmio + PORT_CMD);
  138 + if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
  139 + PORT_CMD_FIS_RX | PORT_CMD_START)) {
  140 + tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
  141 + PORT_CMD_FIS_RX | PORT_CMD_START);
  142 + writel_with_flush(tmp, port_mmio + PORT_CMD);
  143 +
  144 + /* spec says 500 msecs for each bit, so
  145 + * this is slightly incorrect.
  146 + */
  147 + msleep(500);
  148 + }
  149 +
  150 + writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
  151 +
  152 + j = 0;
  153 + while (j < 100) {
  154 + msleep(10);
  155 + tmp = readl(port_mmio + PORT_SCR_STAT);
  156 + if ((tmp & 0xf) == 0x3)
  157 + break;
  158 + j++;
  159 + }
  160 +
  161 + tmp = readl(port_mmio + PORT_SCR_ERR);
  162 + debug("PORT_SCR_ERR 0x%x\n", tmp);
  163 + writel(tmp, port_mmio + PORT_SCR_ERR);
  164 +
  165 + /* ack any pending irq events for this port */
  166 + tmp = readl(port_mmio + PORT_IRQ_STAT);
  167 + debug("PORT_IRQ_STAT 0x%x\n", tmp);
  168 + if (tmp)
  169 + writel(tmp, port_mmio + PORT_IRQ_STAT);
  170 +
  171 + writel(1 << i, mmio + HOST_IRQ_STAT);
  172 +
  173 + /* set irq mask (enables interrupts) */
  174 + writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
  175 +
  176 + /*register linkup ports */
  177 + tmp = readl(port_mmio + PORT_SCR_STAT);
  178 + debug("Port %d status: 0x%x\n", i, tmp);
  179 + if ((tmp & 0xf) == 0x03)
  180 + probe_ent->link_port_map |= (0x01 << i);
  181 + }
  182 +
  183 + tmp = readl(mmio + HOST_CTL);
  184 + debug("HOST_CTL 0x%x\n", tmp);
  185 + writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
  186 + tmp = readl(mmio + HOST_CTL);
  187 + debug("HOST_CTL 0x%x\n", tmp);
  188 +
  189 + pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
  190 + tmp |= PCI_COMMAND_MASTER;
  191 + pci_write_config_word(pdev, PCI_COMMAND, tmp16);
  192 +
  193 + return 0;
  194 +}
  195 +
  196 +
  197 +static void ahci_print_info(struct ahci_probe_ent *probe_ent)
  198 +{
  199 + pci_dev_t pdev = probe_ent->dev;
  200 + volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
  201 + u32 vers, cap, impl, speed;
  202 + const char *speed_s;
  203 + u16 cc;
  204 + const char *scc_s;
  205 +
  206 + vers = readl(mmio + HOST_VERSION);
  207 + cap = probe_ent->cap;
  208 + impl = probe_ent->port_map;
  209 +
  210 + speed = (cap >> 20) & 0xf;
  211 + if (speed == 1)
  212 + speed_s = "1.5";
  213 + else if (speed == 2)
  214 + speed_s = "3";
  215 + else
  216 + speed_s = "?";
  217 +
  218 + pci_read_config_word(pdev, 0x0a, &cc);
  219 + if (cc == 0x0101)
  220 + scc_s = "IDE";
  221 + else if (cc == 0x0106)
  222 + scc_s = "SATA";
  223 + else if (cc == 0x0104)
  224 + scc_s = "RAID";
  225 + else
  226 + scc_s = "unknown";
  227 +
  228 + printf("AHCI %02x%02x.%02x%02x "
  229 + "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
  230 + (vers >> 24) & 0xff,
  231 + (vers >> 16) & 0xff,
  232 + (vers >> 8) & 0xff,
  233 + vers & 0xff,
  234 + ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
  235 +
  236 + printf("flags: "
  237 + "%s%s%s%s%s%s"
  238 + "%s%s%s%s%s%s%s\n",
  239 + cap & (1 << 31) ? "64bit " : "",
  240 + cap & (1 << 30) ? "ncq " : "",
  241 + cap & (1 << 28) ? "ilck " : "",
  242 + cap & (1 << 27) ? "stag " : "",
  243 + cap & (1 << 26) ? "pm " : "",
  244 + cap & (1 << 25) ? "led " : "",
  245 + cap & (1 << 24) ? "clo " : "",
  246 + cap & (1 << 19) ? "nz " : "",
  247 + cap & (1 << 18) ? "only " : "",
  248 + cap & (1 << 17) ? "pmp " : "",
  249 + cap & (1 << 15) ? "pio " : "",
  250 + cap & (1 << 14) ? "slum " : "",
  251 + cap & (1 << 13) ? "part " : "");
  252 +}
  253 +
  254 +static int ahci_init_one(pci_dev_t pdev)
  255 +{
  256 + u32 iobase;
  257 + u16 vendor;
  258 + int rc;
  259 +
  260 + memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS);
  261 +
  262 + probe_ent = malloc(sizeof(struct ahci_probe_ent));
  263 + memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
  264 + probe_ent->dev = pdev;
  265 +
  266 + pci_read_config_dword(pdev, AHCI_PCI_BAR, &iobase);
  267 + iobase &= ~0xf;
  268 +
  269 + probe_ent->host_flags = ATA_FLAG_SATA
  270 + | ATA_FLAG_NO_LEGACY
  271 + | ATA_FLAG_MMIO
  272 + | ATA_FLAG_PIO_DMA
  273 + | ATA_FLAG_NO_ATAPI;
  274 + probe_ent->pio_mask = 0x1f;
  275 + probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
  276 +
  277 + probe_ent->mmio_base = iobase;
  278 +
  279 + /* Take from kernel:
  280 + * JMicron-specific fixup:
  281 + * make sure we're in AHCI mode
  282 + */
  283 + pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
  284 + if (vendor == 0x197b)
  285 + pci_write_config_byte(pdev, 0x41, 0xa1);
  286 +
  287 + /* initialize adapter */
  288 + rc = ahci_host_init(probe_ent);
  289 + if (rc)
  290 + goto err_out;
  291 +
  292 + ahci_print_info(probe_ent);
  293 +
  294 + return 0;
  295 +
  296 + err_out:
  297 + return rc;
  298 +}
  299 +
  300 +
  301 +#define MAX_DATA_BYTE_COUNT (4*1024*1024)
  302 +
  303 +static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len)
  304 +{
  305 + struct ahci_ioports *pp = &(probe_ent->port[port]);
  306 + struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
  307 + u32 sg_count;
  308 + int i;
  309 +
  310 + sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
  311 + if (sg_count > AHCI_MAX_SG) {
  312 + printf("Error:Too much sg!\n");
  313 + return -1;
  314 + }
  315 +
  316 + for (i = 0; i < sg_count; i++) {
  317 + ahci_sg->addr =
  318 + cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT);
  319 + ahci_sg->addr_hi = 0;
  320 + ahci_sg->flags_size = cpu_to_le32(0x3fffff &
  321 + (buf_len < MAX_DATA_BYTE_COUNT
  322 + ? (buf_len - 1)
  323 + : (MAX_DATA_BYTE_COUNT - 1)));
  324 + ahci_sg++;
  325 + buf_len -= MAX_DATA_BYTE_COUNT;
  326 + }
  327 +
  328 + return sg_count;
  329 +}
  330 +
  331 +
  332 +static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
  333 +{
  334 + pp->cmd_slot->opts = cpu_to_le32(opts);
  335 + pp->cmd_slot->status = 0;
  336 + pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff);
  337 + pp->cmd_slot->tbl_addr_hi = 0;
  338 +}
  339 +
  340 +
  341 +static void ahci_set_feature(u8 port)
  342 +{
  343 + struct ahci_ioports *pp = &(probe_ent->port[port]);
  344 + volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
  345 + u32 cmd_fis_len = 5; /* five dwords */
  346 + u8 fis[20];
  347 +
  348 + /*set feature */
  349 + memset(fis, 0, 20);
  350 + fis[0] = 0x27;
  351 + fis[1] = 1 << 7;
  352 + fis[2] = ATA_CMD_SETF;
  353 + fis[3] = SETFEATURES_XFER;
  354 + fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01;
  355 +
  356 + memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
  357 + ahci_fill_cmd_slot(pp, cmd_fis_len);
  358 + writel(1, port_mmio + PORT_CMD_ISSUE);
  359 + readl(port_mmio + PORT_CMD_ISSUE);
  360 +
  361 + if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) {
  362 + printf("set feature error!\n");
  363 + }
  364 +}
  365 +
  366 +
  367 +static int ahci_port_start(u8 port)
  368 +{
  369 + struct ahci_ioports *pp = &(probe_ent->port[port]);
  370 + volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
  371 + u32 port_status;
  372 + u32 mem;
  373 +
  374 + debug("Enter start port: %d\n", port);
  375 + port_status = readl(port_mmio + PORT_SCR_STAT);
  376 + debug("Port %d status: %x\n", port, port_status);
  377 + if ((port_status & 0xf) != 0x03) {
  378 + printf("No Link on this port!\n");
  379 + return -1;
  380 + }
  381 +
  382 + mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);
  383 + if (!mem) {
  384 + free(pp);
  385 + printf("No mem for table!\n");
  386 + return -ENOMEM;
  387 + }
  388 +
  389 + mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */
  390 + memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ);
  391 +
  392 + /*
  393 + * First item in chunk of DMA memory: 32-slot command table,
  394 + * 32 bytes each in size
  395 + */
  396 + pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
  397 + debug("cmd_slot = 0x%x\n", pp->cmd_slot);
  398 + mem += (AHCI_CMD_SLOT_SZ + 224);
  399 +
  400 + /*
  401 + * Second item: Received-FIS area
  402 + */
  403 + pp->rx_fis = mem;
  404 + mem += AHCI_RX_FIS_SZ;
  405 +
  406 + /*
  407 + * Third item: data area for storing a single command
  408 + * and its scatter-gather table
  409 + */
  410 + pp->cmd_tbl = mem;
  411 + debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl);
  412 +
  413 + mem += AHCI_CMD_TBL_HDR;
  414 + pp->cmd_tbl_sg = (struct ahci_sg *)mem;
  415 +
  416 + writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR);
  417 +
  418 + writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
  419 +
  420 + writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
  421 + PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
  422 + PORT_CMD_START, port_mmio + PORT_CMD);
  423 +
  424 + debug("Exit start port %d\n", port);
  425 +
  426 + return 0;
  427 +}
  428 +
  429 +
  430 +static int get_ahci_device_data(u8 port, u8 *fis, int fis_len, u8 *buf,
  431 + int buf_len)
  432 +{
  433 +
  434 + struct ahci_ioports *pp = &(probe_ent->port[port]);
  435 + volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
  436 + u32 opts;
  437 + u32 port_status;
  438 + int sg_count;
  439 +
  440 + debug("Enter get_ahci_device_data: for port %d\n", port);
  441 +
  442 + if (port > probe_ent->n_ports) {
  443 + printf("Invaild port number %d\n", port);
  444 + return -1;
  445 + }
  446 +
  447 + port_status = readl(port_mmio + PORT_SCR_STAT);
  448 + if ((port_status & 0xf) != 0x03) {
  449 + debug("No Link on port %d!\n", port);
  450 + return -1;
  451 + }
  452 +
  453 + memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
  454 +
  455 + sg_count = ahci_fill_sg(port, buf, buf_len);
  456 + opts = (fis_len >> 2) | (sg_count << 16);
  457 + ahci_fill_cmd_slot(pp, opts);
  458 +
  459 + writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
  460 +
  461 + if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) {
  462 + printf("timeout exit!\n");
  463 + return -1;
  464 + }
  465 + debug("get_ahci_device_data: %d byte transferred.\n",
  466 + pp->cmd_slot->status);
  467 +
  468 + return 0;
  469 +}
  470 +
  471 +
  472 +static char *ata_id_strcpy(u16 *target, u16 *src, int len)
  473 +{
  474 + int i;
  475 + for (i = 0; i < len / 2; i++)
  476 + target[i] = le16_to_cpu(src[i]);
  477 + return (char *)target;
  478 +}
  479 +
  480 +
  481 +static void dump_ataid(hd_driveid_t *ataid)
  482 +{
  483 + debug("(49)ataid->capability = 0x%x\n", ataid->capability);
  484 + debug("(53)ataid->field_valid =0x%x\n", ataid->field_valid);
  485 + debug("(63)ataid->dma_mword = 0x%x\n", ataid->dma_mword);
  486 + debug("(64)ataid->eide_pio_modes = 0x%x\n", ataid->eide_pio_modes);
  487 + debug("(75)ataid->queue_depth = 0x%x\n", ataid->queue_depth);
  488 + debug("(80)ataid->major_rev_num = 0x%x\n", ataid->major_rev_num);
  489 + debug("(81)ataid->minor_rev_num = 0x%x\n", ataid->minor_rev_num);
  490 + debug("(82)ataid->command_set_1 = 0x%x\n", ataid->command_set_1);
  491 + debug("(83)ataid->command_set_2 = 0x%x\n", ataid->command_set_2);
  492 + debug("(84)ataid->cfsse = 0x%x\n", ataid->cfsse);
  493 + debug("(85)ataid->cfs_enable_1 = 0x%x\n", ataid->cfs_enable_1);
  494 + debug("(86)ataid->cfs_enable_2 = 0x%x\n", ataid->cfs_enable_2);
  495 + debug("(87)ataid->csf_default = 0x%x\n", ataid->csf_default);
  496 + debug("(88)ataid->dma_ultra = 0x%x\n", ataid->dma_ultra);
  497 + debug("(93)ataid->hw_config = 0x%x\n", ataid->hw_config);
  498 +}
  499 +
  500 +
  501 +/*
  502 + * SCSI INQUIRY command operation.
  503 + */
  504 +static int ata_scsiop_inquiry(ccb *pccb)
  505 +{
  506 + u8 hdr[] = {
  507 + 0,
  508 + 0,
  509 + 0x5, /* claim SPC-3 version compatibility */
  510 + 2,
  511 + 95 - 4,
  512 + };
  513 + u8 fis[20];
  514 + u8 *tmpid;
  515 + u8 port;
  516 +
  517 + /* Clean ccb data buffer */
  518 + memset(pccb->pdata, 0, pccb->datalen);
  519 +
  520 + memcpy(pccb->pdata, hdr, sizeof(hdr));
  521 +
  522 + if (pccb->datalen <= 35)
  523 + return 0;
  524 +
  525 + memset(fis, 0, 20);
  526 + /* Construct the FIS */
  527 + fis[0] = 0x27; /* Host to device FIS. */
  528 + fis[1] = 1 << 7; /* Command FIS. */
  529 + fis[2] = ATA_CMD_IDENT; /* Command byte. */
  530 +
  531 + /* Read id from sata */
  532 + port = pccb->target;
  533 + if (!(tmpid = malloc(sizeof(hd_driveid_t))))
  534 + return -ENOMEM;
  535 +
  536 + if (get_ahci_device_data(port, (u8 *) & fis, 20,
  537 + tmpid, sizeof(hd_driveid_t))) {
  538 + debug("scsi_ahci: SCSI inquiry command failure.\n");
  539 + return -EIO;
  540 + }
  541 +
  542 + if (ataid[port])
  543 + free(ataid[port]);
  544 + ataid[port] = (hd_driveid_t *) tmpid;
  545 +
  546 + memcpy(&pccb->pdata[8], "ATA ", 8);
  547 + ata_id_strcpy((u16 *) &pccb->pdata[16], (u16 *)ataid[port]->model, 16);
  548 + ata_id_strcpy((u16 *) &pccb->pdata[32], (u16 *)ataid[port]->fw_rev, 4);
  549 +
  550 + dump_ataid(ataid[port]);
  551 + return 0;
  552 +}
  553 +
  554 +
  555 +/*
  556 + * SCSI READ10 command operation.
  557 + */
  558 +static int ata_scsiop_read10(ccb * pccb)
  559 +{
  560 + u64 lba = 0;
  561 + u32 len = 0;
  562 + u8 fis[20];
  563 +
  564 + lba = (((u64) pccb->cmd[2]) << 24) | (((u64) pccb->cmd[3]) << 16)
  565 + | (((u64) pccb->cmd[4]) << 8) | ((u64) pccb->cmd[5]);
  566 + len = (((u32) pccb->cmd[7]) << 8) | ((u32) pccb->cmd[8]);
  567 +
  568 + /* For 10-byte and 16-byte SCSI R/W commands, transfer
  569 + * length 0 means transfer 0 block of data.
  570 + * However, for ATA R/W commands, sector count 0 means
  571 + * 256 or 65536 sectors, not 0 sectors as in SCSI.
  572 + *
  573 + * WARNING: one or two older ATA drives treat 0 as 0...
  574 + */
  575 + if (!len)
  576 + return 0;
  577 + memset(fis, 0, 20);
  578 +
  579 + /* Construct the FIS */
  580 + fis[0] = 0x27; /* Host to device FIS. */
  581 + fis[1] = 1 << 7; /* Command FIS. */
  582 + fis[2] = ATA_CMD_RD_DMA; /* Command byte. */
  583 +
  584 + /* LBA address, only support LBA28 in this driver */
  585 + fis[4] = pccb->cmd[5];
  586 + fis[5] = pccb->cmd[4];
  587 + fis[6] = pccb->cmd[3];
  588 + fis[7] = (pccb->cmd[2] & 0x0f) | 0xe0;
  589 +
  590 + /* Sector Count */
  591 + fis[12] = pccb->cmd[8];
  592 + fis[13] = pccb->cmd[7];
  593 +
  594 + /* Read from ahci */
  595 + if (get_ahci_device_data(pccb->target, (u8 *) & fis, 20,
  596 + pccb->pdata, pccb->datalen)) {
  597 + debug("scsi_ahci: SCSI READ10 command failure.\n");
  598 + return -EIO;
  599 + }
  600 +
  601 + return 0;
  602 +}
  603 +
  604 +
  605 +/*
  606 + * SCSI READ CAPACITY10 command operation.
  607 + */
  608 +static int ata_scsiop_read_capacity10(ccb *pccb)
  609 +{
  610 + u8 buf[8];
  611 +
  612 + if (!ataid[pccb->target]) {
  613 + printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
  614 + "\tNo ATA info!\n"
  615 + "\tPlease run SCSI commmand INQUIRY firstly!\n");
  616 + return -EPERM;
  617 + }
  618 +
  619 + memset(buf, 0, 8);
  620 +
  621 + *(u32 *) buf = le32_to_cpu(ataid[pccb->target]->lba_capacity);
  622 +
  623 + buf[6] = 512 >> 8;
  624 + buf[7] = 512 & 0xff;
  625 +
  626 + memcpy(pccb->pdata, buf, 8);
  627 +
  628 + return 0;
  629 +}
  630 +
  631 +
  632 +/*
  633 + * SCSI TEST UNIT READY command operation.
  634 + */
  635 +static int ata_scsiop_test_unit_ready(ccb *pccb)
  636 +{
  637 + return (ataid[pccb->target]) ? 0 : -EPERM;
  638 +}
  639 +
  640 +
  641 +int scsi_exec(ccb *pccb)
  642 +{
  643 + int ret;
  644 +
  645 + switch (pccb->cmd[0]) {
  646 + case SCSI_READ10:
  647 + ret = ata_scsiop_read10(pccb);
  648 + break;
  649 + case SCSI_RD_CAPAC:
  650 + ret = ata_scsiop_read_capacity10(pccb);
  651 + break;
  652 + case SCSI_TST_U_RDY:
  653 + ret = ata_scsiop_test_unit_ready(pccb);
  654 + break;
  655 + case SCSI_INQUIRY:
  656 + ret = ata_scsiop_inquiry(pccb);
  657 + break;
  658 + default:
  659 + printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
  660 + return FALSE;
  661 + }
  662 +
  663 + if (ret) {
  664 + debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
  665 + return FALSE;
  666 + }
  667 + return TRUE;
  668 +
  669 +}
  670 +
  671 +
  672 +void scsi_low_level_init(int busdevfunc)
  673 +{
  674 + int i;
  675 + u32 linkmap;
  676 +
  677 + ahci_init_one(busdevfunc);
  678 +
  679 + linkmap = probe_ent->link_port_map;
  680 +
  681 + for (i = 0; i < CFG_SCSI_MAX_SCSI_ID; i++) {
  682 + if (((linkmap >> i) & 0x01)) {
  683 + if (ahci_port_start((u8) i)) {
  684 + printf("Can not start port %d\n", i);
  685 + continue;
  686 + }
  687 + ahci_set_feature((u8) i);
  688 + }
  689 + }
  690 +}
  691 +
  692 +
  693 +void scsi_bus_reset(void)
  694 +{
  695 + /*Not implement*/
  696 +}
  697 +
  698 +
  699 +void scsi_print_error(ccb * pccb)
  700 +{
  701 + /*The ahci error info can be read in the ahci driver*/
  702 +}
  703 +#endif
drivers/block/ata_piix.c
Diff comments   View file @ 33daf5b
  1 +/*
  2 + * Copyright (C) Procsys. All rights reserved.
  3 + * Author: Mushtaq Khan <mushtaq_k@procsys.com>
  4 + * <mushtaqk_921@yahoo.co.in>
  5 + *
  6 + * This program is free software; you can redistribute it and/or
  7 + * modify it under the terms of the GNU General Public License as
  8 + * published by the Free Software Foundation; either version 2 of
  9 + * the License, or (at your option) any later version.
  10 + *
  11 + * This program is distributed in the hope that it will be useful,
  12 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14 + * GNU General Public License for more details.
  15 + *
  16 + * You should have received a copy of the GNU General Public License
  17 + * along with this program; if not, write to the Free Software
  18 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19 + * MA 02111-1307 USA
  20 + *
  21 + * with the reference to ata_piix driver in kernel 2.4.32
  22 + */
  23 +
  24 +/*
  25 + * This file contains SATA controller and SATA drive initialization functions
  26 + */
  27 +
  28 +#include <common.h>
  29 +#include <pci.h>
  30 +#include <command.h>
  31 +#include <config.h>
  32 +#include <asm/byteorder.h>
  33 +#include <ide.h>
  34 +#include <ata.h>
  35 +
  36 +#ifdef CFG_ATA_PIIX /*ata_piix driver */
  37 +
  38 +#define DEBUG_SATA 0 /*For debug prints set DEBUG_SATA to 1 */
  39 +
  40 +#define DRV_DECL /*For file specific declarations */
  41 +#include <sata.h>
  42 +#undef DRV_DECL
  43 +
  44 +/*Macros realted to PCI*/
  45 +#define PCI_SATA_BUS 0x00
  46 +#define PCI_SATA_DEV 0x1f
  47 +#define PCI_SATA_FUNC 0x02
  48 +
  49 +#define PCI_SATA_BASE1 0x10
  50 +#define PCI_SATA_BASE2 0x14
  51 +#define PCI_SATA_BASE3 0x18
  52 +#define PCI_SATA_BASE4 0x1c
  53 +#define PCI_SATA_BASE5 0x20
  54 +#define PCI_PMR 0x90
  55 +#define PCI_PI 0x09
  56 +#define PCI_PCS 0x92
  57 +#define PCI_DMA_CTL 0x48
  58 +
  59 +#define PORT_PRESENT (1<<0)
  60 +#define PORT_ENABLED (1<<4)
  61 +
  62 +u32 bdf;
  63 +u32 iobase1 = 0; /*Primary cmd block */
  64 +u32 iobase2 = 0; /*Primary ctl block */
  65 +u32 iobase3 = 0; /*Sec cmd block */
  66 +u32 iobase4 = 0; /*sec ctl block */
  67 +u32 iobase5 = 0; /*BMDMA*/
  68 +int
  69 +pci_sata_init (void)
  70 +{
  71 + u32 bus = PCI_SATA_BUS;
  72 + u32 dev = PCI_SATA_DEV;
  73 + u32 fun = PCI_SATA_FUNC;
  74 + u16 cmd = 0;
  75 + u8 lat = 0, pcibios_max_latency = 0xff;
  76 + u8 pmr; /*Port mapping reg */
  77 + u8 pi; /*Prgming Interface reg */
  78 +
  79 + bdf = PCI_BDF (bus, dev, fun);
  80 + pci_read_config_dword (bdf, PCI_SATA_BASE1, &iobase1);
  81 + pci_read_config_dword (bdf, PCI_SATA_BASE2, &iobase2);
  82 + pci_read_config_dword (bdf, PCI_SATA_BASE3, &iobase3);
  83 + pci_read_config_dword (bdf, PCI_SATA_BASE4, &iobase4);
  84 + pci_read_config_dword (bdf, PCI_SATA_BASE5, &iobase5);
  85 +
  86 + if ((iobase1 == 0xFFFFFFFF) || (iobase2 == 0xFFFFFFFF) ||
  87 + (iobase3 == 0xFFFFFFFF) || (iobase4 == 0xFFFFFFFF) ||
  88 + (iobase5 == 0xFFFFFFFF)) {
  89 + printf ("error no base addr for SATA controller\n");
  90 + return 1;
  91 + /*ERROR*/}
  92 +
  93 + iobase1 &= 0xFFFFFFFE;
  94 + iobase2 &= 0xFFFFFFFE;
  95 + iobase3 &= 0xFFFFFFFE;
  96 + iobase4 &= 0xFFFFFFFE;
  97 + iobase5 &= 0xFFFFFFFE;
  98 +
  99 + /*check for mode */
  100 + pci_read_config_byte (bdf, PCI_PMR, &pmr);
  101 + if (pmr > 1) {
  102 + printf ("combined mode not supported\n");
  103 + return 1;
  104 + }
  105 +
  106 + pci_read_config_byte (bdf, PCI_PI, &pi);
  107 + if ((pi & 0x05) != 0x05) {
  108 + printf ("Sata is in Legacy mode\n");
  109 + return 1;
  110 + } else {
  111 + printf ("sata is in Native mode\n");
  112 + }
  113 +
  114 + /*MASTER CFG AND IO CFG */
  115 + pci_read_config_word (bdf, PCI_COMMAND, &cmd);
  116 + cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
  117 + pci_write_config_word (bdf, PCI_COMMAND, cmd);
  118 + pci_read_config_byte (dev, PCI_LATENCY_TIMER, &lat);
  119 +
  120 + if (lat < 16)
  121 + lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
  122 + else if (lat > pcibios_max_latency)
  123 + lat = pcibios_max_latency;
  124 + pci_write_config_byte (dev, PCI_LATENCY_TIMER, lat);
  125 +
  126 + return 0;
  127 +}
  128 +
  129 +int
  130 +sata_bus_probe (int port_no)
  131 +{
  132 + int orig_mask, mask;
  133 + u16 pcs;
  134 +
  135 + mask = (PORT_PRESENT << port_no);
  136 + pci_read_config_word (bdf, PCI_PCS, &pcs);
  137 + orig_mask = (int) pcs & 0xff;
  138 + if ((orig_mask & mask) != mask)
  139 + return 0;
  140 + else
  141 + return 1;
  142 +}
  143 +
  144 +int
  145 +init_sata (void)
  146 +{
  147 + u8 i, rv = 0;
  148 +
  149 + for (i = 0; i < CFG_SATA_MAXDEVICES; i++) {
  150 + sata_dev_desc[i].type = DEV_TYPE_UNKNOWN;
  151 + sata_dev_desc[i].if_type = IF_TYPE_IDE;
  152 + sata_dev_desc[i].dev = i;
  153 + sata_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
  154 + sata_dev_desc[i].blksz = 0;
  155 + sata_dev_desc[i].lba = 0;
  156 + sata_dev_desc[i].block_read = sata_read;
  157 + }
  158 +
  159 + rv = pci_sata_init ();
  160 + if (rv == 1) {
  161 + printf ("pci initialization failed\n");
  162 + return 1;
  163 + }
  164 +
  165 + port[0].port_no = 0;
  166 + port[0].ioaddr.cmd_addr = iobase1;
  167 + port[0].ioaddr.altstatus_addr = port[0].ioaddr.ctl_addr =
  168 + iobase2 | ATA_PCI_CTL_OFS;
  169 + port[0].ioaddr.bmdma_addr = iobase5;
  170 +
  171 + port[1].port_no = 1;
  172 + port[1].ioaddr.cmd_addr = iobase3;
  173 + port[1].ioaddr.altstatus_addr = port[1].ioaddr.ctl_addr =
  174 + iobase4 | ATA_PCI_CTL_OFS;
  175 + port[1].ioaddr.bmdma_addr = iobase5 + 0x8;
  176 +
  177 + for (i = 0; i < CFG_SATA_MAXBUS; i++)
  178 + sata_port (&port[i].ioaddr);
  179 +
  180 + for (i = 0; i < CFG_SATA_MAXBUS; i++) {
  181 + if (!(sata_bus_probe (i))) {
  182 + port[i].port_state = 0;
  183 + printf ("SATA#%d port is not present \n", i);
  184 + } else {
  185 + printf ("SATA#%d port is present\n", i);
  186 + if (sata_bus_softreset (i)) {
  187 + port[i].port_state = 0;
  188 + } else {
  189 + port[i].port_state = 1;
  190 + }
  191 + }
  192 + }
  193 +
  194 + for (i = 0; i < CFG_SATA_MAXBUS; i++) {
  195 + u8 j, devno;
  196 +
  197 + if (port[i].port_state == 0)
  198 + continue;
  199 + for (j = 0; j < CFG_SATA_DEVS_PER_BUS; j++) {
  200 + sata_identify (i, j);
  201 + set_Feature_cmd (i, j);
  202 + devno = i * CFG_SATA_DEVS_PER_BUS + j;
  203 + if ((sata_dev_desc[devno].lba > 0) &&
  204 + (sata_dev_desc[devno].blksz > 0)) {
  205 + dev_print (&sata_dev_desc[devno]);
  206 + /* initialize partition type */
  207 + init_part (&sata_dev_desc[devno]);
  208 + if (curr_dev < 0)
  209 + curr_dev =
  210 + i * CFG_SATA_DEVS_PER_BUS + j;
  211 + }
  212 + }
  213 + }
  214 + return 0;
  215 +}
  216 +#endif
drivers/block/sil680.c
Diff comments   View file @ 33daf5b
  1 +/*
  2 + * (C) Copyright 2007
  3 + * Gary Jennejohn, DENX Software Engineering, garyj@denx.de.
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + *
  23 + */
  24 +/* sil680.c - ide support functions for the Sil0680A controller */
  25 +
  26 +/*
  27 + * The following parameters must be defined in the configuration file
  28 + * of the target board:
  29 + *
  30 + * #define CFG_IDE_SIL680
  31 + *
  32 + * #define CONFIG_PCI_PNP
  33 + * NOTE it may also be necessary to define this if the default of 8 is
  34 + * incorrect for the target board (e.g. the sequoia board requires 0).
  35 + * #define CFG_PCI_CACHE_LINE_SIZE 0
  36 + *
  37 + * #define CONFIG_CMD_IDE
  38 + * #undef CONFIG_IDE_8xx_DIRECT
  39 + * #undef CONFIG_IDE_LED
  40 + * #undef CONFIG_IDE_RESET
  41 + * #define CONFIG_IDE_PREINIT
  42 + * #define CFG_IDE_MAXBUS 2 - modify to suit
  43 + * #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) - modify to suit
  44 + * #define CFG_ATA_BASE_ADDR 0
  45 + * #define CFG_ATA_IDE0_OFFSET 0
  46 + * #define CFG_ATA_IDE1_OFFSET 0
  47 + * #define CFG_ATA_DATA_OFFSET 0
  48 + * #define CFG_ATA_REG_OFFSET 0
  49 + * #define CFG_ATA_ALT_OFFSET 0x0004
  50 + *
  51 + * The mapping for PCI IO-space.
  52 + * NOTE this is the value for the sequoia board. Modify to suit.
  53 + * #define CFG_PCI0_IO_SPACE 0xE8000000
  54 + */
  55 +
  56 +#include <common.h>
  57 +#if defined(CFG_IDE_SIL680)
  58 +#include <ata.h>
  59 +#include <ide.h>
  60 +#include <pci.h>
  61 +
  62 +extern ulong ide_bus_offset[CFG_IDE_MAXBUS];
  63 +
  64 +int ide_preinit (void)
  65 +{
  66 + int status;
  67 + pci_dev_t devbusfn;
  68 + int l;
  69 +
  70 + status = 1;
  71 + for (l = 0; l < CFG_IDE_MAXBUS; l++) {
  72 + ide_bus_offset[l] = -ATA_STATUS;
  73 + }
  74 + devbusfn = pci_find_device (0x1095, 0x0680, 0);
  75 + if (devbusfn != -1) {
  76 + status = 0;
  77 +
  78 + pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0,
  79 + (u32 *) &ide_bus_offset[0]);
  80 + ide_bus_offset[0] &= 0xfffffff8;
  81 + ide_bus_offset[0] += CFG_PCI0_IO_SPACE;
  82 + pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_2,
  83 + (u32 *) &ide_bus_offset[1]);
  84 + ide_bus_offset[1] &= 0xfffffff8;
  85 + ide_bus_offset[1] += CFG_PCI0_IO_SPACE;
  86 + /* init various things - taken from the Linux driver */
  87 + /* set PIO mode */
  88 + pci_write_config_byte(devbusfn, 0x80, 0x00);
  89 + pci_write_config_byte(devbusfn, 0x84, 0x00);
  90 + /* IDE0 */
  91 + pci_write_config_byte(devbusfn, 0xA1, 0x02);
  92 + pci_write_config_word(devbusfn, 0xA2, 0x328A);
  93 + pci_write_config_dword(devbusfn, 0xA4, 0x62DD62DD);
  94 + pci_write_config_dword(devbusfn, 0xA8, 0x43924392);
  95 + pci_write_config_dword(devbusfn, 0xAC, 0x40094009);
  96 + /* IDE1 */
  97 + pci_write_config_byte(devbusfn, 0xB1, 0x02);
  98 + pci_write_config_word(devbusfn, 0xB2, 0x328A);
  99 + pci_write_config_dword(devbusfn, 0xB4, 0x62DD62DD);
  100 + pci_write_config_dword(devbusfn, 0xB8, 0x43924392);
  101 + pci_write_config_dword(devbusfn, 0xBC, 0x40094009);
  102 + }
  103 + return (status);
  104 +}
  105 +
  106 +void ide_set_reset (int flag) {
  107 + return;
  108 +}
  109 +
  110 +#endif /* CFG_IDE_SIL680 */
drivers/block/sym53c8xx.c
Diff comments   View file @ 33daf5b
  1 +/*
  2 + * (C) Copyright 2001
  3 + * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch.
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + * partly derived from
  23 + * linux/drivers/scsi/sym53c8xx.c
  24 + *
  25 + */
  26 +
  27 +/*
  28 + * SCSI support based on the chip sym53C810.
  29 + *
  30 + * 09-19-2001 Andreas Heppel, Sysgo RTS GmbH <aheppel@sysgo.de>
  31 + * The local version of this driver for the BAB750 board does not
  32 + * use interrupts but polls the chip instead (see the call of
  33 + * 'handle_scsi_int()' in 'scsi_issue()'.
  34 + */
  35 +
  36 +#include <common.h>
  37 +
  38 +#ifdef CONFIG_SCSI_SYM53C8XX
  39 +
  40 +#include <command.h>
  41 +#include <pci.h>
  42 +#include <asm/processor.h>
  43 +#include <sym53c8xx.h>
  44 +#include <scsi.h>
  45 +
  46 +#undef SYM53C8XX_DEBUG
  47 +
  48 +#ifdef SYM53C8XX_DEBUG
  49 +#define PRINTF(fmt,args...) printf (fmt ,##args)
  50 +#else
  51 +#define PRINTF(fmt,args...)
  52 +#endif
  53 +
  54 +#if defined(CONFIG_CMD_SCSI) && defined(CONFIG_SCSI_SYM53C8XX)
  55 +
  56 +#undef SCSI_SINGLE_STEP
  57 +/*
  58 + * Single Step is only used for debug purposes
  59 + */
  60 +#ifdef SCSI_SINGLE_STEP
  61 +static unsigned long start_script_select;
  62 +static unsigned long start_script_msgout;
  63 +static unsigned long start_script_msgin;
  64 +static unsigned long start_script_msg_ext;
  65 +static unsigned long start_script_cmd;
  66 +static unsigned long start_script_data_in;
  67 +static unsigned long start_script_data_out;
  68 +static unsigned long start_script_status;
  69 +static unsigned long start_script_complete;
  70 +static unsigned long start_script_error;
  71 +static unsigned long start_script_reselection;
  72 +static unsigned int len_script_select;
  73 +static unsigned int len_script_msgout;
  74 +static unsigned int len_script_msgin;
  75 +static unsigned int len_script_msg_ext;
  76 +static unsigned int len_script_cmd;
  77 +static unsigned int len_script_data_in;
  78 +static unsigned int len_script_data_out;
  79 +static unsigned int len_script_status;
  80 +static unsigned int len_script_complete;
  81 +static unsigned int len_script_error;
  82 +static unsigned int len_script_reselection;
  83 +#endif
  84 +
  85 +
  86 +static unsigned short scsi_int_mask; /* shadow register for SCSI related interrupts */
  87 +static unsigned char script_int_mask; /* shadow register for SCRIPT related interrupts */
  88 +static unsigned long script_select[8]; /* script for selection */
  89 +static unsigned long script_msgout[8]; /* script for message out phase (NOT USED) */
  90 +static unsigned long script_msgin[14]; /* script for message in phase */
  91 +static unsigned long script_msg_ext[32]; /* script for message in phase when more than 1 byte message */
  92 +static unsigned long script_cmd[18]; /* script for command phase */
  93 +static unsigned long script_data_in[8]; /* script for data in phase */
  94 +static unsigned long script_data_out[8]; /* script for data out phase */
  95 +static unsigned long script_status[6]; /* script for status phase */
  96 +static unsigned long script_complete[10]; /* script for complete */
  97 +static unsigned long script_reselection[4]; /* script for reselection (NOT USED) */
  98 +static unsigned long script_error[2]; /* script for error handling */
  99 +
  100 +static unsigned long int_stat[3]; /* interrupt status */
  101 +static unsigned long scsi_mem_addr; /* base memory address =SCSI_MEM_ADDRESS; */
  102 +
  103 +#define bus_to_phys(a) pci_mem_to_phys(busdevfunc, (unsigned long) (a))
  104 +#define phys_to_bus(a) pci_phys_to_mem(busdevfunc, (unsigned long) (a))
  105 +
  106 +#define SCSI_MAX_RETRY 3 /* number of retries in scsi_issue() */
  107 +
  108 +#define SCSI_MAX_RETRY_NOT_READY 10 /* number of retries when device is not ready */
  109 +#define SCSI_NOT_READY_TIME_OUT 500 /* timeout per retry when not ready */
  110 +
  111 +/*********************************************************************************
  112 + * forward declerations
  113 + */
  114 +
  115 +void scsi_chip_init(void);
  116 +void handle_scsi_int(void);
  117 +
  118 +
  119 +/********************************************************************************
  120 + * reports SCSI errors to the user
  121 + */
  122 +void scsi_print_error(ccb *pccb)
  123 +{
  124 + int i;
  125 + printf("SCSI Error: Target %d LUN %d Command %02X\n",pccb->target, pccb->lun, pccb->cmd[0]);
  126 + printf(" CCB: ");
  127 + for(i=0;i<pccb->cmdlen;i++)
  128 + printf("%02X ",pccb->cmd[i]);
  129 + printf("(len=%d)\n",pccb->cmdlen);
  130 + printf(" Cntrl: ");
  131 + switch(pccb->contr_stat) {
  132 + case SIR_COMPLETE: printf("Complete (no Error)\n"); break;
  133 + case SIR_SEL_ATN_NO_MSG_OUT: printf("Selected with ATN no MSG out phase\n"); break;
  134 + case SIR_CMD_OUT_ILL_PH: printf("Command out illegal phase\n"); break;
  135 + case SIR_MSG_RECEIVED: printf("MSG received Error\n"); break;
  136 + case SIR_DATA_IN_ERR: printf("Data in Error\n"); break;
  137 + case SIR_DATA_OUT_ERR: printf("Data out Error\n"); break;
  138 + case SIR_SCRIPT_ERROR: printf("Script Error\n"); break;
  139 + case SIR_MSG_OUT_NO_CMD: printf("MSG out no Command phase\n"); break;
  140 + case SIR_MSG_OVER7: printf("MSG in over 7 bytes\n"); break;
  141 + case INT_ON_FY: printf("Interrupt on fly\n"); break;
  142 + case SCSI_SEL_TIME_OUT: printf("SCSI Selection Timeout\n"); break;
  143 + case SCSI_HNS_TIME_OUT: printf("SCSI Handshake Timeout\n"); break;
  144 + case SCSI_MA_TIME_OUT: printf("SCSI Phase Error\n"); break;
  145 + case SCSI_UNEXP_DIS: printf("SCSI unexpected disconnect\n"); break;
  146 + default: printf("unknown status %lx\n",pccb->contr_stat); break;
  147 + }
  148 + printf(" Sense: SK %x (",pccb->sense_buf[2]&0x0f);
  149 + switch(pccb->sense_buf[2]&0xf) {
  150 + case SENSE_NO_SENSE: printf("No Sense)"); break;
  151 + case SENSE_RECOVERED_ERROR: printf("Recovered Error)"); break;
  152 + case SENSE_NOT_READY: printf("Not Ready)"); break;
  153 + case SENSE_MEDIUM_ERROR: printf("Medium Error)"); break;
  154 + case SENSE_HARDWARE_ERROR: printf("Hardware Error)"); break;
  155 + case SENSE_ILLEGAL_REQUEST: printf("Illegal request)"); break;
  156 + case SENSE_UNIT_ATTENTION: printf("Unit Attention)"); break;
  157 + case SENSE_DATA_PROTECT: printf("Data Protect)"); break;
  158 + case SENSE_BLANK_CHECK: printf("Blank check)"); break;
  159 + case SENSE_VENDOR_SPECIFIC: printf("Vendor specific)"); break;
  160 + case SENSE_COPY_ABORTED: printf("Copy aborted)"); break;
  161 + case SENSE_ABORTED_COMMAND: printf("Aborted Command)"); break;
  162 + case SENSE_VOLUME_OVERFLOW: printf("Volume overflow)"); break;
  163 + case SENSE_MISCOMPARE: printf("Misscompare\n"); break;
  164 + default: printf("Illegal Sensecode\n"); break;
  165 + }
  166 + printf(" ASC %x ASCQ %x\n",pccb->sense_buf[12],pccb->sense_buf[13]);
  167 + printf(" Status: ");
  168 + switch(pccb->status) {
  169 + case S_GOOD : printf("Good\n"); break;
  170 + case S_CHECK_COND: printf("Check condition\n"); break;
  171 + case S_COND_MET: printf("Condition Met\n"); break;
  172 + case S_BUSY: printf("Busy\n"); break;
  173 + case S_INT: printf("Intermediate\n"); break;
  174 + case S_INT_COND_MET: printf("Intermediate condition met\n"); break;
  175 + case S_CONFLICT: printf("Reservation conflict\n"); break;
  176 + case S_TERMINATED: printf("Command terminated\n"); break;
  177 + case S_QUEUE_FULL: printf("Task set full\n"); break;
  178 + default: printf("unknown: %02X\n",pccb->status); break;
  179 + }
  180 +
  181 +}
  182 +
  183 +
  184 +/******************************************************************************
  185 + * sets-up the SCSI controller
  186 + * the base memory address is retrived via the pci_read_config_dword
  187 + */
  188 +void scsi_low_level_init(int busdevfunc)
  189 +{
  190 + unsigned int cmd;
  191 + unsigned int addr;
  192 + unsigned char vec;
  193 +
  194 + pci_read_config_byte(busdevfunc, PCI_INTERRUPT_LINE, &vec);
  195 + pci_read_config_dword(busdevfunc, PCI_BASE_ADDRESS_1, &addr);
  196 +
  197 + addr = bus_to_phys(addr & ~0xf);
  198 +
  199 + /*
  200 + * Enable bus mastering in case this has not been done, yet.
  201 + */
  202 + pci_read_config_dword(busdevfunc, PCI_COMMAND, &cmd);
  203 + cmd |= PCI_COMMAND_MASTER;
  204 + pci_write_config_dword(busdevfunc, PCI_COMMAND, cmd);
  205 +
  206 + scsi_mem_addr = addr;
  207 +
  208 + scsi_chip_init();
  209 + scsi_bus_reset();
  210 +}
  211 +
  212 +
  213 +/************************************************************************************
  214 + * Low level Part of SCSI Driver
  215 + */
  216 +
  217 +/*
  218 + * big-endian -> little endian conversion for the script
  219 + */
  220 +unsigned long swap_script(unsigned long val)
  221 +{
  222 + unsigned long tmp;
  223 + tmp = ((val>>24)&0xff) | ((val>>8)&0xff00) | ((val<<8)&0xff0000) | ((val<<24)&0xff000000);
  224 + return tmp;
  225 +}
  226 +
  227 +
  228 +void scsi_write_byte(ulong offset,unsigned char val)
  229 +{
  230 + out8(scsi_mem_addr+offset,val);
  231 +}
  232 +
  233 +
  234 +unsigned char scsi_read_byte(ulong offset)
  235 +{
  236 + return(in8(scsi_mem_addr+offset));
  237 +}
  238 +
  239 +
  240 +/********************************************************************************
  241 + * interrupt handler
  242 + */
  243 +void handle_scsi_int(void)
  244 +{
  245 + unsigned char stat,stat1,stat2;
  246 + unsigned short sstat;
  247 + int i;
  248 +#ifdef SCSI_SINGLE_STEP
  249 + unsigned long tt;
  250 +#endif
  251 + stat=scsi_read_byte(ISTAT);
  252 + if((stat & DIP)==DIP) { /* DMA Interrupt pending */
  253 + stat1=scsi_read_byte(DSTAT);
  254 +#ifdef SCSI_SINGLE_STEP
  255 + if((stat1 & SSI)==SSI)
  256 + {
  257 + tt=in32r(scsi_mem_addr+DSP);
  258 + if(((tt)>=start_script_select) && ((tt)<start_script_select+len_script_select)) {
  259 + printf("select %d\n",(tt-start_script_select)>>2);
  260 + goto end_single;
  261 + }
  262 + if(((tt)>=start_script_msgout) && ((tt)<start_script_msgout+len_script_msgout)) {
  263 + printf("msgout %d\n",(tt-start_script_msgout)>>2);
  264 + goto end_single;
  265 + }
  266 + if(((tt)>=start_script_msgin) && ((tt)<start_script_msgin+len_script_msgin)) {
  267 + printf("msgin %d\n",(tt-start_script_msgin)>>2);
  268 + goto end_single;
  269 + }
  270 + if(((tt)>=start_script_msg_ext) && ((tt)<start_script_msg_ext+len_script_msg_ext)) {
  271 + printf("msgin_ext %d\n",(tt-start_script_msg_ext)>>2);
  272 + goto end_single;
  273 + }
  274 + if(((tt)>=start_script_cmd) && ((tt)<start_script_cmd+len_script_cmd)) {
  275 + printf("cmd %d\n",(tt-start_script_cmd)>>2);
  276 + goto end_single;
  277 + }
  278 + if(((tt)>=start_script_data_in) && ((tt)<start_script_data_in+len_script_data_in)) {
  279 + printf("data_in %d\n",(tt-start_script_data_in)>>2);
  280 + goto end_single;
  281 + }
  282 + if(((tt)>=start_script_data_out) && ((tt)<start_script_data_out+len_script_data_out)) {
  283 + printf("data_out %d\n",(tt-start_script_data_out)>>2);
  284 + goto end_single;
  285 + }
  286 + if(((tt)>=start_script_status) && ((tt)<start_script_status+len_script_status)) {
  287 + printf("status %d\n",(tt-start_script_status)>>2);
  288 + goto end_single;
  289 + }
  290 + if(((tt)>=start_script_complete) && ((tt)<start_script_complete+len_script_complete)) {
  291 + printf("complete %d\n",(tt-start_script_complete)>>2);
  292 + goto end_single;
  293 + }
  294 + if(((tt)>=start_script_error) && ((tt)<start_script_error+len_script_error)) {
  295 + printf("error %d\n",(tt-start_script_error)>>2);
  296 + goto end_single;
  297 + }
  298 + if(((tt)>=start_script_reselection) && ((tt)<start_script_reselection+len_script_reselection)) {
  299 + printf("reselection %d\n",(tt-start_script_reselection)>>2);
  300 + goto end_single;
  301 + }
  302 + printf("sc: %lx\n",tt);
  303 +end_single:
  304 + stat2=scsi_read_byte(DCNTL);
  305 + stat2|=STD;
  306 + scsi_write_byte(DCNTL,stat2);
  307 + }
  308 +#endif
  309 + if((stat1 & SIR)==SIR) /* script interrupt */
  310 + {
  311 + int_stat[0]=in32(scsi_mem_addr+DSPS);
  312 + }
  313 + if((stat1 & DFE)==0) { /* fifo not epmty */
  314 + scsi_write_byte(CTEST3,CLF); /* Clear DMA FIFO */
  315 + stat2=scsi_read_byte(STEST3);
  316 + scsi_write_byte(STEST3,(stat2 | CSF)); /* Clear SCSI FIFO */
  317 + }
  318 + }
  319 + if((stat & SIP)==SIP) { /* scsi interrupt */
  320 + sstat = (unsigned short)scsi_read_byte(SIST+1);
  321 + sstat <<=8;
  322 + sstat |= (unsigned short)scsi_read_byte(SIST);
  323 + for(i=0;i<3;i++) {
  324 + if(int_stat[i]==0)
  325 + break; /* found an empty int status */
  326 + }
  327 + int_stat[i]=SCSI_INT_STATE | sstat;
  328 + stat1=scsi_read_byte(DSTAT);
  329 + if((stat1 & DFE)==0) { /* fifo not epmty */
  330 + scsi_write_byte(CTEST3,CLF); /* Clear DMA FIFO */
  331 + stat2=scsi_read_byte(STEST3);
  332 + scsi_write_byte(STEST3,(stat2 | CSF)); /* Clear SCSI FIFO */
  333 + }
  334 + }
  335 + if((stat & INTF)==INTF) { /* interrupt on Fly */
  336 + scsi_write_byte(ISTAT,stat); /* clear it */
  337 + for(i=0;i<3;i++) {
  338 + if(int_stat[i]==0)
  339 + break; /* found an empty int status */
  340 + }
  341 + int_stat[i]=INT_ON_FY;
  342 + }
  343 +}
  344 +
  345 +void scsi_bus_reset(void)
  346 +{
  347 + unsigned char t;
  348 + int i;
  349 + int end = CFG_SCSI_SPIN_UP_TIME*1000;
  350 +
  351 + t=scsi_read_byte(SCNTL1);
  352 + scsi_write_byte(SCNTL1,(t | CRST));
  353 + udelay(50);
  354 + scsi_write_byte(SCNTL1,t);
  355 +
  356 + puts("waiting for devices to spin up");
  357 + for(i=0;i<end;i++) {
  358 + udelay(1000); /* give the devices time to spin up */
  359 + if (i % 1000 == 0)
  360 + putc('.');
  361 + }
  362 + putc('\n');
  363 + scsi_chip_init(); /* reinit the chip ...*/
  364 +
  365 +}
  366 +
  367 +void scsi_int_enable(void)
  368 +{
  369 + scsi_write_byte(SIEN,(unsigned char)scsi_int_mask);
  370 + scsi_write_byte(SIEN+1,(unsigned char)(scsi_int_mask>>8));
  371 + scsi_write_byte(DIEN,script_int_mask);
  372 +}
  373 +
  374 +void scsi_write_dsp(unsigned long start)
  375 +{
  376 + unsigned long val;
  377 +#ifdef SCSI_SINGLE_STEP
  378 + unsigned char t;
  379 +#endif
  380 + val = start;
  381 + out32r(scsi_mem_addr + DSP,start);
  382 +#ifdef SCSI_SINGLE_STEP
  383 + t=scsi_read_byte(DCNTL);
  384 + t|=STD;
  385 + scsi_write_byte(DCNTL,t);
  386 +#endif
  387 +}
  388 +
  389 +/* only used for debug purposes */
  390 +void scsi_print_script(void)
  391 +{
  392 + printf("script_select @ 0x%08lX\n",(unsigned long)&script_select[0]);
  393 + printf("script_msgout @ 0x%08lX\n",(unsigned long)&script_msgout[0]);
  394 + printf("script_msgin @ 0x%08lX\n",(unsigned long)&script_msgin[0]);
  395 + printf("script_msgext @ 0x%08lX\n",(unsigned long)&script_msg_ext[0]);
  396 + printf("script_cmd @ 0x%08lX\n",(unsigned long)&script_cmd[0]);
  397 + printf("script_data_in @ 0x%08lX\n",(unsigned long)&script_data_in[0]);
  398 + printf("script_data_out @ 0x%08lX\n",(unsigned long)&script_data_out[0]);
  399 + printf("script_status @ 0x%08lX\n",(unsigned long)&script_status[0]);
  400 + printf("script_complete @ 0x%08lX\n",(unsigned long)&script_complete[0]);
  401 + printf("script_error @ 0x%08lX\n",(unsigned long)&script_error[0]);
  402 +}
  403 +
  404 +
  405 +void scsi_set_script(ccb *pccb)
  406 +{
  407 + int busdevfunc = pccb->priv;
  408 + int i;
  409 + i=0;
  410 + script_select[i++]=swap_script(SCR_REG_REG(GPREG, SCR_AND, 0xfe));
  411 + script_select[i++]=0; /* LED ON */
  412 + script_select[i++]=swap_script(SCR_CLR(SCR_TRG)); /* select initiator mode */
  413 + script_select[i++]=0;
  414 + /* script_select[i++]=swap_script(SCR_SEL_ABS_ATN | pccb->target << 16); */
  415 + script_select[i++]=swap_script(SCR_SEL_ABS | pccb->target << 16);
  416 + script_select[i++]=swap_script(phys_to_bus(&script_cmd[4])); /* error handling */
  417 + script_select[i++]=swap_script(SCR_JUMP); /* next section */
  418 + /* script_select[i++]=swap_script((unsigned long)&script_msgout[0]); */ /* message out */
  419 + script_select[i++]=swap_script(phys_to_bus(&script_cmd[0])); /* command out */
  420 +
  421 +#ifdef SCSI_SINGLE_STEP
  422 + start_script_select=(unsigned long)&script_select[0];
  423 + len_script_select=i*4;
  424 +#endif
  425 +
  426 + i=0;
  427 + script_msgout[i++]=swap_script(SCR_INT ^ IFFALSE (WHEN (SCR_MSG_OUT)));
  428 + script_msgout[i++]=SIR_SEL_ATN_NO_MSG_OUT;
  429 + script_msgout[i++]=swap_script( SCR_MOVE_ABS(1) ^ SCR_MSG_OUT);
  430 + script_msgout[i++]=swap_script(phys_to_bus(&pccb->msgout[0]));
  431 + script_msgout[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_COMMAND))); /* if Command phase */
  432 + script_msgout[i++]=swap_script(phys_to_bus(&script_cmd[0])); /* switch to command */
  433 + script_msgout[i++]=swap_script(SCR_INT); /* interrupt if not */
  434 + script_msgout[i++]=SIR_MSG_OUT_NO_CMD;
  435 +
  436 +#ifdef SCSI_SINGLE_STEP
  437 + start_script_msgout=(unsigned long)&script_msgout[0];
  438 + len_script_msgout=i*4;
  439 +#endif
  440 + i=0;
  441 + script_cmd[i++]=swap_script(SCR_MOVE_ABS(pccb->cmdlen) ^ SCR_COMMAND);
  442 + script_cmd[i++]=swap_script(phys_to_bus(&pccb->cmd[0]));
  443 + script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN))); /* message in ? */
  444 + script_cmd[i++]=swap_script(phys_to_bus(&script_msgin[0]));
  445 + script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_DATA_OUT))); /* data out ? */
  446 + script_cmd[i++]=swap_script(phys_to_bus(&script_data_out[0]));
  447 + script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_DATA_IN))); /* data in ? */
  448 + script_cmd[i++]=swap_script(phys_to_bus(&script_data_in[0]));
  449 + script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_STATUS))); /* status ? */
  450 + script_cmd[i++]=swap_script(phys_to_bus(&script_status[0]));
  451 + script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_COMMAND))); /* command ? */
  452 + script_cmd[i++]=swap_script(phys_to_bus(&script_cmd[0]));
  453 + script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_MSG_OUT))); /* message out ? */
  454 + script_cmd[i++]=swap_script(phys_to_bus(&script_msgout[0]));
  455 + script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_MSG_IN))); /* just for error handling message in ? */
  456 + script_cmd[i++]=swap_script(phys_to_bus(&script_msgin[0]));
  457 + script_cmd[i++]=swap_script(SCR_INT); /* interrupt if not */
  458 + script_cmd[i++]=SIR_CMD_OUT_ILL_PH;
  459 +#ifdef SCSI_SINGLE_STEP
  460 + start_script_cmd=(unsigned long)&script_cmd[0];
  461 + len_script_cmd=i*4;
  462 +#endif
  463 + i=0;
  464 + script_data_out[i++]=swap_script(SCR_MOVE_ABS(pccb->datalen)^ SCR_DATA_OUT); /* move */
  465 + script_data_out[i++]=swap_script(phys_to_bus(pccb->pdata)); /* pointer to buffer */
  466 + script_data_out[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS)));
  467 + script_data_out[i++]=swap_script(phys_to_bus(&script_status[0]));
  468 + script_data_out[i++]=swap_script(SCR_INT);
  469 + script_data_out[i++]=SIR_DATA_OUT_ERR;
  470 +
  471 +#ifdef SCSI_SINGLE_STEP
  472 + start_script_data_out=(unsigned long)&script_data_out[0];
  473 + len_script_data_out=i*4;
  474 +#endif
  475 + i=0;
  476 + script_data_in[i++]=swap_script(SCR_MOVE_ABS(pccb->datalen)^ SCR_DATA_IN); /* move */
  477 + script_data_in[i++]=swap_script(phys_to_bus(pccb->pdata)); /* pointer to buffer */
  478 + script_data_in[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS)));
  479 + script_data_in[i++]=swap_script(phys_to_bus(&script_status[0]));
  480 + script_data_in[i++]=swap_script(SCR_INT);
  481 + script_data_in[i++]=SIR_DATA_IN_ERR;
  482 +#ifdef SCSI_SINGLE_STEP
  483 + start_script_data_in=(unsigned long)&script_data_in[0];
  484 + len_script_data_in=i*4;
  485 +#endif
  486 + i=0;
  487 + script_msgin[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN);
  488 + script_msgin[i++]=swap_script(phys_to_bus(&pccb->msgin[0]));
  489 + script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_COMPLETE)));
  490 + script_msgin[i++]=swap_script(phys_to_bus(&script_complete[0]));
  491 + script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_DISCONNECT)));
  492 + script_msgin[i++]=swap_script(phys_to_bus(&script_complete[0]));
  493 + script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_SAVE_DP)));
  494 + script_msgin[i++]=swap_script(phys_to_bus(&script_complete[0]));
  495 + script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_RESTORE_DP)));
  496 + script_msgin[i++]=swap_script(phys_to_bus(&script_complete[0]));
  497 + script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_EXTENDED)));
  498 + script_msgin[i++]=swap_script(phys_to_bus(&script_msg_ext[0]));
  499 + script_msgin[i++]=swap_script(SCR_INT);
  500 + script_msgin[i++]=SIR_MSG_RECEIVED;
  501 +#ifdef SCSI_SINGLE_STEP
  502 + start_script_msgin=(unsigned long)&script_msgin[0];
  503 + len_script_msgin=i*4;
  504 +#endif
  505 + i=0;
  506 + script_msg_ext[i++]=swap_script(SCR_CLR (SCR_ACK)); /* clear ACK */
  507 + script_msg_ext[i++]=0;
  508 + script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* assuming this is the msg length */
  509 + script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[1]));
  510 + script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN)));
  511 + script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */
  512 + script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */
  513 + script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[2]));
  514 + script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN)));
  515 + script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */
  516 + script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */
  517 + script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[3]));
  518 + script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN)));
  519 + script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */
  520 + script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */
  521 + script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[4]));
  522 + script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN)));
  523 + script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */
  524 + script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */
  525 + script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[5]));
  526 + script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN)));
  527 + script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */
  528 + script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */
  529 + script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[6]));
  530 + script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN)));
  531 + script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */
  532 + script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */
  533 + script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[7]));
  534 + script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN)));
  535 + script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */
  536 + script_msg_ext[i++]=swap_script(SCR_INT);
  537 + script_msg_ext[i++]=SIR_MSG_OVER7;
  538 +#ifdef SCSI_SINGLE_STEP
  539 + start_script_msg_ext=(unsigned long)&script_msg_ext[0];
  540 + len_script_msg_ext=i*4;
  541 +#endif
  542 + i=0;
  543 + script_status[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_STATUS);
  544 + script_status[i++]=swap_script(phys_to_bus(&pccb->status));
  545 + script_status[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)));
  546 + script_status[i++]=swap_script(phys_to_bus(&script_msgin[0]));
  547 + script_status[i++]=swap_script(SCR_INT);
  548 + script_status[i++]=SIR_STATUS_ILL_PH;
  549 +#ifdef SCSI_SINGLE_STEP
  550 + start_script_status=(unsigned long)&script_status[0];
  551 + len_script_status=i*4;
  552 +#endif
  553 + i=0;
  554 + script_complete[i++]=swap_script(SCR_REG_REG (SCNTL2, SCR_AND, 0x7f));
  555 + script_complete[i++]=0;
  556 + script_complete[i++]=swap_script(SCR_CLR (SCR_ACK|SCR_ATN));
  557 + script_complete[i++]=0;
  558 + script_complete[i++]=swap_script(SCR_WAIT_DISC);
  559 + script_complete[i++]=0;
  560 + script_complete[i++]=swap_script(SCR_REG_REG(GPREG, SCR_OR, 0x01));
  561 + script_complete[i++]=0; /* LED OFF */
  562 + script_complete[i++]=swap_script(SCR_INT);
  563 + script_complete[i++]=SIR_COMPLETE;
  564 +#ifdef SCSI_SINGLE_STEP
  565 + start_script_complete=(unsigned long)&script_complete[0];
  566 + len_script_complete=i*4;
  567 +#endif
  568 + i=0;
  569 + script_error[i++]=swap_script(SCR_INT); /* interrupt if error */
  570 + script_error[i++]=SIR_SCRIPT_ERROR;
  571 +#ifdef SCSI_SINGLE_STEP
  572 + start_script_error=(unsigned long)&script_error[0];
  573 + len_script_error=i*4;
  574 +#endif
  575 + i=0;
  576 + script_reselection[i++]=swap_script(SCR_CLR (SCR_TRG)); /* target status */
  577 + script_reselection[i++]=0;
  578 + script_reselection[i++]=swap_script(SCR_WAIT_RESEL);
  579 + script_reselection[i++]=swap_script(phys_to_bus(&script_select[0])); /* len = 4 */
  580 +#ifdef SCSI_SINGLE_STEP
  581 + start_script_reselection=(unsigned long)&script_reselection[0];
  582 + len_script_reselection=i*4;
  583 +#endif
  584 +}
  585 +
  586 +
  587 +void scsi_issue(ccb *pccb)
  588 +{
  589 + int busdevfunc = pccb->priv;
  590 + int i;
  591 + unsigned short sstat;
  592 + int retrycnt; /* retry counter */
  593 + for(i=0;i<3;i++)
  594 + int_stat[i]=0; /* delete all int status */
  595 + /* struct pccb must be set-up correctly */
  596 + retrycnt=0;
  597 + PRINTF("ID %d issue cmd %02X\n",pccb->target,pccb->cmd[0]);
  598 + pccb->trans_bytes=0; /* no bytes transfered yet */
  599 + scsi_set_script(pccb); /* fill in SCRIPT */
  600 + scsi_int_mask=STO | UDC | MA; /* | CMP; / * Interrupts which are enabled */
  601 + script_int_mask=0xff; /* enable all Ints */
  602 + scsi_int_enable();
  603 + scsi_write_dsp(phys_to_bus(&script_select[0])); /* start script */
  604 + /* now we have to wait for IRQs */
  605 +retry:
  606 + /*
  607 + * This version of the driver is _not_ interrupt driven,
  608 + * but polls the chip's interrupt registers (ISTAT, DSTAT).
  609 + */
  610 + while(int_stat[0]==0)
  611 + handle_scsi_int();
  612 +
  613 + if(int_stat[0]==SIR_COMPLETE) {
  614 + if(pccb->msgin[0]==M_DISCONNECT) {
  615 + PRINTF("Wait for reselection\n");
  616 + for(i=0;i<3;i++)
  617 + int_stat[i]=0; /* delete all int status */
  618 + scsi_write_dsp(phys_to_bus(&script_reselection[0])); /* start reselection script */
  619 + goto retry;
  620 + }
  621 + pccb->contr_stat=SIR_COMPLETE;
  622 + return;
  623 + }
  624 + if((int_stat[0] & SCSI_INT_STATE)==SCSI_INT_STATE) { /* scsi interrupt */
  625 + sstat=(unsigned short)int_stat[0];
  626 + if((sstat & STO)==STO) { /* selection timeout */
  627 + pccb->contr_stat=SCSI_SEL_TIME_OUT;
  628 + scsi_write_byte(GPREG,0x01);
  629 + PRINTF("ID: %X Selection Timeout\n",pccb->target);
  630 + return;
  631 + }
  632 + if((sstat & UDC)==UDC) { /* unexpected disconnect */
  633 + pccb->contr_stat=SCSI_UNEXP_DIS;
  634 + scsi_write_byte(GPREG,0x01);
  635 + PRINTF("ID: %X Unexpected Disconnect\n",pccb->target);
  636 + return;
  637 + }
  638 + if((sstat & RSL)==RSL) { /* reselection */
  639 + pccb->contr_stat=SCSI_UNEXP_DIS;
  640 + scsi_write_byte(GPREG,0x01);
  641 + PRINTF("ID: %X Unexpected Disconnect\n",pccb->target);
  642 + return;
  643 + }
  644 + if(((sstat & MA)==MA)||((sstat & HTH)==HTH)) { /* phase missmatch */
  645 + if(retrycnt<SCSI_MAX_RETRY) {
  646 + pccb->trans_bytes=pccb->datalen -
  647 + ((unsigned long)scsi_read_byte(DBC) |
  648 + ((unsigned long)scsi_read_byte(DBC+1)<<8) |
  649 + ((unsigned long)scsi_read_byte(DBC+2)<<16));
  650 + for(i=0;i<3;i++)
  651 + int_stat[i]=0; /* delete all int status */
  652 + retrycnt++;
  653 + PRINTF("ID: %X Phase Missmatch Retry %d Phase %02X transfered %lx\n",
  654 + pccb->target,retrycnt,scsi_read_byte(SBCL),pccb->trans_bytes);
  655 + scsi_write_dsp(phys_to_bus(&script_cmd[4])); /* start retry script */
  656 + goto retry;
  657 + }
  658 + if((sstat & MA)==MA)
  659 + pccb->contr_stat=SCSI_MA_TIME_OUT;
  660 + else
  661 + pccb->contr_stat=SCSI_HNS_TIME_OUT;
  662 + PRINTF("Phase Missmatch stat %lx\n",pccb->contr_stat);
  663 + return;
  664 + } /* no phase int */
  665 +/* if((sstat & CMP)==CMP) {
  666 + pccb->contr_stat=SIR_COMPLETE;
  667 + return;
  668 + }
  669 +*/
  670 + PRINTF("SCSI INT %lX\n",int_stat[0]);
  671 + pccb->contr_stat=int_stat[0];
  672 + return;
  673 + } /* end scsi int */
  674 + PRINTF("SCRIPT INT %lX phase %02X\n",int_stat[0],scsi_read_byte(SBCL));
  675 + pccb->contr_stat=int_stat[0];
  676 + return;
  677 +}
  678 +
  679 +int scsi_exec(ccb *pccb)
  680 +{
  681 + unsigned char tmpcmd[16],tmpstat;
  682 + int i,retrycnt,t;
  683 + unsigned long transbytes,datalen;
  684 + unsigned char *tmpptr;
  685 + retrycnt=0;
  686 +retry:
  687 + scsi_issue(pccb);
  688 + if(pccb->contr_stat!=SIR_COMPLETE)
  689 + return FALSE;
  690 + if(pccb->status==S_GOOD)
  691 + return TRUE;
  692 + if(pccb->status==S_CHECK_COND) { /* check condition */
  693 + for(i=0;i<16;i++)
  694 + tmpcmd[i]=pccb->cmd[i];
  695 + pccb->cmd[0]=SCSI_REQ_SENSE;
  696 + pccb->cmd[1]=pccb->lun<<5;
  697 + pccb->cmd[2]=0;
  698 + pccb->cmd[3]=0;
  699 + pccb->cmd[4]=14;
  700 + pccb->cmd[5]=0;
  701 + pccb->cmdlen=6;
  702 + pccb->msgout[0]=SCSI_IDENTIFY;
  703 + transbytes=pccb->trans_bytes;
  704 + tmpptr=pccb->pdata;
  705 + pccb->pdata=&pccb->sense_buf[0];
  706 + datalen=pccb->datalen;
  707 + pccb->datalen=14;
  708 + tmpstat=pccb->status;
  709 + scsi_issue(pccb);
  710 + for(i=0;i<16;i++)
  711 + pccb->cmd[i]=tmpcmd[i];
  712 + pccb->trans_bytes=transbytes;
  713 + pccb->pdata=tmpptr;
  714 + pccb->datalen=datalen;
  715 + pccb->status=tmpstat;
  716 + PRINTF("Request_sense sense key %x ASC %x ASCQ %x\n",pccb->sense_buf[2]&0x0f,
  717 + pccb->sense_buf[12],pccb->sense_buf[13]);
  718 + switch(pccb->sense_buf[2]&0xf) {
  719 + case SENSE_NO_SENSE:
  720 + case SENSE_RECOVERED_ERROR:
  721 + /* seems to be ok */
  722 + return TRUE;
  723 + break;
  724 + case SENSE_NOT_READY:
  725 + if((pccb->sense_buf[12]!=0x04)||(pccb->sense_buf[13]!=0x01)) {
  726 + /* if device is not in process of becoming ready */
  727 + return FALSE;
  728 + break;
  729 + } /* else fall through */
  730 + case SENSE_UNIT_ATTENTION:
  731 + if(retrycnt<SCSI_MAX_RETRY_NOT_READY) {
  732 + PRINTF("Target %d not ready, retry %d\n",pccb->target,retrycnt);
  733 + for(t=0;t<SCSI_NOT_READY_TIME_OUT;t++)
  734 + udelay(1000); /* 1sec wait */
  735 + retrycnt++;
  736 + goto retry;
  737 + }
  738 + PRINTF("Target %d not ready, %d retried\n",pccb->target,retrycnt);
  739 + return FALSE;
  740 + default:
  741 + return FALSE;
  742 + }
  743 + }
  744 + PRINTF("Status = %X\n",pccb->status);
  745 + return FALSE;
  746 +}
  747 +
  748 +
  749 +void scsi_chip_init(void)
  750 +{
  751 + /* first we issue a soft reset */
  752 + scsi_write_byte(ISTAT,SRST);
  753 + udelay(1000);
  754 + scsi_write_byte(ISTAT,0);
  755 + /* setup chip */
  756 + scsi_write_byte(SCNTL0,0xC0); /* full arbitration no start, no message, parity disabled, master */
  757 + scsi_write_byte(SCNTL1,0x00);
  758 + scsi_write_byte(SCNTL2,0x00);
  759 +#ifndef CFG_SCSI_SYM53C8XX_CCF /* config value for none 40 mhz clocks */
  760 + scsi_write_byte(SCNTL3,0x13); /* synchronous clock 40/4=10MHz, asynchronous 40MHz */
  761 +#else
  762 + scsi_write_byte(SCNTL3,CFG_SCSI_SYM53C8XX_CCF); /* config value for none 40 mhz clocks */
  763 +#endif
  764 + scsi_write_byte(SCID,0x47); /* ID=7, enable reselection */
  765 + scsi_write_byte(SXFER,0x00); /* synchronous transfer period 10MHz, asynchronous */
  766 + scsi_write_byte(SDID,0x00); /* targed SCSI ID = 0 */
  767 + scsi_int_mask=0x0000; /* no Interrupt is enabled */
  768 + script_int_mask=0x00;
  769 + scsi_int_enable();
  770 + scsi_write_byte(GPREG,0x01); /* GPIO0 is LED (off) */
  771 + scsi_write_byte(GPCNTL,0x0E); /* GPIO0 is Output */
  772 + scsi_write_byte(STIME0,0x08); /* handshake timer disabled, selection timeout 512msec */
  773 + scsi_write_byte(RESPID,0x80); /* repond only to the own ID (reselection) */
  774 + scsi_write_byte(STEST1,0x00); /* not isolated, SCLK is used */
  775 + scsi_write_byte(STEST2,0x00); /* no Lowlevel Mode? */
  776 + scsi_write_byte(STEST3,0x80); /* enable tolerANT */
  777 + scsi_write_byte(CTEST3,0x04); /* clear FIFO */
  778 + scsi_write_byte(CTEST4,0x00);
  779 + scsi_write_byte(CTEST5,0x00);
  780 +#ifdef SCSI_SINGLE_STEP
  781 +/* scsi_write_byte(DCNTL,IRQM | SSM); */
  782 + scsi_write_byte(DCNTL,IRQD | SSM);
  783 + scsi_write_byte(DMODE,MAN);
  784 +#else
  785 +/* scsi_write_byte(DCNTL,IRQM); */
  786 + scsi_write_byte(DCNTL,IRQD);
  787 + scsi_write_byte(DMODE,0x00);
  788 +#endif
  789 +}
  790 +#endif
  791 +
  792 +
  793 +#endif /* CONFIG_SCSI_SYM53C8XX */
drivers/block/systemace.c
Diff comments   View file @ 33daf5b
  1 +/*
  2 + * Copyright (c) 2004 Picture Elements, Inc.
  3 + * Stephen Williams (XXXXXXXXXXXXXXXX)
  4 + *
  5 + * This source code is free software; you can redistribute it
  6 + * and/or modify it in source code form under the terms of the GNU
  7 + * General Public License as published by the Free Software
  8 + * Foundation; either version 2 of the License, or (at your option)
  9 + * any later version.
  10 + *
  11 + * This program is distributed in the hope that it will be useful,
  12 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14 + * GNU General Public License for more details.
  15 + *
  16 + * You should have received a copy of the GNU General Public License
  17 + * along with this program; if not, write to the Free Software
  18 + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  19 + */
  20 +
  21 +/*
  22 + * The Xilinx SystemACE chip support is activated by defining
  23 + * CONFIG_SYSTEMACE to turn on support, and CFG_SYSTEMACE_BASE
  24 + * to set the base address of the device. This code currently
  25 + * assumes that the chip is connected via a byte-wide bus.
  26 + *
  27 + * The CONFIG_SYSTEMACE also adds to fat support the device class
  28 + * "ace" that allows the user to execute "fatls ace 0" and the
  29 + * like. This works by making the systemace_get_dev function
  30 + * available to cmd_fat.c:get_dev and filling in a block device
  31 + * description that has all the bits needed for FAT support to
  32 + * read sectors.
  33 + *
  34 + * According to Xilinx technical support, before accessing the
  35 + * SystemACE CF you need to set the following control bits:
  36 + * FORCECFGMODE : 1
  37 + * CFGMODE : 0
  38 + * CFGSTART : 0
  39 + */
  40 +
  41 +#include <common.h>
  42 +#include <command.h>
  43 +#include <systemace.h>
  44 +#include <part.h>
  45 +#include <asm/io.h>
  46 +
  47 +#ifdef CONFIG_SYSTEMACE
  48 +
  49 +/*
  50 + * The ace_readw and writew functions read/write 16bit words, but the
  51 + * offset value is the BYTE offset as most used in the Xilinx
  52 + * datasheet for the SystemACE chip. The CFG_SYSTEMACE_BASE is defined
  53 + * to be the base address for the chip, usually in the local
  54 + * peripheral bus.
  55 + */
  56 +#if (CFG_SYSTEMACE_WIDTH == 8)
  57 +#if !defined(__BIG_ENDIAN)
  58 +#define ace_readw(off) ((readb(CFG_SYSTEMACE_BASE+off)<<8) | \
  59 + (readb(CFG_SYSTEMACE_BASE+off+1)))
  60 +#define ace_writew(val, off) {writeb(val>>8, CFG_SYSTEMACE_BASE+off); \
  61 + writeb(val, CFG_SYSTEMACE_BASE+off+1);}
  62 +#else
  63 +#define ace_readw(off) ((readb(CFG_SYSTEMACE_BASE+off)) | \
  64 + (readb(CFG_SYSTEMACE_BASE+off+1)<<8))
  65 +#define ace_writew(val, off) {writeb(val, CFG_SYSTEMACE_BASE+off); \
  66 + writeb(val>>8, CFG_SYSTEMACE_BASE+off+1);}
  67 +#endif
  68 +#else
  69 +#define ace_readw(off) (in16(CFG_SYSTEMACE_BASE+off))
  70 +#define ace_writew(val, off) (out16(CFG_SYSTEMACE_BASE+off,val))
  71 +#endif
  72 +
  73 +/* */
  74 +
  75 +static unsigned long systemace_read(int dev, unsigned long start,
  76 + unsigned long blkcnt, void *buffer);
  77 +
  78 +static block_dev_desc_t systemace_dev = { 0 };
  79 +
  80 +static int get_cf_lock(void)
  81 +{
  82 + int retry = 10;
  83 +
  84 + /* CONTROLREG = LOCKREG */
  85 + unsigned val = ace_readw(0x18);
  86 + val |= 0x0002;
  87 + ace_writew((val & 0xffff), 0x18);
  88 +
  89 + /* Wait for MPULOCK in STATUSREG[15:0] */
  90 + while (!(ace_readw(0x04) & 0x0002)) {
  91 +
  92 + if (retry < 0)
  93 + return -1;
  94 +
  95 + udelay(100000);
  96 + retry -= 1;
  97 + }
  98 +
  99 + return 0;
  100 +}
  101 +
  102 +static void release_cf_lock(void)
  103 +{
  104 + unsigned val = ace_readw(0x18);
  105 + val &= ~(0x0002);
  106 + ace_writew((val & 0xffff), 0x18);
  107 +}
  108 +
  109 +block_dev_desc_t *systemace_get_dev(int dev)
  110 +{
  111 + /* The first time through this, the systemace_dev object is
  112 + not yet initialized. In that case, fill it in. */
  113 + if (systemace_dev.blksz == 0) {
  114 + systemace_dev.if_type = IF_TYPE_UNKNOWN;
  115 + systemace_dev.dev = 0;
  116 + systemace_dev.part_type = PART_TYPE_UNKNOWN;
  117 + systemace_dev.type = DEV_TYPE_HARDDISK;
  118 + systemace_dev.blksz = 512;
  119 + systemace_dev.removable = 1;
  120 + systemace_dev.block_read = systemace_read;
  121 +
  122 + /*
  123 + * Ensure the correct bus mode (8/16 bits) gets enabled
  124 + */
  125 + ace_writew(CFG_SYSTEMACE_WIDTH == 8 ? 0 : 0x0001, 0);
  126 +
  127 + init_part(&systemace_dev);
  128 +
  129 + }
  130 +
  131 + return &systemace_dev;
  132 +}
  133 +
  134 +/*
  135 + * This function is called (by dereferencing the block_read pointer in
  136 + * the dev_desc) to read blocks of data. The return value is the
  137 + * number of blocks read. A zero return indicates an error.
  138 + */
  139 +static unsigned long systemace_read(int dev, unsigned long start,
  140 + unsigned long blkcnt, void *buffer)
  141 +{
  142 + int retry;
  143 + unsigned blk_countdown;
  144 + unsigned char *dp = buffer;
  145 + unsigned val;
  146 +
  147 + if (get_cf_lock() < 0) {
  148 + unsigned status = ace_readw(0x04);
  149 +
  150 + /* If CFDETECT is false, card is missing. */
  151 + if (!(status & 0x0010)) {
  152 + printf("** CompactFlash card not present. **\n");
  153 + return 0;
  154 + }
  155 +
  156 + printf("**** ACE locked away from me (STATUSREG=%04x)\n",
  157 + status);
  158 + return 0;
  159 + }
  160 +#ifdef DEBUG_SYSTEMACE
  161 + printf("... systemace read %lu sectors at %lu\n", blkcnt, start);
  162 +#endif
  163 +
  164 + retry = 2000;
  165 + for (;;) {
  166 + val = ace_readw(0x04);
  167 +
  168 + /* If CFDETECT is false, card is missing. */
  169 + if (!(val & 0x0010)) {
  170 + printf("**** ACE CompactFlash not found.\n");
  171 + release_cf_lock();
  172 + return 0;
  173 + }
  174 +
  175 + /* If RDYFORCMD, then we are ready to go. */
  176 + if (val & 0x0100)
  177 + break;
  178 +
  179 + if (retry < 0) {
  180 + printf("**** SystemACE not ready.\n");
  181 + release_cf_lock();
  182 + return 0;
  183 + }
  184 +
  185 + udelay(1000);
  186 + retry -= 1;
  187 + }
  188 +
  189 + /* The SystemACE can only transfer 256 sectors at a time, so
  190 + limit the current chunk of sectors. The blk_countdown
  191 + variable is the number of sectors left to transfer. */
  192 +
  193 + blk_countdown = blkcnt;
  194 + while (blk_countdown > 0) {
  195 + unsigned trans = blk_countdown;
  196 +
  197 + if (trans > 256)
  198 + trans = 256;
  199 +
  200 +#ifdef DEBUG_SYSTEMACE
  201 + printf("... transfer %lu sector in a chunk\n", trans);
  202 +#endif
  203 + /* Write LBA block address */
  204 + ace_writew((start >> 0) & 0xffff, 0x10);
  205 + ace_writew((start >> 16) & 0x0fff, 0x12);
  206 +
  207 + /* NOTE: in the Write Sector count below, a count of 0
  208 + causes a transfer of 256, so &0xff gives the right
  209 + value for whatever transfer count we want. */
  210 +
  211 + /* Write sector count | ReadMemCardData. */
  212 + ace_writew((trans & 0xff) | 0x0300, 0x14);
  213 +
  214 +/*
  215 + * For FPGA configuration via SystemACE is reset unacceptable
  216 + * CFGDONE bit in STATUSREG is not set to 1.
  217 + */
  218 +#ifndef SYSTEMACE_CONFIG_FPGA
  219 + /* Reset the configruation controller */
  220 + val = ace_readw(0x18);
  221 + val |= 0x0080;
  222 + ace_writew(val, 0x18);
  223 +#endif
  224 +
  225 + retry = trans * 16;
  226 + while (retry > 0) {
  227 + int idx;
  228 +
  229 + /* Wait for buffer to become ready. */
  230 + while (!(ace_readw(0x04) & 0x0020)) {
  231 + udelay(100);
  232 + }
  233 +
  234 + /* Read 16 words of 2bytes from the sector buffer. */
  235 + for (idx = 0; idx < 16; idx += 1) {
  236 + unsigned short val = ace_readw(0x40);
  237 + *dp++ = val & 0xff;
  238 + *dp++ = (val >> 8) & 0xff;
  239 + }
  240 +
  241 + retry -= 1;
  242 + }
  243 +
  244 + /* Clear the configruation controller reset */
  245 + val = ace_readw(0x18);
  246 + val &= ~0x0080;
  247 + ace_writew(val, 0x18);
  248 +
  249 + /* Count the blocks we transfer this time. */
  250 + start += trans;
  251 + blk_countdown -= trans;
  252 + }
  253 +
  254 + release_cf_lock();
  255 +
  256 + return blkcnt;
  257 +}
  258 +#endif /* CONFIG_SYSTEMACE */
drivers/sil680.c
View file @ 33daf5b
1   -/*
2   - * (C) Copyright 2007
3   - * Gary Jennejohn, DENX Software Engineering, garyj@denx.de.
4   - *
5   - * See file CREDITS for list of people who contributed to this
6   - * project.
7   - *
8   - * This program is free software; you can redistribute it and/or
9   - * modify it under the terms of the GNU General Public License as
10   - * published by the Free Software Foundation; either version 2 of
11   - * the License, or (at your option) any later version.
12   - *
13   - * This program is distributed in the hope that it will be useful,
14   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
15   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16   - * GNU General Public License for more details.
17   - *
18   - * You should have received a copy of the GNU General Public License
19   - * along with this program; if not, write to the Free Software
20   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21   - * MA 02111-1307 USA
22   - *
23   - */
24   -/* sil680.c - ide support functions for the Sil0680A controller */
25   -
26   -/*
27   - * The following parameters must be defined in the configuration file
28   - * of the target board:
29   - *
30   - * #define CFG_IDE_SIL680
31   - *
32   - * #define CONFIG_PCI_PNP
33   - * NOTE it may also be necessary to define this if the default of 8 is
34   - * incorrect for the target board (e.g. the sequoia board requires 0).
35   - * #define CFG_PCI_CACHE_LINE_SIZE 0
36   - *
37   - * #define CONFIG_CMD_IDE
38   - * #undef CONFIG_IDE_8xx_DIRECT
39   - * #undef CONFIG_IDE_LED
40   - * #undef CONFIG_IDE_RESET
41   - * #define CONFIG_IDE_PREINIT
42   - * #define CFG_IDE_MAXBUS 2 - modify to suit
43   - * #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) - modify to suit
44   - * #define CFG_ATA_BASE_ADDR 0
45   - * #define CFG_ATA_IDE0_OFFSET 0
46   - * #define CFG_ATA_IDE1_OFFSET 0
47   - * #define CFG_ATA_DATA_OFFSET 0
48   - * #define CFG_ATA_REG_OFFSET 0
49   - * #define CFG_ATA_ALT_OFFSET 0x0004
50   - *
51   - * The mapping for PCI IO-space.
52   - * NOTE this is the value for the sequoia board. Modify to suit.
53   - * #define CFG_PCI0_IO_SPACE 0xE8000000
54   - */
55   -
56   -#include <common.h>
57   -#if defined(CFG_IDE_SIL680)
58   -#include <ata.h>
59   -#include <ide.h>
60   -#include <pci.h>
61   -
62   -extern ulong ide_bus_offset[CFG_IDE_MAXBUS];
63   -
64   -int ide_preinit (void)
65   -{
66   - int status;
67   - pci_dev_t devbusfn;
68   - int l;
69   -
70   - status = 1;
71   - for (l = 0; l < CFG_IDE_MAXBUS; l++) {
72   - ide_bus_offset[l] = -ATA_STATUS;
73   - }
74   - devbusfn = pci_find_device (0x1095, 0x0680, 0);
75   - if (devbusfn != -1) {
76   - status = 0;
77   -
78   - pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0,
79   - (u32 *) &ide_bus_offset[0]);
80   - ide_bus_offset[0] &= 0xfffffff8;
81   - ide_bus_offset[0] += CFG_PCI0_IO_SPACE;
82   - pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_2,
83   - (u32 *) &ide_bus_offset[1]);
84   - ide_bus_offset[1] &= 0xfffffff8;
85   - ide_bus_offset[1] += CFG_PCI0_IO_SPACE;
86   - /* init various things - taken from the Linux driver */
87   - /* set PIO mode */
88   - pci_write_config_byte(devbusfn, 0x80, 0x00);
89   - pci_write_config_byte(devbusfn, 0x84, 0x00);
90   - /* IDE0 */
91   - pci_write_config_byte(devbusfn, 0xA1, 0x02);
92   - pci_write_config_word(devbusfn, 0xA2, 0x328A);
93   - pci_write_config_dword(devbusfn, 0xA4, 0x62DD62DD);
94   - pci_write_config_dword(devbusfn, 0xA8, 0x43924392);
95   - pci_write_config_dword(devbusfn, 0xAC, 0x40094009);
96   - /* IDE1 */
97   - pci_write_config_byte(devbusfn, 0xB1, 0x02);
98   - pci_write_config_word(devbusfn, 0xB2, 0x328A);
99   - pci_write_config_dword(devbusfn, 0xB4, 0x62DD62DD);
100   - pci_write_config_dword(devbusfn, 0xB8, 0x43924392);
101   - pci_write_config_dword(devbusfn, 0xBC, 0x40094009);
102   - }
103   - return (status);
104   -}
105   -
106   -void ide_set_reset (int flag) {
107   - return;
108   -}
109   -
110   -#endif /* CFG_IDE_SIL680 */
drivers/sym53c8xx.c
View file @ 33daf5b
1   -/*
2   - * (C) Copyright 2001
3   - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch.
4   - *
5   - * See file CREDITS for list of people who contributed to this
6   - * project.
7   - *
8   - * This program is free software; you can redistribute it and/or
9   - * modify it under the terms of the GNU General Public License as
10   - * published by the Free Software Foundation; either version 2 of
11   - * the License, or (at your option) any later version.
12   - *
13   - * This program is distributed in the hope that it will be useful,
14   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
15   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16   - * GNU General Public License for more details.
17   - *
18   - * You should have received a copy of the GNU General Public License
19   - * along with this program; if not, write to the Free Software
20   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21   - * MA 02111-1307 USA
22   - * partly derived from
23   - * linux/drivers/scsi/sym53c8xx.c
24   - *
25   - */
26   -
27   -/*
28   - * SCSI support based on the chip sym53C810.
29   - *
30   - * 09-19-2001 Andreas Heppel, Sysgo RTS GmbH <aheppel@sysgo.de>
31   - * The local version of this driver for the BAB750 board does not
32   - * use interrupts but polls the chip instead (see the call of
33   - * 'handle_scsi_int()' in 'scsi_issue()'.
34   - */
35   -
36   -#include <common.h>
37   -
38   -#ifdef CONFIG_SCSI_SYM53C8XX
39   -
40   -#include <command.h>
41   -#include <pci.h>
42   -#include <asm/processor.h>
43   -#include <sym53c8xx.h>
44   -#include <scsi.h>
45   -
46   -#undef SYM53C8XX_DEBUG
47   -
48   -#ifdef SYM53C8XX_DEBUG
49   -#define PRINTF(fmt,args...) printf (fmt ,##args)
50   -#else
51   -#define PRINTF(fmt,args...)
52   -#endif
53   -
54   -#if defined(CONFIG_CMD_SCSI) && defined(CONFIG_SCSI_SYM53C8XX)
55   -
56   -#undef SCSI_SINGLE_STEP
57   -/*
58   - * Single Step is only used for debug purposes
59   - */
60   -#ifdef SCSI_SINGLE_STEP
61   -static unsigned long start_script_select;
62   -static unsigned long start_script_msgout;
63   -static unsigned long start_script_msgin;
64   -static unsigned long start_script_msg_ext;
65   -static unsigned long start_script_cmd;
66   -static unsigned long start_script_data_in;
67   -static unsigned long start_script_data_out;
68   -static unsigned long start_script_status;
69   -static unsigned long start_script_complete;
70   -static unsigned long start_script_error;
71   -static unsigned long start_script_reselection;
72   -static unsigned int len_script_select;
73   -static unsigned int len_script_msgout;
74   -static unsigned int len_script_msgin;
75   -static unsigned int len_script_msg_ext;
76   -static unsigned int len_script_cmd;
77   -static unsigned int len_script_data_in;
78   -static unsigned int len_script_data_out;
79   -static unsigned int len_script_status;
80   -static unsigned int len_script_complete;
81   -static unsigned int len_script_error;
82   -static unsigned int len_script_reselection;
83   -#endif
84   -
85   -
86   -static unsigned short scsi_int_mask; /* shadow register for SCSI related interrupts */
87   -static unsigned char script_int_mask; /* shadow register for SCRIPT related interrupts */
88   -static unsigned long script_select[8]; /* script for selection */
89   -static unsigned long script_msgout[8]; /* script for message out phase (NOT USED) */
90   -static unsigned long script_msgin[14]; /* script for message in phase */
91   -static unsigned long script_msg_ext[32]; /* script for message in phase when more than 1 byte message */
92   -static unsigned long script_cmd[18]; /* script for command phase */
93   -static unsigned long script_data_in[8]; /* script for data in phase */
94   -static unsigned long script_data_out[8]; /* script for data out phase */
95   -static unsigned long script_status[6]; /* script for status phase */
96   -static unsigned long script_complete[10]; /* script for complete */
97   -static unsigned long script_reselection[4]; /* script for reselection (NOT USED) */
98   -static unsigned long script_error[2]; /* script for error handling */
99   -
100   -static unsigned long int_stat[3]; /* interrupt status */
101   -static unsigned long scsi_mem_addr; /* base memory address =SCSI_MEM_ADDRESS; */
102   -
103   -#define bus_to_phys(a) pci_mem_to_phys(busdevfunc, (unsigned long) (a))
104   -#define phys_to_bus(a) pci_phys_to_mem(busdevfunc, (unsigned long) (a))
105   -
106   -#define SCSI_MAX_RETRY 3 /* number of retries in scsi_issue() */
107   -
108   -#define SCSI_MAX_RETRY_NOT_READY 10 /* number of retries when device is not ready */
109   -#define SCSI_NOT_READY_TIME_OUT 500 /* timeout per retry when not ready */
110   -
111   -/*********************************************************************************
112   - * forward declerations
113   - */
114   -
115   -void scsi_chip_init(void);
116   -void handle_scsi_int(void);
117   -
118   -
119   -/********************************************************************************
120   - * reports SCSI errors to the user
121   - */
122   -void scsi_print_error(ccb *pccb)
123   -{
124   - int i;
125   - printf("SCSI Error: Target %d LUN %d Command %02X\n",pccb->target, pccb->lun, pccb->cmd[0]);
126   - printf(" CCB: ");
127   - for(i=0;i<pccb->cmdlen;i++)
128   - printf("%02X ",pccb->cmd[i]);
129   - printf("(len=%d)\n",pccb->cmdlen);
130   - printf(" Cntrl: ");
131   - switch(pccb->contr_stat) {
132   - case SIR_COMPLETE: printf("Complete (no Error)\n"); break;
133   - case SIR_SEL_ATN_NO_MSG_OUT: printf("Selected with ATN no MSG out phase\n"); break;
134   - case SIR_CMD_OUT_ILL_PH: printf("Command out illegal phase\n"); break;
135   - case SIR_MSG_RECEIVED: printf("MSG received Error\n"); break;
136   - case SIR_DATA_IN_ERR: printf("Data in Error\n"); break;
137   - case SIR_DATA_OUT_ERR: printf("Data out Error\n"); break;
138   - case SIR_SCRIPT_ERROR: printf("Script Error\n"); break;
139   - case SIR_MSG_OUT_NO_CMD: printf("MSG out no Command phase\n"); break;
140   - case SIR_MSG_OVER7: printf("MSG in over 7 bytes\n"); break;
141   - case INT_ON_FY: printf("Interrupt on fly\n"); break;
142   - case SCSI_SEL_TIME_OUT: printf("SCSI Selection Timeout\n"); break;
143   - case SCSI_HNS_TIME_OUT: printf("SCSI Handshake Timeout\n"); break;
144   - case SCSI_MA_TIME_OUT: printf("SCSI Phase Error\n"); break;
145   - case SCSI_UNEXP_DIS: printf("SCSI unexpected disconnect\n"); break;
146   - default: printf("unknown status %lx\n",pccb->contr_stat); break;
147   - }
148   - printf(" Sense: SK %x (",pccb->sense_buf[2]&0x0f);
149   - switch(pccb->sense_buf[2]&0xf) {
150   - case SENSE_NO_SENSE: printf("No Sense)"); break;
151   - case SENSE_RECOVERED_ERROR: printf("Recovered Error)"); break;
152   - case SENSE_NOT_READY: printf("Not Ready)"); break;
153   - case SENSE_MEDIUM_ERROR: printf("Medium Error)"); break;
154   - case SENSE_HARDWARE_ERROR: printf("Hardware Error)"); break;
155   - case SENSE_ILLEGAL_REQUEST: printf("Illegal request)"); break;
156   - case SENSE_UNIT_ATTENTION: printf("Unit Attention)"); break;
157   - case SENSE_DATA_PROTECT: printf("Data Protect)"); break;
158   - case SENSE_BLANK_CHECK: printf("Blank check)"); break;
159   - case SENSE_VENDOR_SPECIFIC: printf("Vendor specific)"); break;
160   - case SENSE_COPY_ABORTED: printf("Copy aborted)"); break;
161   - case SENSE_ABORTED_COMMAND: printf("Aborted Command)"); break;
162   - case SENSE_VOLUME_OVERFLOW: printf("Volume overflow)"); break;
163   - case SENSE_MISCOMPARE: printf("Misscompare\n"); break;
164   - default: printf("Illegal Sensecode\n"); break;
165   - }
166   - printf(" ASC %x ASCQ %x\n",pccb->sense_buf[12],pccb->sense_buf[13]);
167   - printf(" Status: ");
168   - switch(pccb->status) {
169   - case S_GOOD : printf("Good\n"); break;
170   - case S_CHECK_COND: printf("Check condition\n"); break;
171   - case S_COND_MET: printf("Condition Met\n"); break;
172   - case S_BUSY: printf("Busy\n"); break;
173   - case S_INT: printf("Intermediate\n"); break;
174   - case S_INT_COND_MET: printf("Intermediate condition met\n"); break;
175   - case S_CONFLICT: printf("Reservation conflict\n"); break;
176   - case S_TERMINATED: printf("Command terminated\n"); break;
177   - case S_QUEUE_FULL: printf("Task set full\n"); break;
178   - default: printf("unknown: %02X\n",pccb->status); break;
179   - }
180   -
181   -}
182   -
183   -
184   -/******************************************************************************
185   - * sets-up the SCSI controller
186   - * the base memory address is retrived via the pci_read_config_dword
187   - */
188   -void scsi_low_level_init(int busdevfunc)
189   -{
190   - unsigned int cmd;
191   - unsigned int addr;
192   - unsigned char vec;
193   -
194   - pci_read_config_byte(busdevfunc, PCI_INTERRUPT_LINE, &vec);
195   - pci_read_config_dword(busdevfunc, PCI_BASE_ADDRESS_1, &addr);
196   -
197   - addr = bus_to_phys(addr & ~0xf);
198   -
199   - /*
200   - * Enable bus mastering in case this has not been done, yet.
201   - */
202   - pci_read_config_dword(busdevfunc, PCI_COMMAND, &cmd);
203   - cmd |= PCI_COMMAND_MASTER;
204   - pci_write_config_dword(busdevfunc, PCI_COMMAND, cmd);
205   -
206   - scsi_mem_addr = addr;
207   -
208   - scsi_chip_init();
209   - scsi_bus_reset();
210   -}
211   -
212   -
213   -/************************************************************************************
214   - * Low level Part of SCSI Driver
215   - */
216   -
217   -/*
218   - * big-endian -> little endian conversion for the script
219   - */
220   -unsigned long swap_script(unsigned long val)
221   -{
222   - unsigned long tmp;
223   - tmp = ((val>>24)&0xff) | ((val>>8)&0xff00) | ((val<<8)&0xff0000) | ((val<<24)&0xff000000);
224   - return tmp;
225   -}
226   -
227   -
228   -void scsi_write_byte(ulong offset,unsigned char val)
229   -{
230   - out8(scsi_mem_addr+offset,val);
231   -}
232   -
233   -
234   -unsigned char scsi_read_byte(ulong offset)
235   -{
236   - return(in8(scsi_mem_addr+offset));
237   -}
238   -
239   -
240   -/********************************************************************************
241   - * interrupt handler
242   - */
243   -void handle_scsi_int(void)
244   -{
245   - unsigned char stat,stat1,stat2;
246   - unsigned short sstat;
247   - int i;
248   -#ifdef SCSI_SINGLE_STEP
249   - unsigned long tt;
250   -#endif
251   - stat=scsi_read_byte(ISTAT);
252   - if((stat & DIP)==DIP) { /* DMA Interrupt pending */
253   - stat1=scsi_read_byte(DSTAT);
254   -#ifdef SCSI_SINGLE_STEP
255   - if((stat1 & SSI)==SSI)
256   - {
257   - tt=in32r(scsi_mem_addr+DSP);
258   - if(((tt)>=start_script_select) && ((tt)<start_script_select+len_script_select)) {
259   - printf("select %d\n",(tt-start_script_select)>>2);
260   - goto end_single;
261   - }
262   - if(((tt)>=start_script_msgout) && ((tt)<start_script_msgout+len_script_msgout)) {
263   - printf("msgout %d\n",(tt-start_script_msgout)>>2);
264   - goto end_single;
265   - }
266   - if(((tt)>=start_script_msgin) && ((tt)<start_script_msgin+len_script_msgin)) {
267   - printf("msgin %d\n",(tt-start_script_msgin)>>2);
268   - goto end_single;
269   - }
270   - if(((tt)>=start_script_msg_ext) && ((tt)<start_script_msg_ext+len_script_msg_ext)) {
271   - printf("msgin_ext %d\n",(tt-start_script_msg_ext)>>2);
272   - goto end_single;
273   - }
274   - if(((tt)>=start_script_cmd) && ((tt)<start_script_cmd+len_script_cmd)) {
275   - printf("cmd %d\n",(tt-start_script_cmd)>>2);
276   - goto end_single;
277   - }
278   - if(((tt)>=start_script_data_in) && ((tt)<start_script_data_in+len_script_data_in)) {
279   - printf("data_in %d\n",(tt-start_script_data_in)>>2);
280   - goto end_single;
281   - }
282   - if(((tt)>=start_script_data_out) && ((tt)<start_script_data_out+len_script_data_out)) {
283   - printf("data_out %d\n",(tt-start_script_data_out)>>2);
284   - goto end_single;
285   - }
286   - if(((tt)>=start_script_status) && ((tt)<start_script_status+len_script_status)) {
287   - printf("status %d\n",(tt-start_script_status)>>2);
288   - goto end_single;
289   - }
290   - if(((tt)>=start_script_complete) && ((tt)<start_script_complete+len_script_complete)) {
291   - printf("complete %d\n",(tt-start_script_complete)>>2);
292   - goto end_single;
293   - }
294   - if(((tt)>=start_script_error) && ((tt)<start_script_error+len_script_error)) {
295   - printf("error %d\n",(tt-start_script_error)>>2);
296   - goto end_single;
297   - }
298   - if(((tt)>=start_script_reselection) && ((tt)<start_script_reselection+len_script_reselection)) {
299   - printf("reselection %d\n",(tt-start_script_reselection)>>2);
300   - goto end_single;
301   - }
302   - printf("sc: %lx\n",tt);
303   -end_single:
304   - stat2=scsi_read_byte(DCNTL);
305   - stat2|=STD;
306   - scsi_write_byte(DCNTL,stat2);
307   - }
308   -#endif
309   - if((stat1 & SIR)==SIR) /* script interrupt */
310   - {
311   - int_stat[0]=in32(scsi_mem_addr+DSPS);
312   - }
313   - if((stat1 & DFE)==0) { /* fifo not epmty */
314   - scsi_write_byte(CTEST3,CLF); /* Clear DMA FIFO */
315   - stat2=scsi_read_byte(STEST3);
316   - scsi_write_byte(STEST3,(stat2 | CSF)); /* Clear SCSI FIFO */
317   - }
318   - }
319   - if((stat & SIP)==SIP) { /* scsi interrupt */
320   - sstat = (unsigned short)scsi_read_byte(SIST+1);
321   - sstat <<=8;
322   - sstat |= (unsigned short)scsi_read_byte(SIST);
323   - for(i=0;i<3;i++) {
324   - if(int_stat[i]==0)
325   - break; /* found an empty int status */
326   - }
327   - int_stat[i]=SCSI_INT_STATE | sstat;
328   - stat1=scsi_read_byte(DSTAT);
329   - if((stat1 & DFE)==0) { /* fifo not epmty */
330   - scsi_write_byte(CTEST3,CLF); /* Clear DMA FIFO */
331   - stat2=scsi_read_byte(STEST3);
332   - scsi_write_byte(STEST3,(stat2 | CSF)); /* Clear SCSI FIFO */
333   - }
334   - }
335   - if((stat & INTF)==INTF) { /* interrupt on Fly */
336   - scsi_write_byte(ISTAT,stat); /* clear it */
337   - for(i=0;i<3;i++) {
338   - if(int_stat[i]==0)
339   - break; /* found an empty int status */
340   - }
341   - int_stat[i]=INT_ON_FY;
342   - }
343   -}
344   -
345   -void scsi_bus_reset(void)
346   -{
347   - unsigned char t;
348   - int i;
349   - int end = CFG_SCSI_SPIN_UP_TIME*1000;
350   -
351   - t=scsi_read_byte(SCNTL1);
352   - scsi_write_byte(SCNTL1,(t | CRST));
353   - udelay(50);
354   - scsi_write_byte(SCNTL1,t);
355   -
356   - puts("waiting for devices to spin up");
357   - for(i=0;i<end;i++) {
358   - udelay(1000); /* give the devices time to spin up */
359   - if (i % 1000 == 0)
360   - putc('.');
361   - }
362   - putc('\n');
363   - scsi_chip_init(); /* reinit the chip ...*/
364   -
365   -}
366   -
367   -void scsi_int_enable(void)
368   -{
369   - scsi_write_byte(SIEN,(unsigned char)scsi_int_mask);
370   - scsi_write_byte(SIEN+1,(unsigned char)(scsi_int_mask>>8));
371   - scsi_write_byte(DIEN,script_int_mask);
372   -}
373   -
374   -void scsi_write_dsp(unsigned long start)
375   -{
376   - unsigned long val;
377   -#ifdef SCSI_SINGLE_STEP
378   - unsigned char t;
379   -#endif
380   - val = start;
381   - out32r(scsi_mem_addr + DSP,start);
382   -#ifdef SCSI_SINGLE_STEP
383   - t=scsi_read_byte(DCNTL);
384   - t|=STD;
385   - scsi_write_byte(DCNTL,t);
386   -#endif
387   -}
388   -
389   -/* only used for debug purposes */
390   -void scsi_print_script(void)
391   -{
392   - printf("script_select @ 0x%08lX\n",(unsigned long)&script_select[0]);
393   - printf("script_msgout @ 0x%08lX\n",(unsigned long)&script_msgout[0]);
394   - printf("script_msgin @ 0x%08lX\n",(unsigned long)&script_msgin[0]);
395   - printf("script_msgext @ 0x%08lX\n",(unsigned long)&script_msg_ext[0]);
396   - printf("script_cmd @ 0x%08lX\n",(unsigned long)&script_cmd[0]);
397   - printf("script_data_in @ 0x%08lX\n",(unsigned long)&script_data_in[0]);
398   - printf("script_data_out @ 0x%08lX\n",(unsigned long)&script_data_out[0]);
399   - printf("script_status @ 0x%08lX\n",(unsigned long)&script_status[0]);
400   - printf("script_complete @ 0x%08lX\n",(unsigned long)&script_complete[0]);
401   - printf("script_error @ 0x%08lX\n",(unsigned long)&script_error[0]);
402   -}
403   -
404   -
405   -void scsi_set_script(ccb *pccb)
406   -{
407   - int busdevfunc = pccb->priv;
408   - int i;
409   - i=0;
410   - script_select[i++]=swap_script(SCR_REG_REG(GPREG, SCR_AND, 0xfe));
411   - script_select[i++]=0; /* LED ON */
412   - script_select[i++]=swap_script(SCR_CLR(SCR_TRG)); /* select initiator mode */
413   - script_select[i++]=0;
414   - /* script_select[i++]=swap_script(SCR_SEL_ABS_ATN | pccb->target << 16); */
415   - script_select[i++]=swap_script(SCR_SEL_ABS | pccb->target << 16);
416   - script_select[i++]=swap_script(phys_to_bus(&script_cmd[4])); /* error handling */
417   - script_select[i++]=swap_script(SCR_JUMP); /* next section */
418   - /* script_select[i++]=swap_script((unsigned long)&script_msgout[0]); */ /* message out */
419   - script_select[i++]=swap_script(phys_to_bus(&script_cmd[0])); /* command out */
420   -
421   -#ifdef SCSI_SINGLE_STEP
422   - start_script_select=(unsigned long)&script_select[0];
423   - len_script_select=i*4;
424   -#endif
425   -
426   - i=0;
427   - script_msgout[i++]=swap_script(SCR_INT ^ IFFALSE (WHEN (SCR_MSG_OUT)));
428   - script_msgout[i++]=SIR_SEL_ATN_NO_MSG_OUT;
429   - script_msgout[i++]=swap_script( SCR_MOVE_ABS(1) ^ SCR_MSG_OUT);
430   - script_msgout[i++]=swap_script(phys_to_bus(&pccb->msgout[0]));
431   - script_msgout[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_COMMAND))); /* if Command phase */
432   - script_msgout[i++]=swap_script(phys_to_bus(&script_cmd[0])); /* switch to command */
433   - script_msgout[i++]=swap_script(SCR_INT); /* interrupt if not */
434   - script_msgout[i++]=SIR_MSG_OUT_NO_CMD;
435   -
436   -#ifdef SCSI_SINGLE_STEP
437   - start_script_msgout=(unsigned long)&script_msgout[0];
438   - len_script_msgout=i*4;
439   -#endif
440   - i=0;
441   - script_cmd[i++]=swap_script(SCR_MOVE_ABS(pccb->cmdlen) ^ SCR_COMMAND);
442   - script_cmd[i++]=swap_script(phys_to_bus(&pccb->cmd[0]));
443   - script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN))); /* message in ? */
444   - script_cmd[i++]=swap_script(phys_to_bus(&script_msgin[0]));
445   - script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_DATA_OUT))); /* data out ? */
446   - script_cmd[i++]=swap_script(phys_to_bus(&script_data_out[0]));
447   - script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_DATA_IN))); /* data in ? */
448   - script_cmd[i++]=swap_script(phys_to_bus(&script_data_in[0]));
449   - script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_STATUS))); /* status ? */
450   - script_cmd[i++]=swap_script(phys_to_bus(&script_status[0]));
451   - script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_COMMAND))); /* command ? */
452   - script_cmd[i++]=swap_script(phys_to_bus(&script_cmd[0]));
453   - script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_MSG_OUT))); /* message out ? */
454   - script_cmd[i++]=swap_script(phys_to_bus(&script_msgout[0]));
455   - script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_MSG_IN))); /* just for error handling message in ? */
456   - script_cmd[i++]=swap_script(phys_to_bus(&script_msgin[0]));
457   - script_cmd[i++]=swap_script(SCR_INT); /* interrupt if not */
458   - script_cmd[i++]=SIR_CMD_OUT_ILL_PH;
459   -#ifdef SCSI_SINGLE_STEP
460   - start_script_cmd=(unsigned long)&script_cmd[0];
461   - len_script_cmd=i*4;
462   -#endif
463   - i=0;
464   - script_data_out[i++]=swap_script(SCR_MOVE_ABS(pccb->datalen)^ SCR_DATA_OUT); /* move */
465   - script_data_out[i++]=swap_script(phys_to_bus(pccb->pdata)); /* pointer to buffer */
466   - script_data_out[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS)));
467   - script_data_out[i++]=swap_script(phys_to_bus(&script_status[0]));
468   - script_data_out[i++]=swap_script(SCR_INT);
469   - script_data_out[i++]=SIR_DATA_OUT_ERR;
470   -
471   -#ifdef SCSI_SINGLE_STEP
472   - start_script_data_out=(unsigned long)&script_data_out[0];
473   - len_script_data_out=i*4;
474   -#endif
475   - i=0;
476   - script_data_in[i++]=swap_script(SCR_MOVE_ABS(pccb->datalen)^ SCR_DATA_IN); /* move */
477   - script_data_in[i++]=swap_script(phys_to_bus(pccb->pdata)); /* pointer to buffer */
478   - script_data_in[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS)));
479   - script_data_in[i++]=swap_script(phys_to_bus(&script_status[0]));
480   - script_data_in[i++]=swap_script(SCR_INT);
481   - script_data_in[i++]=SIR_DATA_IN_ERR;
482   -#ifdef SCSI_SINGLE_STEP
483   - start_script_data_in=(unsigned long)&script_data_in[0];
484   - len_script_data_in=i*4;
485   -#endif
486   - i=0;
487   - script_msgin[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN);
488   - script_msgin[i++]=swap_script(phys_to_bus(&pccb->msgin[0]));
489   - script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_COMPLETE)));
490   - script_msgin[i++]=swap_script(phys_to_bus(&script_complete[0]));
491   - script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_DISCONNECT)));
492   - script_msgin[i++]=swap_script(phys_to_bus(&script_complete[0]));
493   - script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_SAVE_DP)));
494   - script_msgin[i++]=swap_script(phys_to_bus(&script_complete[0]));
495   - script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_RESTORE_DP)));
496   - script_msgin[i++]=swap_script(phys_to_bus(&script_complete[0]));
497   - script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_EXTENDED)));
498   - script_msgin[i++]=swap_script(phys_to_bus(&script_msg_ext[0]));
499   - script_msgin[i++]=swap_script(SCR_INT);
500   - script_msgin[i++]=SIR_MSG_RECEIVED;
501   -#ifdef SCSI_SINGLE_STEP
502   - start_script_msgin=(unsigned long)&script_msgin[0];
503   - len_script_msgin=i*4;
504   -#endif
505   - i=0;
506   - script_msg_ext[i++]=swap_script(SCR_CLR (SCR_ACK)); /* clear ACK */
507   - script_msg_ext[i++]=0;
508   - script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* assuming this is the msg length */
509   - script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[1]));
510   - script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN)));
511   - script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */
512   - script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */
513   - script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[2]));
514   - script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN)));
515   - script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */
516   - script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */
517   - script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[3]));
518   - script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN)));
519   - script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */
520   - script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */
521   - script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[4]));
522   - script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN)));
523   - script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */
524   - script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */
525   - script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[5]));
526   - script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN)));
527   - script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */
528   - script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */
529   - script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[6]));
530   - script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN)));
531   - script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */
532   - script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */
533   - script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[7]));
534   - script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN)));
535   - script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */
536   - script_msg_ext[i++]=swap_script(SCR_INT);
537   - script_msg_ext[i++]=SIR_MSG_OVER7;
538   -#ifdef SCSI_SINGLE_STEP
539   - start_script_msg_ext=(unsigned long)&script_msg_ext[0];
540   - len_script_msg_ext=i*4;
541   -#endif
542   - i=0;
543   - script_status[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_STATUS);
544   - script_status[i++]=swap_script(phys_to_bus(&pccb->status));
545   - script_status[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)));
546   - script_status[i++]=swap_script(phys_to_bus(&script_msgin[0]));
547   - script_status[i++]=swap_script(SCR_INT);
548   - script_status[i++]=SIR_STATUS_ILL_PH;
549   -#ifdef SCSI_SINGLE_STEP
550   - start_script_status=(unsigned long)&script_status[0];
551   - len_script_status=i*4;
552   -#endif
553   - i=0;
554   - script_complete[i++]=swap_script(SCR_REG_REG (SCNTL2, SCR_AND, 0x7f));
555   - script_complete[i++]=0;
556   - script_complete[i++]=swap_script(SCR_CLR (SCR_ACK|SCR_ATN));
557   - script_complete[i++]=0;
558   - script_complete[i++]=swap_script(SCR_WAIT_DISC);
559   - script_complete[i++]=0;
560   - script_complete[i++]=swap_script(SCR_REG_REG(GPREG, SCR_OR, 0x01));
561   - script_complete[i++]=0; /* LED OFF */
562   - script_complete[i++]=swap_script(SCR_INT);
563   - script_complete[i++]=SIR_COMPLETE;
564   -#ifdef SCSI_SINGLE_STEP
565   - start_script_complete=(unsigned long)&script_complete[0];
566   - len_script_complete=i*4;
567   -#endif
568   - i=0;
569   - script_error[i++]=swap_script(SCR_INT); /* interrupt if error */
570   - script_error[i++]=SIR_SCRIPT_ERROR;
571   -#ifdef SCSI_SINGLE_STEP
572   - start_script_error=(unsigned long)&script_error[0];
573   - len_script_error=i*4;
574   -#endif
575   - i=0;
576   - script_reselection[i++]=swap_script(SCR_CLR (SCR_TRG)); /* target status */
577   - script_reselection[i++]=0;
578   - script_reselection[i++]=swap_script(SCR_WAIT_RESEL);
579   - script_reselection[i++]=swap_script(phys_to_bus(&script_select[0])); /* len = 4 */
580   -#ifdef SCSI_SINGLE_STEP
581   - start_script_reselection=(unsigned long)&script_reselection[0];
582   - len_script_reselection=i*4;
583   -#endif
584   -}
585   -
586   -
587   -void scsi_issue(ccb *pccb)
588   -{
589   - int busdevfunc = pccb->priv;
590   - int i;
591   - unsigned short sstat;
592   - int retrycnt; /* retry counter */
593   - for(i=0;i<3;i++)
594   - int_stat[i]=0; /* delete all int status */
595   - /* struct pccb must be set-up correctly */
596   - retrycnt=0;
597   - PRINTF("ID %d issue cmd %02X\n",pccb->target,pccb->cmd[0]);
598   - pccb->trans_bytes=0; /* no bytes transfered yet */
599   - scsi_set_script(pccb); /* fill in SCRIPT */
600   - scsi_int_mask=STO | UDC | MA; /* | CMP; / * Interrupts which are enabled */
601   - script_int_mask=0xff; /* enable all Ints */
602   - scsi_int_enable();
603   - scsi_write_dsp(phys_to_bus(&script_select[0])); /* start script */
604   - /* now we have to wait for IRQs */
605   -retry:
606   - /*
607   - * This version of the driver is _not_ interrupt driven,
608   - * but polls the chip's interrupt registers (ISTAT, DSTAT).
609   - */
610   - while(int_stat[0]==0)
611   - handle_scsi_int();
612   -
613   - if(int_stat[0]==SIR_COMPLETE) {
614   - if(pccb->msgin[0]==M_DISCONNECT) {
615   - PRINTF("Wait for reselection\n");
616   - for(i=0;i<3;i++)
617   - int_stat[i]=0; /* delete all int status */
618   - scsi_write_dsp(phys_to_bus(&script_reselection[0])); /* start reselection script */
619   - goto retry;
620   - }
621   - pccb->contr_stat=SIR_COMPLETE;
622   - return;
623   - }
624   - if((int_stat[0] & SCSI_INT_STATE)==SCSI_INT_STATE) { /* scsi interrupt */
625   - sstat=(unsigned short)int_stat[0];
626   - if((sstat & STO)==STO) { /* selection timeout */
627   - pccb->contr_stat=SCSI_SEL_TIME_OUT;
628   - scsi_write_byte(GPREG,0x01);
629   - PRINTF("ID: %X Selection Timeout\n",pccb->target);
630   - return;
631   - }
632   - if((sstat & UDC)==UDC) { /* unexpected disconnect */
633   - pccb->contr_stat=SCSI_UNEXP_DIS;
634   - scsi_write_byte(GPREG,0x01);
635   - PRINTF("ID: %X Unexpected Disconnect\n",pccb->target);
636   - return;
637   - }
638   - if((sstat & RSL)==RSL) { /* reselection */
639   - pccb->contr_stat=SCSI_UNEXP_DIS;
640   - scsi_write_byte(GPREG,0x01);
641   - PRINTF("ID: %X Unexpected Disconnect\n",pccb->target);
642   - return;
643   - }
644   - if(((sstat & MA)==MA)||((sstat & HTH)==HTH)) { /* phase missmatch */
645   - if(retrycnt<SCSI_MAX_RETRY) {
646   - pccb->trans_bytes=pccb->datalen -
647   - ((unsigned long)scsi_read_byte(DBC) |
648   - ((unsigned long)scsi_read_byte(DBC+1)<<8) |
649   - ((unsigned long)scsi_read_byte(DBC+2)<<16));
650   - for(i=0;i<3;i++)
651   - int_stat[i]=0; /* delete all int status */
652   - retrycnt++;
653   - PRINTF("ID: %X Phase Missmatch Retry %d Phase %02X transfered %lx\n",
654   - pccb->target,retrycnt,scsi_read_byte(SBCL),pccb->trans_bytes);
655   - scsi_write_dsp(phys_to_bus(&script_cmd[4])); /* start retry script */
656   - goto retry;
657   - }
658   - if((sstat & MA)==MA)
659   - pccb->contr_stat=SCSI_MA_TIME_OUT;
660   - else
661   - pccb->contr_stat=SCSI_HNS_TIME_OUT;
662   - PRINTF("Phase Missmatch stat %lx\n",pccb->contr_stat);
663   - return;
664   - } /* no phase int */
665   -/* if((sstat & CMP)==CMP) {
666   - pccb->contr_stat=SIR_COMPLETE;
667   - return;
668   - }
669   -*/
670   - PRINTF("SCSI INT %lX\n",int_stat[0]);
671   - pccb->contr_stat=int_stat[0];
672   - return;
673   - } /* end scsi int */
674   - PRINTF("SCRIPT INT %lX phase %02X\n",int_stat[0],scsi_read_byte(SBCL));
675   - pccb->contr_stat=int_stat[0];
676   - return;
677   -}
678   -
679   -int scsi_exec(ccb *pccb)
680   -{
681   - unsigned char tmpcmd[16],tmpstat;
682   - int i,retrycnt,t;
683   - unsigned long transbytes,datalen;
684   - unsigned char *tmpptr;
685   - retrycnt=0;
686   -retry:
687   - scsi_issue(pccb);
688   - if(pccb->contr_stat!=SIR_COMPLETE)
689   - return FALSE;
690   - if(pccb->status==S_GOOD)
691   - return TRUE;
692   - if(pccb->status==S_CHECK_COND) { /* check condition */
693   - for(i=0;i<16;i++)
694   - tmpcmd[i]=pccb->cmd[i];
695   - pccb->cmd[0]=SCSI_REQ_SENSE;
696   - pccb->cmd[1]=pccb->lun<<5;
697   - pccb->cmd[2]=0;
698   - pccb->cmd[3]=0;
699   - pccb->cmd[4]=14;
700   - pccb->cmd[5]=0;
701   - pccb->cmdlen=6;
702   - pccb->msgout[0]=SCSI_IDENTIFY;
703   - transbytes=pccb->trans_bytes;
704   - tmpptr=pccb->pdata;
705   - pccb->pdata=&pccb->sense_buf[0];
706   - datalen=pccb->datalen;
707   - pccb->datalen=14;
708   - tmpstat=pccb->status;
709   - scsi_issue(pccb);
710   - for(i=0;i<16;i++)
711   - pccb->cmd[i]=tmpcmd[i];
712   - pccb->trans_bytes=transbytes;
713   - pccb->pdata=tmpptr;
714   - pccb->datalen=datalen;
715   - pccb->status=tmpstat;
716   - PRINTF("Request_sense sense key %x ASC %x ASCQ %x\n",pccb->sense_buf[2]&0x0f,
717   - pccb->sense_buf[12],pccb->sense_buf[13]);
718   - switch(pccb->sense_buf[2]&0xf) {
719   - case SENSE_NO_SENSE:
720   - case SENSE_RECOVERED_ERROR:
721   - /* seems to be ok */
722   - return TRUE;
723   - break;
724   - case SENSE_NOT_READY:
725   - if((pccb->sense_buf[12]!=0x04)||(pccb->sense_buf[13]!=0x01)) {
726   - /* if device is not in process of becoming ready */
727   - return FALSE;
728   - break;
729   - } /* else fall through */
730   - case SENSE_UNIT_ATTENTION:
731   - if(retrycnt<SCSI_MAX_RETRY_NOT_READY) {
732   - PRINTF("Target %d not ready, retry %d\n",pccb->target,retrycnt);
733   - for(t=0;t<SCSI_NOT_READY_TIME_OUT;t++)
734   - udelay(1000); /* 1sec wait */
735   - retrycnt++;
736   - goto retry;
737   - }
738   - PRINTF("Target %d not ready, %d retried\n",pccb->target,retrycnt);
739   - return FALSE;
740   - default:
741   - return FALSE;
742   - }
743   - }
744   - PRINTF("Status = %X\n",pccb->status);
745   - return FALSE;
746   -}
747   -
748   -
749   -void scsi_chip_init(void)
750   -{
751   - /* first we issue a soft reset */
752   - scsi_write_byte(ISTAT,SRST);
753   - udelay(1000);
754   - scsi_write_byte(ISTAT,0);
755   - /* setup chip */
756   - scsi_write_byte(SCNTL0,0xC0); /* full arbitration no start, no message, parity disabled, master */
757   - scsi_write_byte(SCNTL1,0x00);
758   - scsi_write_byte(SCNTL2,0x00);
759   -#ifndef CFG_SCSI_SYM53C8XX_CCF /* config value for none 40 mhz clocks */
760   - scsi_write_byte(SCNTL3,0x13); /* synchronous clock 40/4=10MHz, asynchronous 40MHz */
761   -#else
762   - scsi_write_byte(SCNTL3,CFG_SCSI_SYM53C8XX_CCF); /* config value for none 40 mhz clocks */
763   -#endif
764   - scsi_write_byte(SCID,0x47); /* ID=7, enable reselection */
765   - scsi_write_byte(SXFER,0x00); /* synchronous transfer period 10MHz, asynchronous */
766   - scsi_write_byte(SDID,0x00); /* targed SCSI ID = 0 */
767   - scsi_int_mask=0x0000; /* no Interrupt is enabled */
768   - script_int_mask=0x00;
769   - scsi_int_enable();
770   - scsi_write_byte(GPREG,0x01); /* GPIO0 is LED (off) */
771   - scsi_write_byte(GPCNTL,0x0E); /* GPIO0 is Output */
772   - scsi_write_byte(STIME0,0x08); /* handshake timer disabled, selection timeout 512msec */
773   - scsi_write_byte(RESPID,0x80); /* repond only to the own ID (reselection) */
774   - scsi_write_byte(STEST1,0x00); /* not isolated, SCLK is used */
775   - scsi_write_byte(STEST2,0x00); /* no Lowlevel Mode? */
776   - scsi_write_byte(STEST3,0x80); /* enable tolerANT */
777   - scsi_write_byte(CTEST3,0x04); /* clear FIFO */
778   - scsi_write_byte(CTEST4,0x00);
779   - scsi_write_byte(CTEST5,0x00);
780   -#ifdef SCSI_SINGLE_STEP
781   -/* scsi_write_byte(DCNTL,IRQM | SSM); */
782   - scsi_write_byte(DCNTL,IRQD | SSM);
783   - scsi_write_byte(DMODE,MAN);
784   -#else
785   -/* scsi_write_byte(DCNTL,IRQM); */
786   - scsi_write_byte(DCNTL,IRQD);
787   - scsi_write_byte(DMODE,0x00);
788   -#endif
789   -}
790   -#endif
791   -
792   -
793   -#endif /* CONFIG_SCSI_SYM53C8XX */
drivers/systemace.c
View file @ 33daf5b
1   -/*
2   - * Copyright (c) 2004 Picture Elements, Inc.
3   - * Stephen Williams (XXXXXXXXXXXXXXXX)
4   - *
5   - * This source code is free software; you can redistribute it
6   - * and/or modify it in source code form under the terms of the GNU
7   - * General Public License as published by the Free Software
8   - * Foundation; either version 2 of the License, or (at your option)
9   - * any later version.
10   - *
11   - * This program is distributed in the hope that it will be useful,
12   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
13   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14   - * GNU General Public License for more details.
15   - *
16   - * You should have received a copy of the GNU General Public License
17   - * along with this program; if not, write to the Free Software
18   - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
19   - */
20   -
21   -/*
22   - * The Xilinx SystemACE chip support is activated by defining
23   - * CONFIG_SYSTEMACE to turn on support, and CFG_SYSTEMACE_BASE
24   - * to set the base address of the device. This code currently
25   - * assumes that the chip is connected via a byte-wide bus.
26   - *
27   - * The CONFIG_SYSTEMACE also adds to fat support the device class
28   - * "ace" that allows the user to execute "fatls ace 0" and the
29   - * like. This works by making the systemace_get_dev function
30   - * available to cmd_fat.c:get_dev and filling in a block device
31   - * description that has all the bits needed for FAT support to
32   - * read sectors.
33   - *
34   - * According to Xilinx technical support, before accessing the
35   - * SystemACE CF you need to set the following control bits:
36   - * FORCECFGMODE : 1
37   - * CFGMODE : 0
38   - * CFGSTART : 0
39   - */
40   -
41   -#include <common.h>
42   -#include <command.h>
43   -#include <systemace.h>
44   -#include <part.h>
45   -#include <asm/io.h>
46   -
47   -#ifdef CONFIG_SYSTEMACE
48   -
49   -/*
50   - * The ace_readw and writew functions read/write 16bit words, but the
51   - * offset value is the BYTE offset as most used in the Xilinx
52   - * datasheet for the SystemACE chip. The CFG_SYSTEMACE_BASE is defined
53   - * to be the base address for the chip, usually in the local
54   - * peripheral bus.
55   - */
56   -#if (CFG_SYSTEMACE_WIDTH == 8)
57   -#if !defined(__BIG_ENDIAN)
58   -#define ace_readw(off) ((readb(CFG_SYSTEMACE_BASE+off)<<8) | \
59   - (readb(CFG_SYSTEMACE_BASE+off+1)))
60   -#define ace_writew(val, off) {writeb(val>>8, CFG_SYSTEMACE_BASE+off); \
61   - writeb(val, CFG_SYSTEMACE_BASE+off+1);}
62   -#else
63   -#define ace_readw(off) ((readb(CFG_SYSTEMACE_BASE+off)) | \
64   - (readb(CFG_SYSTEMACE_BASE+off+1)<<8))
65   -#define ace_writew(val, off) {writeb(val, CFG_SYSTEMACE_BASE+off); \
66   - writeb(val>>8, CFG_SYSTEMACE_BASE+off+1);}
67   -#endif
68   -#else
69   -#define ace_readw(off) (in16(CFG_SYSTEMACE_BASE+off))
70   -#define ace_writew(val, off) (out16(CFG_SYSTEMACE_BASE+off,val))
71   -#endif
72   -
73   -/* */
74   -
75   -static unsigned long systemace_read(int dev, unsigned long start,
76   - unsigned long blkcnt, void *buffer);
77   -
78   -static block_dev_desc_t systemace_dev = { 0 };
79   -
80   -static int get_cf_lock(void)
81   -{
82   - int retry = 10;
83   -
84   - /* CONTROLREG = LOCKREG */
85   - unsigned val = ace_readw(0x18);
86   - val |= 0x0002;
87   - ace_writew((val & 0xffff), 0x18);
88   -
89   - /* Wait for MPULOCK in STATUSREG[15:0] */
90   - while (!(ace_readw(0x04) & 0x0002)) {
91   -
92   - if (retry < 0)
93   - return -1;
94   -
95   - udelay(100000);
96   - retry -= 1;
97   - }
98   -
99   - return 0;
100   -}
101   -
102   -static void release_cf_lock(void)
103   -{
104   - unsigned val = ace_readw(0x18);
105   - val &= ~(0x0002);
106   - ace_writew((val & 0xffff), 0x18);
107   -}
108   -
109   -block_dev_desc_t *systemace_get_dev(int dev)
110   -{
111   - /* The first time through this, the systemace_dev object is
112   - not yet initialized. In that case, fill it in. */
113   - if (systemace_dev.blksz == 0) {
114   - systemace_dev.if_type = IF_TYPE_UNKNOWN;
115   - systemace_dev.dev = 0;
116   - systemace_dev.part_type = PART_TYPE_UNKNOWN;
117   - systemace_dev.type = DEV_TYPE_HARDDISK;
118   - systemace_dev.blksz = 512;
119   - systemace_dev.removable = 1;
120   - systemace_dev.block_read = systemace_read;
121   -
122   - /*
123   - * Ensure the correct bus mode (8/16 bits) gets enabled
124   - */
125   - ace_writew(CFG_SYSTEMACE_WIDTH == 8 ? 0 : 0x0001, 0);
126   -
127   - init_part(&systemace_dev);
128   -
129   - }
130   -
131   - return &systemace_dev;
132   -}
133   -
134   -/*
135   - * This function is called (by dereferencing the block_read pointer in
136   - * the dev_desc) to read blocks of data. The return value is the
137   - * number of blocks read. A zero return indicates an error.
138   - */
139   -static unsigned long systemace_read(int dev, unsigned long start,
140   - unsigned long blkcnt, void *buffer)
141   -{
142   - int retry;
143   - unsigned blk_countdown;
144   - unsigned char *dp = buffer;
145   - unsigned val;
146   -
147   - if (get_cf_lock() < 0) {
148   - unsigned status = ace_readw(0x04);
149   -
150   - /* If CFDETECT is false, card is missing. */
151   - if (!(status & 0x0010)) {
152   - printf("** CompactFlash card not present. **\n");
153   - return 0;
154   - }
155   -
156   - printf("**** ACE locked away from me (STATUSREG=%04x)\n",
157   - status);
158   - return 0;
159   - }
160   -#ifdef DEBUG_SYSTEMACE
161   - printf("... systemace read %lu sectors at %lu\n", blkcnt, start);
162   -#endif
163   -
164   - retry = 2000;
165   - for (;;) {
166   - val = ace_readw(0x04);
167   -
168   - /* If CFDETECT is false, card is missing. */
169   - if (!(val & 0x0010)) {
170   - printf("**** ACE CompactFlash not found.\n");
171   - release_cf_lock();
172   - return 0;
173   - }
174   -
175   - /* If RDYFORCMD, then we are ready to go. */
176   - if (val & 0x0100)
177   - break;
178   -
179   - if (retry < 0) {
180   - printf("**** SystemACE not ready.\n");
181   - release_cf_lock();
182   - return 0;
183   - }
184   -
185   - udelay(1000);
186   - retry -= 1;
187   - }
188   -
189   - /* The SystemACE can only transfer 256 sectors at a time, so
190   - limit the current chunk of sectors. The blk_countdown
191   - variable is the number of sectors left to transfer. */
192   -
193   - blk_countdown = blkcnt;
194   - while (blk_countdown > 0) {
195   - unsigned trans = blk_countdown;
196   -
197   - if (trans > 256)
198   - trans = 256;
199   -
200   -#ifdef DEBUG_SYSTEMACE
201   - printf("... transfer %lu sector in a chunk\n", trans);
202   -#endif
203   - /* Write LBA block address */
204   - ace_writew((start >> 0) & 0xffff, 0x10);
205   - ace_writew((start >> 16) & 0x0fff, 0x12);
206   -
207   - /* NOTE: in the Write Sector count below, a count of 0
208   - causes a transfer of 256, so &0xff gives the right
209   - value for whatever transfer count we want. */
210   -
211   - /* Write sector count | ReadMemCardData. */
212   - ace_writew((trans & 0xff) | 0x0300, 0x14);
213   -
214   -/*
215   - * For FPGA configuration via SystemACE is reset unacceptable
216   - * CFGDONE bit in STATUSREG is not set to 1.
217   - */
218   -#ifndef SYSTEMACE_CONFIG_FPGA
219   - /* Reset the configruation controller */
220   - val = ace_readw(0x18);
221   - val |= 0x0080;
222   - ace_writew(val, 0x18);
223   -#endif
224   -
225   - retry = trans * 16;
226   - while (retry > 0) {
227   - int idx;
228   -
229   - /* Wait for buffer to become ready. */
230   - while (!(ace_readw(0x04) & 0x0020)) {
231   - udelay(100);
232   - }
233   -
234   - /* Read 16 words of 2bytes from the sector buffer. */
235   - for (idx = 0; idx < 16; idx += 1) {
236   - unsigned short val = ace_readw(0x40);
237   - *dp++ = val & 0xff;
238   - *dp++ = (val >> 8) & 0xff;
239   - }
240   -
241   - retry -= 1;
242   - }
243   -
244   - /* Clear the configruation controller reset */
245   - val = ace_readw(0x18);
246   - val &= ~0x0080;
247   - ace_writew(val, 0x18);
248   -
249   - /* Count the blocks we transfer this time. */
250   - start += trans;
251   - blk_countdown -= trans;
252   - }
253   -
254   - release_cf_lock();
255   -
256   - return blkcnt;
257   -}
258   -#endif /* CONFIG_SYSTEMACE */