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Commit 33f794be36e846a522c7020e642a1e89c0769b17

Authored by Marek Vasut
Committed by Stefano Babic
1 parent 42dc1230cd
Exists in smarc_8mq_lf_v2020.04 and in 9 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

pci: imx: Factor out hard-coded register base addresses 

Pull out hard-coded register base addresses into driver private
structure in preparation for DM conversion. No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Showing 1 changed file with 44 additions and 31 deletions Side-by-side Diff

drivers/pci/pcie_imx.c
Diff comments   View file @ 33f794b
... ... @@ -92,6 +92,18 @@
92 92 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
93 93 #define PCIE_ATU_UPPER_TARGET 0x91C
94 94  
  95 +struct imx_pcie_priv {
  96 + void __iomem *dbi_base;
  97 + void __iomem *cfg_base;
  98 +};
  99 +
  100 +static struct imx_pcie_priv imx_pcie_priv = {
  101 + .dbi_base = (void __iomem *)MX6_DBI_ADDR,
  102 + .cfg_base = (void __iomem *)MX6_ROOT_ADDR,
  103 +};
  104 +
  105 +static struct imx_pcie_priv *priv = &imx_pcie_priv;
  106 +
95 107 /*
96 108 * PHY access functions
97 109 */
... ... @@ -231,7 +243,7 @@
231 243 int rx_valid, temp;
232 244  
233 245 /* link is debug bit 36, debug register 1 starts at bit 32 */
234   - rc = readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1);
  246 + rc = readl(priv->dbi_base + PCIE_PHY_DEBUG_R1);
235 247 if ((rc & PCIE_PHY_DEBUG_R1_LINK_UP) &&
236 248 !(rc & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING))
237 249 return -EAGAIN;
... ... @@ -243,8 +255,8 @@
243 255 * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition
244 256 * to gen2 is stuck
245 257 */
246   - pcie_phy_read((void *)MX6_DBI_ADDR, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
247   - ltssm = readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R0) & 0x3F;
  258 + pcie_phy_read(priv->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
  259 + ltssm = readl(priv->dbi_base + PCIE_PHY_DEBUG_R0) & 0x3F;
248 260  
249 261 if (rx_valid & 0x01)
250 262 return 0;
251 263  
252 264  
253 265  
... ... @@ -254,15 +266,15 @@
254 266  
255 267 printf("transition to gen2 is stuck, reset PHY!\n");
256 268  
257   - pcie_phy_read((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, &temp);
  269 + pcie_phy_read(priv->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
258 270 temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
259   - pcie_phy_write((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, temp);
  271 + pcie_phy_write(priv->dbi_base, PHY_RX_OVRD_IN_LO, temp);
260 272  
261 273 udelay(3000);
262 274  
263   - pcie_phy_read((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, &temp);
  275 + pcie_phy_read(priv->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
264 276 temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
265   - pcie_phy_write((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, temp);
  277 + pcie_phy_write(priv->dbi_base, PHY_RX_OVRD_IN_LO, temp);
266 278  
267 279 return 0;
268 280 }
269 281  
270 282  
271 283  
272 284  
... ... @@ -285,24 +297,25 @@
285 297 */
286 298  
287 299 /* CMD reg:I/O space, MEM space, and Bus Master Enable */
288   - setbits_le32(MX6_DBI_ADDR | PCI_COMMAND,
  300 + setbits_le32(priv->dbi_base + PCI_COMMAND,
289 301 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
290 302  
291 303 /* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */
292   - setbits_le32(MX6_DBI_ADDR + PCI_CLASS_REVISION,
  304 + setbits_le32(priv->dbi_base + PCI_CLASS_REVISION,
293 305 PCI_CLASS_BRIDGE_PCI << 16);
294 306  
295 307 /* Region #0 is used for Outbound CFG space access. */
296   - writel(0, MX6_DBI_ADDR + PCIE_ATU_VIEWPORT);
  308 + writel(0, priv->dbi_base + PCIE_ATU_VIEWPORT);
297 309  
298   - writel(MX6_ROOT_ADDR, MX6_DBI_ADDR + PCIE_ATU_LOWER_BASE);
299   - writel(0, MX6_DBI_ADDR + PCIE_ATU_UPPER_BASE);
300   - writel(MX6_ROOT_ADDR + MX6_ROOT_SIZE, MX6_DBI_ADDR + PCIE_ATU_LIMIT);
  310 + writel((u32)priv->cfg_base, priv->dbi_base + PCIE_ATU_LOWER_BASE);
  311 + writel(0, priv->dbi_base + PCIE_ATU_UPPER_BASE);
  312 + writel((u32)priv->cfg_base + MX6_ROOT_SIZE,
  313 + priv->dbi_base + PCIE_ATU_LIMIT);
301 314  
302   - writel(0, MX6_DBI_ADDR + PCIE_ATU_LOWER_TARGET);
303   - writel(0, MX6_DBI_ADDR + PCIE_ATU_UPPER_TARGET);
304   - writel(PCIE_ATU_TYPE_CFG0, MX6_DBI_ADDR + PCIE_ATU_CR1);
305   - writel(PCIE_ATU_ENABLE, MX6_DBI_ADDR + PCIE_ATU_CR2);
  315 + writel(0, priv->dbi_base + PCIE_ATU_LOWER_TARGET);
  316 + writel(0, priv->dbi_base + PCIE_ATU_UPPER_TARGET);
  317 + writel(PCIE_ATU_TYPE_CFG0, priv->dbi_base + PCIE_ATU_CR1);
  318 + writel(PCIE_ATU_ENABLE, priv->dbi_base + PCIE_ATU_CR2);
306 319  
307 320 return 0;
308 321 }
309 322  
310 323  
311 324  
312 325  
... ... @@ -315,18 +328,18 @@
315 328 uint32_t va_address;
316 329  
317 330 /* Reconfigure Region #0 */
318   - writel(0, MX6_DBI_ADDR + PCIE_ATU_VIEWPORT);
  331 + writel(0, priv->dbi_base + PCIE_ATU_VIEWPORT);
319 332  
320 333 if (PCI_BUS(d) < 2)
321   - writel(PCIE_ATU_TYPE_CFG0, MX6_DBI_ADDR + PCIE_ATU_CR1);
  334 + writel(PCIE_ATU_TYPE_CFG0, priv->dbi_base + PCIE_ATU_CR1);
322 335 else
323   - writel(PCIE_ATU_TYPE_CFG1, MX6_DBI_ADDR + PCIE_ATU_CR1);
  336 + writel(PCIE_ATU_TYPE_CFG1, priv->dbi_base + PCIE_ATU_CR1);
324 337  
325 338 if (PCI_BUS(d) == 0) {
326   - va_address = MX6_DBI_ADDR;
  339 + va_address = (u32)priv->dbi_base;
327 340 } else {
328   - writel(d << 8, MX6_DBI_ADDR + PCIE_ATU_LOWER_TARGET);
329   - va_address = MX6_IO_ADDR + SZ_16M - SZ_1M;
  341 + writel(d << 8, priv->dbi_base + PCIE_ATU_LOWER_TARGET);
  342 + va_address = (u32)priv->cfg_base;
330 343 }
331 344  
332 345 va_address += (where & ~0x3);
333 346  
... ... @@ -465,12 +478,12 @@
465 478 gpr12 = readl(&iomuxc_regs->gpr[12]);
466 479 if ((gpr1 & IOMUXC_GPR1_PCIE_REF_CLK_EN) &&
467 480 (gpr12 & IOMUXC_GPR12_PCIE_CTL_2)) {
468   - val = readl(MX6_DBI_ADDR + PCIE_PL_PFLR);
  481 + val = readl(priv->dbi_base + PCIE_PL_PFLR);
469 482 val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
470 483 val |= PCIE_PL_PFLR_FORCE_LINK;
471 484  
472 485 imx_pcie_fix_dabt_handler(true);
473   - writel(val, MX6_DBI_ADDR + PCIE_PL_PFLR);
  486 + writel(val, priv->dbi_base + PCIE_PL_PFLR);
474 487 imx_pcie_fix_dabt_handler(false);
475 488  
476 489 gpr12 &= ~IOMUXC_GPR12_PCIE_CTL_2;
477 490  
... ... @@ -621,9 +634,9 @@
621 634 * Force the PCIe RC subordinate to 0xff, otherwise no downstream
622 635 * devices will be detected if the enumeration is applied strictly.
623 636 */
624   - tmp = readl(MX6_DBI_ADDR + 0x18);
  637 + tmp = readl(priv->dbi_base + 0x18);
625 638 tmp |= (0xff << 16);
626   - writel(tmp, MX6_DBI_ADDR + 0x18);
  639 + writel(tmp, priv->dbi_base + 0x18);
627 640  
628 641 /*
629 642 * FIXME: Force the PCIe RC to Gen1 operation
630 643  
... ... @@ -631,10 +644,10 @@
631 644 * up, otherwise no downstream devices are detected. After the
632 645 * link is up, a managed Gen1->Gen2 transition can be initiated.
633 646 */
634   - tmp = readl(MX6_DBI_ADDR + 0x7c);
  647 + tmp = readl(priv->dbi_base + 0x7c);
635 648 tmp &= ~0xf;
636 649 tmp |= 0x1;
637   - writel(tmp, MX6_DBI_ADDR + 0x7c);
  650 + writel(tmp, priv->dbi_base + 0x7c);
638 651  
639 652 /* LTSSM enable, starting link. */
640 653 setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE);
... ... @@ -647,8 +660,8 @@
647 660 puts("PCI: pcie phy link never came up\n");
648 661 #endif
649 662 debug("DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
650   - readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R0),
651   - readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1));
  663 + readl(priv->dbi_base + PCIE_PHY_DEBUG_R0),
  664 + readl(priv->dbi_base + PCIE_PHY_DEBUG_R1));
652 665 return -EINVAL;
653 666 }
654 667 }