arm/ls102xa: Add PSCI support for ls102xa

Base on PSCI services, implement CPU_ON/CPU_OFF for ls102xa platform. Tested on LS1021AQDS, LS1021ATWR. Test CPU hotplug times: 60K Test kernel boot times: 1.2K Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Acked-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>

arm/ls102xa: Add PSCI support for ls102xa
Base on PSCI services, implement CPU_ON/CPU_OFF for ls102xa platform. Tested on LS1021AQDS, LS1021ATWR. Test CPU hotplug times: 60K Test kernel boot times: 1.2K Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Acked-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Wang Dongsheng · York Sun
1 parent 972af2ab51
Showing 4 changed files with 134 additions and 0 deletions Side-by-side Diff
arch/arm/cpu/armv7/ls102xa/Makefile
arch/arm/cpu/armv7/ls102xa/psci.S
include/configs/ls1021aqds.h
include/configs/ls1021atwr.h
@@ -12,4 +12,8 @@
 obj-$(CONFIG_OF_LIBFDT) += fdt.o
 obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o
 obj-$(CONFIG_SPL) += spl.o
+
+ifdef CONFIG_ARMV7_PSCI
+obj-y  += psci.o
+endif
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ * Author: Wang Dongsheng <dongsheng.wang@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+
+#include <asm/armv7.h>
+#include <asm/arch-armv7/generictimer.h>
+#include <asm/psci.h>
+
+#define SCFG_CORE0_SFT_RST      0x130
+#define SCFG_CORESRENCR         0x204
+
+#define DCFG_CCSR_BRR           0x0E4
+#define DCFG_CCSR_SCRATCHRW1    0x200
+
+	.pushsection ._secure.text, "ax"
+
+	.arch_extension sec
+
+#define	ONE_MS		(GENERIC_TIMER_CLK / 1000)
+#define	RESET_WAIT	(30 * ONE_MS)
+
+	@ r1 = target CPU
+	@ r2 = target PC
+.globl	psci_cpu_on
+psci_cpu_on:
+	push	{lr}
+
+	@ Clear and Get the correct CPU number
+	@ r1 = 0xf01
+	and	r1, r1, #0xff
+
+	mov	r0, r1
+	bl	psci_get_cpu_stack_top
+	str	r2, [r0]
+	dsb
+
+	@ Get DCFG base address
+	movw	r4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
+	movt	r4, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
+
+	@ Detect target CPU state
+	ldr	r2, [r4, #DCFG_CCSR_BRR]
+	rev	r2, r2
+	lsr	r2, r2, r1
+	ands	r2, r2, #1
+	beq	holdoff_release
+
+	@ Reset target CPU
+	@ Get SCFG base address
+	movw	r0, #(CONFIG_SYS_FSL_SCFG_ADDR & 0xffff)
+	movt	r0, #(CONFIG_SYS_FSL_SCFG_ADDR >> 16)
+
+	@ Enable CORE Soft Reset
+	movw	r5, #0
+	movt	r5, #(1 << 15)
+	rev	r5, r5
+	str	r5, [r0, #SCFG_CORESRENCR]
+
+	@ Get CPUx offset register
+	mov	r6, #0x4
+	mul	r6, r6, r1
+	add	r2, r0, r6
+
+	@ Do reset on target CPU
+	movw	r5, #0
+	movt	r5, #(1 << 15)
+	rev	r5, r5
+	str	r5, [r2, #SCFG_CORE0_SFT_RST]
+
+	@ Wait target CPU up
+	timer_wait	r2, RESET_WAIT
+
+	@ Disable CORE soft reset
+	mov	r5, #0
+	str	r5, [r0, #SCFG_CORESRENCR]
+
+holdoff_release:
+	@ Release on target CPU
+	ldr	r2, [r4, #DCFG_CCSR_BRR]
+	mov	r6, #1
+	lsl	r6, r6, r1	@ 32 bytes per CPU
+
+	rev	r6, r6
+	orr	r2, r2, r6
+	str	r2, [r4, #DCFG_CCSR_BRR]
+
+	@ Set secondary boot entry
+	ldr	r6, =psci_cpu_entry
+	rev	r6, r6
+	str	r6, [r4, #DCFG_CCSR_SCRATCHRW1]
+
+	isb
+	dsb
+
+	@ Return
+	mov	r0, #ARM_PSCI_RET_SUCCESS
+
+	pop	{lr}
+	bx	lr
+
+.globl	psci_cpu_off
+psci_cpu_off:
+	bl	psci_cpu_off_common
+
+1:	wfi
+	b	1b
+
+.globl	psci_arch_init
+psci_arch_init:
+	mov	r6, lr
+
+	bl	psci_get_cpu_id
+	bl	psci_get_cpu_stack_top
+	mov	sp, r0
+
+	bx	r6
+
+	.globl psci_text_end
+psci_text_end:
+	.popsection
@@ -9,6 +9,8 @@
  
 #define CONFIG_LS102XA
  
+#define CONFIG_ARMV7_PSCI
+
 #define CONFIG_SYS_GENERIC_BOARD
  
 #define CONFIG_DISPLAY_CPUINFO
@@ -9,6 +9,8 @@
  
 #define CONFIG_LS102XA
  
+#define CONFIG_ARMV7_PSCI
+
 #define CONFIG_SYS_GENERIC_BOARD
  
 #define CONFIG_DISPLAY_CPUINFO
...	...	@@ -12,4 +12,8 @@
12	12	obj-$(CONFIG_OF_LIBFDT) += fdt.o
13	13	obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o
14	14	obj-$(CONFIG_SPL) += spl.o
	15	+
	16	+ifdef CONFIG_ARMV7_PSCI
	17	+obj-y += psci.o
	18	+endif
	1	+/*
	2	+ * Copyright 2015 Freescale Semiconductor, Inc.
	3	+ * Author: Wang Dongsheng <dongsheng.wang@freescale.com>
	4	+ *
	5	+ * SPDX-License-Identifier: GPL-2.0+
	6	+ */
	7	+
	8	+#include <config.h>
	9	+#include <linux/linkage.h>
	10	+
	11	+#include <asm/armv7.h>
	12	+#include <asm/arch-armv7/generictimer.h>
	13	+#include <asm/psci.h>
	14	+
	15	+#define SCFG_CORE0_SFT_RST 0x130
	16	+#define SCFG_CORESRENCR 0x204
	17	+
	18	+#define DCFG_CCSR_BRR 0x0E4
	19	+#define DCFG_CCSR_SCRATCHRW1 0x200
	20	+
	21	+ .pushsection ._secure.text, "ax"
	22	+
	23	+ .arch_extension sec
	24	+
	25	+#define ONE_MS (GENERIC_TIMER_CLK / 1000)
	26	+#define RESET_WAIT (30 * ONE_MS)
	27	+
	28	+ @ r1 = target CPU
	29	+ @ r2 = target PC
	30	+.globl psci_cpu_on
	31	+psci_cpu_on:
	32	+ push {lr}
	33	+
	34	+ @ Clear and Get the correct CPU number
	35	+ @ r1 = 0xf01
	36	+ and r1, r1, #0xff
	37	+
	38	+ mov r0, r1
	39	+ bl psci_get_cpu_stack_top
	40	+ str r2, [r0]
	41	+ dsb
	42	+
	43	+ @ Get DCFG base address
	44	+ movw r4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
	45	+ movt r4, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
	46	+
	47	+ @ Detect target CPU state
	48	+ ldr r2, [r4, #DCFG_CCSR_BRR]
	49	+ rev r2, r2
	50	+ lsr r2, r2, r1
	51	+ ands r2, r2, #1
	52	+ beq holdoff_release
	53	+
	54	+ @ Reset target CPU
	55	+ @ Get SCFG base address
	56	+ movw r0, #(CONFIG_SYS_FSL_SCFG_ADDR & 0xffff)
	57	+ movt r0, #(CONFIG_SYS_FSL_SCFG_ADDR >> 16)
	58	+
	59	+ @ Enable CORE Soft Reset
	60	+ movw r5, #0
	61	+ movt r5, #(1 << 15)
	62	+ rev r5, r5
	63	+ str r5, [r0, #SCFG_CORESRENCR]
	64	+
	65	+ @ Get CPUx offset register
	66	+ mov r6, #0x4
	67	+ mul r6, r6, r1
	68	+ add r2, r0, r6
	69	+
	70	+ @ Do reset on target CPU
	71	+ movw r5, #0
	72	+ movt r5, #(1 << 15)
	73	+ rev r5, r5
	74	+ str r5, [r2, #SCFG_CORE0_SFT_RST]
	75	+
	76	+ @ Wait target CPU up
	77	+ timer_wait r2, RESET_WAIT
	78	+
	79	+ @ Disable CORE soft reset
	80	+ mov r5, #0
	81	+ str r5, [r0, #SCFG_CORESRENCR]
	82	+
	83	+holdoff_release:
	84	+ @ Release on target CPU
	85	+ ldr r2, [r4, #DCFG_CCSR_BRR]
	86	+ mov r6, #1
	87	+ lsl r6, r6, r1 @ 32 bytes per CPU
	88	+
	89	+ rev r6, r6
	90	+ orr r2, r2, r6
	91	+ str r2, [r4, #DCFG_CCSR_BRR]
	92	+
	93	+ @ Set secondary boot entry
	94	+ ldr r6, =psci_cpu_entry
	95	+ rev r6, r6
	96	+ str r6, [r4, #DCFG_CCSR_SCRATCHRW1]
	97	+
	98	+ isb
	99	+ dsb
	100	+
	101	+ @ Return
	102	+ mov r0, #ARM_PSCI_RET_SUCCESS
	103	+
	104	+ pop {lr}
	105	+ bx lr
	106	+
	107	+.globl psci_cpu_off
	108	+psci_cpu_off:
	109	+ bl psci_cpu_off_common
	110	+
	111	+1: wfi
	112	+ b 1b
	113	+
	114	+.globl psci_arch_init
	115	+psci_arch_init:
	116	+ mov r6, lr
	117	+
	118	+ bl psci_get_cpu_id
	119	+ bl psci_get_cpu_stack_top
	120	+ mov sp, r0
	121	+
	122	+ bx r6
	123	+
	124	+ .globl psci_text_end
	125	+psci_text_end:
	126	+ .popsection
...	...	@@ -9,6 +9,8 @@
9	9
10	10	#define CONFIG_LS102XA
11	11
	12	+#define CONFIG_ARMV7_PSCI
	13	+
12	14	#define CONFIG_SYS_GENERIC_BOARD
13	15
14	16	#define CONFIG_DISPLAY_CPUINFO