Eric Lee / smarc-uboot | Embedian Git Server

Commit 344c837686b4268882ee4942f2a1e5e5716c7383

Authored by Simon Glass 2015-08-31 06:55:20 +0800

Exists in v2017.01-smarct4x and in 30 other branches

rockchip: Bring in RK3288 device tree file includes and bindings

Bring in required device tree files from Linux. Since mainline Linux is
somewhat behind, use the files from the Chromium tree. We can re-sync once
further code is acccepted upstream.

Signed-off-by: Simon Glass <sjg@chromium.org>

Showing 12 changed files with 2543 additions and 0 deletions Side-by-side Diff

arch/arm/dts/rk3288-thermal.dtsi
arch/arm/dts/rk3288.dtsi
doc/device-tree-bindings/clock/rockchip,rk3188-cru.txt
doc/device-tree-bindings/clock/rockchip,rk3288-cru.txt
doc/device-tree-bindings/clock/rockchip,rk3288-dmc.txt
doc/device-tree-bindings/clock/rockchip.txt
doc/device-tree-bindings/pinctrl/rockchip,pinctrl.txt
doc/device-tree-bindings/thermal/rockchip-thermal.txt
include/dt-bindings/clock/rk3288-cru.h
include/dt-bindings/clock/rockchip,rk808.h
include/dt-bindings/pinctrl/rockchip.h
include/dt-bindings/power-domain/rk3288.h

arch/arm/dts/rk3288-thermal.dtsi

Diff comments View file @ 344c837

	1	+/*
	2	+ * Device Tree Source for RK3288 SoC thermal
	3	+ *
	4	+ * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
	5	+ *
	6	+ * SPDX-License-Identifier: GPL-2.0
	7	+ */
	8	+
	9	+#include <dt-bindings/thermal/thermal.h>
	10	+
	11	+reserve_thermal: reserve_thermal {
	12	+ polling-delay-passive = <1000>; /* milliseconds */
	13	+ polling-delay = <5000>; /* milliseconds */
	14	+
	15	+ /* sensor ID */
	16	+ thermal-sensors = <&tsadc 0>;
	17	+
	18	+};
	19	+
	20	+cpu_thermal: cpu_thermal {
	21	+ polling-delay-passive = <100>; /* milliseconds */
	22	+ polling-delay = <5000>; /* milliseconds */
	23	+
	24	+ /* sensor ID */
	25	+ thermal-sensors = <&tsadc 1>;
	26	+ linux,hwmon;
	27	+
	28	+ trips {
	29	+ cpu_alert0: cpu_alert0 {
	30	+ temperature = <70000>; /* millicelsius */
	31	+ hysteresis = <2000>; /* millicelsius */
	32	+ type = "passive";
	33	+ };
	34	+ cpu_alert1: cpu_alert1 {
	35	+ temperature = <75000>; /* millicelsius */
	36	+ hysteresis = <2000>; /* millicelsius */
	37	+ type = "passive";
	38	+ };
	39	+ cpu_crit: cpu_crit {
	40	+ temperature = <100000>; /* millicelsius */
	41	+ hysteresis = <2000>; /* millicelsius */
	42	+ type = "critical";
	43	+ };
	44	+ };
	45	+
	46	+ cooling-maps {
	47	+ map0 {
	48	+ trip = <&cpu_alert0>;
	49	+ cooling-device =
	50	+ <&cpu0 THERMAL_NO_LIMIT 6>;
	51	+ };
	52	+ map1 {
	53	+ trip = <&cpu_alert1>;
	54	+ cooling-device =
	55	+ <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	56	+ };
	57	+ };
	58	+};
	59	+
	60	+gpu_thermal: gpu_thermal {
	61	+ polling-delay-passive = <100>; /* milliseconds */
	62	+ polling-delay = <5000>; /* milliseconds */
	63	+
	64	+ /* sensor ID */
	65	+ thermal-sensors = <&tsadc 2>;
	66	+ linux,hwmon;
	67	+
	68	+ trips {
	69	+ gpu_alert0: gpu_alert0 {
	70	+ temperature = <80000>; /* millicelsius */
	71	+ hysteresis = <2000>; /* millicelsius */
	72	+ type = "passive";
	73	+ };
	74	+ gpu_crit: gpu_crit {
	75	+ temperature = <100000>; /* millicelsius */
	76	+ hysteresis = <2000>; /* millicelsius */
	77	+ type = "critical";
	78	+ };
	79	+ };
	80	+
	81	+ cooling-maps {
	82	+ map0 {
	83	+ trip = <&gpu_alert0>;
	84	+ cooling-device =
	85	+ <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	86	+ };
	87	+ };
	88	+};

arch/arm/dts/rk3288.dtsi

Diff comments View file @ 344c837

Changes suppressed. Click to show

	1	+/*
	2	+ * SPDX-License-Identifier: GPL-2.0+
	3	+ */
	4	+
	5	+#include <dt-bindings/gpio/gpio.h>
	6	+#include <dt-bindings/interrupt-controller/irq.h>
	7	+#include <dt-bindings/interrupt-controller/arm-gic.h>
	8	+#include <dt-bindings/pinctrl/rockchip.h>
	9	+#include <dt-bindings/clock/rk3288-cru.h>
	10	+#include <dt-bindings/power-domain/rk3288.h>
	11	+#include <dt-bindings/thermal/thermal.h>
	12	+#include "skeleton.dtsi"
	13	+
	14	+/ {
	15	+ compatible = "rockchip,rk3288";
	16	+
	17	+ interrupt-parent = <&gic>;
	18	+ aliases {
	19	+ i2c0 = &i2c0;
	20	+ i2c1 = &i2c1;
	21	+ i2c2 = &i2c2;
	22	+ i2c3 = &i2c3;
	23	+ i2c4 = &i2c4;
	24	+ i2c5 = &i2c5;
	25	+ mmc0 = &emmc;
	26	+ mmc1 = &sdmmc;
	27	+ mmc2 = &sdio0;
	28	+ mmc3 = &sdio1;
	29	+ mshc0 = &emmc;
	30	+ mshc1 = &sdmmc;
	31	+ mshc2 = &sdio0;
	32	+ mshc3 = &sdio1;
	33	+ serial0 = &uart0;
	34	+ serial1 = &uart1;
	35	+ serial2 = &uart2;
	36	+ serial3 = &uart3;
	37	+ serial4 = &uart4;
	38	+ spi0 = &spi0;
	39	+ spi1 = &spi1;
	40	+ spi2 = &spi2;
	41	+ };
	42	+
	43	+ cpus {
	44	+ #address-cells = <1>;
	45	+ #size-cells = <0>;
	46	+ enable-method = "rockchip,rk3066-smp";
	47	+ rockchip,pmu = <&pmu>;
	48	+
	49	+ cpu0: cpu@500 {
	50	+ device_type = "cpu";
	51	+ compatible = "arm,cortex-a12";
	52	+ reg = <0x500>;
	53	+ operating-points = <
	54	+ /* KHz uV */
	55	+ 1800000 1400000
	56	+ 1704000 1350000
	57	+ 1608000 1300000
	58	+ 1512000 1250000
	59	+ 1416000 1200000
	60	+ 1200000 1100000
	61	+ 1008000 1050000
	62	+ 816000 1000000
	63	+ 696000 950000
	64	+ 600000 900000
	65	+ 408000 900000
	66	+ 216000 900000
	67	+ 126000 900000
	68	+ >;
	69	+ #cooling-cells = <2>; /* min followed by max */
	70	+ clock-latency = <40000>;
	71	+ clocks = <&cru ARMCLK>;
	72	+ resets = <&cru SRST_CORE0>;
	73	+ };
	74	+ cpu@501 {
	75	+ device_type = "cpu";
	76	+ compatible = "arm,cortex-a12";
	77	+ reg = <0x501>;
	78	+ resets = <&cru SRST_CORE1>;
	79	+ };
	80	+ cpu@502 {
	81	+ device_type = "cpu";
	82	+ compatible = "arm,cortex-a12";
	83	+ reg = <0x502>;
	84	+ resets = <&cru SRST_CORE2>;
	85	+ };
	86	+ cpu@503 {
	87	+ device_type = "cpu";
	88	+ compatible = "arm,cortex-a12";
	89	+ reg = <0x503>;
	90	+ resets = <&cru SRST_CORE3>;
	91	+ };
	92	+ };
	93	+
	94	+ amba {
	95	+ compatible = "arm,amba-bus";
	96	+ #address-cells = <1>;
	97	+ #size-cells = <1>;
	98	+ ranges;
	99	+
	100	+ dmac_peri: dma-controller@ff250000 {
	101	+ compatible = "arm,pl330", "arm,primecell";
	102	+ broken-no-flushp;
	103	+ reg = <0xff250000 0x4000>;
	104	+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
	105	+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	106	+ #dma-cells = <1>;
	107	+ clocks = <&cru ACLK_DMAC2>;
	108	+ clock-names = "apb_pclk";
	109	+ };
	110	+
	111	+ dmac_bus_ns: dma-controller@ff600000 {
	112	+ compatible = "arm,pl330", "arm,primecell";
	113	+ broken-no-flushp;
	114	+ reg = <0xff600000 0x4000>;
	115	+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	116	+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
	117	+ #dma-cells = <1>;
	118	+ clocks = <&cru ACLK_DMAC1>;
	119	+ clock-names = "apb_pclk";
	120	+ status = "disabled";
	121	+ };
	122	+
	123	+ dmac_bus_s: dma-controller@ffb20000 {
	124	+ compatible = "arm,pl330", "arm,primecell";
	125	+ broken-no-flushp;
	126	+ reg = <0xffb20000 0x4000>;
	127	+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	128	+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
	129	+ #dma-cells = <1>;
	130	+ clocks = <&cru ACLK_DMAC1>;
	131	+ clock-names = "apb_pclk";
	132	+ };
	133	+ };
	134	+
	135	+ xin24m: oscillator {
	136	+ compatible = "fixed-clock";
	137	+ clock-frequency = <24000000>;
	138	+ clock-output-names = "xin24m";
	139	+ #clock-cells = <0>;
	140	+ };
	141	+
	142	+ timer {
	143	+ arm,use-physical-timer;
	144	+ compatible = "arm,armv7-timer";
	145	+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	146	+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	147	+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	148	+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	149	+ clock-frequency = <24000000>;
	150	+ always-on;
	151	+ };
	152	+
	153	+ display-subsystem {
	154	+ compatible = "rockchip,display-subsystem";
	155	+ ports = <&vopl_out>, <&vopb_out>;
	156	+ };
	157	+
	158	+ sdmmc: dwmmc@ff0c0000 {
	159	+ compatible = "rockchip,rk3288-dw-mshc";
	160	+ clock-freq-min-max = <400000 150000000>;
	161	+ clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
	162	+ <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
	163	+ clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
	164	+ fifo-depth = <0x100>;
	165	+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	166	+ reg = <0xff0c0000 0x4000>;
	167	+ status = "disabled";
	168	+ };
	169	+
	170	+ sdio0: dwmmc@ff0d0000 {
	171	+ compatible = "rockchip,rk3288-dw-mshc";
	172	+ clock-freq-min-max = <400000 150000000>;
	173	+ clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
	174	+ <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
	175	+ clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
	176	+ fifo-depth = <0x100>;
	177	+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
	178	+ reg = <0xff0d0000 0x4000>;
	179	+ status = "disabled";
	180	+ };
	181	+
	182	+ sdio1: dwmmc@ff0e0000 {
	183	+ compatible = "rockchip,rk3288-dw-mshc";
	184	+ clock-freq-min-max = <400000 150000000>;
	185	+ clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
	186	+ <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
	187	+ clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
	188	+ fifo-depth = <0x100>;
	189	+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
	190	+ reg = <0xff0e0000 0x4000>;
	191	+ status = "disabled";
	192	+ };
	193	+
	194	+ emmc: dwmmc@ff0f0000 {
	195	+ compatible = "rockchip,rk3288-dw-mshc";
	196	+ clock-freq-min-max = <400000 150000000>;
	197	+ clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
	198	+ <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
	199	+ clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
	200	+ fifo-depth = <0x100>;
	201	+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
	202	+ reg = <0xff0f0000 0x4000>;
	203	+ status = "disabled";
	204	+ };
	205	+
	206	+ saradc: saradc@ff100000 {
	207	+ compatible = "rockchip,saradc";
	208	+ reg = <0xff100000 0x100>;
	209	+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	210	+ #io-channel-cells = <1>;
	211	+ clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
	212	+ clock-names = "saradc", "apb_pclk";
	213	+ status = "disabled";
	214	+ };
	215	+
	216	+ spi0: spi@ff110000 {
	217	+ compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
	218	+ clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
	219	+ clock-names = "spiclk", "apb_pclk";
	220	+ dmas = <&dmac_peri 11>, <&dmac_peri 12>;
	221	+ dma-names = "tx", "rx";
	222	+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
	223	+ pinctrl-names = "default";
	224	+ pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
	225	+ reg = <0xff110000 0x1000>;
	226	+ #address-cells = <1>;
	227	+ #size-cells = <0>;
	228	+ status = "disabled";
	229	+ };
	230	+
	231	+ spi1: spi@ff120000 {
	232	+ compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
	233	+ clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
	234	+ clock-names = "spiclk", "apb_pclk";
	235	+ dmas = <&dmac_peri 13>, <&dmac_peri 14>;
	236	+ dma-names = "tx", "rx";
	237	+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
	238	+ pinctrl-names = "default";
	239	+ pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
	240	+ reg = <0xff120000 0x1000>;
	241	+ #address-cells = <1>;
	242	+ #size-cells = <0>;
	243	+ status = "disabled";
	244	+ };
	245	+
	246	+ spi2: spi@ff130000 {
	247	+ compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
	248	+ clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
	249	+ clock-names = "spiclk", "apb_pclk";
	250	+ dmas = <&dmac_peri 15>, <&dmac_peri 16>;
	251	+ dma-names = "tx", "rx";
	252	+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
	253	+ pinctrl-names = "default";
	254	+ pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
	255	+ reg = <0xff130000 0x1000>;
	256	+ #address-cells = <1>;
	257	+ #size-cells = <0>;
	258	+ status = "disabled";
	259	+ };
	260	+
	261	+ i2c1: i2c@ff140000 {
	262	+ compatible = "rockchip,rk3288-i2c";
	263	+ reg = <0xff140000 0x1000>;
	264	+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
	265	+ #address-cells = <1>;
	266	+ #size-cells = <0>;
	267	+ clock-names = "i2c";
	268	+ clocks = <&cru PCLK_I2C1>;
	269	+ pinctrl-names = "default";
	270	+ pinctrl-0 = <&i2c1_xfer>;
	271	+ status = "disabled";
	272	+ };
	273	+
	274	+ i2c3: i2c@ff150000 {
	275	+ compatible = "rockchip,rk3288-i2c";
	276	+ reg = <0xff150000 0x1000>;
	277	+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
	278	+ #address-cells = <1>;
	279	+ #size-cells = <0>;
	280	+ clock-names = "i2c";
	281	+ clocks = <&cru PCLK_I2C3>;
	282	+ pinctrl-names = "default";
	283	+ pinctrl-0 = <&i2c3_xfer>;
	284	+ status = "disabled";
	285	+ };
	286	+
	287	+ i2c4: i2c@ff160000 {
	288	+ compatible = "rockchip,rk3288-i2c";
	289	+ reg = <0xff160000 0x1000>;
	290	+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
	291	+ #address-cells = <1>;
	292	+ #size-cells = <0>;
	293	+ clock-names = "i2c";
	294	+ clocks = <&cru PCLK_I2C4>;
	295	+ pinctrl-names = "default";
	296	+ pinctrl-0 = <&i2c4_xfer>;
	297	+ status = "disabled";
	298	+ };
	299	+
	300	+ i2c5: i2c@ff170000 {
	301	+ compatible = "rockchip,rk3288-i2c";
	302	+ reg = <0xff170000 0x1000>;
	303	+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
	304	+ #address-cells = <1>;
	305	+ #size-cells = <0>;
	306	+ clock-names = "i2c";
	307	+ clocks = <&cru PCLK_I2C5>;
	308	+ pinctrl-names = "default";
	309	+ pinctrl-0 = <&i2c5_xfer>;
	310	+ status = "disabled";
	311	+ };
	312	+ uart0: serial@ff180000 {
	313	+ compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
	314	+ reg = <0xff180000 0x100>;
	315	+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
	316	+ reg-shift = <2>;
	317	+ reg-io-width = <4>;
	318	+ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
	319	+ clock-names = "baudclk", "apb_pclk";
	320	+ pinctrl-names = "default";
	321	+ pinctrl-0 = <&uart0_xfer>;
	322	+ status = "disabled";
	323	+ };
	324	+
	325	+ uart1: serial@ff190000 {
	326	+ compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
	327	+ reg = <0xff190000 0x100>;
	328	+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
	329	+ reg-shift = <2>;
	330	+ reg-io-width = <4>;
	331	+ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
	332	+ clock-names = "baudclk", "apb_pclk";
	333	+ pinctrl-names = "default";
	334	+ pinctrl-0 = <&uart1_xfer>;
	335	+ status = "disabled";
	336	+ };
	337	+
	338	+ uart2: serial@ff690000 {
	339	+ compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
	340	+ reg = <0xff690000 0x100>;
	341	+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
	342	+ reg-shift = <2>;
	343	+ reg-io-width = <4>;
	344	+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
	345	+ clock-names = "baudclk", "apb_pclk";
	346	+ pinctrl-names = "default";
	347	+ pinctrl-0 = <&uart2_xfer>;
	348	+ status = "disabled";
	349	+ };
	350	+ uart3: serial@ff1b0000 {
	351	+ compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
	352	+ reg = <0xff1b0000 0x100>;
	353	+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
	354	+ reg-shift = <2>;
	355	+ reg-io-width = <4>;
	356	+ clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
	357	+ clock-names = "baudclk", "apb_pclk";
	358	+ pinctrl-names = "default";
	359	+ pinctrl-0 = <&uart3_xfer>;
	360	+ status = "disabled";
	361	+ };
	362	+
	363	+ uart4: serial@ff1c0000 {
	364	+ compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
	365	+ reg = <0xff1c0000 0x100>;
	366	+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
	367	+ reg-shift = <2>;
	368	+ reg-io-width = <4>;
	369	+ clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
	370	+ clock-names = "baudclk", "apb_pclk";
	371	+ pinctrl-names = "default";
	372	+ pinctrl-0 = <&uart4_xfer>;
	373	+ status = "disabled";
	374	+ };
	375	+ thermal: thermal-zones {
	376	+ #include "rk3288-thermal.dtsi"
	377	+ };
	378	+
	379	+ tsadc: tsadc@ff280000 {
	380	+ compatible = "rockchip,rk3288-tsadc";
	381	+ reg = <0xff280000 0x100>;
	382	+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	383	+ clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
	384	+ clock-names = "tsadc", "apb_pclk";
	385	+ resets = <&cru SRST_TSADC>;
	386	+ reset-names = "tsadc-apb";
	387	+ pinctrl-names = "otp_out";
	388	+ pinctrl-0 = <&otp_out>;
	389	+ #thermal-sensor-cells = <1>;
	390	+ hw-shut-temp = <125000>;
	391	+ status = "disabled";
	392	+ };
	393	+
	394	+ gmac: ethernet@ff290000 {
	395	+ compatible = "rockchip,rk3288-gmac";
	396	+ reg = <0xff290000 0x10000>;
	397	+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
	398	+ interrupt-names = "macirq";
	399	+ rockchip,grf = <&grf>;
	400	+ clocks = <&cru SCLK_MAC>,
	401	+ <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
	402	+ <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
	403	+ <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
	404	+ clock-names = "stmmaceth",
	405	+ "mac_clk_rx", "mac_clk_tx",
	406	+ "clk_mac_ref", "clk_mac_refout",
	407	+ "aclk_mac", "pclk_mac";
	408	+ };
	409	+
	410	+ usb_host0_ehci: usb@ff500000 {
	411	+ compatible = "generic-ehci";
	412	+ reg = <0xff500000 0x100>;
	413	+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
	414	+ clocks = <&cru HCLK_USBHOST0>;
	415	+ clock-names = "usbhost";
	416	+ phys = <&usbphy1>;
	417	+ phy-names = "usb";
	418	+ status = "disabled";
	419	+ };
	420	+
	421	+ /* NOTE: ohci@ff520000 doesn't actually work on hardware */
	422	+
	423	+ usb_host1: usb@ff540000 {
	424	+ compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
	425	+ "snps,dwc2";
	426	+ reg = <0xff540000 0x40000>;
	427	+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	428	+ clocks = <&cru HCLK_USBHOST1>;
	429	+ clock-names = "otg";
	430	+ phys = <&usbphy2>;
	431	+ phy-names = "usb2-phy";
	432	+ status = "disabled";
	433	+ };
	434	+
	435	+ usb_otg: usb@ff580000 {
	436	+ compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
	437	+ "snps,dwc2";
	438	+ reg = <0xff580000 0x40000>;
	439	+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	440	+ clocks = <&cru HCLK_OTG0>;
	441	+ clock-names = "otg";
	442	+ phys = <&usbphy0>;
	443	+ phy-names = "usb2-phy";
	444	+ status = "disabled";
	445	+ };
	446	+
	447	+ usb_hsic: usb@ff5c0000 {
	448	+ compatible = "generic-ehci";
	449	+ reg = <0xff5c0000 0x100>;
	450	+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
	451	+ clocks = <&cru HCLK_HSIC>;
	452	+ clock-names = "usbhost";
	453	+ status = "disabled";
	454	+ };
	455	+
	456	+ dmc: dmc@ff610000 {
	457	+ compatible = "rockchip,rk3288-dmc", "syscon";
	458	+ rockchip,cru = <&cru>;
	459	+ rockchip,grf = <&grf>;
	460	+ rockchip,pmu = <&pmu>;
	461	+ rockchip,sgrf = <&sgrf>;
	462	+ rockchip,noc = <&noc>;
	463	+ reg = <0xff610000 0x3fc
	464	+ 0xff620000 0x294
	465	+ 0xff630000 0x3fc
	466	+ 0xff640000 0x294>;
	467	+ rockchip,sram = <&ddr_sram>;
	468	+ clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
	469	+ <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
	470	+ <&cru ARMCLK>;
	471	+ clock-names = "pclk_ddrupctl0", "pclk_publ0",
	472	+ "pclk_ddrupctl1", "pclk_publ1",
	473	+ "arm_clk";
	474	+ };
	475	+
	476	+ i2c0: i2c@ff650000 {
	477	+ compatible = "rockchip,rk3288-i2c";
	478	+ reg = <0xff650000 0x1000>;
	479	+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
	480	+ #address-cells = <1>;
	481	+ #size-cells = <0>;
	482	+ clock-names = "i2c";
	483	+ clocks = <&cru PCLK_I2C0>;
	484	+ pinctrl-names = "default";
	485	+ pinctrl-0 = <&i2c0_xfer>;
	486	+ status = "disabled";
	487	+ };
	488	+
	489	+ i2c2: i2c@ff660000 {
	490	+ compatible = "rockchip,rk3288-i2c";
	491	+ reg = <0xff660000 0x1000>;
	492	+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
	493	+ #address-cells = <1>;
	494	+ #size-cells = <0>;
	495	+ clock-names = "i2c";
	496	+ clocks = <&cru PCLK_I2C2>;
	497	+ pinctrl-names = "default";
	498	+ pinctrl-0 = <&i2c2_xfer>;
	499	+ status = "disabled";
	500	+ };
	501	+
	502	+ pwm0: pwm@ff680000 {
	503	+ compatible = "rockchip,rk3288-pwm";
	504	+ reg = <0xff680000 0x10>;
	505	+ #pwm-cells = <3>;
	506	+ pinctrl-names = "default";
	507	+ pinctrl-0 = <&pwm0_pin>;
	508	+ clocks = <&cru PCLK_PWM>;
	509	+ clock-names = "pwm";
	510	+ rockchip,grf = <&grf>;
	511	+ status = "disabled";
	512	+ };
	513	+
	514	+ pwm1: pwm@ff680010 {
	515	+ compatible = "rockchip,rk3288-pwm";
	516	+ reg = <0xff680010 0x10>;
	517	+ #pwm-cells = <3>;
	518	+ pinctrl-names = "default";
	519	+ pinctrl-0 = <&pwm1_pin>;
	520	+ clocks = <&cru PCLK_PWM>;
	521	+ clock-names = "pwm";
	522	+ rockchip,grf = <&grf>;
	523	+ status = "disabled";
	524	+ };
	525	+
	526	+ pwm2: pwm@ff680020 {
	527	+ compatible = "rockchip,rk3288-pwm";
	528	+ reg = <0xff680020 0x10>;
	529	+ #pwm-cells = <3>;
	530	+ pinctrl-names = "default";
	531	+ pinctrl-0 = <&pwm2_pin>;
	532	+ clocks = <&cru PCLK_PWM>;
	533	+ clock-names = "pwm";
	534	+ rockchip,grf = <&grf>;
	535	+ status = "disabled";
	536	+ };
	537	+
	538	+ pwm3: pwm@ff680030 {
	539	+ compatible = "rockchip,rk3288-pwm";
	540	+ reg = <0xff680030 0x10>;
	541	+ #pwm-cells = <2>;
	542	+ pinctrl-names = "default";
	543	+ pinctrl-0 = <&pwm3_pin>;
	544	+ clocks = <&cru PCLK_PWM>;
	545	+ clock-names = "pwm";
	546	+ rockchip,grf = <&grf>;
	547	+ status = "disabled";
	548	+ };
	549	+
	550	+ bus_intmem@ff700000 {
	551	+ compatible = "mmio-sram";
	552	+ reg = <0xff700000 0x18000>;
	553	+ #address-cells = <1>;
	554	+ #size-cells = <1>;
	555	+ ranges = <0 0xff700000 0x18000>;
	556	+ smp-sram@0 {
	557	+ compatible = "rockchip,rk3066-smp-sram";
	558	+ reg = <0x00 0x10>;
	559	+ };
	560	+ ddr_sram: ddr-sram@1000 {
	561	+ compatible = "rockchip,rk3288-ddr-sram";
	562	+ reg = <0x1000 0x4000>;
	563	+ };
	564	+ };
	565	+
	566	+ sram@ff720000 {
	567	+ compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
	568	+ reg = <0xff720000 0x1000>;
	569	+ };
	570	+
	571	+ pmu: power-management@ff730000 {
	572	+ compatible = "rockchip,rk3288-pmu", "syscon";
	573	+ reg = <0xff730000 0x100>;
	574	+ };
	575	+
	576	+ sgrf: syscon@ff740000 {
	577	+ compatible = "rockchip,rk3288-sgrf", "syscon";
	578	+ reg = <0xff740000 0x1000>;
	579	+ };
	580	+
	581	+ cru: clock-controller@ff760000 {
	582	+ compatible = "rockchip,rk3288-cru";
	583	+ reg = <0xff760000 0x1000>;
	584	+ rockchip,grf = <&grf>;
	585	+ #clock-cells = <1>;
	586	+ #reset-cells = <1>;
	587	+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
	588	+ <&cru PLL_GPLL>, <&cru PLL_CPLL>,
	589	+ <&cru PLL_NPLL>, <&cru ACLK_CPU>,
	590	+ <&cru HCLK_CPU>, <&cru PCLK_CPU>,
	591	+ <&cru ACLK_PERI>, <&cru HCLK_PERI>,
	592	+ <&cru PCLK_PERI>;
	593	+ assigned-clock-rates = <0>, <0>,
	594	+ <594000000>, <400000000>,
	595	+ <500000000>, <300000000>,
	596	+ <150000000>, <75000000>,
	597	+ <300000000>, <150000000>,
	598	+ <75000000>;
	599	+ assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>;
	600	+ };
	601	+
	602	+ grf: syscon@ff770000 {
	603	+ compatible = "rockchip,rk3288-grf", "syscon";
	604	+ reg = <0xff770000 0x1000>;
	605	+ };
	606	+
	607	+ wdt: watchdog@ff800000 {
	608	+ compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
	609	+ reg = <0xff800000 0x100>;
	610	+ clocks = <&cru PCLK_WDT>;
	611	+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
	612	+ status = "disabled";
	613	+ };
	614	+
	615	+ i2s: i2s@ff890000 {
	616	+ compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
	617	+ reg = <0xff890000 0x10000>;
	618	+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
	619	+ #address-cells = <1>;
	620	+ #size-cells = <0>;
	621	+ dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
	622	+ dma-names = "tx", "rx";
	623	+ clock-names = "i2s_hclk", "i2s_clk";
	624	+ clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
	625	+ pinctrl-names = "default";
	626	+ pinctrl-0 = <&i2s0_bus>;
	627	+ status = "disabled";
	628	+ };
	629	+
	630	+ vopb: vop@ff930000 {
	631	+ compatible = "rockchip,rk3288-vop";
	632	+ reg = <0xff930000 0x19c>;
	633	+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
	634	+ clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
	635	+ clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
	636	+ resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
	637	+ reset-names = "axi", "ahb", "dclk";
	638	+ iommus = <&vopb_mmu>;
	639	+ power-domains = <&power RK3288_PD_VIO>;
	640	+ status = "disabled";
	641	+ vopb_out: port {
	642	+ #address-cells = <1>;
	643	+ #size-cells = <0>;
	644	+ vopb_out_edp: endpoint@0 {
	645	+ reg = <0>;
	646	+ remote-endpoint = <&edp_in_vopb>;
	647	+ };
	648	+ vopb_out_hdmi: endpoint@1 {
	649	+ reg = <1>;
	650	+ remote-endpoint = <&hdmi_in_vopb>;
	651	+ };
	652	+ };
	653	+ };
	654	+
	655	+ vopb_mmu: iommu@ff930300 {
	656	+ compatible = "rockchip,iommu";
	657	+ reg = <0xff930300 0x100>;
	658	+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
	659	+ interrupt-names = "vopb_mmu";
	660	+ power-domains = <&power RK3288_PD_VIO>;
	661	+ #iommu-cells = <0>;
	662	+ status = "disabled";
	663	+ };
	664	+
	665	+ vopl: vop@ff940000 {
	666	+ compatible = "rockchip,rk3288-vop";
	667	+ reg = <0xff940000 0x19c>;
	668	+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	669	+ clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
	670	+ clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
	671	+ resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
	672	+ reset-names = "axi", "ahb", "dclk";
	673	+ iommus = <&vopl_mmu>;
	674	+ power-domains = <&power RK3288_PD_VIO>;
	675	+ status = "disabled";
	676	+ vopl_out: port {
	677	+ #address-cells = <1>;
	678	+ #size-cells = <0>;
	679	+ vopl_out_edp: endpoint@0 {
	680	+ reg = <0>;
	681	+ remote-endpoint = <&edp_in_vopl>;
	682	+ };
	683	+ vopl_out_hdmi: endpoint@1 {
	684	+ reg = <1>;
	685	+ remote-endpoint = <&hdmi_in_vopl>;
	686	+ };
	687	+
	688	+ };
	689	+ };
	690	+
	691	+ vopl_mmu: iommu@ff940300 {
	692	+ compatible = "rockchip,iommu";
	693	+ reg = <0xff940300 0x100>;
	694	+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	695	+ interrupt-names = "vopl_mmu";
	696	+ power-domains = <&power RK3288_PD_VIO>;
	697	+ #iommu-cells = <0>;
	698	+ status = "disabled";
	699	+ };
	700	+
	701	+ edp: edp@ff970000 {
	702	+ compatible = "rockchip,rk3288-edp";
	703	+ reg = <0xff970000 0x4000>;
	704	+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
	705	+ clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
	706	+ rockchip,grf = <&grf>;
	707	+ clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
	708	+ resets = <&cru 111>;
	709	+ reset-names = "edp";
	710	+ power-domains = <&power RK3288_PD_VIO>;
	711	+ status = "disabled";
	712	+ ports {
	713	+ edp_in: port {
	714	+ #address-cells = <1>;
	715	+ #size-cells = <0>;
	716	+ edp_in_vopb: endpoint@0 {
	717	+ reg = <0>;
	718	+ remote-endpoint = <&vopb_out_edp>;
	719	+ };
	720	+ edp_in_vopl: endpoint@1 {
	721	+ reg = <1>;
	722	+ remote-endpoint = <&vopl_out_edp>;
	723	+ };
	724	+ };
	725	+ };
	726	+ };
	727	+
	728	+ hdmi: hdmi@ff980000 {
	729	+ compatible = "rockchip,rk3288-dw-hdmi";
	730	+ reg = <0xff980000 0x20000>;
	731	+ reg-io-width = <4>;
	732	+ ddc-i2c-bus = <&i2c5>;
	733	+ rockchip,grf = <&grf>;
	734	+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
	735	+ clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
	736	+ clock-names = "iahb", "isfr";
	737	+ status = "disabled";
	738	+ ports {
	739	+ hdmi_in: port {
	740	+ #address-cells = <1>;
	741	+ #size-cells = <0>;
	742	+ hdmi_in_vopb: endpoint@0 {
	743	+ reg = <0>;
	744	+ remote-endpoint = <&vopb_out_hdmi>;
	745	+ };
	746	+ hdmi_in_vopl: endpoint@1 {
	747	+ reg = <1>;
	748	+ remote-endpoint = <&vopl_out_hdmi>;
	749	+ };
	750	+ };
	751	+ };
	752	+ };
	753	+
	754	+ hdmi_audio: hdmi_audio {
	755	+ compatible = "rockchip,rk3288-hdmi-audio";
	756	+ i2s-controller = <&i2s>;
	757	+ status = "disable";
	758	+ };
	759	+
	760	+ vpu: video-codec@ff9a0000 {
	761	+ compatible = "rockchip,rk3288-vpu";
	762	+ reg = <0xff9a0000 0x800>;
	763	+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
	764	+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	765	+ interrupt-names = "vepu", "vdpu";
	766	+ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
	767	+ clock-names = "aclk_vcodec", "hclk_vcodec";
	768	+ power-domains = <&power RK3288_PD_VIDEO>;
	769	+ iommus = <&vpu_mmu>;
	770	+ };
	771	+
	772	+ vpu_mmu: iommu@ff9a0800 {
	773	+ compatible = "rockchip,iommu";
	774	+ reg = <0xff9a0800 0x100>;
	775	+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	776	+ interrupt-names = "vpu_mmu";
	777	+ power-domains = <&power RK3288_PD_VIDEO>;
	778	+ #iommu-cells = <0>;
	779	+ };
	780	+
	781	+ gpu: gpu@ffa30000 {
	782	+ compatible = "arm,malit764",
	783	+ "arm,malit76x",
	784	+ "arm,malit7xx",
	785	+ "arm,mali-midgard";
	786	+ reg = <0xffa30000 0x10000>;
	787	+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
	788	+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
	789	+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	790	+ interrupt-names = "JOB", "MMU", "GPU";
	791	+ clocks = <&cru ACLK_GPU>;
	792	+ clock-names = "aclk_gpu";
	793	+ operating-points = <
	794	+ /* KHz uV */
	795	+ 100000 950000
	796	+ 200000 950000
	797	+ 300000 1000000
	798	+ 400000 1100000
	799	+ /* 500000 1200000 - See crosbug.com/p/33857 */
	800	+ 600000 1250000
	801	+ >;
	802	+ power-domains = <&power RK3288_PD_GPU>;
	803	+ status = "disabled";
	804	+ };
	805	+
	806	+ noc: syscon@ffac0000 {
	807	+ compatible = "rockchip,rk3288-noc", "syscon";
	808	+ reg = <0xffac0000 0x2000>;
	809	+ };
	810	+
	811	+ efuse: efuse@ffb40000 {
	812	+ compatible = "rockchip,rk3288-efuse";
	813	+ reg = <0xffb40000 0x10000>;
	814	+ status = "disabled";
	815	+ };
	816	+
	817	+ gic: interrupt-controller@ffc01000 {
	818	+ compatible = "arm,gic-400";
	819	+ interrupt-controller;
	820	+ #interrupt-cells = <3>;
	821	+ #address-cells = <0>;
	822	+
	823	+ reg = <0xffc01000 0x1000>,
	824	+ <0xffc02000 0x1000>,
	825	+ <0xffc04000 0x2000>,
	826	+ <0xffc06000 0x2000>;
	827	+ interrupts = <GIC_PPI 9 0xf04>;
	828	+ };
	829	+
	830	+ cpuidle: cpuidle {
	831	+ compatible = "rockchip,rk3288-cpuidle";
	832	+ };
	833	+
	834	+ usbphy: phy {
	835	+ compatible = "rockchip,rk3288-usb-phy";
	836	+ rockchip,grf = <&grf>;
	837	+ #address-cells = <1>;
	838	+ #size-cells = <0>;
	839	+ status = "disabled";
	840	+
	841	+ usbphy0: usb-phy0 {
	842	+ #phy-cells = <0>;
	843	+ reg = <0x320>;
	844	+ clocks = <&cru SCLK_OTGPHY0>;
	845	+ clock-names = "phyclk";
	846	+ };
	847	+
	848	+ usbphy1: usb-phy1 {
	849	+ #phy-cells = <0>;
	850	+ reg = <0x334>;
	851	+ clocks = <&cru SCLK_OTGPHY1>;
	852	+ clock-names = "phyclk";
	853	+ };
	854	+
	855	+ usbphy2: usb-phy2 {
	856	+ #phy-cells = <0>;
	857	+ reg = <0x348>;
	858	+ clocks = <&cru SCLK_OTGPHY2>;
	859	+ clock-names = "phyclk";
	860	+ };
	861	+ };
	862	+
	863	+ pinctrl: pinctrl {
	864	+ compatible = "rockchip,rk3288-pinctrl";
	865	+ rockchip,grf = <&grf>;
	866	+ rockchip,pmu = <&pmu>;
	867	+ #address-cells = <1>;
	868	+ #size-cells = <1>;
	869	+ ranges;
	870	+
	871	+ gpio0: gpio0@ff750000 {
	872	+ compatible = "rockchip,gpio-bank";
	873	+ reg = <0xff750000 0x100>;
	874	+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
	875	+ clocks = <&cru PCLK_GPIO0>;
	876	+
	877	+ gpio-controller;
	878	+ #gpio-cells = <2>;
	879	+
	880	+ interrupt-controller;
	881	+ #interrupt-cells = <2>;
	882	+ };
	883	+
	884	+ gpio1: gpio1@ff780000 {
	885	+ compatible = "rockchip,gpio-bank";
	886	+ reg = <0xff780000 0x100>;
	887	+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
	888	+ clocks = <&cru PCLK_GPIO1>;
	889	+
	890	+ gpio-controller;
	891	+ #gpio-cells = <2>;
	892	+
	893	+ interrupt-controller;
	894	+ #interrupt-cells = <2>;
	895	+ };
	896	+
	897	+ gpio2: gpio2@ff790000 {
	898	+ compatible = "rockchip,gpio-bank";
	899	+ reg = <0xff790000 0x100>;
	900	+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
	901	+ clocks = <&cru PCLK_GPIO2>;
	902	+
	903	+ gpio-controller;
	904	+ #gpio-cells = <2>;
	905	+
	906	+ interrupt-controller;
	907	+ #interrupt-cells = <2>;
	908	+ };
	909	+
	910	+ gpio3: gpio3@ff7a0000 {
	911	+ compatible = "rockchip,gpio-bank";
	912	+ reg = <0xff7a0000 0x100>;
	913	+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	914	+ clocks = <&cru PCLK_GPIO3>;
	915	+
	916	+ gpio-controller;
	917	+ #gpio-cells = <2>;
	918	+
	919	+ interrupt-controller;
	920	+ #interrupt-cells = <2>;
	921	+ };
	922	+
	923	+ gpio4: gpio4@ff7b0000 {
	924	+ compatible = "rockchip,gpio-bank";
	925	+ reg = <0xff7b0000 0x100>;
	926	+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
	927	+ clocks = <&cru PCLK_GPIO4>;
	928	+
	929	+ gpio-controller;
	930	+ #gpio-cells = <2>;
	931	+
	932	+ interrupt-controller;
	933	+ #interrupt-cells = <2>;
	934	+ };
	935	+
	936	+ gpio5: gpio5@ff7c0000 {
	937	+ compatible = "rockchip,gpio-bank";
	938	+ reg = <0xff7c0000 0x100>;
	939	+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
	940	+ clocks = <&cru PCLK_GPIO5>;
	941	+
	942	+ gpio-controller;
	943	+ #gpio-cells = <2>;
	944	+
	945	+ interrupt-controller;
	946	+ #interrupt-cells = <2>;
	947	+ };
	948	+
	949	+ gpio6: gpio6@ff7d0000 {
	950	+ compatible = "rockchip,gpio-bank";
	951	+ reg = <0xff7d0000 0x100>;
	952	+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
	953	+ clocks = <&cru PCLK_GPIO6>;
	954	+
	955	+ gpio-controller;
	956	+ #gpio-cells = <2>;
	957	+
	958	+ interrupt-controller;
	959	+ #interrupt-cells = <2>;
	960	+ };
	961	+
	962	+ gpio7: gpio7@ff7e0000 {
	963	+ compatible = "rockchip,gpio-bank";
	964	+ reg = <0xff7e0000 0x100>;
	965	+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
	966	+ clocks = <&cru PCLK_GPIO7>;
	967	+
	968	+ gpio-controller;
	969	+ #gpio-cells = <2>;
	970	+
	971	+ interrupt-controller;
	972	+ #interrupt-cells = <2>;
	973	+ };
	974	+
	975	+ gpio8: gpio8@ff7f0000 {
	976	+ compatible = "rockchip,gpio-bank";
	977	+ reg = <0xff7f0000 0x100>;
	978	+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
	979	+ clocks = <&cru PCLK_GPIO8>;
	980	+
	981	+ gpio-controller;
	982	+ #gpio-cells = <2>;
	983	+
	984	+ interrupt-controller;
	985	+ #interrupt-cells = <2>;
	986	+ };
	987	+
	988	+ pcfg_pull_up: pcfg-pull-up {
	989	+ bias-pull-up;
	990	+ };
	991	+
	992	+ pcfg_pull_down: pcfg-pull-down {
	993	+ bias-pull-down;
	994	+ };
	995	+
	996	+ pcfg_pull_none: pcfg-pull-none {
	997	+ bias-disable;
	998	+ };
	999	+
	1000	+ pcfg_pull_none_12ma: pcfg-pull-none-12ma {
	1001	+ bias-disable;
	1002	+ drive-strength = <12>;
	1003	+ };
	1004	+
	1005	+ sleep {
	1006	+ global_pwroff: global-pwroff {
	1007	+ rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
	1008	+ };
	1009	+
	1010	+ ddrio_pwroff: ddrio-pwroff {
	1011	+ rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
	1012	+ };
	1013	+
	1014	+ ddr0_retention: ddr0-retention {
	1015	+ rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
	1016	+ };
	1017	+
	1018	+ ddr1_retention: ddr1-retention {
	1019	+ rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
	1020	+ };
	1021	+ };
	1022	+
	1023	+ i2c0 {
	1024	+ i2c0_xfer: i2c0-xfer {
	1025	+ rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
	1026	+ <0 16 RK_FUNC_1 &pcfg_pull_none>;
	1027	+ };
	1028	+ };
	1029	+
	1030	+ i2c1 {
	1031	+ i2c1_xfer: i2c1-xfer {
	1032	+ rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
	1033	+ <8 5 RK_FUNC_1 &pcfg_pull_none>;
	1034	+ };
	1035	+ };
	1036	+
	1037	+ i2c2 {
	1038	+ i2c2_xfer: i2c2-xfer {
	1039	+ rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
	1040	+ <6 10 RK_FUNC_1 &pcfg_pull_none>;
	1041	+ };
	1042	+ };
	1043	+
	1044	+ i2c3 {
	1045	+ i2c3_xfer: i2c3-xfer {
	1046	+ rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
	1047	+ <2 17 RK_FUNC_1 &pcfg_pull_none>;
	1048	+ };
	1049	+ };
	1050	+
	1051	+ i2c4 {
	1052	+ i2c4_xfer: i2c4-xfer {
	1053	+ rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
	1054	+ <7 18 RK_FUNC_1 &pcfg_pull_none>;
	1055	+ };
	1056	+ };
	1057	+
	1058	+ i2c5 {
	1059	+ i2c5_xfer: i2c5-xfer {
	1060	+ rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
	1061	+ <7 20 RK_FUNC_1 &pcfg_pull_none>;
	1062	+ };
	1063	+ };
	1064	+
	1065	+ i2s0 {
	1066	+ i2s0_bus: i2s0-bus {
	1067	+ rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
	1068	+ <6 1 RK_FUNC_1 &pcfg_pull_none>,
	1069	+ <6 2 RK_FUNC_1 &pcfg_pull_none>,
	1070	+ <6 3 RK_FUNC_1 &pcfg_pull_none>,
	1071	+ <6 4 RK_FUNC_1 &pcfg_pull_none>,
	1072	+ <6 8 RK_FUNC_1 &pcfg_pull_none>;
	1073	+ };
	1074	+ };
	1075	+
	1076	+ sdmmc {
	1077	+ sdmmc_clk: sdmmc-clk {
	1078	+ rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
	1079	+ };
	1080	+
	1081	+ sdmmc_cmd: sdmmc-cmd {
	1082	+ rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
	1083	+ };
	1084	+
	1085	+ sdmmc_cd: sdmcc-cd {
	1086	+ rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
	1087	+ };
	1088	+
	1089	+ sdmmc_bus1: sdmmc-bus1 {
	1090	+ rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
	1091	+ };
	1092	+
	1093	+ sdmmc_bus4: sdmmc-bus4 {
	1094	+ rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
	1095	+ <6 17 RK_FUNC_1 &pcfg_pull_up>,
	1096	+ <6 18 RK_FUNC_1 &pcfg_pull_up>,
	1097	+ <6 19 RK_FUNC_1 &pcfg_pull_up>;
	1098	+ };
	1099	+ };
	1100	+
	1101	+ sdio0 {
	1102	+ sdio0_bus1: sdio0-bus1 {
	1103	+ rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
	1104	+ };
	1105	+
	1106	+ sdio0_bus4: sdio0-bus4 {
	1107	+ rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
	1108	+ <4 21 RK_FUNC_1 &pcfg_pull_up>,
	1109	+ <4 22 RK_FUNC_1 &pcfg_pull_up>,
	1110	+ <4 23 RK_FUNC_1 &pcfg_pull_up>;
	1111	+ };
	1112	+
	1113	+ sdio0_cmd: sdio0-cmd {
	1114	+ rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
	1115	+ };
	1116	+
	1117	+ sdio0_clk: sdio0-clk {
	1118	+ rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
	1119	+ };
	1120	+
	1121	+ sdio0_cd: sdio0-cd {
	1122	+ rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
	1123	+ };
	1124	+
	1125	+ sdio0_wp: sdio0-wp {
	1126	+ rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
	1127	+ };
	1128	+
	1129	+ sdio0_pwr: sdio0-pwr {
	1130	+ rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
	1131	+ };
	1132	+
	1133	+ sdio0_bkpwr: sdio0-bkpwr {
	1134	+ rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
	1135	+ };
	1136	+
	1137	+ sdio0_int: sdio0-int {
	1138	+ rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
	1139	+ };
	1140	+ };
	1141	+
	1142	+ sdio1 {
	1143	+ sdio1_bus1: sdio1-bus1 {
	1144	+ rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>;
	1145	+ };
	1146	+
	1147	+ sdio1_bus4: sdio1-bus4 {
	1148	+ rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>,
	1149	+ <3 25 RK_FUNC_4 &pcfg_pull_up>,
	1150	+ <3 26 RK_FUNC_4 &pcfg_pull_up>,
	1151	+ <3 27 RK_FUNC_4 &pcfg_pull_up>;
	1152	+ };
	1153	+
	1154	+ sdio1_cd: sdio1-cd {
	1155	+ rockchip,pins = <3 28 RK_FUNC_4 &pcfg_pull_up>;
	1156	+ };
	1157	+
	1158	+ sdio1_wp: sdio1-wp {
	1159	+ rockchip,pins = <3 29 RK_FUNC_4 &pcfg_pull_up>;
	1160	+ };
	1161	+
	1162	+ sdio1_bkpwr: sdio1-bkpwr {
	1163	+ rockchip,pins = <3 30 RK_FUNC_4 &pcfg_pull_up>;
	1164	+ };
	1165	+
	1166	+ sdio1_int: sdio1-int {
	1167	+ rockchip,pins = <3 31 RK_FUNC_4 &pcfg_pull_up>;
	1168	+ };
	1169	+
	1170	+ sdio1_cmd: sdio1-cmd {
	1171	+ rockchip,pins = <4 6 RK_FUNC_4 &pcfg_pull_up>;
	1172	+ };
	1173	+
	1174	+ sdio1_clk: sdio1-clk {
	1175	+ rockchip,pins = <4 7 RK_FUNC_4 &pcfg_pull_none>;
	1176	+ };
	1177	+
	1178	+ sdio1_pwr: sdio1-pwr {
	1179	+ rockchip,pins = <4 9 RK_FUNC_4 &pcfg_pull_up>;
	1180	+ };
	1181	+ };
	1182	+
	1183	+ emmc {
	1184	+ emmc_clk: emmc-clk {
	1185	+ rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
	1186	+ };
	1187	+
	1188	+ emmc_cmd: emmc-cmd {
	1189	+ rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
	1190	+ };
	1191	+
	1192	+ emmc_pwr: emmc-pwr {
	1193	+ rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
	1194	+ };
	1195	+
	1196	+ emmc_bus1: emmc-bus1 {
	1197	+ rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
	1198	+ };
	1199	+
	1200	+ emmc_bus4: emmc-bus4 {
	1201	+ rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
	1202	+ <3 1 RK_FUNC_2 &pcfg_pull_up>,
	1203	+ <3 2 RK_FUNC_2 &pcfg_pull_up>,
	1204	+ <3 3 RK_FUNC_2 &pcfg_pull_up>;
	1205	+ };
	1206	+
	1207	+ emmc_bus8: emmc-bus8 {
	1208	+ rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
	1209	+ <3 1 RK_FUNC_2 &pcfg_pull_up>,
	1210	+ <3 2 RK_FUNC_2 &pcfg_pull_up>,
	1211	+ <3 3 RK_FUNC_2 &pcfg_pull_up>,
	1212	+ <3 4 RK_FUNC_2 &pcfg_pull_up>,
	1213	+ <3 5 RK_FUNC_2 &pcfg_pull_up>,
	1214	+ <3 6 RK_FUNC_2 &pcfg_pull_up>,
	1215	+ <3 7 RK_FUNC_2 &pcfg_pull_up>;
	1216	+ };
	1217	+ };
	1218	+
	1219	+ spi0 {
	1220	+ spi0_clk: spi0-clk {
	1221	+ rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
	1222	+ };
	1223	+ spi0_cs0: spi0-cs0 {
	1224	+ rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
	1225	+ };
	1226	+ spi0_tx: spi0-tx {
	1227	+ rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
	1228	+ };
	1229	+ spi0_rx: spi0-rx {
	1230	+ rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
	1231	+ };
	1232	+ spi0_cs1: spi0-cs1 {
	1233	+ rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
	1234	+ };
	1235	+ };
	1236	+ spi1 {
	1237	+ spi1_clk: spi1-clk {
	1238	+ rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
	1239	+ };
	1240	+ spi1_cs0: spi1-cs0 {
	1241	+ rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
	1242	+ };
	1243	+ spi1_rx: spi1-rx {
	1244	+ rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
	1245	+ };
	1246	+ spi1_tx: spi1-tx {
	1247	+ rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
	1248	+ };
	1249	+ };
	1250	+
	1251	+ spi2 {
	1252	+ spi2_cs1: spi2-cs1 {
	1253	+ rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
	1254	+ };
	1255	+ spi2_clk: spi2-clk {
	1256	+ rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
	1257	+ };
	1258	+ spi2_cs0: spi2-cs0 {
	1259	+ rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
	1260	+ };
	1261	+ spi2_rx: spi2-rx {
	1262	+ rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
	1263	+ };
	1264	+ spi2_tx: spi2-tx {
	1265	+ rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
	1266	+ };
	1267	+ };
	1268	+
	1269	+ uart0 {
	1270	+ uart0_xfer: uart0-xfer {
	1271	+ rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
	1272	+ <4 17 RK_FUNC_1 &pcfg_pull_none>;
	1273	+ };
	1274	+
	1275	+ uart0_cts: uart0-cts {
	1276	+ rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
	1277	+ };
	1278	+
	1279	+ uart0_rts: uart0-rts {
	1280	+ rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
	1281	+ };
	1282	+ };
	1283	+
	1284	+ uart1 {
	1285	+ uart1_xfer: uart1-xfer {
	1286	+ rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
	1287	+ <5 9 RK_FUNC_1 &pcfg_pull_none>;
	1288	+ };
	1289	+
	1290	+ uart1_cts: uart1-cts {
	1291	+ rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
	1292	+ };
	1293	+
	1294	+ uart1_rts: uart1-rts {
	1295	+ rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
	1296	+ };
	1297	+ };
	1298	+
	1299	+ uart2 {
	1300	+ uart2_xfer: uart2-xfer {
	1301	+ rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
	1302	+ <7 23 RK_FUNC_1 &pcfg_pull_none>;
	1303	+ };
	1304	+ /* no rts / cts for uart2 */
	1305	+ };
	1306	+
	1307	+ uart3 {
	1308	+ uart3_xfer: uart3-xfer {
	1309	+ rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
	1310	+ <7 8 RK_FUNC_1 &pcfg_pull_none>;
	1311	+ };
	1312	+
	1313	+ uart3_cts: uart3-cts {
	1314	+ rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
	1315	+ };
	1316	+
	1317	+ uart3_rts: uart3-rts {
	1318	+ rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
	1319	+ };
	1320	+ };
	1321	+
	1322	+ uart4 {
	1323	+ uart4_xfer: uart4-xfer {
	1324	+ rockchip,pins = <5 12 3 &pcfg_pull_up>,
	1325	+ <5 13 3 &pcfg_pull_none>;
	1326	+ };
	1327	+
	1328	+ uart4_cts: uart4-cts {
	1329	+ rockchip,pins = <5 14 3 &pcfg_pull_none>;
	1330	+ };
	1331	+
	1332	+ uart4_rts: uart4-rts {
	1333	+ rockchip,pins = <5 15 3 &pcfg_pull_none>;
	1334	+ };
	1335	+ };
	1336	+
	1337	+ tsadc {
	1338	+ otp_out: otp-out {
	1339	+ rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
	1340	+ };
	1341	+ };
	1342	+
	1343	+ pwm0 {
	1344	+ pwm0_pin: pwm0-pin {
	1345	+ rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
	1346	+ };
	1347	+ };
	1348	+
	1349	+ pwm1 {
	1350	+ pwm1_pin: pwm1-pin {
	1351	+ rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
	1352	+ };
	1353	+ };
	1354	+
	1355	+ pwm2 {
	1356	+ pwm2_pin: pwm2-pin {
	1357	+ rockchip,pins = <7 22 RK_FUNC_3 &pcfg_pull_none>;
	1358	+ };
	1359	+ };
	1360	+
	1361	+ pwm3 {
	1362	+ pwm3_pin: pwm3-pin {
	1363	+ rockchip,pins = <7 23 RK_FUNC_3 &pcfg_pull_none>;
	1364	+ };
	1365	+ };
	1366	+
	1367	+ gmac {
	1368	+ rgmii_pins: rgmii-pins {
	1369	+ rockchip,pins = <3 30 3 &pcfg_pull_none>,
	1370	+ <3 31 3 &pcfg_pull_none>,
	1371	+ <3 26 3 &pcfg_pull_none>,
	1372	+ <3 27 3 &pcfg_pull_none>,
	1373	+ <3 28 3 &pcfg_pull_none_12ma>,
	1374	+ <3 29 3 &pcfg_pull_none_12ma>,
	1375	+ <3 24 3 &pcfg_pull_none_12ma>,
	1376	+ <3 25 3 &pcfg_pull_none_12ma>,
	1377	+ <4 0 3 &pcfg_pull_none>,
	1378	+ <4 5 3 &pcfg_pull_none>,
	1379	+ <4 6 3 &pcfg_pull_none>,
	1380	+ <4 9 3 &pcfg_pull_none_12ma>,
	1381	+ <4 4 3 &pcfg_pull_none_12ma>,
	1382	+ <4 1 3 &pcfg_pull_none>,
	1383	+ <4 3 3 &pcfg_pull_none>;
	1384	+ };
	1385	+
	1386	+ rmii_pins: rmii-pins {
	1387	+ rockchip,pins = <3 30 3 &pcfg_pull_none>,
	1388	+ <3 31 3 &pcfg_pull_none>,
	1389	+ <3 28 3 &pcfg_pull_none>,
	1390	+ <3 29 3 &pcfg_pull_none>,
	1391	+ <4 0 3 &pcfg_pull_none>,
	1392	+ <4 5 3 &pcfg_pull_none>,
	1393	+ <4 4 3 &pcfg_pull_none>,
	1394	+ <4 1 3 &pcfg_pull_none>,
	1395	+ <4 2 3 &pcfg_pull_none>,
	1396	+ <4 3 3 &pcfg_pull_none>;
	1397	+ };
	1398	+ };
	1399	+ };
	1400	+
	1401	+ power: power-controller {
	1402	+ compatible = "rockchip,rk3288-power-controller";
	1403	+ #power-domain-cells = <1>;
	1404	+ rockchip,pmu = <&pmu>;
	1405	+ #address-cells = <1>;
	1406	+ #size-cells = <0>;
	1407	+
	1408	+ pd_gpu {
	1409	+ reg = <RK3288_PD_GPU>;
	1410	+ clocks = <&cru ACLK_GPU>;
	1411	+ };
	1412	+
	1413	+ pd_hevc {
	1414	+ reg = <RK3288_PD_HEVC>;
	1415	+ clocks = <&cru ACLK_HEVC>,
	1416	+ <&cru SCLK_HEVC_CABAC>,
	1417	+ <&cru SCLK_HEVC_CORE>,
	1418	+ <&cru HCLK_HEVC>;
	1419	+ };
	1420	+
	1421	+ pd_vio {
	1422	+ reg = <RK3288_PD_VIO>;
	1423	+ clocks = <&cru ACLK_IEP>,
	1424	+ <&cru ACLK_ISP>,
	1425	+ <&cru ACLK_RGA>,
	1426	+ <&cru ACLK_VIP>,
	1427	+ <&cru ACLK_VOP0>,
	1428	+ <&cru ACLK_VOP1>,
	1429	+ <&cru DCLK_VOP0>,
	1430	+ <&cru DCLK_VOP1>,
	1431	+ <&cru HCLK_IEP>,
	1432	+ <&cru HCLK_ISP>,
	1433	+ <&cru HCLK_RGA>,
	1434	+ <&cru HCLK_VIP>,
	1435	+ <&cru HCLK_VOP0>,
	1436	+ <&cru HCLK_VOP1>,
	1437	+ <&cru PCLK_EDP_CTRL>,
	1438	+ <&cru PCLK_HDMI_CTRL>,
	1439	+ <&cru PCLK_LVDS_PHY>,
	1440	+ <&cru PCLK_MIPI_CSI>,
	1441	+ <&cru PCLK_MIPI_DSI0>,
	1442	+ <&cru PCLK_MIPI_DSI1>,
	1443	+ <&cru SCLK_EDP_24M>,
	1444	+ <&cru SCLK_EDP>,
	1445	+ <&cru SCLK_HDMI_CEC>,
	1446	+ <&cru SCLK_HDMI_HDCP>,
	1447	+ <&cru SCLK_ISP_JPE>,
	1448	+ <&cru SCLK_ISP>,
	1449	+ <&cru SCLK_RGA>;
	1450	+ };
	1451	+
	1452	+ pd_video {
	1453	+ reg = <RK3288_PD_VIDEO>;
	1454	+ clocks = <&cru ACLK_VCODEC>,
	1455	+ <&cru HCLK_VCODEC>;
	1456	+ };
	1457	+ };
	1458	+};

doc/device-tree-bindings/clock/rockchip,rk3188-cru.txt

Diff comments View file @ 344c837

	1	+* Rockchip RK3188/RK3066 Clock and Reset Unit
	2	+
	3	+The RK3188/RK3066 clock controller generates and supplies clock to various
	4	+controllers within the SoC and also implements a reset controller for SoC
	5	+peripherals.
	6	+
	7	+Required Properties:
	8	+
	9	+- compatible: should be "rockchip,rk3188-cru", "rockchip,rk3188a-cru" or
	10	+ "rockchip,rk3066a-cru"
	11	+- reg: physical base address of the controller and length of memory mapped
	12	+ region.
	13	+- #clock-cells: should be 1.
	14	+- #reset-cells: should be 1.
	15	+
	16	+Optional Properties:
	17	+
	18	+- rockchip,grf: phandle to the syscon managing the "general register files"
	19	+ If missing pll rates are not changable, due to the missing pll lock status.
	20	+
	21	+Each clock is assigned an identifier and client nodes can use this identifier
	22	+to specify the clock which they consume. All available clocks are defined as
	23	+preprocessor macros in the dt-bindings/clock/rk3188-cru.h and
	24	+dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources.
	25	+Similar macros exist for the reset sources in these files.
	26	+
	27	+External clocks:
	28	+
	29	+There are several clocks that are generated outside the SoC. It is expected
	30	+that they are defined using standard clock bindings with following
	31	+clock-output-names:
	32	+ - "xin24m" - crystal input - required,
	33	+ - "xin32k" - rtc clock - optional,
	34	+ - "xin27m" - 27mhz crystal input on rk3066 - optional,
	35	+ - "ext_hsadc" - external HSADC clock - optional,
	36	+ - "ext_cif0" - external camera clock - optional,
	37	+ - "ext_rmii" - external RMII clock - optional,
	38	+ - "ext_jtag" - externalJTAG clock - optional
	39	+
	40	+Example: Clock controller node:
	41	+
	42	+ cru: cru@20000000 {
	43	+ compatible = "rockchip,rk3188-cru";
	44	+ reg = <0x20000000 0x1000>;
	45	+ rockchip,grf = <&grf>;
	46	+
	47	+ #clock-cells = <1>;
	48	+ #reset-cells = <1>;
	49	+ };
	50	+
	51	+Example: UART controller node that consumes the clock generated by the clock
	52	+ controller:
	53	+
	54	+ uart0: serial@10124000 {
	55	+ compatible = "snps,dw-apb-uart";
	56	+ reg = <0x10124000 0x400>;
	57	+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
	58	+ reg-shift = <2>;
	59	+ reg-io-width = <1>;
	60	+ clocks = <&cru SCLK_UART0>;
	61	+ };

doc/device-tree-bindings/clock/rockchip,rk3288-cru.txt

Diff comments View file @ 344c837

	1	+* Rockchip RK3288 Clock and Reset Unit
	2	+
	3	+The RK3288 clock controller generates and supplies clock to various
	4	+controllers within the SoC and also implements a reset controller for SoC
	5	+peripherals.
	6	+
	7	+Required Properties:
	8	+
	9	+- compatible: should be "rockchip,rk3288-cru"
	10	+- reg: physical base address of the controller and length of memory mapped
	11	+ region.
	12	+- #clock-cells: should be 1.
	13	+- #reset-cells: should be 1.
	14	+
	15	+Optional Properties:
	16	+
	17	+- rockchip,grf: phandle to the syscon managing the "general register files"
	18	+ If missing pll rates are not changable, due to the missing pll lock status.
	19	+
	20	+Each clock is assigned an identifier and client nodes can use this identifier
	21	+to specify the clock which they consume. All available clocks are defined as
	22	+preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be
	23	+used in device tree sources. Similar macros exist for the reset sources in
	24	+these files.
	25	+
	26	+External clocks:
	27	+
	28	+There are several clocks that are generated outside the SoC. It is expected
	29	+that they are defined using standard clock bindings with following
	30	+clock-output-names:
	31	+ - "xin24m" - crystal input - required,
	32	+ - "xin32k" - rtc clock - optional,
	33	+ - "ext_i2s" - external I2S clock - optional,
	34	+ - "ext_hsadc" - external HSADC clock - optional,
	35	+ - "ext_edp_24m" - external display port clock - optional,
	36	+ - "ext_vip" - external VIP clock - optional,
	37	+ - "ext_isp" - external ISP clock - optional,
	38	+ - "ext_jtag" - external JTAG clock - optional
	39	+
	40	+Example: Clock controller node:
	41	+
	42	+ cru: cru@20000000 {
	43	+ compatible = "rockchip,rk3188-cru";
	44	+ reg = <0x20000000 0x1000>;
	45	+ rockchip,grf = <&grf>;
	46	+
	47	+ #clock-cells = <1>;
	48	+ #reset-cells = <1>;
	49	+ };
	50	+
	51	+Example: UART controller node that consumes the clock generated by the clock
	52	+ controller:
	53	+
	54	+ uart0: serial@10124000 {
	55	+ compatible = "snps,dw-apb-uart";
	56	+ reg = <0x10124000 0x400>;
	57	+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
	58	+ reg-shift = <2>;
	59	+ reg-io-width = <1>;
	60	+ clocks = <&cru SCLK_UART0>;
	61	+ };

doc/device-tree-bindings/clock/rockchip,rk3288-dmc.txt

Diff comments View file @ 344c837

	1	+Rockchip Dynamic Memory Controller Driver
	2	+Required properties:
	3	+- compatible: "rockchip,rk3288-dmc", "syscon"
	4	+- rockchip,cru: this driver should access cru regs, so need get cru here
	5	+- rockchip,grf: this driver should access grf regs, so need get grf here
	6	+- rockchip,pmu: this driver should access pmu regs, so need get pmu here
	7	+- rockchip,sgrf: this driver should access sgrf regs, so need get sgrf here
	8	+- rockchip,noc: this driver should access noc regs, so need get noc here
	9	+- reg: dynamic ram protocol controller(PCTL) address and phy controller(PHYCTL) address
	10	+- clock: must include clock specifiers corresponding to entries in the clock-names property.
	11	+- clock-output-names: from common clock binding to override the default output clock name
	12	+ Must contain
	13	+ pclk_ddrupctl0: support clock for access protocol controller registers of channel 0
	14	+ pclk_publ0: support clock for access phy controller registers of channel 0
	15	+ pclk_ddrupctl1: support clock for access protocol controller registers of channel 1
	16	+ pclk_publ1: support clock for access phy controller registers of channel 1
	17	+ arm_clk: for get arm frequency
	18	+-logic-supply: this driver should adjust VDD_LOGIC according to dmc frequency, so need get logic-supply here
	19	+-timings:
	20	+ Must contain
	21	+ rockchip,odt-disable-freq: if ddr clock frequency low than odt-disable-freq,this driver should disable DDR ODT
	22	+ rockchip,dll-disable-freq: if ddr clock frequency low than dll-disable-freq,this driver should disable DDR DLL
	23	+ rockchip,sr-enable-freq: if ddr clock frequency high than sr-enable-freq,this driver should enable the automatic self refresh function
	24	+ rockchip,pd-enable-freq: if ddr clock frequency high than pd-enable-freq,this driver should enable the automatic power down function
	25	+ rockchip,auto-self-refresh-cnt: Self Refresh idle period. Memories are placed into Self-Refresh mode if the NIF is idle in Access state for auto-self-refresh-cnt * 32 * n_clk cycles.The automatic self refresh function is disabled when auto-self-refresh-cnt=0.
	26	+ rockchip,auto-power-down-cnt: Power-down idle period. Memories are placed into power-down mode if the NIF is idle for auto-power-down-cnt n_clk cycles.The automatic power down function is disabled when auto-power-down-cnt=0.
	27	+ rockchip,ddr-speed-bin: DDR3 type,AC timing parameters from the memory data-sheet
	28	+ 0.DDR3_800D (5-5-5)
	29	+ 1.DDR3_800E (6-6-6)
	30	+ 2.DDR3_1066E (6-6-6)
	31	+ 3.DDR3_1066F (7-7-7)
	32	+ 4.DDR3_1066G (8-8-8)
	33	+ 5.DDR3_1333F (7-7-7)
	34	+ 6.DDR3_1333G (8-8-8)
	35	+ 7.DDR3_1333H (9-9-9)
	36	+ 8.DDR3_1333J (10-10-10)
	37	+ 9.DDR3_1600G (8-8-8)
	38	+ 10.DDR3_1600H (9-9-9)
	39	+ 11.DDR3_1600J (10-10-10)
	40	+ 12.DDR3_1600K (11-11-11)
	41	+ 13.DDR3_1866J (10-10-10)
	42	+ 14.DDR3_1866K (11-11-11)
	43	+ 15.DDR3_1866L (12-12-12)
	44	+ 16.DDR3_1866M (13-13-13)
	45	+ 17.DDR3_2133K (11-11-11)
	46	+ 18.DDR3_2133L (12-12-12)
	47	+ 19.DDR3_2133M (13-13-13)
	48	+ 20.DDR3_2133N (14-14-14)
	49	+ 21.DDR3_DEFAULT
	50	+ rockchip,trcd: tRCD,AC timing parameters from the memory data-sheet
	51	+ rockchip,trp: tRP,AC timing parameters from the memory data-sheet
	52	+-rockchip,num-channels: number of SDRAM channels (1 or 2)
	53	+-rockchip,pctl-timing: parameters for the SDRAM setup, in this order:
	54	+ togcnt1u
	55	+ tinit
	56	+ trsth
	57	+ togcnt100n
	58	+ trefi
	59	+ tmrd
	60	+ trfc
	61	+ trp
	62	+ trtw
	63	+ tal
	64	+ tcl
	65	+ tcwl
	66	+ tras
	67	+ trc
	68	+ trcd
	69	+ trrd
	70	+ trtp
	71	+ twr
	72	+ twtr
	73	+ texsr
	74	+ txp
	75	+ txpdll
	76	+ tzqcs
	77	+ tzqcsi
	78	+ tdqs
	79	+ tcksre
	80	+ tcksrx
	81	+ tcke
	82	+ tmod
	83	+ trstl
	84	+ tzqcl
	85	+ tmrr
	86	+ tckesr
	87	+ tdpd
	88	+-rockchip,phy-timing: PHY timing information in this order:
	89	+ dtpr0
	90	+ dtpr1
	91	+ dtpr2
	92	+ mr0..mr3
	93	+-rockchip,sdram-channel: SDRAM channel information, each 8 bits. Both channels
	94	+will be set up the same. The parameters are in this order:
	95	+ rank
	96	+ col
	97	+ bk
	98	+ bw
	99	+ dbw
	100	+ row_3_4
	101	+ cs0_row
	102	+ cs1_row
	103	+- rockchip,sdram-params: SDRAM base parameters, in this order:
	104	+ NOC timing - value for ddrtiming register
	105	+ NOC activate - value for activate register
	106	+ ddrconf - value for ddrconf register
	107	+ DDR frequency in MHz
	108	+ DRAM type (3=DDR3, 6=LPDDR3)
	109	+ stride - stride value for soc_con2 register
	110	+ odt - 1 to enable DDR ODT, 0 to disable
	111	+
	112	+Example:
	113	+ dmc: dmc@ff610000 {
	114	+ compatible = "rockchip,rk3288-dmc", "syscon";
	115	+ rockchip,cru = <&cru>;
	116	+ rockchip,grf = <&grf>;
	117	+ rockchip,pmu = <&pmu>;
	118	+ rockchip,sgrf = <&sgrf>;
	119	+ rockchip,noc = <&noc>;
	120	+ reg = <0xff610000 0x3fc
	121	+ 0xff620000 0x294
	122	+ 0xff630000 0x3fc
	123	+ 0xff640000 0x294>;
	124	+ clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
	125	+ <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
	126	+ <&cru ARMCLK>;
	127	+ clock-names = "pclk_ddrupctl0", "pclk_publ0",
	128	+ "pclk_ddrupctl1", "pclk_publ1",
	129	+ "arm_clk";
	130	+ };
	131	+
	132	+ &dmc {
	133	+ logic-supply = <&vdd_logic>;
	134	+ timings {
	135	+ rockchip,odt-disable-freq = <333000000>;
	136	+ rockchip,dll-disable-freq = <333000000>;
	137	+ rockchip,sr-enable-freq = <333000000>;
	138	+ rockchip,pd-enable-freq = <666000000>;
	139	+ rockchip,auto-self-refresh-cnt = <0>;
	140	+ rockchip,auto-power-down-cnt = <64>;
	141	+ rockchip,ddr-speed-bin = <21>;
	142	+ rockchip,trcd = <10>;
	143	+ rockchip,trp = <10>;
	144	+ };
	145	+ rockchip,num-channels = <2>;
	146	+ rockchip,pctl-timing = <0x29a 0x1f4 0xc8 0x42 0x4e 0x4 0xea 0xa
	147	+ 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
	148	+ 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
	149	+ 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
	150	+ 0x5 0x0>;
	151	+ rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
	152	+ 0xa60 0x40 0x10 0x0>;
	153	+ rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf>;
	154	+ rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
	155	+ };

doc/device-tree-bindings/clock/rockchip.txt

Diff comments View file @ 344c837

	1	+Device Tree Clock bindings for arch-rockchip
	2	+
	3	+This binding uses the common clock binding[1].
	4	+
	5	+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
	6	+
	7	+== Gate clocks ==
	8	+
	9	+These bindings are deprecated!
	10	+Please use the soc specific CRU bindings instead.
	11	+
	12	+The gate registers form a continuos block which makes the dt node
	13	+structure a matter of taste, as either all gates can be put into
	14	+one gate clock spanning all registers or they can be divided into
	15	+the 10 individual gates containing 16 clocks each.
	16	+The code supports both approaches.
	17	+
	18	+Required properties:
	19	+- compatible : "rockchip,rk2928-gate-clk"
	20	+- reg : shall be the control register address(es) for the clock.
	21	+- #clock-cells : from common clock binding; shall be set to 1
	22	+- clock-output-names : the corresponding gate names that the clock controls
	23	+- clocks : should contain the parent clock for each individual gate,
	24	+ therefore the number of clocks elements should match the number of
	25	+ clock-output-names
	26	+
	27	+Example using multiple gate clocks:
	28	+
	29	+ clk_gates0: gate-clk@200000d0 {
	30	+ compatible = "rockchip,rk2928-gate-clk";
	31	+ reg = <0x200000d0 0x4>;
	32	+ clocks = <&dummy>, <&dummy>,
	33	+ <&dummy>, <&dummy>,
	34	+ <&dummy>, <&dummy>,
	35	+ <&dummy>, <&dummy>,
	36	+ <&dummy>, <&dummy>,
	37	+ <&dummy>, <&dummy>,
	38	+ <&dummy>, <&dummy>,
	39	+ <&dummy>, <&dummy>;
	40	+
	41	+ clock-output-names =
	42	+ "gate_core_periph", "gate_cpu_gpll",
	43	+ "gate_ddrphy", "gate_aclk_cpu",
	44	+ "gate_hclk_cpu", "gate_pclk_cpu",
	45	+ "gate_atclk_cpu", "gate_i2s0",
	46	+ "gate_i2s0_frac", "gate_i2s1",
	47	+ "gate_i2s1_frac", "gate_i2s2",
	48	+ "gate_i2s2_frac", "gate_spdif",
	49	+ "gate_spdif_frac", "gate_testclk";
	50	+
	51	+ #clock-cells = <1>;
	52	+ };
	53	+
	54	+ clk_gates1: gate-clk@200000d4 {
	55	+ compatible = "rockchip,rk2928-gate-clk";
	56	+ reg = <0x200000d4 0x4>;
	57	+ clocks = <&xin24m>, <&xin24m>,
	58	+ <&xin24m>, <&dummy>,
	59	+ <&dummy>, <&xin24m>,
	60	+ <&xin24m>, <&dummy>,
	61	+ <&xin24m>, <&dummy>,
	62	+ <&xin24m>, <&dummy>,
	63	+ <&xin24m>, <&dummy>,
	64	+ <&xin24m>, <&dummy>;
	65	+
	66	+ clock-output-names =
	67	+ "gate_timer0", "gate_timer1",
	68	+ "gate_timer2", "gate_jtag",
	69	+ "gate_aclk_lcdc1_src", "gate_otgphy0",
	70	+ "gate_otgphy1", "gate_ddr_gpll",
	71	+ "gate_uart0", "gate_frac_uart0",
	72	+ "gate_uart1", "gate_frac_uart1",
	73	+ "gate_uart2", "gate_frac_uart2",
	74	+ "gate_uart3", "gate_frac_uart3";
	75	+
	76	+ #clock-cells = <1>;
	77	+ };

doc/device-tree-bindings/pinctrl/rockchip,pinctrl.txt

Diff comments View file @ 344c837

	1	+* Rockchip Pinmux Controller
	2	+
	3	+The Rockchip Pinmux Controller, enables the IC
	4	+to share one PAD to several functional blocks. The sharing is done by
	5	+multiplexing the PAD input/output signals. For each PAD there are several
	6	+muxing options with option 0 being the use as a GPIO.
	7	+
	8	+Please refer to pinctrl-bindings.txt in this directory for details of the
	9	+common pinctrl bindings used by client devices, including the meaning of the
	10	+phrase "pin configuration node".
	11	+
	12	+The Rockchip pin configuration node is a node of a group of pins which can be
	13	+used for a specific device or function. This node represents both mux and
	14	+config of the pins in that group. The 'pins' selects the function mode(also
	15	+named pin mode) this pin can work on and the 'config' configures various pad
	16	+settings such as pull-up, etc.
	17	+
	18	+The pins are grouped into up to 5 individual pin banks which need to be
	19	+defined as gpio sub-nodes of the pinmux controller.
	20	+
	21	+Required properties for iomux controller:
	22	+ - compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl"
	23	+ "rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl"
	24	+ "rockchip,rk3288-pinctrl"
	25	+ - rockchip,grf: phandle referencing a syscon providing the
	26	+ "general register files"
	27	+
	28	+Optional properties for iomux controller:
	29	+ - rockchip,pmu: phandle referencing a syscon providing the pmu registers
	30	+ as some SoCs carry parts of the iomux controller registers there.
	31	+ Required for at least rk3188 and rk3288.
	32	+
	33	+Deprecated properties for iomux controller:
	34	+ - reg: first element is the general register space of the iomux controller
	35	+ It should be large enough to contain also separate pull registers.
	36	+ second element is the separate pull register space of the rk3188.
	37	+ Use rockchip,grf and rockchip,pmu described above instead.
	38	+
	39	+Required properties for gpio sub nodes:
	40	+ - compatible: "rockchip,gpio-bank"
	41	+ - reg: register of the gpio bank (different than the iomux registerset)
	42	+ - interrupts: base interrupt of the gpio bank in the interrupt controller
	43	+ - clocks: clock that drives this bank
	44	+ - gpio-controller: identifies the node as a gpio controller and pin bank.
	45	+ - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
	46	+ binding is used, the amount of cells must be specified as 2. See generic
	47	+ GPIO binding documentation for description of particular cells.
	48	+ - interrupt-controller: identifies the controller node as interrupt-parent.
	49	+ - #interrupt-cells: the value of this property should be 2 and the interrupt
	50	+ cells should use the standard two-cell scheme described in
	51	+ bindings/interrupt-controller/interrupts.txt
	52	+
	53	+Deprecated properties for gpio sub nodes:
	54	+ - compatible: "rockchip,rk3188-gpio-bank0"
	55	+ - reg: second element: separate pull register for rk3188 bank0, use
	56	+ rockchip,pmu described above instead
	57	+
	58	+Required properties for pin configuration node:
	59	+ - rockchip,pins: 3 integers array, represents a group of pins mux and config
	60	+ setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX &phandle>.
	61	+ The MUX 0 means gpio and MUX 1 to N mean the specific device function.
	62	+ The phandle of a node containing the generic pinconfig options
	63	+ to use, as described in pinctrl-bindings.txt in this directory.
	64	+
	65	+Examples:
	66	+
	67	+#include <dt-bindings/pinctrl/rockchip.h>
	68	+
	69	+...
	70	+
	71	+pinctrl@20008000 {
	72	+ compatible = "rockchip,rk3066a-pinctrl";
	73	+ rockchip,grf = <&grf>;
	74	+
	75	+ #address-cells = <1>;
	76	+ #size-cells = <1>;
	77	+ ranges;
	78	+
	79	+ gpio0: gpio0@20034000 {
	80	+ compatible = "rockchip,gpio-bank";
	81	+ reg = <0x20034000 0x100>;
	82	+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
	83	+ clocks = <&clk_gates8 9>;
	84	+
	85	+ gpio-controller;
	86	+ #gpio-cells = <2>;
	87	+
	88	+ interrupt-controller;
	89	+ #interrupt-cells = <2>;
	90	+ };
	91	+
	92	+ ...
	93	+
	94	+ pcfg_pull_default: pcfg_pull_default {
	95	+ bias-pull-pin-default
	96	+ };
	97	+
	98	+ uart2 {
	99	+ uart2_xfer: uart2-xfer {
	100	+ rockchip,pins = <RK_GPIO1 8 1 &pcfg_pull_default>,
	101	+ <RK_GPIO1 9 1 &pcfg_pull_default>;
	102	+ };
	103	+ };
	104	+};
	105	+
	106	+uart2: serial@20064000 {
	107	+ compatible = "snps,dw-apb-uart";
	108	+ reg = <0x20064000 0x400>;
	109	+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	110	+ reg-shift = <2>;
	111	+ reg-io-width = <1>;
	112	+ clocks = <&mux_uart2>;
	113	+ status = "okay";
	114	+
	115	+ pinctrl-names = "default";
	116	+ pinctrl-0 = <&uart2_xfer>;
	117	+};
	118	+
	119	+Example for rk3188:
	120	+
	121	+ pinctrl@20008000 {
	122	+ compatible = "rockchip,rk3188-pinctrl";
	123	+ rockchip,grf = <&grf>;
	124	+ rockchip,pmu = <&pmu>;
	125	+ #address-cells = <1>;
	126	+ #size-cells = <1>;
	127	+ ranges;
	128	+
	129	+ gpio0: gpio0@0x2000a000 {
	130	+ compatible = "rockchip,rk3188-gpio-bank0";
	131	+ reg = <0x2000a000 0x100>;
	132	+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
	133	+ clocks = <&clk_gates8 9>;
	134	+
	135	+ gpio-controller;
	136	+ #gpio-cells = <2>;
	137	+
	138	+ interrupt-controller;
	139	+ #interrupt-cells = <2>;
	140	+ };
	141	+
	142	+ gpio1: gpio1@0x2003c000 {
	143	+ compatible = "rockchip,gpio-bank";
	144	+ reg = <0x2003c000 0x100>;
	145	+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
	146	+ clocks = <&clk_gates8 10>;
	147	+
	148	+ gpio-controller;
	149	+ #gpio-cells = <2>;
	150	+
	151	+ interrupt-controller;
	152	+ #interrupt-cells = <2>;
	153	+ };
	154	+
	155	+ ...
	156	+
	157	+ };

doc/device-tree-bindings/thermal/rockchip-thermal.txt

Diff comments View file @ 344c837

	1	+* Temperature Sensor ADC (TSADC) on rockchip SoCs
	2	+
	3	+Required properties:
	4	+- compatible : "rockchip,rk3288-tsadc"
	5	+- reg : physical base address of the controller and length of memory mapped
	6	+ region.
	7	+- interrupts : The interrupt number to the cpu. The interrupt specifier format
	8	+ depends on the interrupt controller.
	9	+- clocks : Must contain an entry for each entry in clock-names.
	10	+- clock-names : Shall be "tsadc" for the converter-clock, and "apb_pclk" for
	11	+ the peripheral clock.
	12	+- resets : Must contain an entry for each entry in reset-names.
	13	+ See ../reset/reset.txt for details.
	14	+- reset-names : Must include the name "tsadc-apb".
	15	+- #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description.
	16	+- rockchip,hw-tshut-temp : The hardware-controlled shutdown temperature value.
	17	+- rockchip,hw-tshut-mode : The hardware-controlled shutdown mode 0:CRU 1:GPIO.
	18	+- rockchip,hw-tshut-polarity : The hardware-controlled active polarity 0:LOW
	19	+ 1:HIGH.
	20	+
	21	+Exiample:
	22	+tsadc: tsadc@ff280000 {
	23	+ compatible = "rockchip,rk3288-tsadc";
	24	+ reg = <0xff280000 0x100>;
	25	+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	26	+ clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
	27	+ clock-names = "tsadc", "apb_pclk";
	28	+ resets = <&cru SRST_TSADC>;
	29	+ reset-names = "tsadc-apb";
	30	+ pinctrl-names = "default";
	31	+ pinctrl-0 = <&otp_out>;
	32	+ #thermal-sensor-cells = <1>;
	33	+ rockchip,hw-tshut-temp = <95000>;
	34	+ rockchip,hw-tshut-mode = <0>;
	35	+ rockchip,hw-tshut-polarity = <0>;
	36	+};
	37	+
	38	+Example: referring to thermal sensors:
	39	+thermal-zones {
	40	+ cpu_thermal: cpu_thermal {
	41	+ polling-delay-passive = <1000>; /* milliseconds */
	42	+ polling-delay = <5000>; /* milliseconds */
	43	+
	44	+ /* sensor ID */
	45	+ thermal-sensors = <&tsadc 1>;
	46	+
	47	+ trips {
	48	+ cpu_alert0: cpu_alert {
	49	+ temperature = <70000>; /* millicelsius */
	50	+ hysteresis = <2000>; /* millicelsius */
	51	+ type = "passive";
	52	+ };
	53	+ cpu_crit: cpu_crit {
	54	+ temperature = <90000>; /* millicelsius */
	55	+ hysteresis = <2000>; /* millicelsius */
	56	+ type = "critical";
	57	+ };
	58	+ };
	59	+
	60	+ cooling-maps {
	61	+ map0 {
	62	+ trip = <&cpu_alert0>;
	63	+ cooling-device =
	64	+ <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	65	+ };
	66	+ };
	67	+ };
	68	+};

include/dt-bindings/clock/rk3288-cru.h

Diff comments View file @ 344c837

	1	+/*
	2	+ * Copyright (c) 2014 MundoReader S.L.
	3	+ * Author: Heiko Stuebner <heiko@sntech.de>
	4	+ *
	5	+ * SPDX-License-Identifier: GPL-2.0+
	6	+ */
	7	+
	8	+/* core clocks */
	9	+#define PLL_APLL 1
	10	+#define PLL_DPLL 2
	11	+#define PLL_CPLL 3
	12	+#define PLL_GPLL 4
	13	+#define PLL_NPLL 5
	14	+#define ARMCLK 6
	15	+
	16	+/* sclk gates (special clocks) */
	17	+#define SCLK_GPU 64
	18	+#define SCLK_SPI0 65
	19	+#define SCLK_SPI1 66
	20	+#define SCLK_SPI2 67
	21	+#define SCLK_SDMMC 68
	22	+#define SCLK_SDIO0 69
	23	+#define SCLK_SDIO1 70
	24	+#define SCLK_EMMC 71
	25	+#define SCLK_TSADC 72
	26	+#define SCLK_SARADC 73
	27	+#define SCLK_PS2C 74
	28	+#define SCLK_NANDC0 75
	29	+#define SCLK_NANDC1 76
	30	+#define SCLK_UART0 77
	31	+#define SCLK_UART1 78
	32	+#define SCLK_UART2 79
	33	+#define SCLK_UART3 80
	34	+#define SCLK_UART4 81
	35	+#define SCLK_I2S0 82
	36	+#define SCLK_SPDIF 83
	37	+#define SCLK_SPDIF8CH 84
	38	+#define SCLK_TIMER0 85
	39	+#define SCLK_TIMER1 86
	40	+#define SCLK_TIMER2 87
	41	+#define SCLK_TIMER3 88
	42	+#define SCLK_TIMER4 89
	43	+#define SCLK_TIMER5 90
	44	+#define SCLK_TIMER6 91
	45	+#define SCLK_HSADC 92
	46	+#define SCLK_OTGPHY0 93
	47	+#define SCLK_OTGPHY1 94
	48	+#define SCLK_OTGPHY2 95
	49	+#define SCLK_OTG_ADP 96
	50	+#define SCLK_HSICPHY480M 97
	51	+#define SCLK_HSICPHY12M 98
	52	+#define SCLK_MACREF 99
	53	+#define SCLK_LCDC_PWM0 100
	54	+#define SCLK_LCDC_PWM1 101
	55	+#define SCLK_MAC_RX 102
	56	+#define SCLK_MAC_TX 103
	57	+#define SCLK_EDP_24M 104
	58	+#define SCLK_EDP 105
	59	+#define SCLK_RGA 106
	60	+#define SCLK_ISP 107
	61	+#define SCLK_ISP_JPE 108
	62	+#define SCLK_HDMI_HDCP 109
	63	+#define SCLK_HDMI_CEC 110
	64	+#define SCLK_HEVC_CABAC 111
	65	+#define SCLK_HEVC_CORE 112
	66	+#define SCLK_I2S0_OUT 113
	67	+#define SCLK_SDMMC_DRV 114
	68	+#define SCLK_SDIO0_DRV 115
	69	+#define SCLK_SDIO1_DRV 116
	70	+#define SCLK_EMMC_DRV 117
	71	+#define SCLK_SDMMC_SAMPLE 118
	72	+#define SCLK_SDIO0_SAMPLE 119
	73	+#define SCLK_SDIO1_SAMPLE 120
	74	+#define SCLK_EMMC_SAMPLE 121
	75	+#define SCLK_USBPHY480M_SRC 122
	76	+#define SCLK_PVTM_CORE 123
	77	+#define SCLK_PVTM_GPU 124
	78	+
	79	+#define SCLK_MAC 151
	80	+#define SCLK_MACREF_OUT 152
	81	+
	82	+#define DCLK_VOP0 190
	83	+#define DCLK_VOP1 191
	84	+
	85	+/* aclk gates */
	86	+#define ACLK_GPU 192
	87	+#define ACLK_DMAC1 193
	88	+#define ACLK_DMAC2 194
	89	+#define ACLK_MMU 195
	90	+#define ACLK_GMAC 196
	91	+#define ACLK_VOP0 197
	92	+#define ACLK_VOP1 198
	93	+#define ACLK_CRYPTO 199
	94	+#define ACLK_RGA 200
	95	+#define ACLK_RGA_NIU 201
	96	+#define ACLK_IEP 202
	97	+#define ACLK_VIO0_NIU 203
	98	+#define ACLK_VIP 204
	99	+#define ACLK_ISP 205
	100	+#define ACLK_VIO1_NIU 206
	101	+#define ACLK_HEVC 207
	102	+#define ACLK_VCODEC 208
	103	+#define ACLK_CPU 209
	104	+#define ACLK_PERI 210
	105	+
	106	+/* pclk gates */
	107	+#define PCLK_GPIO0 320
	108	+#define PCLK_GPIO1 321
	109	+#define PCLK_GPIO2 322
	110	+#define PCLK_GPIO3 323
	111	+#define PCLK_GPIO4 324
	112	+#define PCLK_GPIO5 325
	113	+#define PCLK_GPIO6 326
	114	+#define PCLK_GPIO7 327
	115	+#define PCLK_GPIO8 328
	116	+#define PCLK_GRF 329
	117	+#define PCLK_SGRF 330
	118	+#define PCLK_PMU 331
	119	+#define PCLK_I2C0 332
	120	+#define PCLK_I2C1 333
	121	+#define PCLK_I2C2 334
	122	+#define PCLK_I2C3 335
	123	+#define PCLK_I2C4 336
	124	+#define PCLK_I2C5 337
	125	+#define PCLK_SPI0 338
	126	+#define PCLK_SPI1 339
	127	+#define PCLK_SPI2 340
	128	+#define PCLK_UART0 341
	129	+#define PCLK_UART1 342
	130	+#define PCLK_UART2 343
	131	+#define PCLK_UART3 344
	132	+#define PCLK_UART4 345
	133	+#define PCLK_TSADC 346
	134	+#define PCLK_SARADC 347
	135	+#define PCLK_SIM 348
	136	+#define PCLK_GMAC 349
	137	+#define PCLK_PWM 350
	138	+#define PCLK_RKPWM 351
	139	+#define PCLK_PS2C 352
	140	+#define PCLK_TIMER 353
	141	+#define PCLK_TZPC 354
	142	+#define PCLK_EDP_CTRL 355
	143	+#define PCLK_MIPI_DSI0 356
	144	+#define PCLK_MIPI_DSI1 357
	145	+#define PCLK_MIPI_CSI 358
	146	+#define PCLK_LVDS_PHY 359
	147	+#define PCLK_HDMI_CTRL 360
	148	+#define PCLK_VIO2_H2P 361
	149	+#define PCLK_CPU 362
	150	+#define PCLK_PERI 363
	151	+#define PCLK_DDRUPCTL0 364
	152	+#define PCLK_PUBL0 365
	153	+#define PCLK_DDRUPCTL1 366
	154	+#define PCLK_PUBL1 367
	155	+#define PCLK_WDT 368
	156	+
	157	+/* hclk gates */
	158	+#define HCLK_GPS 448
	159	+#define HCLK_OTG0 449
	160	+#define HCLK_USBHOST0 450
	161	+#define HCLK_USBHOST1 451
	162	+#define HCLK_HSIC 452
	163	+#define HCLK_NANDC0 453
	164	+#define HCLK_NANDC1 454
	165	+#define HCLK_TSP 455
	166	+#define HCLK_SDMMC 456
	167	+#define HCLK_SDIO0 457
	168	+#define HCLK_SDIO1 458
	169	+#define HCLK_EMMC 459
	170	+#define HCLK_HSADC 460
	171	+#define HCLK_CRYPTO 461
	172	+#define HCLK_I2S0 462
	173	+#define HCLK_SPDIF 463
	174	+#define HCLK_SPDIF8CH 464
	175	+#define HCLK_VOP0 465
	176	+#define HCLK_VOP1 466
	177	+#define HCLK_ROM 467
	178	+#define HCLK_IEP 468
	179	+#define HCLK_ISP 469
	180	+#define HCLK_RGA 470
	181	+#define HCLK_VIO_AHB_ARBI 471
	182	+#define HCLK_VIO_NIU 472
	183	+#define HCLK_VIP 473
	184	+#define HCLK_VIO2_H2P 474
	185	+#define HCLK_HEVC 475
	186	+#define HCLK_VCODEC 476
	187	+#define HCLK_CPU 477
	188	+#define HCLK_PERI 478
	189	+
	190	+#define CLK_NR_CLKS (HCLK_PERI + 1)
	191	+
	192	+/* soft-reset indices */
	193	+#define SRST_CORE0 0
	194	+#define SRST_CORE1 1
	195	+#define SRST_CORE2 2
	196	+#define SRST_CORE3 3
	197	+#define SRST_CORE0_PO 4
	198	+#define SRST_CORE1_PO 5
	199	+#define SRST_CORE2_PO 6
	200	+#define SRST_CORE3_PO 7
	201	+#define SRST_PDCORE_STRSYS 8
	202	+#define SRST_PDBUS_STRSYS 9
	203	+#define SRST_L2C 10
	204	+#define SRST_TOPDBG 11
	205	+#define SRST_CORE0_DBG 12
	206	+#define SRST_CORE1_DBG 13
	207	+#define SRST_CORE2_DBG 14
	208	+#define SRST_CORE3_DBG 15
	209	+
	210	+#define SRST_PDBUG_AHB_ARBITOR 16
	211	+#define SRST_EFUSE256 17
	212	+#define SRST_DMAC1 18
	213	+#define SRST_INTMEM 19
	214	+#define SRST_ROM 20
	215	+#define SRST_SPDIF8CH 21
	216	+#define SRST_TIMER 22
	217	+#define SRST_I2S0 23
	218	+#define SRST_SPDIF 24
	219	+#define SRST_TIMER0 25
	220	+#define SRST_TIMER1 26
	221	+#define SRST_TIMER2 27
	222	+#define SRST_TIMER3 28
	223	+#define SRST_TIMER4 29
	224	+#define SRST_TIMER5 30
	225	+#define SRST_EFUSE 31
	226	+
	227	+#define SRST_GPIO0 32
	228	+#define SRST_GPIO1 33
	229	+#define SRST_GPIO2 34
	230	+#define SRST_GPIO3 35
	231	+#define SRST_GPIO4 36
	232	+#define SRST_GPIO5 37
	233	+#define SRST_GPIO6 38
	234	+#define SRST_GPIO7 39
	235	+#define SRST_GPIO8 40
	236	+#define SRST_I2C0 42
	237	+#define SRST_I2C1 43
	238	+#define SRST_I2C2 44
	239	+#define SRST_I2C3 45
	240	+#define SRST_I2C4 46
	241	+#define SRST_I2C5 47
	242	+
	243	+#define SRST_DWPWM 48
	244	+#define SRST_MMC_PERI 49
	245	+#define SRST_PERIPH_MMU 50
	246	+#define SRST_DAP 51
	247	+#define SRST_DAP_SYS 52
	248	+#define SRST_TPIU 53
	249	+#define SRST_PMU_APB 54
	250	+#define SRST_GRF 55
	251	+#define SRST_PMU 56
	252	+#define SRST_PERIPH_AXI 57
	253	+#define SRST_PERIPH_AHB 58
	254	+#define SRST_PERIPH_APB 59
	255	+#define SRST_PERIPH_NIU 60
	256	+#define SRST_PDPERI_AHB_ARBI 61
	257	+#define SRST_EMEM 62
	258	+#define SRST_USB_PERI 63
	259	+
	260	+#define SRST_DMAC2 64
	261	+#define SRST_MAC 66
	262	+#define SRST_GPS 67
	263	+#define SRST_RKPWM 69
	264	+#define SRST_CCP 71
	265	+#define SRST_USBHOST0 72
	266	+#define SRST_HSIC 73
	267	+#define SRST_HSIC_AUX 74
	268	+#define SRST_HSIC_PHY 75
	269	+#define SRST_HSADC 76
	270	+#define SRST_NANDC0 77
	271	+#define SRST_NANDC1 78
	272	+
	273	+#define SRST_TZPC 80
	274	+#define SRST_SPI0 83
	275	+#define SRST_SPI1 84
	276	+#define SRST_SPI2 85
	277	+#define SRST_SARADC 87
	278	+#define SRST_PDALIVE_NIU 88
	279	+#define SRST_PDPMU_INTMEM 89
	280	+#define SRST_PDPMU_NIU 90
	281	+#define SRST_SGRF 91
	282	+
	283	+#define SRST_VIO_ARBI 96
	284	+#define SRST_RGA_NIU 97
	285	+#define SRST_VIO0_NIU_AXI 98
	286	+#define SRST_VIO_NIU_AHB 99
	287	+#define SRST_LCDC0_AXI 100
	288	+#define SRST_LCDC0_AHB 101
	289	+#define SRST_LCDC0_DCLK 102
	290	+#define SRST_VIO1_NIU_AXI 103
	291	+#define SRST_VIP 104
	292	+#define SRST_RGA_CORE 105
	293	+#define SRST_IEP_AXI 106
	294	+#define SRST_IEP_AHB 107
	295	+#define SRST_RGA_AXI 108
	296	+#define SRST_RGA_AHB 109
	297	+#define SRST_ISP 110
	298	+#define SRST_EDP 111
	299	+
	300	+#define SRST_VCODEC_AXI 112
	301	+#define SRST_VCODEC_AHB 113
	302	+#define SRST_VIO_H2P 114
	303	+#define SRST_MIPIDSI0 115
	304	+#define SRST_MIPIDSI1 116
	305	+#define SRST_MIPICSI 117
	306	+#define SRST_LVDS_PHY 118
	307	+#define SRST_LVDS_CON 119
	308	+#define SRST_GPU 120
	309	+#define SRST_HDMI 121
	310	+#define SRST_CORE_PVTM 124
	311	+#define SRST_GPU_PVTM 125
	312	+
	313	+#define SRST_MMC0 128
	314	+#define SRST_SDIO0 129
	315	+#define SRST_SDIO1 130
	316	+#define SRST_EMMC 131
	317	+#define SRST_USBOTG_AHB 132
	318	+#define SRST_USBOTG_PHY 133
	319	+#define SRST_USBOTG_CON 134
	320	+#define SRST_USBHOST0_AHB 135
	321	+#define SRST_USBHOST0_PHY 136
	322	+#define SRST_USBHOST0_CON 137
	323	+#define SRST_USBHOST1_AHB 138
	324	+#define SRST_USBHOST1_PHY 139
	325	+#define SRST_USBHOST1_CON 140
	326	+#define SRST_USB_ADP 141
	327	+#define SRST_ACC_EFUSE 142
	328	+
	329	+#define SRST_CORESIGHT 144
	330	+#define SRST_PD_CORE_AHB_NOC 145
	331	+#define SRST_PD_CORE_APB_NOC 146
	332	+#define SRST_PD_CORE_MP_AXI 147
	333	+#define SRST_GIC 148
	334	+#define SRST_LCDC_PWM0 149
	335	+#define SRST_LCDC_PWM1 150
	336	+#define SRST_VIO0_H2P_BRG 151
	337	+#define SRST_VIO1_H2P_BRG 152
	338	+#define SRST_RGA_H2P_BRG 153
	339	+#define SRST_HEVC 154
	340	+#define SRST_TSADC 159
	341	+
	342	+#define SRST_DDRPHY0 160
	343	+#define SRST_DDRPHY0_APB 161
	344	+#define SRST_DDRCTRL0 162
	345	+#define SRST_DDRCTRL0_APB 163
	346	+#define SRST_DDRPHY0_CTRL 164
	347	+#define SRST_DDRPHY1 165
	348	+#define SRST_DDRPHY1_APB 166
	349	+#define SRST_DDRCTRL1 167
	350	+#define SRST_DDRCTRL1_APB 168
	351	+#define SRST_DDRPHY1_CTRL 169
	352	+#define SRST_DDRMSCH0 170
	353	+#define SRST_DDRMSCH1 171
	354	+#define SRST_CRYPTO 174
	355	+#define SRST_C2C_HOST 175
	356	+
	357	+#define SRST_LCDC1_AXI 176
	358	+#define SRST_LCDC1_AHB 177
	359	+#define SRST_LCDC1_DCLK 178
	360	+#define SRST_UART0 179
	361	+#define SRST_UART1 180
	362	+#define SRST_UART2 181
	363	+#define SRST_UART3 182
	364	+#define SRST_UART4 183
	365	+#define SRST_SIMC 186
	366	+#define SRST_PS2C 187
	367	+#define SRST_TSP 188
	368	+#define SRST_TSP_CLKIN0 189
	369	+#define SRST_TSP_CLKIN1 190
	370	+#define SRST_TSP_27M 191

include/dt-bindings/clock/rockchip,rk808.h

Diff comments View file @ 344c837

	1	+/*
	2	+ * This header provides constants clk index RK808 pmic clkout
	3	+ */
	4	+#ifndef _CLK_ROCKCHIP_RK808
	5	+#define _CLK_ROCKCHIP_RK808
	6	+
	7	+/* CLOCKOUT index */
	8	+#define RK808_CLKOUT0 0
	9	+#define RK808_CLKOUT1 1
	10	+
	11	+#endif

include/dt-bindings/pinctrl/rockchip.h

Diff comments View file @ 344c837

	1	+/*
	2	+ * Header providing constants for Rockchip pinctrl bindings.
	3	+ *
	4	+ * Copyright (c) 2013 MundoReader S.L.
	5	+ * Author: Heiko Stuebner <heiko@sntech.de>
	6	+ *
	7	+ * SPDX-License-Identifier: GPL-2.0+
	8	+ */
	9	+
	10	+#ifndef __DT_BINDINGS_ROCKCHIP_PINCTRL_H__
	11	+#define __DT_BINDINGS_ROCKCHIP_PINCTRL_H__
	12	+
	13	+#define RK_GPIO0 0
	14	+#define RK_GPIO1 1
	15	+#define RK_GPIO2 2
	16	+#define RK_GPIO3 3
	17	+#define RK_GPIO4 4
	18	+#define RK_GPIO6 6
	19	+
	20	+#define RK_FUNC_GPIO 0
	21	+#define RK_FUNC_1 1
	22	+#define RK_FUNC_2 2
	23	+#define RK_FUNC_3 3
	24	+#define RK_FUNC_4 4
	25	+
	26	+#endif

include/dt-bindings/power-domain/rk3288.h

Diff comments View file @ 344c837

	1	+#ifndef __DT_BINDINGS_POWER_DOMAIN_RK3288_H__
	2	+#define __DT_BINDINGS_POWER_DOMAIN_RK3288_H__
	3	+
	4	+/* RK3288 power domain index */
	5	+#define RK3288_PD_GPU 0
	6	+#define RK3288_PD_VIO 1
	7	+#define RK3288_PD_VIDEO 2
	8	+#define RK3288_PD_HEVC 3
	9	+#define RK3288_PD_PERI 4
	10	+
	11	+#endif