Eric Lee / smarc-uboot

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Commit 344e04ed3aaea04a5911978163968b4eb3b55475

Authored by Ye Li
1 parent f9cdd005fc
Exists in smarc_8mq-imx_v2020.04_5.4.24_2.1.0 and in 3 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, smarc-8m-android-10.0.0_2.6.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0

MLK-22398-1 pcie_imx: Update PCIE IMX driver 

Update PCIE IMX DM driver supports iMX8QM/QXP and
iMX6QDL/QP/SX. Non-DM driver supports iMX6QDL/QP/SX.
The changes in DM parses cfg/mem/io ranges, gpios, regulators and
clocks (imx8 only) from DTS for RC mode, and set iATU mapping for
each regions.

The original iATU mapping sets full PCI region to CFG space. iATU
translates MEM/IO TLP to CFG TLP when the address is falled into
the region.
The new mapping sets CFG/IO/MEM spaces to align with kernel like below
   ATU region 0 for MEM access
   ATU region 1 for CFG0 or CFG1 access by bus id
   ATU region 2 for IO access

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit eb0959cbf2118342a544440f124e0c81eeba70e3)

Showing 1 changed file with 960 additions and 122 deletions Side-by-side Diff

drivers/pci/pcie_imx.c
Diff comments   View file @ 344e04e
Changes suppressed. Click to show
... ... @@ -5,6 +5,7 @@
5 5 * Copyright (C) 2013 Marek Vasut <marex@denx.de>
6 6 *
7 7 * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
  8 + * Copyright 2019 NXP
8 9 *
9 10 * Based on upstream Linux kernel driver:
10 11 * pci-imx6.c: Sean Cross <xobs@kosagi.com>
11 12  
12 13  
13 14  
14 15  
15 16  
16 17  
17 18  
18 19  
19 20  
... ... @@ -15,34 +16,55 @@
15 16 #include <init.h>
16 17 #include <malloc.h>
17 18 #include <pci.h>
  19 +#if CONFIG_IS_ENABLED(CLK)
  20 +#include <clk.h>
  21 +#else
18 22 #include <asm/arch/clock.h>
  23 +#endif
19 24 #include <asm/arch/iomux.h>
  25 +#ifdef CONFIG_MX6
20 26 #include <asm/arch/crm_regs.h>
  27 +#endif
21 28 #include <asm/gpio.h>
22 29 #include <asm/io.h>
23 30 #include <dm.h>
24 31 #include <linux/sizes.h>
  32 +#include <linux/ioport.h>
25 33 #include <errno.h>
26 34 #include <asm/arch/sys_proto.h>
  35 +#include <syscon.h>
  36 +#include <regmap.h>
  37 +#include <asm-generic/gpio.h>
  38 +#include <dt-bindings/soc/imx8_hsio.h>
  39 +#include <power/regulator.h>
  40 +#include <dm/device_compat.h>
27 41  
  42 +enum imx_pcie_variants {
  43 + IMX6Q,
  44 + IMX6SX,
  45 + IMX6QP,
  46 + IMX8QM,
  47 + IMX8QXP,
  48 +};
  49 +
28 50 #define PCI_ACCESS_READ 0
29 51 #define PCI_ACCESS_WRITE 1
30 52  
31 53 #ifdef CONFIG_MX6SX
32 54 #define MX6_DBI_ADDR 0x08ffc000
33   -#define MX6_IO_ADDR 0x08000000
34   -#define MX6_MEM_ADDR 0x08100000
  55 +#define MX6_IO_ADDR 0x08f80000
  56 +#define MX6_MEM_ADDR 0x08000000
35 57 #define MX6_ROOT_ADDR 0x08f00000
36 58 #else
37 59 #define MX6_DBI_ADDR 0x01ffc000
38   -#define MX6_IO_ADDR 0x01000000
39   -#define MX6_MEM_ADDR 0x01100000
  60 +#define MX6_IO_ADDR 0x01f80000
  61 +#define MX6_MEM_ADDR 0x01000000
40 62 #define MX6_ROOT_ADDR 0x01f00000
41 63 #endif
42 64 #define MX6_DBI_SIZE 0x4000
43   -#define MX6_IO_SIZE 0x100000
44   -#define MX6_MEM_SIZE 0xe00000
45   -#define MX6_ROOT_SIZE 0xfc000
  65 +#define MX6_IO_SIZE 0x10000
  66 +#define MX6_MEM_SIZE 0xf00000
  67 +#define MX6_ROOT_SIZE 0x80000
46 68  
47 69 /* PCIe Port Logic registers (memory-mapped) */
48 70 #define PL_OFFSET 0x700
... ... @@ -54,6 +76,22 @@
54 76 #define PCIE_PHY_DEBUG_R1_LINK_UP (1 << 4)
55 77 #define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (1 << 29)
56 78  
  79 +#define PCIE_PORT_LINK_CONTROL 0x710
  80 +#define PORT_LINK_MODE_MASK (0x3f << 16)
  81 +#define PORT_LINK_MODE_1_LANES (0x1 << 16)
  82 +#define PORT_LINK_MODE_2_LANES (0x3 << 16)
  83 +#define PORT_LINK_MODE_4_LANES (0x7 << 16)
  84 +#define PORT_LINK_MODE_8_LANES (0xf << 16)
  85 +
  86 +
  87 +#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
  88 +#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
  89 +#define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8)
  90 +#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
  91 +#define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
  92 +#define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
  93 +#define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8)
  94 +
57 95 #define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
58 96 #define PCIE_PHY_CTRL_DATA_LOC 0
59 97 #define PCIE_PHY_CTRL_CAP_ADR_LOC 16
... ... @@ -78,6 +116,7 @@
78 116 #define PCIE_ATU_VIEWPORT 0x900
79 117 #define PCIE_ATU_REGION_INBOUND (0x1 << 31)
80 118 #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
  119 +#define PCIE_ATU_REGION_INDEX2 (0x2 << 0)
81 120 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
82 121 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
83 122 #define PCIE_ATU_CR1 0x904
84 123  
... ... @@ -97,11 +136,58 @@
97 136 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
98 137 #define PCIE_ATU_UPPER_TARGET 0x91C
99 138  
100   -struct imx_pcie_priv {
101   - void __iomem *dbi_base;
102   - void __iomem *cfg_base;
103   -};
  139 +#define PCIE_MISC_CTRL (PL_OFFSET + 0x1BC)
  140 +#define PCIE_MISC_DBI_RO_WR_EN BIT(0)
104 141  
  142 +/* iMX8 HSIO registers */
  143 +#define IMX8QM_LPCG_PHYX2_OFFSET 0x00000
  144 +#define IMX8QM_CSR_PHYX2_OFFSET 0x90000
  145 +#define IMX8QM_CSR_PHYX1_OFFSET 0xA0000
  146 +#define IMX8QM_CSR_PHYX_STTS0_OFFSET 0x4
  147 +#define IMX8QM_CSR_PCIEA_OFFSET 0xB0000
  148 +#define IMX8QM_CSR_PCIEB_OFFSET 0xC0000
  149 +#define IMX8QM_CSR_PCIE_CTRL1_OFFSET 0x4
  150 +#define IMX8QM_CSR_PCIE_CTRL2_OFFSET 0x8
  151 +#define IMX8QM_CSR_PCIE_STTS0_OFFSET 0xC
  152 +#define IMX8QM_CSR_MISC_OFFSET 0xE0000
  153 +
  154 +#define IMX8QM_LPCG_PHY_PCG0 BIT(1)
  155 +#define IMX8QM_LPCG_PHY_PCG1 BIT(5)
  156 +
  157 +#define IMX8QM_CTRL_LTSSM_ENABLE BIT(4)
  158 +#define IMX8QM_CTRL_READY_ENTR_L23 BIT(5)
  159 +#define IMX8QM_CTRL_PM_XMT_TURNOFF BIT(9)
  160 +#define IMX8QM_CTRL_BUTTON_RST_N BIT(21)
  161 +#define IMX8QM_CTRL_PERST_N BIT(22)
  162 +#define IMX8QM_CTRL_POWER_UP_RST_N BIT(23)
  163 +
  164 +#define IMX8QM_CTRL_STTS0_PM_LINKST_IN_L2 BIT(13)
  165 +#define IMX8QM_CTRL_STTS0_PM_REQ_CORE_RST BIT(19)
  166 +#define IMX8QM_STTS0_LANE0_TX_PLL_LOCK BIT(4)
  167 +#define IMX8QM_STTS0_LANE1_TX_PLL_LOCK BIT(12)
  168 +
  169 +#define IMX8QM_PCIE_TYPE_MASK (0xF << 24)
  170 +
  171 +#define IMX8QM_PHYX2_CTRL0_APB_MASK 0x3
  172 +#define IMX8QM_PHY_APB_RSTN_0 BIT(0)
  173 +#define IMX8QM_PHY_APB_RSTN_1 BIT(1)
  174 +
  175 +#define IMX8QM_MISC_IOB_RXENA BIT(0)
  176 +#define IMX8QM_MISC_IOB_TXENA BIT(1)
  177 +#define IMX8QM_CSR_MISC_IOB_A_0_TXOE BIT(2)
  178 +#define IMX8QM_CSR_MISC_IOB_A_0_M1M0_MASK (0x3 << 3)
  179 +#define IMX8QM_CSR_MISC_IOB_A_0_M1M0_2 BIT(4)
  180 +#define IMX8QM_MISC_PHYX1_EPCS_SEL BIT(12)
  181 +#define IMX8QM_MISC_PCIE_AB_SELECT BIT(13)
  182 +
  183 +#define HW_PHYX2_CTRL0_PIPE_LN2LK_MASK (0xF << 13)
  184 +#define HW_PHYX2_CTRL0_PIPE_LN2LK_0 BIT(13)
  185 +#define HW_PHYX2_CTRL0_PIPE_LN2LK_1 BIT(14)
  186 +#define HW_PHYX2_CTRL0_PIPE_LN2LK_2 BIT(15)
  187 +#define HW_PHYX2_CTRL0_PIPE_LN2LK_3 BIT(16)
  188 +
  189 +#define PHY_PLL_LOCK_WAIT_MAX_RETRIES 2000
  190 +
105 191 #ifdef DEBUG
106 192  
107 193 #ifdef DEBUG_STRESS_WR /* warm-reset stress tests */
... ... @@ -112,6 +198,7 @@
112 198  
113 199 static void print_regs(int contain_pcie_reg)
114 200 {
  201 +#ifdef CONFIG_MX6
115 202 u32 val;
116 203 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
117 204 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
118 205  
... ... @@ -133,12 +220,53 @@
133 220 val = readl(MX6_DBI_ADDR + 0x72c);
134 221 DBGF("dbr1 offset 0x72c %08x\n", val);
135 222 }
  223 +#endif
136 224 }
137 225 #else
138 226 #define DBGF(x...)
139 227 static void print_regs(int contain_pcie_reg) {}
140 228 #endif
141 229  
  230 +struct imx_pcie_priv {
  231 + void __iomem *dbi_base;
  232 + void __iomem *cfg_base;
  233 + void __iomem *cfg1_base;
  234 + enum imx_pcie_variants variant;
  235 + struct regmap *iomuxc_gpr;
  236 + u32 hsio_cfg;
  237 + u32 ctrl_id;
  238 + u32 ext_osc;
  239 + u32 cpu_base;
  240 + u32 lanes;
  241 + u32 cfg_size;
  242 + int cpu_addr_offset;
  243 + struct gpio_desc clkreq_gpio;
  244 + struct gpio_desc dis_gpio;
  245 + struct gpio_desc reset_gpio;
  246 + struct gpio_desc power_on_gpio;
  247 +
  248 + struct pci_region *io;
  249 + struct pci_region *mem;
  250 + struct pci_region *pref;
  251 +
  252 +#if CONFIG_IS_ENABLED(CLK)
  253 + struct clk pcie_bus;
  254 + struct clk pcie_phy;
  255 + struct clk pcie_inbound_axi;
  256 + struct clk pcie_per;
  257 + struct clk phy_per;
  258 + struct clk misc_per;
  259 + struct clk pcie;
  260 + struct clk pcie_ext_src;
  261 +#endif
  262 +
  263 +#if CONFIG_IS_ENABLED(DM_REGULATOR)
  264 + struct udevice *epdev_on;
  265 + struct udevice *pcie_bus_regulator;
  266 + struct udevice *pcie_phy_regulator;
  267 +#endif
  268 +};
  269 +
142 270 /*
143 271 * PHY access functions
144 272 */
... ... @@ -272,6 +400,32 @@
272 400 return 0;
273 401 }
274 402  
  403 +#if !CONFIG_IS_ENABLED(DM_PCI)
  404 +void imx_pcie_gpr_read(struct imx_pcie_priv *priv, uint offset, uint *valp)
  405 +{
  406 + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  407 + *valp = readl(&iomuxc_regs->gpr[offset >> 2]);
  408 +}
  409 +
  410 +void imx_pcie_gpr_update_bits(struct imx_pcie_priv *priv, uint offset, uint mask, uint val)
  411 +{
  412 + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  413 + clrsetbits_32(&iomuxc_regs->gpr[offset >> 2], mask, val);
  414 +}
  415 +
  416 +#else
  417 +void imx_pcie_gpr_read(struct imx_pcie_priv *priv, uint offset, uint *valp)
  418 +{
  419 + regmap_read(priv->iomuxc_gpr, offset, valp);
  420 +}
  421 +
  422 +void imx_pcie_gpr_update_bits(struct imx_pcie_priv *priv, uint offset, uint mask, uint val)
  423 +{
  424 + regmap_update_bits(priv->iomuxc_gpr, offset, mask, val);
  425 +}
  426 +
  427 +#endif
  428 +
275 429 static int imx6_pcie_link_up(struct imx_pcie_priv *priv)
276 430 {
277 431 u32 rc, ltssm;
278 432  
279 433  
280 434  
281 435  
282 436  
283 437  
284 438  
285 439  
... ... @@ -314,46 +468,123 @@
314 468 return 0;
315 469 }
316 470  
317   -/*
318   - * iATU region setup
319   - */
320   -static int imx_pcie_regions_setup(struct imx_pcie_priv *priv)
  471 +/* Fix class value */
  472 +static void imx_pcie_fix_class(struct imx_pcie_priv *priv)
321 473 {
322   - /*
323   - * i.MX6 defines 16MB in the AXI address map for PCIe.
324   - *
325   - * That address space excepted the pcie registers is
326   - * split and defined into different regions by iATU,
327   - * with sizes and offsets as follows:
328   - *
329   - * 0x0100_0000 --- 0x010F_FFFF 1MB IORESOURCE_IO
330   - * 0x0110_0000 --- 0x01EF_FFFF 14MB IORESOURCE_MEM
331   - * 0x01F0_0000 --- 0x01FF_FFFF 1MB Cfg + Registers
332   - */
  474 + writew(PCI_CLASS_BRIDGE_PCI, priv->dbi_base + PCI_CLASS_DEVICE);
  475 +}
333 476  
334   - /* CMD reg:I/O space, MEM space, and Bus Master Enable */
335   - setbits_le32(priv->dbi_base + PCI_COMMAND,
336   - PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
  477 +/* Clear multi-function bit */
  478 +static void imx_pcie_clear_multifunction(struct imx_pcie_priv *priv)
  479 +{
  480 + writeb(PCI_HEADER_TYPE_BRIDGE, priv->dbi_base + PCI_HEADER_TYPE);
  481 +}
337 482  
338   - /* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */
339   - setbits_le32(priv->dbi_base + PCI_CLASS_REVISION,
340   - PCI_CLASS_BRIDGE_PCI << 16);
  483 +static void imx_pcie_setup_ctrl(struct imx_pcie_priv *priv)
  484 +{
  485 + u32 val;
341 486  
342   - /* Region #0 is used for Outbound CFG space access. */
343   - writel(0, priv->dbi_base + PCIE_ATU_VIEWPORT);
  487 + writel(PCIE_MISC_DBI_RO_WR_EN, priv->dbi_base + PCIE_MISC_CTRL);
344 488  
345   - writel(lower_32_bits((uintptr_t)priv->cfg_base),
346   - priv->dbi_base + PCIE_ATU_LOWER_BASE);
347   - writel(upper_32_bits((uintptr_t)priv->cfg_base),
348   - priv->dbi_base + PCIE_ATU_UPPER_BASE);
349   - writel(lower_32_bits((uintptr_t)priv->cfg_base + MX6_ROOT_SIZE),
350   - priv->dbi_base + PCIE_ATU_LIMIT);
  489 + /* Set the number of lanes */
  490 + val = readl(priv->dbi_base + PCIE_PORT_LINK_CONTROL);
  491 + val &= ~PORT_LINK_MODE_MASK;
  492 + switch (priv->lanes) {
  493 + case 1:
  494 + val |= PORT_LINK_MODE_1_LANES;
  495 + break;
  496 + case 2:
  497 + val |= PORT_LINK_MODE_2_LANES;
  498 + break;
  499 + case 4:
  500 + val |= PORT_LINK_MODE_4_LANES;
  501 + break;
  502 + case 8:
  503 + val |= PORT_LINK_MODE_8_LANES;
  504 + break;
  505 + default:
  506 + printf("num-lanes %u: invalid value\n", priv->lanes);
  507 + return;
  508 + }
  509 + writel(val, priv->dbi_base + PCIE_PORT_LINK_CONTROL);
351 510  
352   - writel(0, priv->dbi_base + PCIE_ATU_LOWER_TARGET);
353   - writel(0, priv->dbi_base + PCIE_ATU_UPPER_TARGET);
354   - writel(PCIE_ATU_TYPE_CFG0, priv->dbi_base + PCIE_ATU_CR1);
  511 + /* Set link width speed control register */
  512 + val = readl(priv->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
  513 + val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
  514 + switch (priv->lanes) {
  515 + case 1:
  516 + val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
  517 + break;
  518 + case 2:
  519 + val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
  520 + break;
  521 + case 4:
  522 + val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
  523 + break;
  524 + case 8:
  525 + val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
  526 + break;
  527 + }
  528 + writel(val, priv->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
  529 +
  530 + /* setup RC BARs */
  531 + writel(0, priv->dbi_base + PCI_BASE_ADDRESS_0);
  532 + writel(0, priv->dbi_base + PCI_BASE_ADDRESS_1);
  533 +
  534 + /* setup bus numbers */
  535 + val = readl(priv->dbi_base + PCI_PRIMARY_BUS);
  536 + val &= 0xff000000;
  537 + val |= 0x00ff0100;
  538 + writel(val, priv->dbi_base + PCI_PRIMARY_BUS);
  539 +
  540 + /* setup command register */
  541 + val = readl(priv->dbi_base + PCI_COMMAND);
  542 + val &= 0xffff0000;
  543 + val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
  544 + PCI_COMMAND_MASTER;
  545 + writel(val, priv->dbi_base + PCI_COMMAND);
  546 +
  547 + imx_pcie_fix_class(priv);
  548 + imx_pcie_clear_multifunction(priv);
  549 +
  550 + writel(0, priv->dbi_base + PCIE_MISC_CTRL);
  551 +}
  552 +
  553 +static void imx_pcie_atu_outbound_set(struct imx_pcie_priv *priv, int idx, int type,
  554 + u64 phys, u64 bus_addr, u32 size)
  555 +{
  556 + writel(PCIE_ATU_REGION_OUTBOUND | idx, priv->dbi_base + PCIE_ATU_VIEWPORT);
  557 + writel((u32)(phys + priv->cpu_addr_offset), priv->dbi_base + PCIE_ATU_LOWER_BASE);
  558 + writel((phys + priv->cpu_addr_offset) >> 32, priv->dbi_base + PCIE_ATU_UPPER_BASE);
  559 + writel((u32)(phys + priv->cpu_addr_offset) + size - 1, priv->dbi_base + PCIE_ATU_LIMIT);
  560 + writel((u32)bus_addr, priv->dbi_base + PCIE_ATU_LOWER_TARGET);
  561 + writel(bus_addr >> 32, priv->dbi_base + PCIE_ATU_UPPER_TARGET);
  562 + writel(type, priv->dbi_base + PCIE_ATU_CR1);
355 563 writel(PCIE_ATU_ENABLE, priv->dbi_base + PCIE_ATU_CR2);
  564 +}
356 565  
  566 +/*
  567 + * iATU region setup
  568 + */
  569 +static int imx_pcie_regions_setup(struct imx_pcie_priv *priv)
  570 +{
  571 + if (priv->io)
  572 + /* ATU : OUTBOUND : IO */
  573 + imx_pcie_atu_outbound_set(priv, PCIE_ATU_REGION_INDEX2,
  574 + PCIE_ATU_TYPE_IO,
  575 + priv->io->phys_start,
  576 + priv->io->bus_start,
  577 + priv->io->size);
  578 +
  579 + if (priv->mem)
  580 + /* ATU : OUTBOUND : MEM */
  581 + imx_pcie_atu_outbound_set(priv, PCIE_ATU_REGION_INDEX0,
  582 + PCIE_ATU_TYPE_MEM,
  583 + priv->mem->phys_start,
  584 + priv->mem->bus_start,
  585 + priv->mem->size);
  586 +
  587 +
357 588 return 0;
358 589 }
359 590  
360 591  
361 592  
362 593  
363 594  
364 595  
... ... @@ -365,30 +596,40 @@
365 596 {
366 597 void __iomem *va_address;
367 598  
368   - /* Reconfigure Region #0 */
369   - writel(0, priv->dbi_base + PCIE_ATU_VIEWPORT);
370   -
371   - if (PCI_BUS(d) < 2)
372   - writel(PCIE_ATU_TYPE_CFG0, priv->dbi_base + PCIE_ATU_CR1);
373   - else
374   - writel(PCIE_ATU_TYPE_CFG1, priv->dbi_base + PCIE_ATU_CR1);
375   -
376 599 if (PCI_BUS(d) == 0) {
  600 + /* Outbound TLP matched primary interface of the bridge */
377 601 va_address = priv->dbi_base;
378 602 } else {
379   - writel(d << 8, priv->dbi_base + PCIE_ATU_LOWER_TARGET);
380   - va_address = priv->cfg_base;
  603 + if (PCI_BUS(d) < 2) {
  604 + /* Outbound TLP matched secondary interface of the bridge changes to CFG0 */
  605 + imx_pcie_atu_outbound_set(priv, PCIE_ATU_REGION_INDEX1,
  606 + PCIE_ATU_TYPE_CFG0,
  607 + (ulong)priv->cfg_base,
  608 + d << 8,
  609 + priv->cfg_size >> 1);
  610 + va_address = priv->cfg_base;
  611 + } else {
  612 + /* Outbound TLP matched the bus behind the bridge uses type CFG1 */
  613 + imx_pcie_atu_outbound_set(priv, PCIE_ATU_REGION_INDEX1,
  614 + PCIE_ATU_TYPE_CFG1,
  615 + (ulong)priv->cfg1_base,
  616 + d << 8,
  617 + priv->cfg_size >> 1);
  618 + va_address = priv->cfg1_base;
  619 + }
381 620 }
382 621  
383 622 va_address += (where & ~0x3);
384 623  
385 624 return va_address;
  625 +
386 626 }
387 627  
388 628 static int imx_pcie_addr_valid(pci_dev_t d)
389 629 {
390   - if ((PCI_BUS(d) == 0) && (PCI_DEV(d) > 1))
  630 + if ((PCI_BUS(d) == 0) && (PCI_DEV(d) > 0))
391 631 return -EINVAL;
  632 + /* ARI forward is not enabled, so non-zero device at downstream must be blocked */
392 633 if ((PCI_BUS(d) == 1) && (PCI_DEV(d) > 0))
393 634 return -EINVAL;
394 635 return 0;
... ... @@ -409,6 +650,7 @@
409 650 */
410 651 static void imx_pcie_fix_dabt_handler(bool set)
411 652 {
  653 +#ifdef CONFIG_MX6
412 654 extern uint32_t *_data_abort;
413 655 uint32_t *data_abort_addr = (uint32_t *)&_data_abort;
414 656  
... ... @@ -423,6 +665,7 @@
423 665 } else {
424 666 *data_abort_addr = data_abort_backup;
425 667 }
  668 +#endif
426 669 }
427 670  
428 671 static int imx_pcie_read_cfg(struct imx_pcie_priv *priv, pci_dev_t d,
... ... @@ -434,7 +677,7 @@
434 677 ret = imx_pcie_addr_valid(d);
435 678 if (ret) {
436 679 *val = 0xffffffff;
437   - return ret;
  680 + return 0;
438 681 }
439 682  
440 683 va_address = get_bus_address(priv, d, where);
441 684  
442 685  
443 686  
444 687  
... ... @@ -478,28 +721,337 @@
478 721 return 0;
479 722 }
480 723  
  724 +static int imx8_pcie_assert_core_reset(struct imx_pcie_priv *priv,
  725 + bool prepare_for_boot)
  726 +{
  727 + u32 val;
  728 +
  729 + switch (priv->variant) {
  730 + case IMX8QXP:
  731 + val = IMX8QM_CSR_PCIEB_OFFSET;
  732 + imx_pcie_gpr_update_bits(priv,
  733 + val + IMX8QM_CSR_PCIE_CTRL2_OFFSET,
  734 + IMX8QM_CTRL_BUTTON_RST_N,
  735 + IMX8QM_CTRL_BUTTON_RST_N);
  736 + imx_pcie_gpr_update_bits(priv,
  737 + val + IMX8QM_CSR_PCIE_CTRL2_OFFSET,
  738 + IMX8QM_CTRL_PERST_N,
  739 + IMX8QM_CTRL_PERST_N);
  740 + imx_pcie_gpr_update_bits(priv,
  741 + val + IMX8QM_CSR_PCIE_CTRL2_OFFSET,
  742 + IMX8QM_CTRL_POWER_UP_RST_N,
  743 + IMX8QM_CTRL_POWER_UP_RST_N);
  744 + break;
  745 + case IMX8QM:
  746 + val = IMX8QM_CSR_PCIEA_OFFSET + priv->ctrl_id * SZ_64K;
  747 + imx_pcie_gpr_update_bits(priv,
  748 + val + IMX8QM_CSR_PCIE_CTRL2_OFFSET,
  749 + IMX8QM_CTRL_BUTTON_RST_N,
  750 + IMX8QM_CTRL_BUTTON_RST_N);
  751 + imx_pcie_gpr_update_bits(priv,
  752 + val + IMX8QM_CSR_PCIE_CTRL2_OFFSET,
  753 + IMX8QM_CTRL_PERST_N,
  754 + IMX8QM_CTRL_PERST_N);
  755 + imx_pcie_gpr_update_bits(priv,
  756 + val + IMX8QM_CSR_PCIE_CTRL2_OFFSET,
  757 + IMX8QM_CTRL_POWER_UP_RST_N,
  758 + IMX8QM_CTRL_POWER_UP_RST_N);
  759 + break;
  760 + default:
  761 + break;
  762 + }
  763 +
  764 + return 0;
  765 +}
  766 +
  767 +static int imx8_pcie_init_phy(struct imx_pcie_priv *priv)
  768 +{
  769 + u32 tmp, val;
  770 +
  771 + if (priv->variant == IMX8QM
  772 + || priv->variant == IMX8QXP) {
  773 + switch (priv->hsio_cfg) {
  774 + case PCIEAX2SATA:
  775 + /*
  776 + * bit 0 rx ena 1.
  777 + * bit12 PHY_X1_EPCS_SEL 1.
  778 + * bit13 phy_ab_select 0.
  779 + */
  780 + imx_pcie_gpr_update_bits(priv,
  781 + IMX8QM_CSR_PHYX2_OFFSET,
  782 + IMX8QM_PHYX2_CTRL0_APB_MASK,
  783 + IMX8QM_PHY_APB_RSTN_0
  784 + | IMX8QM_PHY_APB_RSTN_1);
  785 +
  786 + imx_pcie_gpr_update_bits(priv,
  787 + IMX8QM_CSR_MISC_OFFSET,
  788 + IMX8QM_MISC_PHYX1_EPCS_SEL,
  789 + IMX8QM_MISC_PHYX1_EPCS_SEL);
  790 + imx_pcie_gpr_update_bits(priv,
  791 + IMX8QM_CSR_MISC_OFFSET,
  792 + IMX8QM_MISC_PCIE_AB_SELECT,
  793 + 0);
  794 + break;
  795 +
  796 + case PCIEAX1PCIEBX1SATA:
  797 + tmp = IMX8QM_PHY_APB_RSTN_1;
  798 + tmp |= IMX8QM_PHY_APB_RSTN_0;
  799 + imx_pcie_gpr_update_bits(priv,
  800 + IMX8QM_CSR_PHYX2_OFFSET,
  801 + IMX8QM_PHYX2_CTRL0_APB_MASK, tmp);
  802 +
  803 + imx_pcie_gpr_update_bits(priv,
  804 + IMX8QM_CSR_MISC_OFFSET,
  805 + IMX8QM_MISC_PHYX1_EPCS_SEL,
  806 + IMX8QM_MISC_PHYX1_EPCS_SEL);
  807 + imx_pcie_gpr_update_bits(priv,
  808 + IMX8QM_CSR_MISC_OFFSET,
  809 + IMX8QM_MISC_PCIE_AB_SELECT,
  810 + IMX8QM_MISC_PCIE_AB_SELECT);
  811 +
  812 + imx_pcie_gpr_update_bits(priv,
  813 + IMX8QM_CSR_PHYX2_OFFSET,
  814 + HW_PHYX2_CTRL0_PIPE_LN2LK_MASK,
  815 + HW_PHYX2_CTRL0_PIPE_LN2LK_3 | HW_PHYX2_CTRL0_PIPE_LN2LK_0);
  816 +
  817 + break;
  818 +
  819 + case PCIEAX2PCIEBX1:
  820 + /*
  821 + * bit 0 rx ena 1.
  822 + * bit12 PHY_X1_EPCS_SEL 0.
  823 + * bit13 phy_ab_select 1.
  824 + */
  825 + if (priv->ctrl_id)
  826 + imx_pcie_gpr_update_bits(priv,
  827 + IMX8QM_CSR_PHYX1_OFFSET,
  828 + IMX8QM_PHY_APB_RSTN_0,
  829 + IMX8QM_PHY_APB_RSTN_0);
  830 + else
  831 + imx_pcie_gpr_update_bits(priv,
  832 + IMX8QM_CSR_PHYX2_OFFSET,
  833 + IMX8QM_PHYX2_CTRL0_APB_MASK,
  834 + IMX8QM_PHY_APB_RSTN_0
  835 + | IMX8QM_PHY_APB_RSTN_1);
  836 +
  837 + imx_pcie_gpr_update_bits(priv,
  838 + IMX8QM_CSR_MISC_OFFSET,
  839 + IMX8QM_MISC_PHYX1_EPCS_SEL,
  840 + 0);
  841 + imx_pcie_gpr_update_bits(priv,
  842 + IMX8QM_CSR_MISC_OFFSET,
  843 + IMX8QM_MISC_PCIE_AB_SELECT,
  844 + IMX8QM_MISC_PCIE_AB_SELECT);
  845 + break;
  846 + }
  847 +
  848 + if (priv->ext_osc) {
  849 + imx_pcie_gpr_update_bits(priv,
  850 + IMX8QM_CSR_MISC_OFFSET,
  851 + IMX8QM_MISC_IOB_RXENA,
  852 + IMX8QM_MISC_IOB_RXENA);
  853 + imx_pcie_gpr_update_bits(priv,
  854 + IMX8QM_CSR_MISC_OFFSET,
  855 + IMX8QM_MISC_IOB_TXENA,
  856 + 0);
  857 + } else {
  858 + /* Try to used the internal pll as ref clk */
  859 + imx_pcie_gpr_update_bits(priv,
  860 + IMX8QM_CSR_MISC_OFFSET,
  861 + IMX8QM_MISC_IOB_RXENA,
  862 + 0);
  863 + imx_pcie_gpr_update_bits(priv,
  864 + IMX8QM_CSR_MISC_OFFSET,
  865 + IMX8QM_MISC_IOB_TXENA,
  866 + IMX8QM_MISC_IOB_TXENA);
  867 + imx_pcie_gpr_update_bits(priv,
  868 + IMX8QM_CSR_MISC_OFFSET,
  869 + IMX8QM_CSR_MISC_IOB_A_0_TXOE
  870 + | IMX8QM_CSR_MISC_IOB_A_0_M1M0_MASK,
  871 + IMX8QM_CSR_MISC_IOB_A_0_TXOE
  872 + | IMX8QM_CSR_MISC_IOB_A_0_M1M0_2);
  873 + }
  874 +
  875 + val = IMX8QM_CSR_PCIEA_OFFSET
  876 + + priv->ctrl_id * SZ_64K;
  877 + imx_pcie_gpr_update_bits(priv,
  878 + val, IMX8QM_PCIE_TYPE_MASK,
  879 + 0x4 << 24);
  880 +
  881 + mdelay(10);
  882 + }
  883 +
  884 + return 0;
  885 +}
  886 +
  887 +static int imx8_pcie_wait_for_phy_pll_lock(struct imx_pcie_priv *priv)
  888 +{
  889 + u32 val, tmp, orig;
  890 + unsigned int retries = 0;
  891 +
  892 + if (priv->variant == IMX8QXP
  893 + || priv->variant == IMX8QM) {
  894 + for (retries = 0; retries < PHY_PLL_LOCK_WAIT_MAX_RETRIES;
  895 + retries++) {
  896 + if (priv->hsio_cfg == PCIEAX1PCIEBX1SATA) {
  897 + imx_pcie_gpr_read(priv,
  898 + IMX8QM_CSR_PHYX2_OFFSET + 0x4,
  899 + &tmp);
  900 + if (priv->ctrl_id == 0) /* pciea 1 lanes */
  901 + orig = IMX8QM_STTS0_LANE0_TX_PLL_LOCK;
  902 + else /* pcieb 1 lanes */
  903 + orig = IMX8QM_STTS0_LANE1_TX_PLL_LOCK;
  904 + tmp &= orig;
  905 + if (tmp == orig) {
  906 + imx_pcie_gpr_update_bits(priv,
  907 + IMX8QM_LPCG_PHYX2_OFFSET,
  908 + IMX8QM_LPCG_PHY_PCG0
  909 + | IMX8QM_LPCG_PHY_PCG1,
  910 + IMX8QM_LPCG_PHY_PCG0
  911 + | IMX8QM_LPCG_PHY_PCG1);
  912 + break;
  913 + }
  914 + }
  915 +
  916 + if (priv->hsio_cfg == PCIEAX2PCIEBX1) {
  917 + val = IMX8QM_CSR_PHYX2_OFFSET
  918 + + priv->ctrl_id * SZ_64K;
  919 + imx_pcie_gpr_read(priv,
  920 + val + IMX8QM_CSR_PHYX_STTS0_OFFSET,
  921 + &tmp);
  922 + orig = IMX8QM_STTS0_LANE0_TX_PLL_LOCK;
  923 + if (priv->ctrl_id == 0) /* pciea 2 lanes */
  924 + orig |= IMX8QM_STTS0_LANE1_TX_PLL_LOCK;
  925 + tmp &= orig;
  926 + if (tmp == orig) {
  927 + val = IMX8QM_CSR_PHYX2_OFFSET
  928 + + priv->ctrl_id * SZ_64K;
  929 + imx_pcie_gpr_update_bits(priv,
  930 + val, IMX8QM_LPCG_PHY_PCG0,
  931 + IMX8QM_LPCG_PHY_PCG0);
  932 + break;
  933 + }
  934 + }
  935 + udelay(10);
  936 + }
  937 + }
  938 +
  939 + if (retries >= PHY_PLL_LOCK_WAIT_MAX_RETRIES) {
  940 + printf("pcie phy pll can't be locked.\n");
  941 + return -ENODEV;
  942 + } else {
  943 + debug("pcie phy pll is locked.\n");
  944 + return 0;
  945 + }
  946 +}
  947 +
  948 +static int imx8_pcie_deassert_core_reset(struct imx_pcie_priv *priv)
  949 +{
  950 + int ret, i;
  951 + u32 val, tmp;
  952 +
  953 +#if CONFIG_IS_ENABLED(CLK)
  954 + ret = clk_enable(&priv->pcie);
  955 + if (ret) {
  956 + printf("unable to enable pcie clock\n");
  957 + return ret;
  958 + }
  959 +
  960 + ret = clk_enable(&priv->pcie_phy);
  961 + if (ret) {
  962 + printf("unable to enable pcie_phy clock\n");
  963 + goto err_pcie;
  964 + }
  965 +#endif
  966 +
  967 + if (priv->variant == IMX8QM
  968 + || priv->variant == IMX8QXP) {
  969 +
  970 +#if CONFIG_IS_ENABLED(CLK)
  971 + ret = clk_enable(&priv->pcie_inbound_axi);
  972 + if (ret) {
  973 + printf("unable to enable pcie_axi clock\n");
  974 + goto err_pcie_phy;
  975 + }
  976 + ret = clk_enable(&priv->pcie_per);
  977 + if (ret) {
  978 + printf("unable to enable pcie_per clock\n");
  979 + clk_disable(&priv->pcie_inbound_axi);
  980 + goto err_pcie_phy;
  981 + }
  982 +#endif
  983 + /* allow the clocks to stabilize */
  984 + udelay(200);
  985 +
  986 + /* bit19 PM_REQ_CORE_RST of pciex#_stts0 should be cleared. */
  987 + for (i = 0; i < 100; i++) {
  988 + val = IMX8QM_CSR_PCIEA_OFFSET
  989 + + priv->ctrl_id * SZ_64K;
  990 + imx_pcie_gpr_read(priv,
  991 + val + IMX8QM_CSR_PCIE_STTS0_OFFSET,
  992 + &tmp);
  993 + if ((tmp & IMX8QM_CTRL_STTS0_PM_REQ_CORE_RST) == 0)
  994 + break;
  995 + udelay(10);
  996 + }
  997 +
  998 + if ((tmp & IMX8QM_CTRL_STTS0_PM_REQ_CORE_RST) != 0)
  999 + printf("ERROR PM_REQ_CORE_RST is still set.\n");
  1000 +
  1001 + /* wait for phy pll lock firstly. */
  1002 + if (imx8_pcie_wait_for_phy_pll_lock(priv)) {
  1003 + ret = -ENODEV;
  1004 + goto err_ref_clk;;
  1005 + }
  1006 +
  1007 + if (dm_gpio_is_valid(&priv->reset_gpio)) {
  1008 + dm_gpio_set_value(&priv->reset_gpio, 1);
  1009 + mdelay(20);
  1010 + dm_gpio_set_value(&priv->reset_gpio, 0);
  1011 + mdelay(20);
  1012 + }
  1013 +
  1014 + return 0;
  1015 + }
  1016 +
  1017 +err_ref_clk:
  1018 +#if CONFIG_IS_ENABLED(CLK)
  1019 + clk_disable(&priv->pcie_per);
  1020 + clk_disable(&priv->pcie_inbound_axi);
  1021 +err_pcie_phy:
  1022 + clk_disable(&priv->pcie_phy);
  1023 +err_pcie:
  1024 + clk_disable(&priv->pcie);
  1025 +#endif
  1026 +
  1027 + return ret;
  1028 +}
  1029 +
  1030 +#ifdef CONFIG_MX6
481 1031 /*
482 1032 * Initial bus setup
483 1033 */
484 1034 static int imx6_pcie_assert_core_reset(struct imx_pcie_priv *priv,
485 1035 bool prepare_for_boot)
486 1036 {
487   - struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  1037 + if (priv->variant == IMX6QP)
  1038 + imx_pcie_gpr_update_bits(priv, 4, IOMUXC_GPR1_PCIE_SW_RST, IOMUXC_GPR1_PCIE_SW_RST);
488 1039  
489   - if (is_mx6dqp())
490   - setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
491   -
492 1040 #if defined(CONFIG_MX6SX)
493   - struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
  1041 + if (priv->variant == IMX6SX) {
  1042 + struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
494 1043  
495   - /* SSP_EN is not used on MX6SX anymore */
496   - setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
497   - /* Force PCIe PHY reset */
498   - setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
499   - /* Power up PCIe PHY */
500   - setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ);
501   - pcie_power_up();
502   -#else
  1044 + /* SSP_EN is not used on MX6SX anymore */
  1045 + imx_pcie_gpr_update_bits(priv, 48, IOMUXC_GPR12_TEST_POWERDOWN, IOMUXC_GPR12_TEST_POWERDOWN);
  1046 + /* Force PCIe PHY reset */
  1047 + imx_pcie_gpr_update_bits(priv, 20, IOMUXC_GPR5_PCIE_BTNRST, IOMUXC_GPR5_PCIE_BTNRST);
  1048 + /* Power up PCIe PHY */
  1049 + setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ);
  1050 + pcie_power_up();
  1051 +
  1052 + return 0;
  1053 + }
  1054 +#endif
503 1055 /*
504 1056 * If the bootloader already enabled the link we need some special
505 1057 * handling to get the core back into a state where it is safe to
506 1058  
... ... @@ -511,11 +1063,11 @@
511 1063 * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong
512 1064 * indication that the bootloader activated the link.
513 1065 */
514   - if (is_mx6dq() && prepare_for_boot) {
  1066 + if (priv->variant == IMX6QP && prepare_for_boot) {
515 1067 u32 val, gpr1, gpr12;
516 1068  
517   - gpr1 = readl(&iomuxc_regs->gpr[1]);
518   - gpr12 = readl(&iomuxc_regs->gpr[12]);
  1069 + imx_pcie_gpr_read(priv, 4, &gpr1);
  1070 + imx_pcie_gpr_read(priv, 48, &gpr12);
519 1071 if ((gpr1 & IOMUXC_GPR1_PCIE_REF_CLK_EN) &&
520 1072 (gpr12 & IOMUXC_GPR12_PCIE_CTL_2)) {
521 1073 val = readl(priv->dbi_base + PCIE_PL_PFLR);
522 1074  
523 1075  
524 1076  
525 1077  
526 1078  
527 1079  
528 1080  
529 1081  
530 1082  
531 1083  
... ... @@ -526,44 +1078,44 @@
526 1078 writel(val, priv->dbi_base + PCIE_PL_PFLR);
527 1079 imx_pcie_fix_dabt_handler(false);
528 1080  
529   - gpr12 &= ~IOMUXC_GPR12_PCIE_CTL_2;
530   - writel(val, &iomuxc_regs->gpr[12]);
  1081 + imx_pcie_gpr_update_bits(priv, 48, IOMUXC_GPR12_PCIE_CTL_2, 0);
531 1082 }
532 1083 }
533   - setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
534   - clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
535   -#endif
536 1084  
  1085 + if (priv->variant == IMX6QP || priv->variant == IMX6Q) {
  1086 + imx_pcie_gpr_update_bits(priv, 4, IOMUXC_GPR1_TEST_POWERDOWN,
  1087 + IOMUXC_GPR1_TEST_POWERDOWN);
  1088 + imx_pcie_gpr_update_bits(priv, 4, IOMUXC_GPR1_REF_SSP_EN, 0);
  1089 + }
  1090 +
537 1091 return 0;
538 1092 }
539 1093  
540   -static int imx6_pcie_init_phy(void)
  1094 +static int imx6_pcie_init_phy(struct imx_pcie_priv *priv)
541 1095 {
542   - struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
543   -
544 1096 #ifndef DEBUG
545   - clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE);
  1097 + imx_pcie_gpr_update_bits(priv, 48, IOMUXC_GPR12_APPS_LTSSM_ENABLE, 0);
546 1098 #endif
547 1099  
548   - clrsetbits_le32(&iomuxc_regs->gpr[12],
  1100 + imx_pcie_gpr_update_bits(priv, 48,
549 1101 IOMUXC_GPR12_DEVICE_TYPE_MASK,
550 1102 IOMUXC_GPR12_DEVICE_TYPE_RC);
551   - clrsetbits_le32(&iomuxc_regs->gpr[12],
  1103 + imx_pcie_gpr_update_bits(priv, 48,
552 1104 IOMUXC_GPR12_LOS_LEVEL_MASK,
553 1105 IOMUXC_GPR12_LOS_LEVEL_9);
554 1106  
555   -#ifdef CONFIG_MX6SX
556   - clrsetbits_le32(&iomuxc_regs->gpr[12],
557   - IOMUXC_GPR12_RX_EQ_MASK,
558   - IOMUXC_GPR12_RX_EQ_2);
559   -#endif
  1107 + if (priv->variant == IMX6SX) {
  1108 + imx_pcie_gpr_update_bits(priv, 48,
  1109 + IOMUXC_GPR12_RX_EQ_MASK,
  1110 + IOMUXC_GPR12_RX_EQ_2);
  1111 + }
560 1112  
561   - writel((0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET) |
  1113 + imx_pcie_gpr_update_bits(priv, 32, 0xffffffff,
  1114 + (0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET) |
562 1115 (0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET) |
563 1116 (20 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET) |
564 1117 (127 << IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET) |
565   - (127 << IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET),
566   - &iomuxc_regs->gpr[8]);
  1118 + (127 << IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET));
567 1119  
568 1120 return 0;
569 1121 }
570 1122  
571 1123  
572 1124  
573 1125  
... ... @@ -621,19 +1173,20 @@
621 1173 #else
622 1174 puts("WARNING: Make sure the PCIe #PERST line is connected!\n");
623 1175 #endif
  1176 +
624 1177 return 0;
625 1178 }
626 1179  
627   -static int imx6_pcie_deassert_core_reset(void)
  1180 +static int imx6_pcie_deassert_core_reset(struct imx_pcie_priv *priv)
628 1181 {
629   - struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
630   -
  1182 +#if !CONFIG_IS_ENABLED(DM_PCI)
631 1183 imx6_pcie_toggle_power();
  1184 +#endif
632 1185  
633 1186 enable_pcie_clock();
634 1187  
635   - if (is_mx6dqp())
636   - clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
  1188 + if (priv->variant == IMX6QP)
  1189 + imx_pcie_gpr_update_bits(priv, 4, IOMUXC_GPR1_PCIE_SW_RST, 0);
637 1190  
638 1191 /*
639 1192 * Wait for the clock to settle a bit, when the clock are sourced
640 1193  
641 1194  
642 1195  
643 1196  
644 1197  
645 1198  
646 1199  
... ... @@ -641,32 +1194,135 @@
641 1194 */
642 1195 mdelay(50);
643 1196  
644   -#if defined(CONFIG_MX6SX)
645   - /* SSP_EN is not used on MX6SX anymore */
646   - clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
647   - /* Clear PCIe PHY reset bit */
648   - clrbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
  1197 + if (priv->variant == IMX6SX) {
  1198 + /* SSP_EN is not used on MX6SX anymore */
  1199 + imx_pcie_gpr_update_bits(priv, 48, IOMUXC_GPR12_TEST_POWERDOWN, 0);
  1200 + /* Clear PCIe PHY reset bit */
  1201 + imx_pcie_gpr_update_bits(priv, 20, IOMUXC_GPR5_PCIE_BTNRST, 0);
  1202 + } else {
  1203 + /* Enable PCIe */
  1204 + imx_pcie_gpr_update_bits(priv, 4, IOMUXC_GPR1_TEST_POWERDOWN, 0);
  1205 + imx_pcie_gpr_update_bits(priv, 4, IOMUXC_GPR1_REF_SSP_EN, IOMUXC_GPR1_REF_SSP_EN);
  1206 + }
  1207 +
  1208 +#if !CONFIG_IS_ENABLED(DM_PCI)
  1209 + imx6_pcie_toggle_reset();
649 1210 #else
650   - /* Enable PCIe */
651   - clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
652   - setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
  1211 + if (dm_gpio_is_valid(&priv->reset_gpio)) {
  1212 + dm_gpio_set_value(&priv->reset_gpio, 1);
  1213 + mdelay(20);
  1214 + dm_gpio_set_value(&priv->reset_gpio, 0);
  1215 + mdelay(20);
  1216 + }
653 1217 #endif
654 1218  
655   - imx6_pcie_toggle_reset();
656   -
657 1219 return 0;
658 1220 }
  1221 +#endif
659 1222  
  1223 +static int imx_pcie_assert_core_reset(struct imx_pcie_priv *priv,
  1224 + bool prepare_for_boot)
  1225 +{
  1226 + switch (priv->variant) {
  1227 +#ifdef CONFIG_MX6
  1228 + case IMX6Q:
  1229 + case IMX6QP:
  1230 + case IMX6SX:
  1231 + return imx6_pcie_assert_core_reset(priv, prepare_for_boot);
  1232 +#endif
  1233 + case IMX8QM:
  1234 + case IMX8QXP:
  1235 + return imx8_pcie_assert_core_reset(priv, prepare_for_boot);
  1236 + default:
  1237 + return -EPERM;
  1238 + }
  1239 +}
  1240 +
  1241 +static int imx_pcie_init_phy(struct imx_pcie_priv *priv)
  1242 +{
  1243 + switch (priv->variant) {
  1244 +#ifdef CONFIG_MX6
  1245 + case IMX6Q:
  1246 + case IMX6QP:
  1247 + case IMX6SX:
  1248 + return imx6_pcie_init_phy(priv);
  1249 +#endif
  1250 + case IMX8QM:
  1251 + case IMX8QXP:
  1252 + return imx8_pcie_init_phy(priv);
  1253 + default:
  1254 + return -EPERM;
  1255 + }
  1256 +}
  1257 +
  1258 +static int imx_pcie_deassert_core_reset(struct imx_pcie_priv *priv)
  1259 +{
  1260 + switch (priv->variant) {
  1261 +#ifdef CONFIG_MX6
  1262 + case IMX6Q:
  1263 + case IMX6QP:
  1264 + case IMX6SX:
  1265 + return imx6_pcie_deassert_core_reset(priv);
  1266 +#endif
  1267 + case IMX8QM:
  1268 + case IMX8QXP:
  1269 + return imx8_pcie_deassert_core_reset(priv);
  1270 + default:
  1271 + return -EPERM;
  1272 + }
  1273 +}
  1274 +
  1275 +static void imx_pcie_ltssm_enable(struct imx_pcie_priv *priv, bool enable)
  1276 +{
  1277 + u32 val;
  1278 +
  1279 + switch (priv->variant) {
  1280 +#ifdef CONFIG_MX6
  1281 + case IMX6Q:
  1282 + case IMX6SX:
  1283 + case IMX6QP:
  1284 + if (enable)
  1285 + imx_pcie_gpr_update_bits(priv, 48, IOMUXC_GPR12_APPS_LTSSM_ENABLE,
  1286 + IOMUXC_GPR12_APPS_LTSSM_ENABLE); /* LTSSM enable, starting link. */
  1287 + else
  1288 + imx_pcie_gpr_update_bits(priv, 48, IOMUXC_GPR12_APPS_LTSSM_ENABLE, 0);
  1289 +
  1290 + break;
  1291 +#endif
  1292 + case IMX8QXP:
  1293 + case IMX8QM:
  1294 + /* Bit4 of the CTRL2 */
  1295 + val = IMX8QM_CSR_PCIEA_OFFSET
  1296 + + priv->ctrl_id * SZ_64K;
  1297 + if (enable) {
  1298 + imx_pcie_gpr_update_bits(priv,
  1299 + val + IMX8QM_CSR_PCIE_CTRL2_OFFSET,
  1300 + IMX8QM_CTRL_LTSSM_ENABLE,
  1301 + IMX8QM_CTRL_LTSSM_ENABLE);
  1302 + } else {
  1303 + imx_pcie_gpr_update_bits(priv,
  1304 + val + IMX8QM_CSR_PCIE_CTRL2_OFFSET,
  1305 + IMX8QM_CTRL_LTSSM_ENABLE,
  1306 + 0);
  1307 + }
  1308 + break;
  1309 + default:
  1310 + break;
  1311 + }
  1312 +
  1313 +}
  1314 +
  1315 +
660 1316 static int imx_pcie_link_up(struct imx_pcie_priv *priv)
661 1317 {
662   - struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
663 1318 uint32_t tmp;
664 1319 int count = 0;
665 1320  
666   - imx6_pcie_assert_core_reset(priv, false);
667   - imx6_pcie_init_phy();
668   - imx6_pcie_deassert_core_reset();
  1321 + imx_pcie_assert_core_reset(priv, false);
  1322 + imx_pcie_init_phy(priv);
  1323 + imx_pcie_deassert_core_reset(priv);
669 1324  
  1325 + imx_pcie_setup_ctrl(priv);
670 1326 imx_pcie_regions_setup(priv);
671 1327  
672 1328 /*
... ... @@ -692,7 +1348,7 @@
692 1348 writel(tmp, priv->dbi_base + 0x7c);
693 1349  
694 1350 /* LTSSM enable, starting link. */
695   - setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE);
  1351 + imx_pcie_ltssm_enable(priv, true);
696 1352  
697 1353 while (!imx6_pcie_link_up(priv)) {
698 1354 udelay(10);
699 1355  
700 1356  
701 1357  
... ... @@ -701,17 +1357,26 @@
701 1357 print_regs(1);
702 1358 /* link down, try reset ep, and re-try link here */
703 1359 DBGF("pcie link is down, reset ep, then retry!\n");
  1360 +
  1361 +#if CONFIG_IS_ENABLED(DM_PCI)
  1362 + if (dm_gpio_is_valid(&priv->reset_gpio)) {
  1363 + dm_gpio_set_value(&priv->reset_gpio, 1);
  1364 + mdelay(20);
  1365 + dm_gpio_set_value(&priv->reset_gpio, 0);
  1366 + mdelay(20);
  1367 + }
  1368 +#elif defined(CONFIG_MX6)
704 1369 imx6_pcie_toggle_reset();
  1370 +#endif
705 1371 continue;
706 1372 }
707 1373 #ifdef DEBUG
708 1374 else if (count >= 2000) {
709 1375 print_regs(1);
710 1376 /* link is down, stop here */
711   - setenv("bootcmd", "sleep 2;");
  1377 + env_set("bootcmd", "sleep 2;");
712 1378 DBGF("pcie link is down, stop here!\n");
713   - clrbits_le32(&iomuxc_regs->gpr[12],
714   - IOMUXC_GPR12_APPS_LTSSM_ENABLE);
  1379 + imx_pcie_ltssm_enable(priv, false);
715 1380 return -EINVAL;
716 1381 }
717 1382 #endif
... ... @@ -722,8 +1387,7 @@
722 1387 debug("DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
723 1388 readl(priv->dbi_base + PCIE_PHY_DEBUG_R0),
724 1389 readl(priv->dbi_base + PCIE_PHY_DEBUG_R1));
725   - clrbits_le32(&iomuxc_regs->gpr[12],
726   - IOMUXC_GPR12_APPS_LTSSM_ENABLE);
  1390 + imx_pcie_ltssm_enable(priv, false);
727 1391 return -EINVAL;
728 1392 }
729 1393 }
730 1394  
... ... @@ -735,10 +1399,14 @@
735 1399 static struct imx_pcie_priv imx_pcie_priv = {
736 1400 .dbi_base = (void __iomem *)MX6_DBI_ADDR,
737 1401 .cfg_base = (void __iomem *)MX6_ROOT_ADDR,
  1402 + .cfg1_base = (void __iomem *)(MX6_ROOT_ADDR + MX6_ROOT_SIZE / 2),
  1403 + .cfg_size = MX6_ROOT_SIZE,
  1404 + .lanes = 1,
738 1405 };
739 1406  
740 1407 static struct imx_pcie_priv *priv = &imx_pcie_priv;
741 1408  
  1409 +
742 1410 static int imx_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
743 1411 int where, u32 *val)
744 1412 {
745 1413  
... ... @@ -768,11 +1436,18 @@
768 1436  
769 1437 memset(&pcc, 0, sizeof(pcc));
770 1438  
  1439 + if (is_mx6sx())
  1440 + priv->variant = IMX6SX;
  1441 + else if (is_mx6dqp())
  1442 + priv->variant = IMX6QP;
  1443 + else
  1444 + priv->variant = IMX6Q;
  1445 +
771 1446 hose->priv_data = priv;
772 1447  
773 1448 /* PCI I/O space */
774 1449 pci_set_region(&hose->regions[0],
775   - MX6_IO_ADDR, MX6_IO_ADDR,
  1450 + 0, MX6_IO_ADDR,
776 1451 MX6_IO_SIZE, PCI_REGION_IO);
777 1452  
778 1453 /* PCI memory space */
... ... @@ -785,6 +1460,9 @@
785 1460 MMDC0_ARB_BASE_ADDR, MMDC0_ARB_BASE_ADDR,
786 1461 0xefffffff, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
787 1462  
  1463 + priv->io = &hose->regions[0];
  1464 + priv->mem = &hose->regions[1];
  1465 +
788 1466 hose->region_count = 3;
789 1467  
790 1468 pci_set_ops(hose,
... ... @@ -822,6 +1500,12 @@
822 1500 {
823 1501 imx_pcie_init();
824 1502 }
  1503 +
  1504 +int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
  1505 +{
  1506 + return 0;
  1507 +}
  1508 +
825 1509 #else
826 1510 static int imx_pcie_dm_read_config(const struct udevice *dev, pci_dev_t bdf,
827 1511 uint offset, ulong *value,
828 1512  
... ... @@ -857,8 +1541,126 @@
857 1541  
858 1542 static int imx_pcie_dm_probe(struct udevice *dev)
859 1543 {
  1544 + int ret = 0;
860 1545 struct imx_pcie_priv *priv = dev_get_priv(dev);
861 1546  
  1547 +#if CONFIG_IS_ENABLED(DM_REGULATOR)
  1548 + ret = device_get_supply_regulator(dev, "epdev_on", &priv->epdev_on);
  1549 + if (ret) {
  1550 + priv->epdev_on = NULL;
  1551 + dev_dbg(dev, "no epdev_on\n");
  1552 + } else {
  1553 + ret = regulator_set_enable(priv->epdev_on, true);
  1554 + if (ret) {
  1555 + dev_err(dev, "fail to enable epdev_on\n");
  1556 + return ret;
  1557 + }
  1558 + }
  1559 +
  1560 + mdelay(100);
  1561 +#endif
  1562 +
  1563 + /* Enable the osc clk */
  1564 + ret = gpio_request_by_name(dev, "clkreq-gpio", 0, &priv->clkreq_gpio,
  1565 + (GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE));
  1566 + if (ret) {
  1567 + dev_info(dev, "%d unable to get clkreq.\n", ret);
  1568 + }
  1569 +
  1570 + /* enable */
  1571 + ret = gpio_request_by_name(dev, "disable-gpio", 0, &priv->dis_gpio,
  1572 + (GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE));
  1573 + if (ret) {
  1574 + dev_info(dev, "%d unable to get disable-gpio.\n", ret);
  1575 + }
  1576 +
  1577 + /* Set to power on */
  1578 + ret = gpio_request_by_name(dev, "power-on-gpio", 0, &priv->power_on_gpio,
  1579 + (GPIOD_IS_OUT |GPIOD_IS_OUT_ACTIVE));
  1580 + if (ret) {
  1581 + dev_info(dev, "%d unable to get power-on-gpio.\n", ret);
  1582 + }
  1583 +
  1584 + /* Set to reset status */
  1585 + ret = gpio_request_by_name(dev, "reset-gpio", 0, &priv->reset_gpio,
  1586 + (GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE));
  1587 + if (ret) {
  1588 + dev_info(dev, "%d unable to get power-on-gpio.\n", ret);
  1589 + }
  1590 +
  1591 +#if CONFIG_IS_ENABLED(CLK)
  1592 + ret = clk_get_by_name(dev, "pcie_phy", &priv->pcie_phy);
  1593 + if (ret) {
  1594 + printf("Failed to get pcie_phy clk\n");
  1595 + return ret;
  1596 + }
  1597 +
  1598 + ret = clk_get_by_name(dev, "pcie_bus", &priv->pcie_bus);
  1599 + if (ret) {
  1600 + printf("Failed to get pcie_bus clk\n");
  1601 + return ret;
  1602 + }
  1603 +
  1604 + ret = clk_get_by_name(dev, "pcie", &priv->pcie);
  1605 + if (ret) {
  1606 + printf("Failed to get pcie clk\n");
  1607 + return ret;
  1608 + }
  1609 +#endif
  1610 +
  1611 + if (priv->variant == IMX8QM || priv->variant == IMX8QXP) {
  1612 +#if CONFIG_IS_ENABLED(CLK)
  1613 + ret = clk_get_by_name(dev, "pcie_per", &priv->pcie_per);
  1614 + if (ret) {
  1615 + printf("Failed to get pcie_per clk\n");
  1616 + return ret;
  1617 + }
  1618 +
  1619 + ret = clk_get_by_name(dev, "pcie_inbound_axi", &priv->pcie_inbound_axi);
  1620 + if (ret) {
  1621 + printf("Failed to get pcie_inbound_axi clk\n");
  1622 + return ret;
  1623 + }
  1624 +#endif
  1625 + priv->iomuxc_gpr =
  1626 + syscon_regmap_lookup_by_phandle(dev, "hsio");
  1627 + if (IS_ERR(priv->iomuxc_gpr)) {
  1628 + dev_err(dev, "unable to find gpr registers\n");
  1629 + return PTR_ERR(priv->iomuxc_gpr);
  1630 + }
  1631 + } else {
  1632 +#if CONFIG_IS_ENABLED(DM_REGULATOR)
  1633 + if (priv->variant == IMX6QP) {
  1634 + ret = device_get_supply_regulator(dev, "pcie-bus", &priv->pcie_bus_regulator);
  1635 + if (ret) {
  1636 + dev_dbg(dev, "no pcie_bus_regulator\n");
  1637 + priv->pcie_bus_regulator = NULL;
  1638 + }
  1639 + } else if (priv->variant == IMX6SX) {
  1640 + ret = device_get_supply_regulator(dev, "pcie-phy", &priv->pcie_phy_regulator);
  1641 + if (ret) {
  1642 + dev_dbg(dev, "no pcie_phy_regulator\n");
  1643 + priv->pcie_phy_regulator = NULL;
  1644 + }
  1645 + }
  1646 +#endif
  1647 +
  1648 + priv->iomuxc_gpr =
  1649 + syscon_regmap_lookup_by_phandle(dev, "gpr");
  1650 + if (IS_ERR(priv->iomuxc_gpr)) {
  1651 + dev_err(dev, "unable to find gpr registers\n");
  1652 + return PTR_ERR(priv->iomuxc_gpr);
  1653 + }
  1654 + }
  1655 +
  1656 + pci_get_regions(dev, &priv->io, &priv->mem, &priv->pref);
  1657 +
  1658 + if (priv->cpu_base)
  1659 + priv->cpu_addr_offset = priv->cpu_base
  1660 + - priv->mem->phys_start;
  1661 + else
  1662 + priv->cpu_addr_offset = 0;
  1663 +
862 1664 return imx_pcie_link_up(priv);
863 1665 }
864 1666  
... ... @@ -866,7 +1668,7 @@
866 1668 {
867 1669 struct imx_pcie_priv *priv = dev_get_priv(dev);
868 1670  
869   - imx6_pcie_assert_core_reset(priv, true);
  1671 + imx_pcie_assert_core_reset(priv, true);
870 1672  
871 1673 return 0;
872 1674 }
873 1675  
874 1676  
... ... @@ -874,12 +1676,45 @@
874 1676 static int imx_pcie_ofdata_to_platdata(struct udevice *dev)
875 1677 {
876 1678 struct imx_pcie_priv *priv = dev_get_priv(dev);
  1679 + int ret;
  1680 + struct resource cfg_res;
877 1681  
878 1682 priv->dbi_base = (void __iomem *)devfdt_get_addr_index(dev, 0);
879   - priv->cfg_base = (void __iomem *)devfdt_get_addr_index(dev, 1);
880   - if (!priv->dbi_base || !priv->cfg_base)
  1683 + if (!priv->dbi_base)
881 1684 return -EINVAL;
882 1685  
  1686 + ret = dev_read_resource_byname(dev, "config", &cfg_res);
  1687 + if (ret) {
  1688 + printf("can't get config resource(ret = %d)\n", ret);
  1689 + return -ENOMEM;
  1690 + }
  1691 +
  1692 + priv->cfg_base = map_physmem(cfg_res.start,
  1693 + resource_size(&cfg_res),
  1694 + MAP_NOCACHE);
  1695 + priv->cfg1_base = priv->cfg_base + resource_size(&cfg_res) / 2;
  1696 + priv->cfg_size = resource_size(&cfg_res);
  1697 +
  1698 + priv->variant = (enum imx_pcie_variants)dev_get_driver_data(dev);
  1699 +
  1700 + if (dev_read_u32u(dev, "hsio-cfg", &priv->hsio_cfg))
  1701 + priv->hsio_cfg = 0;
  1702 +
  1703 + if (dev_read_u32u(dev, "ctrl-id", &priv->ctrl_id))
  1704 + priv->ctrl_id = 0;
  1705 +
  1706 + if (dev_read_u32u(dev, "ext_osc", &priv->ext_osc))
  1707 + priv->ext_osc = 0;
  1708 +
  1709 + if (dev_read_u32u(dev, "cpu-base-addr", &priv->cpu_base))
  1710 + priv->cpu_base = 0;
  1711 +
  1712 + if (dev_read_u32u(dev, "num-lanes", &priv->lanes))
  1713 + priv->lanes = 1;
  1714 +
  1715 + debug("hsio-cfg %u, ctrl-id %u, ext_osc %u, cpu-base 0x%x\n",
  1716 + priv->hsio_cfg, priv->ctrl_id, priv->ext_osc, priv->cpu_base);
  1717 +
883 1718 return 0;
884 1719 }
885 1720  
... ... @@ -889,8 +1724,11 @@
889 1724 };
890 1725  
891 1726 static const struct udevice_id imx_pcie_ids[] = {
892   - { .compatible = "fsl,imx6q-pcie" },
893   - { .compatible = "fsl,imx6sx-pcie" },
  1727 + { .compatible = "fsl,imx6q-pcie", .data = (ulong)IMX6Q, },
  1728 + { .compatible = "fsl,imx6sx-pcie", .data = (ulong)IMX6SX, },
  1729 + { .compatible = "fsl,imx6qp-pcie", .data = (ulong)IMX6QP, },
  1730 + { .compatible = "fsl,imx8qm-pcie", .data = (ulong)IMX8QM, },
  1731 + { .compatible = "fsl,imx8qxp-pcie", .data = (ulong)IMX8QXP, },
894 1732 { }
895 1733 };
896 1734