SystemACE: Remove

This driver is no longer used on any supported platform in U-Boot and there is no interest in maintaining it further from people that have used it historically. Cc: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> c: Alexey Brodkin <alexey.brodkin@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Michal Simek <michal.simek@xilinx.com>

SystemACE: Remove
This driver is no longer used on any supported platform in U-Boot and there is no interest in maintaining it further from people that have used it historically. Cc: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> c: Alexey Brodkin <alexey.brodkin@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
Tom Rini
1 parent fbca0e66cc
Showing 7 changed files with 0 additions and 333 deletions Side-by-side Diff
arch/sandbox/include/asm/io.h
configs/sandbox_defconfig
drivers/block/Kconfig
drivers/block/Makefile
drivers/block/blk-uclass.c
drivers/block/systemace.c
include/blk.h
@@ -171,10 +171,6 @@
 #define insw(port, buf, ns)		_insw((u16 *)port, buf, ns)
 #define outsw(port, buf, ns)		_outsw((u16 *)port, buf, ns)
  
-/* For systemace.c */
-#define out16(addr, val)
-#define in16(addr)		0
-
 #include <iotrace.h>
 #include <asm/types.h>
  
@@ -81,9 +81,6 @@
 CONFIG_DEBUG_DEVRES=y
 CONFIG_ADC=y
 CONFIG_ADC_SANDBOX=y
-CONFIG_SYSTEMACE=y
-CONFIG_SYS_SYSTEMACE_BASE=0x0
-CONFIG_SYS_SYSTEMACE_WIDTH=16
 CONFIG_CLK=y
 CONFIG_CPU=y
 CONFIG_DM_DEMO=y
@@ -44,23 +44,4 @@
 	  This allows access to raw blocks and filesystems on an IDE drive
 	  from U-Boot. See also CMD_IDE which provides an 'ide' command for
 	  performing various IDE operations.
-
-config SYSTEMACE
-	bool "Xilinx SystemACE support"
-	select HAVE_BLOCK_DEVICE
-	help
-	  Adding this option adds support for Xilinx SystemACE chips attached
-	  via some sort of local bus. The address of the chip must also be
-	  defined in the CONFIG_SYS_SYSTEMACE_BASE macro.
-
-	  When SystemACE support is added, the "ace" device type becomes
-	  available to the fat commands, i.e. fatls.
-
-config SYS_SYSTEMACE_BASE
-	hex "Base address of SystemACE chip"
-	depends on SYSTEMACE
-
-config SYS_SYSTEMACE_WIDTH
-	int "Word size of access to the of SystemACE chip"
-	depends on SYSTEMACE
@@ -13,6 +13,5 @@
  
 obj-$(CONFIG_IDE) += ide.o
 obj-$(CONFIG_SANDBOX) += sandbox.o
-obj-$(CONFIG_SYSTEMACE) += systemace.o
 obj-$(CONFIG_BLOCK_CACHE) += blkcache.o
@@ -22,7 +22,6 @@
 	[IF_TYPE_SD]		= "sd",
 	[IF_TYPE_SATA]		= "sata",
 	[IF_TYPE_HOST]		= "host",
-	[IF_TYPE_SYSTEMACE]	= "ace",
 	[IF_TYPE_NVME]		= "nvme",
 	[IF_TYPE_EFI]		= "efi",
 };
@@ -37,7 +36,6 @@
 	[IF_TYPE_SD]		= UCLASS_INVALID,
 	[IF_TYPE_SATA]		= UCLASS_AHCI,
 	[IF_TYPE_HOST]		= UCLASS_ROOT,
-	[IF_TYPE_SYSTEMACE]	= UCLASS_INVALID,
 	[IF_TYPE_NVME]		= UCLASS_NVME,
 	[IF_TYPE_EFI]		= UCLASS_EFI,
 };
-/*
- * Copyright (c) 2004 Picture Elements, Inc.
- *    Stephen Williams (XXXXXXXXXXXXXXXX)
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * The Xilinx SystemACE chip support is activated by defining
- * CONFIG_SYSTEMACE to turn on support, and CONFIG_SYS_SYSTEMACE_BASE
- * to set the base address of the device. This code currently
- * assumes that the chip is connected via a byte-wide bus.
- *
- * The CONFIG_SYSTEMACE also adds to fat support the device class
- * "ace" that allows the user to execute "fatls ace 0" and the
- * like. This works by making the systemace_get_dev function
- * available to cmd_fat.c:get_dev and filling in a block device
- * description that has all the bits needed for FAT support to
- * read sectors.
- *
- * According to Xilinx technical support, before accessing the
- * SystemACE CF you need to set the following control bits:
- *      FORCECFGMODE : 1
- *      CFGMODE : 0
- *      CFGSTART : 0
- */
-
-#include <common.h>
-#include <command.h>
-#include <dm.h>
-#include <part.h>
-#include <asm/io.h>
-
-/*
- * The ace_readw and writew functions read/write 16bit words, but the
- * offset value is the BYTE offset as most used in the Xilinx
- * datasheet for the SystemACE chip. The CONFIG_SYS_SYSTEMACE_BASE is defined
- * to be the base address for the chip, usually in the local
- * peripheral bus.
- */
-
-static u32 base = CONFIG_SYS_SYSTEMACE_BASE;
-static u32 width = CONFIG_SYS_SYSTEMACE_WIDTH;
-
-static void ace_writew(u16 val, unsigned off)
-{
-	if (width == 8) {
-#if !defined(__BIG_ENDIAN)
-		writeb(val >> 8, base + off);
-		writeb(val, base + off + 1);
-#else
-		writeb(val, base + off);
-		writeb(val >> 8, base + off + 1);
-#endif
-	} else
-		out16(base + off, val);
-}
-
-static u16 ace_readw(unsigned off)
-{
-	if (width == 8) {
-#if !defined(__BIG_ENDIAN)
-		return (readb(base + off) << 8) | readb(base + off + 1);
-#else
-		return readb(base + off) | (readb(base + off + 1) << 8);
-#endif
-	}
-
-	return in16(base + off);
-}
-
-#ifndef CONFIG_BLK
-static struct blk_desc systemace_dev = { 0 };
-#endif
-
-static int get_cf_lock(void)
-{
-	int retry = 10;
-
-	/* CONTROLREG = LOCKREG */
-	unsigned val = ace_readw(0x18);
-	val |= 0x0002;
-	ace_writew((val & 0xffff), 0x18);
-
-	/* Wait for MPULOCK in STATUSREG[15:0] */
-	while (!(ace_readw(0x04) & 0x0002)) {
-
-		if (retry < 0)
-			return -1;
-
-		udelay(100000);
-		retry -= 1;
-	}
-
-	return 0;
-}
-
-static void release_cf_lock(void)
-{
-	unsigned val = ace_readw(0x18);
-	val &= ~(0x0002);
-	ace_writew((val & 0xffff), 0x18);
-}
-
-/*
- * This function is called (by dereferencing the block_read pointer in
- * the dev_desc) to read blocks of data. The return value is the
- * number of blocks read. A zero return indicates an error.
- */
-#ifdef CONFIG_BLK
-static unsigned long systemace_read(struct udevice *dev, unsigned long start,
-				    lbaint_t blkcnt, void *buffer)
-#else
-static unsigned long systemace_read(struct blk_desc *block_dev,
-				    unsigned long start, lbaint_t blkcnt,
-				    void *buffer)
-#endif
-{
-	int retry;
-	unsigned blk_countdown;
-	unsigned char *dp = buffer;
-	unsigned val;
-
-	if (get_cf_lock() < 0) {
-		unsigned status = ace_readw(0x04);
-
-		/* If CFDETECT is false, card is missing. */
-		if (!(status & 0x0010)) {
-			printf("** CompactFlash card not present. **\n");
-			return 0;
-		}
-
-		printf("**** ACE locked away from me (STATUSREG=%04x)\n",
-		       status);
-		return 0;
-	}
-#ifdef DEBUG_SYSTEMACE
-	printf("... systemace read %lu sectors at %lu\n", blkcnt, start);
-#endif
-
-	retry = 2000;
-	for (;;) {
-		val = ace_readw(0x04);
-
-		/* If CFDETECT is false, card is missing. */
-		if (!(val & 0x0010)) {
-			printf("**** ACE CompactFlash not found.\n");
-			release_cf_lock();
-			return 0;
-		}
-
-		/* If RDYFORCMD, then we are ready to go. */
-		if (val & 0x0100)
-			break;
-
-		if (retry < 0) {
-			printf("**** SystemACE not ready.\n");
-			release_cf_lock();
-			return 0;
-		}
-
-		udelay(1000);
-		retry -= 1;
-	}
-
-	/* The SystemACE can only transfer 256 sectors at a time, so
-	   limit the current chunk of sectors. The blk_countdown
-	   variable is the number of sectors left to transfer. */
-
-	blk_countdown = blkcnt;
-	while (blk_countdown > 0) {
-		unsigned trans = blk_countdown;
-
-		if (trans > 256)
-			trans = 256;
-
-#ifdef DEBUG_SYSTEMACE
-		printf("... transfer %lu sector in a chunk\n", trans);
-#endif
-		/* Write LBA block address */
-		ace_writew((start >> 0) & 0xffff, 0x10);
-		ace_writew((start >> 16) & 0x0fff, 0x12);
-
-		/* NOTE: in the Write Sector count below, a count of 0
-		   causes a transfer of 256, so &0xff gives the right
-		   value for whatever transfer count we want. */
-
-		/* Write sector count | ReadMemCardData. */
-		ace_writew((trans & 0xff) | 0x0300, 0x14);
-
-/*
- * For FPGA configuration via SystemACE is reset unacceptable
- * CFGDONE bit in STATUSREG is not set to 1.
- */
-#ifndef SYSTEMACE_CONFIG_FPGA
-		/* Reset the configruation controller */
-		val = ace_readw(0x18);
-		val |= 0x0080;
-		ace_writew(val, 0x18);
-#endif
-
-		retry = trans * 16;
-		while (retry > 0) {
-			int idx;
-
-			/* Wait for buffer to become ready. */
-			while (!(ace_readw(0x04) & 0x0020)) {
-				udelay(100);
-			}
-
-			/* Read 16 words of 2bytes from the sector buffer. */
-			for (idx = 0; idx < 16; idx += 1) {
-				unsigned short val = ace_readw(0x40);
-				*dp++ = val & 0xff;
-				*dp++ = (val >> 8) & 0xff;
-			}
-
-			retry -= 1;
-		}
-
-		/* Clear the configruation controller reset */
-		val = ace_readw(0x18);
-		val &= ~0x0080;
-		ace_writew(val, 0x18);
-
-		/* Count the blocks we transfer this time. */
-		start += trans;
-		blk_countdown -= trans;
-	}
-
-	release_cf_lock();
-
-	return blkcnt;
-}
-
-#ifdef CONFIG_BLK
-static int systemace_bind(struct udevice *dev)
-{
-	struct blk_desc *bdesc;
-	struct udevice *bdev;
-	int ret;
-
-	ret = blk_create_devicef(dev, "systemace_blk", "blk", IF_TYPE_SYSTEMACE,
-				 -1, 512, 0, &bdev);
-	if (ret) {
-		debug("Cannot create block device\n");
-		return ret;
-	}
-	bdesc = dev_get_uclass_platdata(bdev);
-	bdesc->removable = 1;
-	bdesc->part_type = PART_TYPE_UNKNOWN;
-	bdesc->log2blksz = LOG2(bdesc->blksz);
-
-	/* Ensure the correct bus mode (8/16 bits) gets enabled */
-	ace_writew(width == 8 ? 0 : 0x0001, 0);
-
-	return 0;
-}
-
-static const struct blk_ops systemace_blk_ops = {
-	.read	= systemace_read,
-};
-
-U_BOOT_DRIVER(systemace_blk) = {
-	.name		= "systemace_blk",
-	.id		= UCLASS_BLK,
-	.ops		= &systemace_blk_ops,
-	.bind		= systemace_bind,
-};
-#else
-static int systemace_get_dev(int dev, struct blk_desc **descp)
-{
-	/* The first time through this, the systemace_dev object is
-	   not yet initialized. In that case, fill it in. */
-	if (systemace_dev.blksz == 0) {
-		systemace_dev.if_type = IF_TYPE_UNKNOWN;
-		systemace_dev.devnum = 0;
-		systemace_dev.part_type = PART_TYPE_UNKNOWN;
-		systemace_dev.type = DEV_TYPE_HARDDISK;
-		systemace_dev.blksz = 512;
-		systemace_dev.log2blksz = LOG2(systemace_dev.blksz);
-		systemace_dev.removable = 1;
-		systemace_dev.block_read = systemace_read;
-
-		/*
-		 * Ensure the correct bus mode (8/16 bits) gets enabled
-		 */
-		ace_writew(width == 8 ? 0 : 0x0001, 0);
-
-		part_init(&systemace_dev);
-	}
-	*descp = &systemace_dev;
-
-	return 0;
-}
-
-U_BOOT_LEGACY_BLK(systemace) = {
-	.if_typename	= "ace",
-	.if_type	= IF_TYPE_SYSTEMACE,
-	.max_devs	= 1,
-	.get_dev	= systemace_get_dev,
-};
-#endif
@@ -32,7 +32,6 @@
 	IF_TYPE_SD,
 	IF_TYPE_SATA,
 	IF_TYPE_HOST,
-	IF_TYPE_SYSTEMACE,
 	IF_TYPE_NVME,
 	IF_TYPE_EFI,
...	...	@@ -171,10 +171,6 @@
171	171	#define insw(port, buf, ns) _insw((u16 *)port, buf, ns)
172	172	#define outsw(port, buf, ns) _outsw((u16 *)port, buf, ns)
173	173
174		-/* For systemace.c */
175		-#define out16(addr, val)
176		-#define in16(addr) 0
177		-
178	174	#include <iotrace.h>
179	175	#include <asm/types.h>
180	176
...	...	@@ -81,9 +81,6 @@
81	81	CONFIG_DEBUG_DEVRES=y
82	82	CONFIG_ADC=y
83	83	CONFIG_ADC_SANDBOX=y
84		-CONFIG_SYSTEMACE=y
85		-CONFIG_SYS_SYSTEMACE_BASE=0x0
86		-CONFIG_SYS_SYSTEMACE_WIDTH=16
87	84	CONFIG_CLK=y
88	85	CONFIG_CPU=y
89	86	CONFIG_DM_DEMO=y
...	...	@@ -44,23 +44,4 @@
44	44	This allows access to raw blocks and filesystems on an IDE drive
45	45	from U-Boot. See also CMD_IDE which provides an 'ide' command for
46	46	performing various IDE operations.
47		-
48		-config SYSTEMACE
49		- bool "Xilinx SystemACE support"
50		- select HAVE_BLOCK_DEVICE
51		- help
52		- Adding this option adds support for Xilinx SystemACE chips attached
53		- via some sort of local bus. The address of the chip must also be
54		- defined in the CONFIG_SYS_SYSTEMACE_BASE macro.
55		-
56		- When SystemACE support is added, the "ace" device type becomes
57		- available to the fat commands, i.e. fatls.
58		-
59		-config SYS_SYSTEMACE_BASE
60		- hex "Base address of SystemACE chip"
61		- depends on SYSTEMACE
62		-
63		-config SYS_SYSTEMACE_WIDTH
64		- int "Word size of access to the of SystemACE chip"
65		- depends on SYSTEMACE
...	...	@@ -13,6 +13,5 @@
13	13
14	14	obj-$(CONFIG_IDE) += ide.o
15	15	obj-$(CONFIG_SANDBOX) += sandbox.o
16		-obj-$(CONFIG_SYSTEMACE) += systemace.o
17	16	obj-$(CONFIG_BLOCK_CACHE) += blkcache.o
...	...	@@ -22,7 +22,6 @@
22	22	[IF_TYPE_SD] = "sd",
23	23	[IF_TYPE_SATA] = "sata",
24	24	[IF_TYPE_HOST] = "host",
25		- [IF_TYPE_SYSTEMACE] = "ace",
26	25	[IF_TYPE_NVME] = "nvme",
27	26	[IF_TYPE_EFI] = "efi",
28	27	};
...	...	@@ -37,7 +36,6 @@
37	36	[IF_TYPE_SD] = UCLASS_INVALID,
38	37	[IF_TYPE_SATA] = UCLASS_AHCI,
39	38	[IF_TYPE_HOST] = UCLASS_ROOT,
40		- [IF_TYPE_SYSTEMACE] = UCLASS_INVALID,
41	39	[IF_TYPE_NVME] = UCLASS_NVME,
42	40	[IF_TYPE_EFI] = UCLASS_EFI,
43	41	};
1		-/*
2		- * Copyright (c) 2004 Picture Elements, Inc.
3		- * Stephen Williams (XXXXXXXXXXXXXXXX)
4		- *
5		- * SPDX-License-Identifier: GPL-2.0+
6		- */
7		-
8		-/*
9		- * The Xilinx SystemACE chip support is activated by defining
10		- * CONFIG_SYSTEMACE to turn on support, and CONFIG_SYS_SYSTEMACE_BASE
11		- * to set the base address of the device. This code currently
12		- * assumes that the chip is connected via a byte-wide bus.
13		- *
14		- * The CONFIG_SYSTEMACE also adds to fat support the device class
15		- * "ace" that allows the user to execute "fatls ace 0" and the
16		- * like. This works by making the systemace_get_dev function
17		- * available to cmd_fat.c:get_dev and filling in a block device
18		- * description that has all the bits needed for FAT support to
19		- * read sectors.
20		- *
21		- * According to Xilinx technical support, before accessing the
22		- * SystemACE CF you need to set the following control bits:
23		- * FORCECFGMODE : 1
24		- * CFGMODE : 0
25		- * CFGSTART : 0
26		- */
27		-
28		-#include <common.h>
29		-#include <command.h>
30		-#include <dm.h>
31		-#include <part.h>
32		-#include <asm/io.h>
33		-
34		-/*
35		- * The ace_readw and writew functions read/write 16bit words, but the
36		- * offset value is the BYTE offset as most used in the Xilinx
37		- * datasheet for the SystemACE chip. The CONFIG_SYS_SYSTEMACE_BASE is defined
38		- * to be the base address for the chip, usually in the local
39		- * peripheral bus.
40		- */
41		-
42		-static u32 base = CONFIG_SYS_SYSTEMACE_BASE;
43		-static u32 width = CONFIG_SYS_SYSTEMACE_WIDTH;
44		-
45		-static void ace_writew(u16 val, unsigned off)
46		-{
47		- if (width == 8) {
48		-#if !defined(__BIG_ENDIAN)
49		- writeb(val >> 8, base + off);
50		- writeb(val, base + off + 1);
51		-#else
52		- writeb(val, base + off);
53		- writeb(val >> 8, base + off + 1);
54		-#endif
55		- } else
56		- out16(base + off, val);
57		-}
58		-
59		-static u16 ace_readw(unsigned off)
60		-{
61		- if (width == 8) {
62		-#if !defined(__BIG_ENDIAN)
63		- return (readb(base + off) << 8) \| readb(base + off + 1);
64		-#else
65		- return readb(base + off) \| (readb(base + off + 1) << 8);
66		-#endif
67		- }
68		-
69		- return in16(base + off);
70		-}
71		-
72		-#ifndef CONFIG_BLK
73		-static struct blk_desc systemace_dev = { 0 };
74		-#endif
75		-
76		-static int get_cf_lock(void)
77		-{
78		- int retry = 10;
79		-
80		- /* CONTROLREG = LOCKREG */
81		- unsigned val = ace_readw(0x18);
82		- val \|= 0x0002;
83		- ace_writew((val & 0xffff), 0x18);
84		-
85		- /* Wait for MPULOCK in STATUSREG[15:0] */
86		- while (!(ace_readw(0x04) & 0x0002)) {
87		-
88		- if (retry < 0)
89		- return -1;
90		-
91		- udelay(100000);
92		- retry -= 1;
93		- }
94		-
95		- return 0;
96		-}
97		-
98		-static void release_cf_lock(void)
99		-{
100		- unsigned val = ace_readw(0x18);
101		- val &= ~(0x0002);
102		- ace_writew((val & 0xffff), 0x18);
103		-}
104		-
105		-/*
106		- * This function is called (by dereferencing the block_read pointer in
107		- * the dev_desc) to read blocks of data. The return value is the
108		- * number of blocks read. A zero return indicates an error.
109		- */
110		-#ifdef CONFIG_BLK
111		-static unsigned long systemace_read(struct udevice *dev, unsigned long start,
112		- lbaint_t blkcnt, void *buffer)
113		-#else
114		-static unsigned long systemace_read(struct blk_desc *block_dev,
115		- unsigned long start, lbaint_t blkcnt,
116		- void *buffer)
117		-#endif
118		-{
119		- int retry;
120		- unsigned blk_countdown;
121		- unsigned char *dp = buffer;
122		- unsigned val;
123		-
124		- if (get_cf_lock() < 0) {
125		- unsigned status = ace_readw(0x04);
126		-
127		- /* If CFDETECT is false, card is missing. */
128		- if (!(status & 0x0010)) {
129		- printf(" CompactFlash card not present. \n");
130		- return 0;
131		- }
132		-
133		- printf("**** ACE locked away from me (STATUSREG=%04x)\n",
134		- status);
135		- return 0;
136		- }
137		-#ifdef DEBUG_SYSTEMACE
138		- printf("... systemace read %lu sectors at %lu\n", blkcnt, start);
139		-#endif
140		-
141		- retry = 2000;
142		- for (;;) {
143		- val = ace_readw(0x04);
144		-
145		- /* If CFDETECT is false, card is missing. */
146		- if (!(val & 0x0010)) {
147		- printf("**** ACE CompactFlash not found.\n");
148		- release_cf_lock();
149		- return 0;
150		- }
151		-
152		- /* If RDYFORCMD, then we are ready to go. */
153		- if (val & 0x0100)
154		- break;
155		-
156		- if (retry < 0) {
157		- printf("**** SystemACE not ready.\n");
158		- release_cf_lock();
159		- return 0;
160		- }
161		-
162		- udelay(1000);
163		- retry -= 1;
164		- }
165		-
166		- /* The SystemACE can only transfer 256 sectors at a time, so
167		- limit the current chunk of sectors. The blk_countdown
168		- variable is the number of sectors left to transfer. */
169		-
170		- blk_countdown = blkcnt;
171		- while (blk_countdown > 0) {
172		- unsigned trans = blk_countdown;
173		-
174		- if (trans > 256)
175		- trans = 256;
176		-
177		-#ifdef DEBUG_SYSTEMACE
178		- printf("... transfer %lu sector in a chunk\n", trans);
179		-#endif
180		- /* Write LBA block address */
181		- ace_writew((start >> 0) & 0xffff, 0x10);
182		- ace_writew((start >> 16) & 0x0fff, 0x12);
183		-
184		- /* NOTE: in the Write Sector count below, a count of 0
185		- causes a transfer of 256, so &0xff gives the right
186		- value for whatever transfer count we want. */
187		-
188		- /* Write sector count \| ReadMemCardData. */
189		- ace_writew((trans & 0xff) \| 0x0300, 0x14);
190		-
191		-/*
192		- * For FPGA configuration via SystemACE is reset unacceptable
193		- * CFGDONE bit in STATUSREG is not set to 1.
194		- */
195		-#ifndef SYSTEMACE_CONFIG_FPGA
196		- /* Reset the configruation controller */
197		- val = ace_readw(0x18);
198		- val \|= 0x0080;
199		- ace_writew(val, 0x18);
200		-#endif
201		-
202		- retry = trans * 16;
203		- while (retry > 0) {
204		- int idx;
205		-
206		- /* Wait for buffer to become ready. */
207		- while (!(ace_readw(0x04) & 0x0020)) {
208		- udelay(100);
209		- }
210		-
211		- /* Read 16 words of 2bytes from the sector buffer. */
212		- for (idx = 0; idx < 16; idx += 1) {
213		- unsigned short val = ace_readw(0x40);
214		- *dp++ = val & 0xff;
215		- *dp++ = (val >> 8) & 0xff;
216		- }
217		-
218		- retry -= 1;
219		- }
220		-
221		- /* Clear the configruation controller reset */
222		- val = ace_readw(0x18);
223		- val &= ~0x0080;
224		- ace_writew(val, 0x18);
225		-
226		- /* Count the blocks we transfer this time. */
227		- start += trans;
228		- blk_countdown -= trans;
229		- }
230		-
231		- release_cf_lock();
232		-
233		- return blkcnt;
234		-}
235		-
236		-#ifdef CONFIG_BLK
237		-static int systemace_bind(struct udevice *dev)
238		-{
239		- struct blk_desc *bdesc;
240		- struct udevice *bdev;
241		- int ret;
242		-
243		- ret = blk_create_devicef(dev, "systemace_blk", "blk", IF_TYPE_SYSTEMACE,
244		- -1, 512, 0, &bdev);
245		- if (ret) {
246		- debug("Cannot create block device\n");
247		- return ret;
248		- }
249		- bdesc = dev_get_uclass_platdata(bdev);
250		- bdesc->removable = 1;
251		- bdesc->part_type = PART_TYPE_UNKNOWN;
252		- bdesc->log2blksz = LOG2(bdesc->blksz);
253		-
254		- /* Ensure the correct bus mode (8/16 bits) gets enabled */
255		- ace_writew(width == 8 ? 0 : 0x0001, 0);
256		-
257		- return 0;
258		-}
259		-
260		-static const struct blk_ops systemace_blk_ops = {
261		- .read = systemace_read,
262		-};
263		-
264		-U_BOOT_DRIVER(systemace_blk) = {
265		- .name = "systemace_blk",
266		- .id = UCLASS_BLK,
267		- .ops = &systemace_blk_ops,
268		- .bind = systemace_bind,
269		-};
270		-#else
271		-static int systemace_get_dev(int dev, struct blk_desc **descp)
272		-{
273		- /* The first time through this, the systemace_dev object is
274		- not yet initialized. In that case, fill it in. */
275		- if (systemace_dev.blksz == 0) {
276		- systemace_dev.if_type = IF_TYPE_UNKNOWN;
277		- systemace_dev.devnum = 0;
278		- systemace_dev.part_type = PART_TYPE_UNKNOWN;
279		- systemace_dev.type = DEV_TYPE_HARDDISK;
280		- systemace_dev.blksz = 512;
281		- systemace_dev.log2blksz = LOG2(systemace_dev.blksz);
282		- systemace_dev.removable = 1;
283		- systemace_dev.block_read = systemace_read;
284		-
285		- /*
286		- * Ensure the correct bus mode (8/16 bits) gets enabled
287		- */
288		- ace_writew(width == 8 ? 0 : 0x0001, 0);
289		-
290		- part_init(&systemace_dev);
291		- }
292		- *descp = &systemace_dev;
293		-
294		- return 0;
295		-}
296		-
297		-U_BOOT_LEGACY_BLK(systemace) = {
298		- .if_typename = "ace",
299		- .if_type = IF_TYPE_SYSTEMACE,
300		- .max_devs = 1,
301		- .get_dev = systemace_get_dev,
302		-};
303		-#endif
...	...	@@ -32,7 +32,6 @@
32	32	IF_TYPE_SD,
33	33	IF_TYPE_SATA,
34	34	IF_TYPE_HOST,
35		- IF_TYPE_SYSTEMACE,
36	35	IF_TYPE_NVME,
37	36	IF_TYPE_EFI,
38	37