Commit 34c3c0e01dbf1f8cc2bd08de92f2b89ba84921eb

Authored by Matthew McClintock
Committed by Jon Loeliger
1 parent b6c5e1373b
Exists in master and in 55 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

* Switched default PCI speed for 8540 ADS back to 33MHz

* Added comments and a printf to warn that PCI-X won't
  work at 33MHz
  Patch by Andy Fleming 17-Mar-2006

Signed-off-by: Andy Fleming <afleming@freescale.com>

Showing 3 changed files with 11 additions and 1 deletions Side-by-side Diff

... ... @@ -72,6 +72,9 @@
72 72  
73 73 if (!(gur->pordevsr & PORDEVSR_PCI)) {
74 74 /* PCI-X init */
  75 + if (CONFIG_SYS_CLK_FREQ < 66000000)
  76 + printf("PCI-X will only work at 66 MHz\n");
  77 +
75 78 reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
76 79 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
77 80 pci_hose_write_config_word(hose, dev, PCIX_COMMAND, reg16);
doc/README.mpc85xxads
... ... @@ -100,6 +100,9 @@
100 100 SW7[1:4] = 0101 = 5 => 5 x 66 = 330 CCB Sysclk
101 101 SW7[5:6] = 01 => 5:2 x 330 = 825 Core clock
102 102  
  103 + In order to use PCI-X (only in the first PCI slot. The one with
  104 + the RIO connector), you need to set SW1[4] (config) to 1 (off).
  105 + Also, configure the board to run PCI at 66 MHz.
103 106  
104 107 2. MEMORY MAP TO WORK WITH LINUX KERNEL
105 108  
include/configs/MPC8540ADS.h
... ... @@ -68,10 +68,14 @@
68 68 * The board, however, can run at 66MHz. In any event, this value
69 69 * must match the settings of some switches. Details can be found
70 70 * in the README.mpc85xxads.
  71 + *
  72 + * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to
  73 + * 33MHz to accommodate, based on a PCI pin.
  74 + * Note that PCI-X won't work at 33MHz.
71 75 */
72 76  
73 77 #ifndef CONFIG_SYS_CLK_FREQ
74   -#define CONFIG_SYS_CLK_FREQ 66000000
  78 +#define CONFIG_SYS_CLK_FREQ 33000000
75 79 #endif
76 80  
77 81