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Commit 350b50eea31ac740e71f5d59b9a6a04b316c6d8d

Authored by Stefan Roese
Committed by Luka Perkov
1 parent ace97d2617
Exists in v2017.01-smarct4x and in 34 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

arm: armada-xp: Move SoC sources to mach-mvebu 

Move arch/arm/cpu/armv7armada-xp/* -> arch/arm/mach-mvebu/*

Since this platform will be extended to support other Marvell SoC's as
well, lets rename it directly to mvebu.

This will be used by the upcoming Armada 38x suport (A38x).

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Tested-by: Dirk Eibach <dirk.eibach@gdsys.cc>

Showing 10 changed files with 302 additions and 302 deletions Side-by-side Diff

... ... @@ -48,6 +48,7 @@
48 48 machine-$(CONFIG_ARCH_KEYSTONE) += keystone
49 49 # TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD
50 50 machine-$(CONFIG_KIRKWOOD) += kirkwood
  51 +machine-$(CONFIG_ARMADA_XP) += mvebu
51 52 # TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA
52 53 machine-$(CONFIG_ARCH_NOMADIK) += nomadik
53 54 # TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
arch/arm/cpu/armv7/Makefile
Diff comments   View file @ 350b50e
... ... @@ -38,7 +38,6 @@
38 38 endif
39 39  
40 40 obj-$(if $(filter am33xx,$(SOC)),y) += am33xx/
41   -obj-$(if $(filter armada-xp,$(SOC)),y) += armada-xp/
42 41 obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/
43 42 obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/
44 43 obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/
arch/arm/cpu/armv7/armada-xp/Makefile
View file @ 350b50e
1   -#
2   -# Copyright (C) 2014 Stefan Roese <sr@denx.de>
3   -#
4   -# SPDX-License-Identifier: GPL-2.0+
5   -#
6   -
7   -obj-y = cpu.o
8   -obj-$(CONFIG_SPL_BUILD) += spl.o
9   -obj-$(CONFIG_SPL_BUILD) += lowlevel_spl.o
arch/arm/cpu/armv7/armada-xp/cpu.c
View file @ 350b50e
1   -/*
2   - * Copyright (C) 2014 Stefan Roese <sr@denx.de>
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - */
6   -
7   -#include <common.h>
8   -#include <netdev.h>
9   -#include <asm/io.h>
10   -#include <asm/arch/cpu.h>
11   -#include <asm/arch/soc.h>
12   -
13   -#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
14   -#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
15   -
16   -static struct mbus_win windows[] = {
17   - /* PCIE MEM address space */
18   - { DEFADR_PCI_MEM, 256 << 20, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_MEM },
19   -
20   - /* PCIE IO address space */
21   - { DEFADR_PCI_IO, 64 << 10, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_IO },
22   -
23   - /* SPI */
24   - { DEFADR_SPIF, 8 << 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI,
25   - CPU_ATTR_SPIFLASH },
26   -
27   - /* NOR */
28   - { DEFADR_BOOTROM, 8 << 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI,
29   - CPU_ATTR_BOOTROM },
30   -};
31   -
32   -void reset_cpu(unsigned long ignored)
33   -{
34   - struct mvebu_system_registers *reg =
35   - (struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE;
36   -
37   - writel(readl(&reg->rstoutn_mask) | 1, &reg->rstoutn_mask);
38   - writel(readl(&reg->sys_soft_rst) | 1, &reg->sys_soft_rst);
39   - while (1)
40   - ;
41   -}
42   -
43   -#if defined(CONFIG_DISPLAY_CPUINFO)
44   -int print_cpuinfo(void)
45   -{
46   - u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
47   - u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff;
48   -
49   - puts("SoC: ");
50   -
51   - switch (devid) {
52   - case SOC_MV78460_ID:
53   - puts("MV78460-");
54   - break;
55   - default:
56   - puts("Unknown-");
57   - break;
58   - }
59   -
60   - switch (revid) {
61   - case 1:
62   - puts("A0\n");
63   - break;
64   - case 2:
65   - puts("B0\n");
66   - break;
67   - default:
68   - puts("??\n");
69   - break;
70   - }
71   -
72   - return 0;
73   -}
74   -#endif /* CONFIG_DISPLAY_CPUINFO */
75   -
76   -/*
77   - * This function initialize Controller DRAM Fastpath windows.
78   - * It takes the CS size information from the 0x1500 scratch registers
79   - * and sets the correct windows sizes and base addresses accordingly.
80   - *
81   - * These values are set in the scratch registers by the Marvell
82   - * DDR3 training code, which is executed by the BootROM before the
83   - * main payload (U-Boot) is executed. This training code is currently
84   - * only available in the Marvell U-Boot version. It needs to be
85   - * ported to mainline U-Boot SPL at some point.
86   - */
87   -static void update_sdram_window_sizes(void)
88   -{
89   - u64 base = 0;
90   - u32 size, temp;
91   - int i;
92   -
93   - for (i = 0; i < SDRAM_MAX_CS; i++) {
94   - size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) & SDRAM_ADDR_MASK;
95   - if (size != 0) {
96   - size |= ~(SDRAM_ADDR_MASK);
97   -
98   - /* Set Base Address */
99   - temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF);
100   - writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i));
101   -
102   - /*
103   - * Check if out of max window size and resize
104   - * the window
105   - */
106   - temp = (readl(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)) &
107   - ~(SDRAM_ADDR_MASK)) | 1;
108   - temp |= (size & SDRAM_ADDR_MASK);
109   - writel(temp, MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i));
110   -
111   - base += ((u64)size + 1);
112   - } else {
113   - /*
114   - * Disable window if not used, otherwise this
115   - * leads to overlapping enabled windows with
116   - * pretty strange results
117   - */
118   - clrbits_le32(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i), 1);
119   - }
120   - }
121   -}
122   -
123   -#ifdef CONFIG_ARCH_CPU_INIT
124   -int arch_cpu_init(void)
125   -{
126   - /* Linux expects the internal registers to be at 0xf1000000 */
127   - writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
128   -
129   - /*
130   - * We need to call mvebu_mbus_probe() before calling
131   - * update_sdram_window_sizes() as it disables all previously
132   - * configured mbus windows and then configures them as
133   - * required for U-Boot. Calling update_sdram_window_sizes()
134   - * without this configuration will not work, as the internal
135   - * registers can't be accessed reliably because of potenial
136   - * double mapping.
137   - * After updating the SDRAM access windows we need to call
138   - * mvebu_mbus_probe() again, as this now correctly configures
139   - * the SDRAM areas that are later used by the MVEBU drivers
140   - * (e.g. USB, NETA).
141   - */
142   -
143   - /*
144   - * First disable all windows
145   - */
146   - mvebu_mbus_probe(NULL, 0);
147   -
148   - /*
149   - * Now the SDRAM access windows can be reconfigured using
150   - * the information in the SDRAM scratch pad registers
151   - */
152   - update_sdram_window_sizes();
153   -
154   - /*
155   - * Finally the mbus windows can be configured with the
156   - * updated SDRAM sizes
157   - */
158   - mvebu_mbus_probe(windows, ARRAY_SIZE(windows));
159   -
160   - return 0;
161   -}
162   -#endif /* CONFIG_ARCH_CPU_INIT */
163   -
164   -/*
165   - * SOC specific misc init
166   - */
167   -#if defined(CONFIG_ARCH_MISC_INIT)
168   -int arch_misc_init(void)
169   -{
170   - /* Nothing yet, perhaps we need something here later */
171   - return 0;
172   -}
173   -#endif /* CONFIG_ARCH_MISC_INIT */
174   -
175   -#ifdef CONFIG_MVNETA
176   -int cpu_eth_init(bd_t *bis)
177   -{
178   - mvneta_initialize(bis, MVEBU_EGIGA0_BASE, 0, CONFIG_PHY_BASE_ADDR + 0);
179   - mvneta_initialize(bis, MVEBU_EGIGA1_BASE, 1, CONFIG_PHY_BASE_ADDR + 1);
180   - mvneta_initialize(bis, MVEBU_EGIGA2_BASE, 2, CONFIG_PHY_BASE_ADDR + 2);
181   - mvneta_initialize(bis, MVEBU_EGIGA3_BASE, 3, CONFIG_PHY_BASE_ADDR + 3);
182   -
183   - return 0;
184   -}
185   -#endif
186   -
187   -#ifndef CONFIG_SYS_DCACHE_OFF
188   -void enable_caches(void)
189   -{
190   - /* Enable D-cache. I-cache is already enabled in start.S */
191   - dcache_enable();
192   -}
193   -#endif
arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S
View file @ 350b50e
1   -/*
2   - * SPDX-License-Identifier: GPL-2.0+
3   - */
4   -
5   -#include <config.h>
6   -#include <linux/linkage.h>
7   -
8   -ENTRY(save_boot_params)
9   - b save_boot_params_ret
10   -ENDPROC(save_boot_params)
11   -
12   -/*
13   - * cache_inv - invalidate Cache line
14   - * r0 - dest
15   - */
16   - .global cache_inv
17   - .type cache_inv, %function
18   - cache_inv:
19   -
20   - stmfd sp!, {r1-r12}
21   -
22   - mcr p15, 0, r0, c7, c6, 1
23   -
24   - ldmfd sp!, {r1-r12}
25   - bx lr
26   -
27   -
28   -/*
29   - * flush_l1_v6 - l1 cache clean invalidate
30   - * r0 - dest
31   - */
32   - .global flush_l1_v6
33   - .type flush_l1_v6, %function
34   - flush_l1_v6:
35   -
36   - stmfd sp!, {r1-r12}
37   -
38   - mcr p15, 0, r0, c7, c10, 5 /* @ data memory barrier */
39   - mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
40   - mcr p15, 0, r0, c7, c10, 4 /* @ data sync barrier */
41   -
42   - ldmfd sp!, {r1-r12}
43   - bx lr
44   -
45   -
46   -/*
47   - * flush_l1_v7 - l1 cache clean invalidate
48   - * r0 - dest
49   - */
50   - .global flush_l1_v7
51   - .type flush_l1_v7, %function
52   - flush_l1_v7:
53   -
54   - stmfd sp!, {r1-r12}
55   -
56   - dmb /* @data memory barrier */
57   - mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
58   - dsb /* @data sync barrier */
59   -
60   - ldmfd sp!, {r1-r12}
61   - bx lr
arch/arm/cpu/armv7/armada-xp/spl.c
View file @ 350b50e
1   -/*
2   - * Copyright (C) 2014 Stefan Roese <sr@denx.de>
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - */
6   -
7   -#include <common.h>
8   -#include <spl.h>
9   -#include <asm/io.h>
10   -#include <asm/arch/cpu.h>
11   -#include <asm/arch/soc.h>
12   -
13   -DECLARE_GLOBAL_DATA_PTR;
14   -
15   -u32 spl_boot_device(void)
16   -{
17   - /* Right now only booting via SPI NOR flash is supported */
18   - return BOOT_DEVICE_SPI;
19   -}
20   -
21   -void board_init_f(ulong dummy)
22   -{
23   - /* Set global data pointer */
24   - gd = &gdata;
25   -
26   - /* Linux expects the internal registers to be at 0xf1000000 */
27   - arch_cpu_init();
28   -
29   - preloader_console_init();
30   -
31   - /* First init the serdes PHY's */
32   - serdes_phy_config();
33   -
34   - /* Setup DDR */
35   - ddr3_init();
36   -
37   - board_init_r(NULL, 0);
38   -}
arch/arm/mach-mvebu/Makefile
Diff comments   View file @ 350b50e
  1 +#
  2 +# Copyright (C) 2014 Stefan Roese <sr@denx.de>
  3 +#
  4 +# SPDX-License-Identifier: GPL-2.0+
  5 +#
  6 +
  7 +obj-y = cpu.o
  8 +obj-$(CONFIG_SPL_BUILD) += spl.o
  9 +obj-$(CONFIG_SPL_BUILD) += lowlevel_spl.o
arch/arm/mach-mvebu/cpu.c
Diff comments   View file @ 350b50e
  1 +/*
  2 + * Copyright (C) 2014 Stefan Roese <sr@denx.de>
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <netdev.h>
  9 +#include <asm/io.h>
  10 +#include <asm/arch/cpu.h>
  11 +#include <asm/arch/soc.h>
  12 +
  13 +#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
  14 +#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
  15 +
  16 +static struct mbus_win windows[] = {
  17 + /* PCIE MEM address space */
  18 + { DEFADR_PCI_MEM, 256 << 20, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_MEM },
  19 +
  20 + /* PCIE IO address space */
  21 + { DEFADR_PCI_IO, 64 << 10, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_IO },
  22 +
  23 + /* SPI */
  24 + { DEFADR_SPIF, 8 << 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI,
  25 + CPU_ATTR_SPIFLASH },
  26 +
  27 + /* NOR */
  28 + { DEFADR_BOOTROM, 8 << 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI,
  29 + CPU_ATTR_BOOTROM },
  30 +};
  31 +
  32 +void reset_cpu(unsigned long ignored)
  33 +{
  34 + struct mvebu_system_registers *reg =
  35 + (struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE;
  36 +
  37 + writel(readl(&reg->rstoutn_mask) | 1, &reg->rstoutn_mask);
  38 + writel(readl(&reg->sys_soft_rst) | 1, &reg->sys_soft_rst);
  39 + while (1)
  40 + ;
  41 +}
  42 +
  43 +#if defined(CONFIG_DISPLAY_CPUINFO)
  44 +int print_cpuinfo(void)
  45 +{
  46 + u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
  47 + u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff;
  48 +
  49 + puts("SoC: ");
  50 +
  51 + switch (devid) {
  52 + case SOC_MV78460_ID:
  53 + puts("MV78460-");
  54 + break;
  55 + default:
  56 + puts("Unknown-");
  57 + break;
  58 + }
  59 +
  60 + switch (revid) {
  61 + case 1:
  62 + puts("A0\n");
  63 + break;
  64 + case 2:
  65 + puts("B0\n");
  66 + break;
  67 + default:
  68 + puts("??\n");
  69 + break;
  70 + }
  71 +
  72 + return 0;
  73 +}
  74 +#endif /* CONFIG_DISPLAY_CPUINFO */
  75 +
  76 +/*
  77 + * This function initialize Controller DRAM Fastpath windows.
  78 + * It takes the CS size information from the 0x1500 scratch registers
  79 + * and sets the correct windows sizes and base addresses accordingly.
  80 + *
  81 + * These values are set in the scratch registers by the Marvell
  82 + * DDR3 training code, which is executed by the BootROM before the
  83 + * main payload (U-Boot) is executed. This training code is currently
  84 + * only available in the Marvell U-Boot version. It needs to be
  85 + * ported to mainline U-Boot SPL at some point.
  86 + */
  87 +static void update_sdram_window_sizes(void)
  88 +{
  89 + u64 base = 0;
  90 + u32 size, temp;
  91 + int i;
  92 +
  93 + for (i = 0; i < SDRAM_MAX_CS; i++) {
  94 + size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) & SDRAM_ADDR_MASK;
  95 + if (size != 0) {
  96 + size |= ~(SDRAM_ADDR_MASK);
  97 +
  98 + /* Set Base Address */
  99 + temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF);
  100 + writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i));
  101 +
  102 + /*
  103 + * Check if out of max window size and resize
  104 + * the window
  105 + */
  106 + temp = (readl(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)) &
  107 + ~(SDRAM_ADDR_MASK)) | 1;
  108 + temp |= (size & SDRAM_ADDR_MASK);
  109 + writel(temp, MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i));
  110 +
  111 + base += ((u64)size + 1);
  112 + } else {
  113 + /*
  114 + * Disable window if not used, otherwise this
  115 + * leads to overlapping enabled windows with
  116 + * pretty strange results
  117 + */
  118 + clrbits_le32(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i), 1);
  119 + }
  120 + }
  121 +}
  122 +
  123 +#ifdef CONFIG_ARCH_CPU_INIT
  124 +int arch_cpu_init(void)
  125 +{
  126 + /* Linux expects the internal registers to be at 0xf1000000 */
  127 + writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
  128 +
  129 + /*
  130 + * We need to call mvebu_mbus_probe() before calling
  131 + * update_sdram_window_sizes() as it disables all previously
  132 + * configured mbus windows and then configures them as
  133 + * required for U-Boot. Calling update_sdram_window_sizes()
  134 + * without this configuration will not work, as the internal
  135 + * registers can't be accessed reliably because of potenial
  136 + * double mapping.
  137 + * After updating the SDRAM access windows we need to call
  138 + * mvebu_mbus_probe() again, as this now correctly configures
  139 + * the SDRAM areas that are later used by the MVEBU drivers
  140 + * (e.g. USB, NETA).
  141 + */
  142 +
  143 + /*
  144 + * First disable all windows
  145 + */
  146 + mvebu_mbus_probe(NULL, 0);
  147 +
  148 + /*
  149 + * Now the SDRAM access windows can be reconfigured using
  150 + * the information in the SDRAM scratch pad registers
  151 + */
  152 + update_sdram_window_sizes();
  153 +
  154 + /*
  155 + * Finally the mbus windows can be configured with the
  156 + * updated SDRAM sizes
  157 + */
  158 + mvebu_mbus_probe(windows, ARRAY_SIZE(windows));
  159 +
  160 + return 0;
  161 +}
  162 +#endif /* CONFIG_ARCH_CPU_INIT */
  163 +
  164 +/*
  165 + * SOC specific misc init
  166 + */
  167 +#if defined(CONFIG_ARCH_MISC_INIT)
  168 +int arch_misc_init(void)
  169 +{
  170 + /* Nothing yet, perhaps we need something here later */
  171 + return 0;
  172 +}
  173 +#endif /* CONFIG_ARCH_MISC_INIT */
  174 +
  175 +#ifdef CONFIG_MVNETA
  176 +int cpu_eth_init(bd_t *bis)
  177 +{
  178 + mvneta_initialize(bis, MVEBU_EGIGA0_BASE, 0, CONFIG_PHY_BASE_ADDR + 0);
  179 + mvneta_initialize(bis, MVEBU_EGIGA1_BASE, 1, CONFIG_PHY_BASE_ADDR + 1);
  180 + mvneta_initialize(bis, MVEBU_EGIGA2_BASE, 2, CONFIG_PHY_BASE_ADDR + 2);
  181 + mvneta_initialize(bis, MVEBU_EGIGA3_BASE, 3, CONFIG_PHY_BASE_ADDR + 3);
  182 +
  183 + return 0;
  184 +}
  185 +#endif
  186 +
  187 +#ifndef CONFIG_SYS_DCACHE_OFF
  188 +void enable_caches(void)
  189 +{
  190 + /* Enable D-cache. I-cache is already enabled in start.S */
  191 + dcache_enable();
  192 +}
  193 +#endif
arch/arm/mach-mvebu/lowlevel_spl.S
Diff comments   View file @ 350b50e
  1 +/*
  2 + * SPDX-License-Identifier: GPL-2.0+
  3 + */
  4 +
  5 +#include <config.h>
  6 +#include <linux/linkage.h>
  7 +
  8 +ENTRY(save_boot_params)
  9 + b save_boot_params_ret
  10 +ENDPROC(save_boot_params)
  11 +
  12 +/*
  13 + * cache_inv - invalidate Cache line
  14 + * r0 - dest
  15 + */
  16 + .global cache_inv
  17 + .type cache_inv, %function
  18 + cache_inv:
  19 +
  20 + stmfd sp!, {r1-r12}
  21 +
  22 + mcr p15, 0, r0, c7, c6, 1
  23 +
  24 + ldmfd sp!, {r1-r12}
  25 + bx lr
  26 +
  27 +
  28 +/*
  29 + * flush_l1_v6 - l1 cache clean invalidate
  30 + * r0 - dest
  31 + */
  32 + .global flush_l1_v6
  33 + .type flush_l1_v6, %function
  34 + flush_l1_v6:
  35 +
  36 + stmfd sp!, {r1-r12}
  37 +
  38 + mcr p15, 0, r0, c7, c10, 5 /* @ data memory barrier */
  39 + mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
  40 + mcr p15, 0, r0, c7, c10, 4 /* @ data sync barrier */
  41 +
  42 + ldmfd sp!, {r1-r12}
  43 + bx lr
  44 +
  45 +
  46 +/*
  47 + * flush_l1_v7 - l1 cache clean invalidate
  48 + * r0 - dest
  49 + */
  50 + .global flush_l1_v7
  51 + .type flush_l1_v7, %function
  52 + flush_l1_v7:
  53 +
  54 + stmfd sp!, {r1-r12}
  55 +
  56 + dmb /* @data memory barrier */
  57 + mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
  58 + dsb /* @data sync barrier */
  59 +
  60 + ldmfd sp!, {r1-r12}
  61 + bx lr
arch/arm/mach-mvebu/spl.c
Diff comments   View file @ 350b50e
  1 +/*
  2 + * Copyright (C) 2014 Stefan Roese <sr@denx.de>
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <spl.h>
  9 +#include <asm/io.h>
  10 +#include <asm/arch/cpu.h>
  11 +#include <asm/arch/soc.h>
  12 +
  13 +DECLARE_GLOBAL_DATA_PTR;
  14 +
  15 +u32 spl_boot_device(void)
  16 +{
  17 + /* Right now only booting via SPI NOR flash is supported */
  18 + return BOOT_DEVICE_SPI;
  19 +}
  20 +
  21 +void board_init_f(ulong dummy)
  22 +{
  23 + /* Set global data pointer */
  24 + gd = &gdata;
  25 +
  26 + /* Linux expects the internal registers to be at 0xf1000000 */
  27 + arch_cpu_init();
  28 +
  29 + preloader_console_init();
  30 +
  31 + /* First init the serdes PHY's */
  32 + serdes_phy_config();
  33 +
  34 + /* Setup DDR */
  35 + ddr3_init();
  36 +
  37 + board_init_r(NULL, 0);
  38 +}