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Commit 35e07b92f38436f04a0f8728cfc6a72f52aeddda

Authored by Eric Lee 2017-03-31 23:38:01 +0800

1 parent cd7520d6af

Exists in v2016.05-dlt

initial commit for delta touch board

Showing 5 changed files with 96 additions and 36 deletions Inline Diff

board/embedian/smarct335x/board.c
board/embedian/smarct335x/mux.c
drivers/i2c/i2c_core.c
include/configs/smarct335x_evm.h
include/i2c.h

board/embedian/smarct335x/board.c

Diff comments View file @ 35e07b9

 /*
  * board.c
  *
  * Board functions for TI AM335X based boards
  *
  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
 #include <errno.h>
 #include <spl.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/omap.h>
 #include <asm/arch/ddr_defs.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mem.h>
 #include <asm/io.h>
 #include <asm/emif.h>
 #include <asm/gpio.h>
 #include <i2c.h>
 #include <miiphy.h>
 #include <cpsw.h>
 #include <power/tps65217.h>
 #include <power/tps65910.h>
 #include <environment.h>
 #include <watchdog.h>
 #include "board.h"
 DECLARE_GLOBAL_DATA_PTR;
 /* GPIO that controls power to DDR on EVM-SK */
 #define GPIO_DDR_VTT_EN		7
 /* GPIO that controls power of LCD backlight */
 #define GPIO_LCD_BKLT_EN       	54
 /* GPIO that controls LCD backlight PWM */
 #define GPIO_LCD_PWM_EN        	7
+/* GPIO that controls WDT */
+#define GPIO_WDT_EN         	66
+/* GPIO of SER_INT */
+#define GPIO_SER_INT            100
 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 /*
  * Read header information from EEPROM into global structure.
  */
 static int read_eeprom(struct am335x_baseboard_id *header)
 {
 	/* Check if baseboard eeprom is available */
 	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
 		puts("Could not probe the EEPROM; something fundamentally "
 			"wrong on the I2C bus.\n");
 		return -ENODEV;
 	}
 	/* read the eeprom using i2c */
 	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
 		     sizeof(struct am335x_baseboard_id))) {
 		puts("Could not read the EEPROM; something fundamentally"
 			" wrong on the I2C bus.\n");
 		return -EIO;
 	}
 	if (header->magic != 0xEE3355AA) {
 		/*
 		 * read the eeprom using i2c again,
 		 * but use only a 1 byte address
 		 */
 		if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
 			     sizeof(struct am335x_baseboard_id))) {
 			puts("Could not read the EEPROM; something "
 				"fundamentally wrong on the I2C bus.\n");
 			return -EIO;
 		}
 		if (header->magic != 0xEE3355AA) {
 			printf("Incorrect magic number (0x%x) in EEPROM\n",
 					header->magic);
 			return -EINVAL;
 		}
 	}
 	return 0;
 }
 /*#ifndef CONFIG_SKIP_LOWLEVEL_INIT*/
 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
 static const struct ddr_data ddr2_data = {
 	.datardsratio0 = MT47H128M16RT25E_RD_DQS,
 	.datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
 	.datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
 };
 static const struct cmd_control ddr2_cmd_ctrl_data = {
 	.cmd0csratio = MT47H128M16RT25E_RATIO,
 	.cmd1csratio = MT47H128M16RT25E_RATIO,
 	.cmd2csratio = MT47H128M16RT25E_RATIO,
 };
 static const struct emif_regs ddr2_emif_reg_data = {
 	.sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
 	.ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
 	.sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
 	.sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
 	.sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
 	.emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
 };
 static const struct ddr_data ddr3_data = {
 	.datardsratio0 = MT41J128MJT125_RD_DQS,
 	.datawdsratio0 = MT41J128MJT125_WR_DQS,
 	.datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
 	.datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
 };
 static const struct ddr_data ddr3_beagleblack_data = {
 	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
 	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
 	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
 	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
 };
 static const struct ddr_data ddr3_smarct335x_data = {
         .datardsratio0 = K4B4G1646EBYK0_RD_DQS,
         .datawdsratio0 = K4B4G1646EBYK0_WR_DQS,
         .datafwsratio0 = K4B4G1646EBYK0_PHY_FIFO_WE,
         .datawrsratio0 = K4B4G1646EBYK0_PHY_WR_DATA,
 };
 static const struct ddr_data ddr3_smarct335x80_data = {
         .datardsratio0 = MT41K256M16HA125ITE_RD_DQS,
         .datawdsratio0 = MT41K256M16HA125ITE_WR_DQS,
         .datafwsratio0 = MT41K256M16HA125ITE_PHY_FIFO_WE,
         .datawrsratio0 = MT41K256M16HA125ITE_PHY_WR_DATA,
 };
 static const struct ddr_data ddr3_evm_data = {
 	.datardsratio0 = MT41J512M8RH125_RD_DQS,
 	.datawdsratio0 = MT41J512M8RH125_WR_DQS,
 	.datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
 	.datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
 };
 static const struct cmd_control ddr3_cmd_ctrl_data = {
 	.cmd0csratio = MT41J128MJT125_RATIO,
 	.cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
 	.cmd1csratio = MT41J128MJT125_RATIO,
 	.cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
 	.cmd2csratio = MT41J128MJT125_RATIO,
 	.cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
 };
 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
 	.cmd0csratio = MT41K256M16HA125E_RATIO,
 	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 	.cmd1csratio = MT41K256M16HA125E_RATIO,
 	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 	.cmd2csratio = MT41K256M16HA125E_RATIO,
 	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 };
 static const struct cmd_control ddr3_smarct335x_cmd_ctrl_data = {
         .cmd0csratio = K4B4G1646EBYK0_RATIO,
         .cmd0iclkout = K4B4G1646EBYK0_INVERT_CLKOUT,
         .cmd1csratio = K4B4G1646EBYK0_RATIO,
         .cmd1iclkout = K4B4G1646EBYK0_INVERT_CLKOUT,
         .cmd2csratio = K4B4G1646EBYK0_RATIO,
         .cmd2iclkout = K4B4G1646EBYK0_INVERT_CLKOUT,
 };
 static const struct cmd_control ddr3_smarct335x80_cmd_ctrl_data = {
         .cmd0csratio = MT41K256M16HA125ITE_RATIO,
         .cmd0iclkout = MT41K256M16HA125ITE_INVERT_CLKOUT,
         .cmd1csratio = MT41K256M16HA125ITE_RATIO,
         .cmd1iclkout = MT41K256M16HA125ITE_INVERT_CLKOUT,
         .cmd2csratio = MT41K256M16HA125ITE_RATIO,
         .cmd2iclkout = MT41K256M16HA125ITE_INVERT_CLKOUT,
 };
 static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
 	.cmd0csratio = MT41J512M8RH125_RATIO,
 	.cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 	.cmd1csratio = MT41J512M8RH125_RATIO,
 	.cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 	.cmd2csratio = MT41J512M8RH125_RATIO,
 	.cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 };
 static struct emif_regs ddr3_emif_reg_data = {
 	.sdram_config = MT41J128MJT125_EMIF_SDCFG,
 	.ref_ctrl = MT41J128MJT125_EMIF_SDREF,
 	.sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
 	.sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
 	.sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
 	.zq_config = MT41J128MJT125_ZQ_CFG,
 	.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
 				PHY_EN_DYN_PWRDN,
 };
 static struct emif_regs ddr3_beagleblack_emif_reg_data = {
 	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
 	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
 	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
 	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
 	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
 	.zq_config = MT41K256M16HA125E_ZQ_CFG,
 	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
 };
 static struct emif_regs ddr3_smarct335x_emif_reg_data = {
         .sdram_config = K4B4G1646EBYK0_EMIF_SDCFG,
         .ref_ctrl = K4B4G1646EBYK0_EMIF_SDREF,
         .sdram_tim1 = K4B4G1646EBYK0_EMIF_TIM1,
         .sdram_tim2 = K4B4G1646EBYK0_EMIF_TIM2,
         .sdram_tim3 = K4B4G1646EBYK0_EMIF_TIM3,
         .zq_config = K4B4G1646EBYK0_ZQ_CFG,
         .emif_ddr_phy_ctlr_1 = K4B4G1646EBYK0_EMIF_READ_LATENCY,
 };
 static struct emif_regs ddr3_smarct335x80_emif_reg_data = {
         .sdram_config = MT41K256M16HA125ITE_EMIF_SDCFG,
         .ref_ctrl = MT41K256M16HA125ITE_EMIF_SDREF,
         .sdram_tim1 = MT41K256M16HA125ITE_EMIF_TIM1,
         .sdram_tim2 = MT41K256M16HA125ITE_EMIF_TIM2,
         .sdram_tim3 = MT41K256M16HA125ITE_EMIF_TIM3,
         .zq_config = MT41K256M16HA125ITE_ZQ_CFG,
         .emif_ddr_phy_ctlr_1 = MT41K256M16HA125ITE_EMIF_READ_LATENCY,
 };
 static struct emif_regs ddr3_evm_emif_reg_data = {
 	.sdram_config = MT41J512M8RH125_EMIF_SDCFG,
 	.ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
 	.sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
 	.sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
 	.sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
 	.zq_config = MT41J512M8RH125_ZQ_CFG,
 	.emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
 				PHY_EN_DYN_PWRDN,
 };
 #ifdef CONFIG_SPL_OS_BOOT
 int spl_start_uboot(void)
 {
 	/* break into full u-boot on 'c' */
 	if (serial_tstc() && serial_getc() == 'c')
 		return 1;
 #ifdef CONFIG_SPL_ENV_SUPPORT
 	env_init();
 	env_relocate_spec();
 	if (getenv_yesno("boot_os") != 1)
 		return 1;
 #endif
 	return 0;
 }
 #endif
 #define OSC	(V_OSCK/1000000)
 const struct dpll_params dpll_ddr = {
 		266, OSC-1, 1, -1, -1, -1, -1};
 const struct dpll_params dpll_ddr_evm_sk = {
 		303, OSC-1, 1, -1, -1, -1, -1};
 const struct dpll_params dpll_ddr_bone_black = {
 		400, OSC-1, 1, -1, -1, -1, -1};
 const struct dpll_params dpll_ddr_smarc_t335x = {
                 400, OSC-1, 1, -1, -1, -1, -1};
 void am33xx_spl_board_init(void)
 {
 	struct am335x_baseboard_id header;
 	int mpu_vdd;
 	if (read_eeprom(&header) < 0)
 		puts("Could not get board ID.\n");
 	/* Get the frequency */
 	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
 	if (board_is_bone(&header) || board_is_bone_lt(&header) || board_is_smarc_t335x(&header) || board_is_smarc_t335x_80(&header) || board_is_smarc_t335x_1g(&header)) {
 		/* BeagleBone PMIC Code */
 		int usb_cur_lim;
 		/*
 		 * Only perform PMIC configurations if board rev > A1
 		 * on Beaglebone White
 		 */
 		if (board_is_bone(&header) && !strncmp(header.version,
 						       "00A1", 4))
 			return;
 		if (i2c_probe(TPS65217_CHIP_PM))
 			return;
 		/*
 		 * On Beaglebone White we need to ensure we have AC power
 		 * before increasing the frequency.
 		 */
 		if (board_is_bone(&header)) {
 			uchar pmic_status_reg;
 			if (tps65217_reg_read(TPS65217_STATUS,
 					      &pmic_status_reg))
 				return;
 			if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
 				puts("No AC power, disabling frequency switch\n");
 				return;
 			}
 		}
                 /*
                  * Override what we have detected since we know if we have
                  * a Beaglebone Black it supports 1GHz.
                  */
                 if ((board_is_bone_lt(&header) || board_is_smarc_t335x_1g(&header)))
                         dpll_mpu_opp100.m = MPUPLL_M_1000;
                 /*
                  * Increase USB current limit to 1300mA or 1800mA and set
                  * the MPU voltage controller as needed.
                  */
 		if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
 			usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
 			mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
 		} else {
 			usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
 			mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
 		}
 		if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
 				       TPS65217_POWER_PATH,
 				       usb_cur_lim,
 				       TPS65217_USB_INPUT_CUR_LIMIT_MASK))
 			puts("tps65217_reg_write failure\n");
 		/* Set DCDC3 (CORE) voltage to 1.125V */
 		if (tps65217_voltage_update(TPS65217_DEFDCDC3,
 					    TPS65217_DCDC_VOLT_SEL_1125MV)) {
 			puts("tps65217_voltage_update failure\n");
 			return;
 		}
 		/* Set CORE Frequencies to OPP100 */
 		do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
 		/* Set DCDC2 (MPU) voltage */
 		if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
 			puts("tps65217_voltage_update failure\n");
 			return;
 		}
 		/*
 		 * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
 		 * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
 		 */
 		if (board_is_bone(&header)) {
 			if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 					       TPS65217_DEFLS1,
 					       TPS65217_LDO_VOLTAGE_OUT_3_3,
 					       TPS65217_LDO_MASK))
 				puts("tps65217_reg_write failure\n");
 		} else {
 			if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 					       TPS65217_DEFLS1,
 					       TPS65217_LDO_VOLTAGE_OUT_1_8,
 					       TPS65217_LDO_MASK))
 				puts("tps65217_reg_write failure\n");
 		}
 		if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 				       TPS65217_DEFLS2,
 				       TPS65217_LDO_VOLTAGE_OUT_3_3,
 				       TPS65217_LDO_MASK))
 			puts("tps65217_reg_write failure\n");
 	} else {
 		int sil_rev;
 		/*
 		 * The GP EVM, IDK and EVM SK use a TPS65910 PMIC.  For all
 		 * MPU frequencies we support we use a CORE voltage of
 		 * 1.1375V.  For MPU voltage we need to switch based on
 		 * the frequency we are running at.
 		 */
 		if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
 			return;
 		/*
 		 * Depending on MPU clock and PG we will need a different
 		 * VDD to drive at that speed.
 		 */
 		sil_rev = readl(&cdev->deviceid) >> 28;
 		mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
 						      dpll_mpu_opp100.m);
 		/* Tell the TPS65910 to use i2c */
 		tps65910_set_i2c_control();
 		/* First update MPU voltage. */
 		if (tps65910_voltage_update(MPU, mpu_vdd))
 			return;
 		/* Second, update the CORE voltage. */
 		if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
 			return;
 		/* Set CORE Frequencies to OPP100 */
 		do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
 	}
 	/* Set MPU Frequency to what we detected now that voltages are set */
 	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
 }
 const struct dpll_params *get_dpll_ddr_params(void)
 {
 	struct am335x_baseboard_id header;
 	enable_i2c0_pin_mux();
 	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 	if (read_eeprom(&header) < 0)
 		puts("Could not get board ID.\n");
 	if (board_is_evm_sk(&header))
 		return &dpll_ddr_evm_sk;
 	else if (board_is_bone_lt(&header))
 		return &dpll_ddr_bone_black;
         else if (board_is_smarc_t335x(&header) || board_is_smarc_t335x_80(&header) || board_is_smarc_t335x_1g(&header))
                 return &dpll_ddr_smarc_t335x;
 	else if (board_is_evm_15_or_later(&header))
 		return &dpll_ddr_evm_sk;
 	else
 		return &dpll_ddr;
 }
 void set_uart_mux_conf(void)
 {
 #if CONFIG_CONS_INDEX == 1
 	enable_uart0_pin_mux();
 #elif CONFIG_CONS_INDEX == 2
 	enable_uart1_pin_mux();
 #elif CONFIG_CONS_INDEX == 3
 	enable_uart2_pin_mux();
 #elif CONFIG_CONS_INDEX == 4
 	enable_uart3_pin_mux();
 #elif CONFIG_CONS_INDEX == 5
 	enable_uart4_pin_mux();
 #elif CONFIG_CONS_INDEX == 6
 	enable_uart5_pin_mux();
 #endif
 }
 void set_mux_conf_regs(void)
 {
 	__maybe_unused struct am335x_baseboard_id header;
 	if (read_eeprom(&header) < 0)
 		puts("Could not get board ID.\n");
 	enable_board_pin_mux(&header);
 }
 const struct ctrl_ioregs ioregs_evmsk = {
 	.cm0ioctl		= MT41J128MJT125_IOCTRL_VALUE,
 	.cm1ioctl		= MT41J128MJT125_IOCTRL_VALUE,
 	.cm2ioctl		= MT41J128MJT125_IOCTRL_VALUE,
 	.dt0ioctl		= MT41J128MJT125_IOCTRL_VALUE,
 	.dt1ioctl		= MT41J128MJT125_IOCTRL_VALUE,
 };
 const struct ctrl_ioregs ioregs_bonelt = {
 	.cm0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
 	.cm1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
 	.cm2ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
 	.dt0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
 	.dt1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
 };
 const struct ctrl_ioregs ioregs_smarct335x = {
         .cm0ioctl               = K4B4G1646EBYK0_IOCTRL_VALUE,
         .cm1ioctl               = K4B4G1646EBYK0_IOCTRL_VALUE,
         .cm2ioctl               = K4B4G1646EBYK0_IOCTRL_VALUE,
         .dt0ioctl               = K4B4G1646EBYK0_IOCTRL_VALUE,
         .dt1ioctl               = K4B4G1646EBYK0_IOCTRL_VALUE,
 };
 const struct ctrl_ioregs ioregs_smarct335x80 = {
         .cm0ioctl               = MT41K256M16HA125ITE_IOCTRL_VALUE,
         .cm1ioctl               = MT41K256M16HA125ITE_IOCTRL_VALUE,
         .cm2ioctl               = MT41K256M16HA125ITE_IOCTRL_VALUE,
         .dt0ioctl               = MT41K256M16HA125ITE_IOCTRL_VALUE,
         .dt1ioctl               = MT41K256M16HA125ITE_IOCTRL_VALUE,
 };
 const struct ctrl_ioregs ioregs_evm15 = {
 	.cm0ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
 	.cm1ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
 	.cm2ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
 	.dt0ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
 	.dt1ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
 };
 const struct ctrl_ioregs ioregs = {
 	.cm0ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
 	.cm1ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
 	.cm2ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
 	.dt0ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
 	.dt1ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
 };
 void sdram_init(void)
 {
 	__maybe_unused struct am335x_baseboard_id header;
 	if (read_eeprom(&header) < 0)
 		puts("Could not get board ID.\n");
 	if (board_is_evm_sk(&header)) {
 		/*
 		 * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
 		 * This is safe enough to do on older revs.
 		 */
 		gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
 		gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 	}
 	if (board_is_evm_sk(&header))
 		config_ddr(303, &ioregs_evmsk, &ddr3_data,
 			   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 	else if (board_is_bone_lt(&header))
 		config_ddr(400, &ioregs_bonelt,
 			   &ddr3_beagleblack_data,
 			   &ddr3_beagleblack_cmd_ctrl_data,
 			   &ddr3_beagleblack_emif_reg_data, 0);
         else if (board_is_smarc_t335x(&header) || board_is_smarc_t335x_1g(&header)) {
                 /*
                  * SMARC T335X rev. 00B0 and later use gpio0_7 as LCD backlight PWM and gpio1_22 as LCD backlight enable.
                  * This is safe enough to do on older revs.
                  */
-                gpio_request(GPIO_LCD_BKLT_EN, "lcd_bklt_en");
+                gpio_request(GPIO_WDT_EN, "wdt_en");
-                gpio_direction_output(GPIO_LCD_BKLT_EN, 1);
+                gpio_direction_output(GPIO_WDT_EN, 0);
-                gpio_request(GPIO_LCD_PWM_EN, "lcd_pwm_en");
+                gpio_request(GPIO_SER_INT, "ser_int");
-                gpio_direction_output(GPIO_LCD_PWM_EN, 1);
+                gpio_direction_input(GPIO_SER_INT);
                 config_ddr(400, &ioregs_smarct335x,
 			   &ddr3_smarct335x_data,
                            &ddr3_smarct335x_cmd_ctrl_data,
 			   &ddr3_smarct335x_emif_reg_data, 0);
 		udelay(3600);
         }
         else if (board_is_smarc_t335x_80(&header)) {
                 /*
                  * SMARC T335X rev. 00B0 and later use gpio0_7 as LCD backlight PWM and gpio1_22 as LCD backlight enable.
                  * This is safe enough to do on older revs.
                  */
                 gpio_request(GPIO_LCD_BKLT_EN, "lcd_bklt_en");
                 gpio_direction_output(GPIO_LCD_BKLT_EN, 1);
                 gpio_request(GPIO_LCD_PWM_EN, "lcd_pwm_en");
                 gpio_direction_output(GPIO_LCD_PWM_EN, 1);
                 config_ddr(400, &ioregs_smarct335x80,
                            &ddr3_smarct335x80_data,
                            &ddr3_smarct335x80_cmd_ctrl_data,
                            &ddr3_smarct335x80_emif_reg_data, 0);
 		udelay(3600);
         }
 	else if (board_is_evm_15_or_later(&header))
 		config_ddr(400, &ioregs_evm15, &ddr3_evm_data,
 			   &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
 	else
 		config_ddr(266, &ioregs, &ddr2_data,
 			   &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
 }
 #endif
 /*
  * Basic board specific setup.  Pinmux has been handled already.
  */
 int board_init(void)
 {
 	u32 sys_reboot;
 	sys_reboot = readl(PRM_RSTST);
 	if (sys_reboot & (1 << 9))
 		puts("Reset Source: IcePick reset has occurred.\n");
 	if (sys_reboot & (1 << 5))
 		puts("Reset Source: Global external warm reset has occurred.\n");
 	if (sys_reboot & (1 << 4))
 		puts("Reset Source: watchdog reset has occurred.\n");
 	if (sys_reboot & (1 << 1))
 		puts("Reset Source: Global warm SW reset has occurred.\n");
 	if (sys_reboot & (1 << 0))
 		puts("Reset Source: Power-on reset has occurred.\n");
 #if defined(CONFIG_HW_WATCHDOG)
 	hw_watchdog_init();
 #endif
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 #if defined(CONFIG_NOR) || defined(CONFIG_NAND)
 	gpmc_init();
 #endif
 	return 0;
 }
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 	char safe_string[HDR_NAME_LEN + 1];
 	struct am335x_baseboard_id header;
 	if (read_eeprom(&header) < 0)
 		puts("Could not get board ID.\n");
         /* Read Board Info from EEPROM */
         puts("-----------------------------------------\n");
         printf("Board ID:               %.*s\n",
                sizeof(header.name), header.name);
         printf("Board Revision:         %.*s\n",
                sizeof(header.version), header.version);
         printf("Board Serial#:          %.*s\n",
                sizeof(header.serial), header.serial);
         puts("-----------------------------------------\n");
+	gpio_request(69, "i2c_multiplexer_reset");
+	/*gpio_direction_output(69, 0);*/
+	gpio_direction_output(69, 1);
+	/* Turn on I2C switch PCA9546 channel */
+        i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR);
+	uint8_t i2cbuf;
+	i2cbuf = CONFIG_SYS_I2C_PCA9546_ENABLE;
+	i2c_write(CONFIG_SYS_I2C_PCA9546_ADDR, 1, CONFIG_SYS_I2C_PCA9546_ADDR_LEN, &i2cbuf, 1);
+	/* Enable DS90UB925 I2C Pass Through */
+        i2cbuf = CONFIG_SYS_I2C_SER_PASSTROUGH;
+        i2c_write(CONFIG_SYS_I2C_SER_ADDR, 0x03, 1, &i2cbuf, 1);
+        /* Enable DS90UB925 I2C Pass ALL */
+        i2cbuf = CONFIG_SYS_I2C_SER_PASSALL;
+        i2c_write(CONFIG_SYS_I2C_SER_ADDR, 0x17, 1, &i2cbuf, 1);
+	/* Enable DS90UB925 IRQ */
+        i2cbuf = CONFIG_SYS_I2C_SER_IRQ_ENABLE;
+        i2c_write(CONFIG_SYS_I2C_SER_ADDR, 0xc6, 1, &i2cbuf, 1);
 	/* Now set variables based on the header. */
 	strncpy(safe_string, (char *)header.name, sizeof(header.name));
 	safe_string[sizeof(header.name)] = 0;
 	setenv("board_name", safe_string);
 	/* BeagleBone Green has 0x1a at [0], they are free to increment 'a' */
 	if ( (header.version[0] != 0x30) && (header.version[0] & (1 << 4)) ) {
 		setenv("board_rev", "BBG1");
 	} else {
 		strncpy(safe_string, (char *)header.version, sizeof(header.version));
 		safe_string[sizeof(header.version)] = 0;
 		setenv("board_rev", safe_string);
 	}
 #endif
 	return 0;
 }
 #endif
 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 static void cpsw_control(int enabled)
 {
 	/* VTP can be added here */
 	return;
 }
 static struct cpsw_slave_data cpsw_slaves[] = {
 	{
 		.slave_reg_ofs	= 0x208,
 		.sliver_reg_ofs	= 0xd80,
 		.phy_addr	= 0,
 	},
 	{
 		.slave_reg_ofs	= 0x308,
 		.sliver_reg_ofs	= 0xdc0,
 		.phy_addr	= 1,
 	},
 };
 static struct cpsw_platform_data cpsw_data = {
 	.mdio_base		= CPSW_MDIO_BASE,
 	.cpsw_base		= CPSW_BASE,
 	.mdio_div		= 0xff,
 	.channels		= 8,
 	.cpdma_reg_ofs		= 0x800,
 	.slaves			= 1,
 	.slave_data		= cpsw_slaves,
 	.ale_reg_ofs		= 0xd00,
 	.ale_entries		= 1024,
 	.host_port_reg_ofs	= 0x108,
 	.hw_stats_reg_ofs	= 0x900,
 	.bd_ram_ofs		= 0x2000,
 	.mac_control		= (1 << 5),
 	.control		= cpsw_control,
 	.host_port_num		= 0,
 	.version		= CPSW_CTRL_VERSION_2,
 };
 #endif
 /*
  * This function will:
  * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
  * in the environment
  * Perform fixups to the PHY present on certain boards.  We only need this
  * function in:
  * - SPL with either CPSW or USB ethernet support
  * - Full U-Boot, with either CPSW or USB ethernet
  * Build in only these cases to avoid warnings about unused variables
  * when we build an SPL that has neither option but full U-Boot will.
  */
 #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \
 		&& defined(CONFIG_SPL_BUILD)) || \
 	((defined(CONFIG_DRIVER_TI_CPSW) || \
 	  defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
 	 !defined(CONFIG_SPL_BUILD))
 int board_eth_init(bd_t *bis)
 {
 	int rv, n = 0;
 	uint8_t mac_addr[6];
 	uint32_t mac_hi, mac_lo;
 	__maybe_unused struct am335x_baseboard_id header;
 	/* try reading mac address from efuse */
 	mac_lo = readl(&cdev->macid0l);
 	mac_hi = readl(&cdev->macid0h);
 	mac_addr[0] = mac_hi & 0xFF;
 	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 	mac_addr[4] = mac_lo & 0xFF;
 	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 	if (!getenv("ethaddr")) {
 		printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 		if (is_valid_ethaddr(mac_addr))
 			eth_setenv_enetaddr("ethaddr", mac_addr);
 	}
 #ifdef CONFIG_DRIVER_TI_CPSW
 	mac_lo = readl(&cdev->macid1l);
 	mac_hi = readl(&cdev->macid1h);
 	mac_addr[0] = mac_hi & 0xFF;
 	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 	mac_addr[4] = mac_lo & 0xFF;
 	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 	if (!getenv("eth1addr")) {
 		if (is_valid_ethaddr(mac_addr))
 			eth_setenv_enetaddr("eth1addr", mac_addr);
 	}
 	if (read_eeprom(&header) < 0)
 		puts("Could not get board ID.\n");
 	if (board_is_bone(&header) || board_is_bone_lt(&header) ||
 	    board_is_idk(&header)) {
 		writel(MII_MODE_ENABLE, &cdev->miisel);
 		cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 				PHY_INTERFACE_MODE_MII;
         } else if (board_is_smarc_t335x(&header) || board_is_smarc_t335x_80(&header) || board_is_smarc_t335x_1g(&header)) {
                writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
                cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
                                PHY_INTERFACE_MODE_RMII;
 	} else {
 		writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
 		cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 				PHY_INTERFACE_MODE_RGMII;
 	}
 	rv = cpsw_register(&cpsw_data);
 	if (rv < 0)
 		printf("Error %d registering CPSW switch\n", rv);
 	else
 		n += rv;
 #endif
 	/*
 	 *
 	 * CPSW RGMII Internal Delay Mode is not supported in all PVT
 	 * operating points.  So we must set the TX clock delay feature
 	 * in the AR8051 PHY.  Since we only support a single ethernet
 	 * device in U-Boot, we only do this for the first instance.
 	 */
 #define AR8051_PHY_DEBUG_ADDR_REG	0x1d
 #define AR8051_PHY_DEBUG_DATA_REG	0x1e
 #define AR8051_DEBUG_RGMII_CLK_DLY_REG	0x5
 #define AR8051_RGMII_TX_CLK_DLY		0x100
 	if (board_is_evm_sk(&header) || board_is_gp_evm(&header)) {
 		const char *devname;
 		devname = miiphy_get_current_dev();
 		miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
 				AR8051_DEBUG_RGMII_CLK_DLY_REG);
 		miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
 				AR8051_RGMII_TX_CLK_DLY);
 	}
 #endif
 #if defined(CONFIG_USB_ETHER) && \
 	(!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
 	if (is_valid_ethaddr(mac_addr))
 		eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
 	rv = usb_eth_initialize(bis);
 	if (rv < 0)
 		printf("Error %d registering USB_ETHER\n", rv);
 	else
 		n += rv;
 #endif
 	return n;
 }
 #endif
 #ifdef CONFIG_SPL_LOAD_FIT
 int board_fit_config_name_match(const char *name)
 {
         if (board_is_gp_evm(&header) && !strcmp(header->name, "A33515BB"))
                 return 0;
         else if (board_is_bone(&header) && !strcmp(header->name, "A335BONE", 8))
                 return 0;
         else if (board_is_bone_lt(&header) && !strcmp(header->name, "A335BNLT", 8))
                 return 0;
         else if (board_is_evm_sk(&header) && !strcmp(header->name, "A335X_SK", 8))
                 return 0;
         else if (board_is_bbg1(&header) && !strcmp(header->name, "BBG1", 4))
                 return 0;
         else if (board_is_icev2(&header) && !strcmp(header->name, "A335_ICE", 8))
                 return 0;
         else if (board_is_smarc_t335x(&header) && !strcmp(header->name, "SMARCT33", 8))
                 return 0;
         else if (board_is_smarc_t335x_80(&header) && !strcmp(header->name, "SMARCT80", 8))
                 return 0;
         else if (board_is_smarc_t335x_1g(&header) && !strcmp(header->name, "SMARCT1G", 8))
                 return 0;
         else
                 return -1;
 }
 #endif
 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 static const char cpsw_eth0_alias[] = "/ocp/ethernet@4a100000/slave@4a100200";
 static const char cpsw_eth1_alias[] = "/ocp/ethernet@4a100000/slave@4a100300";
 int ft_board_setup(void *fdt, bd_t *bd)
 {
         const char *path;
         int offs;
         int ret;
         if (!board_is_icev2())
                 return 0;
         /* Board DT default is both ports are MII */
         if (eth0_is_mii && eth1_is_mii)
                 return 0;
         if (eth0_is_mii != eth1_is_mii) {
                 printf("Unsupported Ethernet port configuration\n");
                 printf("Both ports must be set as RMII or MII\n");
                 return 0;
         }
         printf("Fixing up ETH0 & ETH1 to CPSW Ethernet\n");
         /* Disable PRUSS-MDIO */
         path = "/ocp/pruss@4a300000/mdio@4a332400";
         offs = fdt_path_offset(fdt, path);
         if (offs < 0)
                 goto no_node;
         ret = fdt_status_disabled(fdt, offs);
         if (ret < 0)
                 goto disable_failed;
         /* Disable PRU-ICSS Ethernet */
         path = "/pruss_eth";
         offs = fdt_path_offset(fdt, path);
         if (offs < 0)
                 goto no_node;
         ret = fdt_status_disabled(fdt, offs);
         if (ret < 0)
                 goto disable_failed;
         /* Enable CPSW Ethernet */
         path = "/ocp/ethernet@4a100000";
         offs = fdt_path_offset(fdt, path);
         if (offs < 0)
                 goto no_node;
         ret = fdt_status_okay(fdt, offs);
         if (ret < 0)
                 goto enable_failed;
         /* Enable CPSW-MDIO */
         path = "/ocp/ethernet@4a100000/mdio@4a101000";
         offs = fdt_path_offset(fdt, path);
         if (offs < 0)
                 goto no_node;
         ret = fdt_status_okay(fdt, offs);
         if (ret < 0)
                 goto enable_failed;
         /* Set MUX_MII_CTL1 pin high */
         path = "/ocp/gpio@481ae000/p10";
         offs = fdt_path_offset(fdt, path);
         if (offs < 0) {
                 printf("Node %s not found.\n", path);
                 return offs;
         }
         ret = fdt_delprop(fdt, offs, "output-low");
         if (ret < 0) {
                 printf("Could not delete output-low property from node %s: %s\n",
                        path, fdt_strerror(ret));
                 return ret;
         }
         ret = fdt_setprop(fdt, offs, "output-high", NULL, 0);
         if (ret < 0) {
                 printf("Could not add output-high property to node %s: %s\n",
                        path, fdt_strerror(ret));
                 return ret;
         }
         /* Fixup ethernet aliases */
         path = "/aliases";
         offs = fdt_path_offset(fdt, path);
         if (offs < 0)
                 goto no_node;
         ret = fdt_setprop(fdt, offs, "ethernet0", cpsw_eth0_alias,
                           strlen(cpsw_eth0_alias) + 1);
         if (ret < 0) {
                 printf("Could not change ethernet0 alias: %s\n",
                        fdt_strerror(ret));
                 return ret;
         }
         ret = fdt_setprop(fdt, offs, "ethernet1", cpsw_eth1_alias,
                           strlen(cpsw_eth0_alias) + 1);
         if (ret < 0) {
                 printf("Could not change ethernet0 alias: %s\n",
                        fdt_strerror(ret));
                 return ret;
         }
         return 0;
 no_node:
         printf("Node %s not found. Please update DTB.\n", path);
         /* Return 0 as we don't want to prevent booting with older DTBs */
         return 0;
 disable_failed:
         printf("Could not disable node %s: %s\n",
                path, fdt_strerror(ret));
         return ret;
 enable_failed:
         printf("Could not enable node %s: %s\n",
                path, fdt_strerror(ret));
         return ret;
 }
 #endif

board/embedian/smarct335x/mux.c

Diff comments View file @ 35e07b9

 /*
  * mux.c
  *
  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation version 2.
  *
  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  * kind, whether express or implied; without even the implied warranty
  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  * GNU General Public License for more details.
  */
 #include <common.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/mux.h>
 #include <asm/io.h>
 #include <i2c.h>
 #include "board.h"
 static struct module_pin_mux uart0_pin_mux[] = {
 	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART0_RXD */
 	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},		/* UART0_TXD */
+       	{OFFSET(uart0_ctsn), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART0_CTSN */
+       	{OFFSET(uart0_rtsn), (MODE(0) | PULLUDEN)},            	/* UART0_RTSN */
 	{-1},
 };
 static struct module_pin_mux uart1_pin_mux[] = {
-	{OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART1_RXD */
+       	{OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},  /* UART1_RXD */
-	{OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},		/* UART1_TXD */
+       	{OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},              /* UART1_TXD */
+       	{OFFSET(uart1_rtsn), (MODE(0) | PULLUDEN)},             /* UART1_RTSN */
 	{-1},
 };
 static struct module_pin_mux uart2_pin_mux[] = {
         {OFFSET(mii1_txclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
         {OFFSET(mii1_rxclk), (MODE(1) | PULLUDEN)},             /* UART2_TXD */
         {-1},
 };
 static struct module_pin_mux uart3_pin_mux[] = {
         {OFFSET(mii1_rxd3), (MODE(1) | PULLUP_EN | RXACTIVE)},  /* UART3_RXD */
         {OFFSET(mii1_rxd2), (MODE(1) | PULLUDEN)},      /* UART3_TXD */
         {-1},
 };
 static struct module_pin_mux uart4_pin_mux[] = {
 	{OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)},	/* UART4_RXD */
 	{OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)},		/* UART4_TXD */
 	{-1},
 };
 static struct module_pin_mux uart5_pin_mux[] = {
 	{OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)},	/* UART5_RXD */
 	{OFFSET(lcd_data8), (MODE(4) | PULLUDEN)},		/* UART5_TXD */
 	{-1},
 };
 static struct module_pin_mux mmc0_pin_mux[] = {
 	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
 	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
 	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT1 */
 	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT0 */
 	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
 	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
        	{OFFSET(gpmc_a2), (MODE(7) | RXACTIVE)},               	/* MMC0_WP */
        	{OFFSET(gpmc_a1), (MODE(7) | RXACTIVE | PULLUP_EN)},   	/* MMC0_CD */
 	{-1},
 };
 static struct module_pin_mux mmc0_no_cd_pin_mux[] = {
 	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
 	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
 	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT1 */
 	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT0 */
 	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
 	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
 	{OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)},		/* MMC0_WP */
 	{-1},
 };
 static struct module_pin_mux mmc0_pin_mux_sk_evm[] = {
 	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
 	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
 	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT1 */
 	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT0 */
 	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
 	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
 	{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)},	/* MMC0_CD */
 	{-1},
 };
 static struct module_pin_mux mmc1_pin_mux[] = {
         {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)},   /* MMC1_DAT3 */
         {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)},   /* MMC1_DAT2 */
         {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)},   /* MMC1_DAT1 */
         {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)},   /* MMC1_DAT0 */
         {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)},  /* MMC1_CLK */
         {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)},  /* MMC1_CMD */
         {-1},
 };
 static struct module_pin_mux i2c0_pin_mux[] = {
 	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
 			PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
 	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
 			PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
 	{-1},
 };
-static struct module_pin_mux i2c1_pin_mux[] = {
-        {OFFSET(uart1_rxd), (MODE(3) | RXACTIVE |
-                        PULLUDEN | SLEWCTRL)},  /* I2C_DATA */
-        {OFFSET(uart1_txd), (MODE(3) | RXACTIVE |
-                        PULLUDEN | SLEWCTRL)},  /* I2C_SCLK */
-        {-1},
-};
 static struct module_pin_mux spi0_pin_mux[] = {
 	{OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)},	/* SPI0_SCLK */
 	{OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
 			PULLUDEN | PULLUP_EN)},			/* SPI0_D0 */
 	{OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)},	/* SPI0_D1 */
 	{OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
 			PULLUDEN | PULLUP_EN)},			/* SPI0_CS0 */
+        {OFFSET(spi0_cs1), (MODE(0) | RXACTIVE |
+                        PULLUDEN | PULLUP_EN)},                 /* SPI0_CS1 */
 	{-1},
 };
+static struct module_pin_mux spi1_pin_mux[] = {
+        {OFFSET(mcasp0_aclkx), (MODE(3) | RXACTIVE | PULLUDEN)},   /* SPI1_SCLK */
+        {OFFSET(mcasp0_fsx), (MODE(3) | RXACTIVE |
+                        PULLUDEN | PULLUP_EN)},                 /* SPI1_D0 */
+        {OFFSET(mcasp0_axr0), (MODE(3) | RXACTIVE | PULLUDEN)},     /* SPI1_D1 */
+        {OFFSET(mcasp0_ahclkr), (MODE(3) | RXACTIVE |
+                        PULLUDEN | PULLUP_EN)},                 /* SPI1_CS0 */
+        {OFFSET(xdma_event_intr0), (MODE(4) | RXACTIVE |
+                        PULLUDEN | PULLUP_EN)},                 /* SPI1_CS1 */
+        {-1},
+};
 static struct module_pin_mux gpio0_7_pin_mux[] = {
 	{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)},	/* GPIO0_7 */
 	{-1},
 };
 static struct module_pin_mux smarc_gpio_pin_mux[] = {
         {OFFSET(gpmc_a7), (MODE(7) | PULLUDEN | PULLUP_EN)},   	/* GPIO1_23, LCD VDD_EN */
         {OFFSET(gpmc_a6), (MODE(7) | PULLUDEN | PULLUP_EN)},   	/* GPIO1_22, LCD Backlight Enable */
         {OFFSET(gpmc_a3), (MODE(7) | PULLUDEN | PULLUP_EN)},   	/* GPIO1_19, MMC0_PWREN Enable*/
         {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)},     	/* GPIO0_7, LCD_BKLT_PWM */
 /* By SMARC Spec. GPIO0-5 is recommended for use as outputs and GPIO6-11 is recommended for use of inputs */
-        {OFFSET(mii1_rxdv), MODE(7)},                          	/* GPIO3_4, GPIO0 */
+        {OFFSET(mii1_rxdv), MODE(7) | RXACTIVE},                /* GPIO3_4, GPIO0 */
-        {OFFSET(gpmc_be0n_cle), MODE(7)},                     	/* GPIO2_5, GPIO1 */
         {OFFSET(gpmc_a9), MODE(7)},                           	/* GPIO1_25, GPIO2 */
-        {OFFSET(gpmc_a8), MODE(7)},                            	/* GPIO1_24, GPIO3 */
+        {OFFSET(gpmc_a8), MODE(7) | RXACTIVE},                 	/* GPIO1_24, GPIO3 */
-        {OFFSET(gpmc_wen), MODE(7)},                          	/* GPIO2_4, GPIO4 */
+        {OFFSET(gpmc_wen), MODE(7) | RXACTIVE},                	/* GPIO2_4, GPIO4 */
-        {OFFSET(gpmc_oen_ren), MODE(7)},                      	/* GPIO2_3, GPIO5 */
+        {OFFSET(gpmc_oen_ren), MODE(7) | RXACTIVE},            	/* GPIO2_3, GPIO5 */
         {OFFSET(gpmc_be1n), MODE(7) | RXACTIVE},              	/* GPIO1_28, GPIO6 */
         {OFFSET(gpmc_csn0), MODE(7) | RXACTIVE},               	/* GPIO1_29, GPIO7 */
         {OFFSET(gpmc_csn3), MODE(7) | RXACTIVE},               	/* GPIO2_0, GPIO8 */
-        {OFFSET(gpmc_clk), MODE(7) | RXACTIVE},                	/* GPIO2_1, GPIO9 */
+        {OFFSET(gpmc_clk), MODE(7)},                            /* GPIO2_1, GPIO9 */
-        {OFFSET(emu0), MODE(7)},                              	/* GPIO3_7, GPIO10 for Buzzer */
+        {OFFSET(emu0), MODE(7) | PULLUDEN},                     /* GPIO3_7, GPIO10 for Buzzer */
         {OFFSET(emu1), MODE(7)  | RXACTIVE},                  	/* GPIO3_8, GPIO11 */
-        /* i2c1 (pin37 and pin38 on P1 connector) in SBC-SMART-MEN is set as GPIOs*/
+	{OFFSET(gpmc_advn_ale), MODE(7) | PULLDOWN_EN},        	/* GPIO2_2 WDT_TIMEOUT */
-        {OFFSET(uart1_txd), MODE(7)},                          	/* uart1_txd.gpio0_15 */
+        {OFFSET(gpmc_be0n_cle), MODE(7) | PULLUP_EN},         /* I2C Mux Reset */
-        {OFFSET(uart1_rxd), MODE(7)},                          	/* uart1_rxd.gpio0_14 */
         {-1},
 };
 /* Module pin mux for LCDC */
 static struct module_pin_mux lcdc_pin_mux[] = {
     {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)},                /*lcd_data0",        OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT*/
     {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)},
     {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)},
     {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)},
     {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)},
     {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)},
     {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)},
     {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)},
     {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)},
     {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)},
     {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)},
     {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)},
     {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)},
     {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)},
     {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)},
     {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)},
 //  new signals
     {OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)},
     {OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)},
     {OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)},
     {OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)},
     {OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)},
     {OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)},
     {OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)},
     {OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)},
 //
     {OFFSET(lcd_vsync), (MODE(0) | PULLUDEN)},
     {OFFSET(lcd_hsync), (MODE(0) | PULLUDEN)},
     {OFFSET(lcd_pclk), (MODE(0) | PULLUDEN)},
     {OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDEN)},
     {-1},
  };
 static struct module_pin_mux rgmii1_pin_mux[] = {
 	{OFFSET(mii1_txen), MODE(2)},			/* RGMII1_TCTL */
 	{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE},	/* RGMII1_RCTL */
 	{OFFSET(mii1_txd3), MODE(2)},			/* RGMII1_TD3 */
 	{OFFSET(mii1_txd2), MODE(2)},			/* RGMII1_TD2 */
 	{OFFSET(mii1_txd1), MODE(2)},			/* RGMII1_TD1 */
 	{OFFSET(mii1_txd0), MODE(2)},			/* RGMII1_TD0 */
 	{OFFSET(mii1_txclk), MODE(2)},			/* RGMII1_TCLK */
 	{OFFSET(mii1_rxclk), MODE(2) | RXACTIVE},	/* RGMII1_RCLK */
 	{OFFSET(mii1_rxd3), MODE(2) | RXACTIVE},	/* RGMII1_RD3 */
 	{OFFSET(mii1_rxd2), MODE(2) | RXACTIVE},	/* RGMII1_RD2 */
 	{OFFSET(mii1_rxd1), MODE(2) | RXACTIVE},	/* RGMII1_RD1 */
 	{OFFSET(mii1_rxd0), MODE(2) | RXACTIVE},	/* RGMII1_RD0 */
 	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
 	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
 	{-1},
 };
 static struct module_pin_mux rmii1_pin_mux[] = {
         {OFFSET(mii1_crs), MODE(1) | RXACTIVE},         /* RMII1_CRS */
         {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE},       /* RMII1_RXERR */
         {OFFSET(mii1_txen), MODE(1)},                   /* RMII1_TXEN */
         {OFFSET(mii1_txd1), MODE(1)},                   /* RMII1_TXD1 */
         {OFFSET(mii1_txd0), MODE(1)},                   /* RMII1_TXD0 */
         {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE},        /* RMII1_RXD1 */
         {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE},        /* RMII1_RXD0 */
         {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
         {OFFSET(mdio_clk), MODE(0) | PULLUP_EN},        /* MDIO_CLK */
         {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE},     /* RMII1_REFCLK */
         {-1},
 };
 static struct module_pin_mux rmii2_pin_mux[] = {
         {OFFSET(gpmc_wait0), MODE(3) | RXACTIVE},       /* RMII2_CRS */
         {OFFSET(gpmc_wpn), MODE(3) | RXACTIVE},         /* RMII2_RXERR */
         {OFFSET(gpmc_a0), MODE(3)},                     /* RMII2_TXEN */
         {OFFSET(gpmc_a4), MODE(3)},                     /* RMII2_TXD1 */
         {OFFSET(gpmc_a5), MODE(3)},                     /* RMII2_TXD0 */
         {OFFSET(gpmc_a10), MODE(3) | RXACTIVE},         /* RMII2_RXD1 */
         {OFFSET(gpmc_a11), MODE(3) | RXACTIVE},         /* RMII2_RXD0 */
         {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
         {OFFSET(mdio_clk), MODE(0) | PULLUP_EN},        /* MDIO_CLK */
         {OFFSET(mii1_col), MODE(1) | RXACTIVE},         /* RMII2_REFCLK */
         {-1},
 };
 static struct module_pin_mux mii1_pin_mux[] = {
 	{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE},	/* MII1_RXERR */
 	{OFFSET(mii1_txen), MODE(0)},			/* MII1_TXEN */
 	{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE},	/* MII1_RXDV */
 	{OFFSET(mii1_txd3), MODE(0)},			/* MII1_TXD3 */
 	{OFFSET(mii1_txd2), MODE(0)},			/* MII1_TXD2 */
 	{OFFSET(mii1_txd1), MODE(0)},			/* MII1_TXD1 */
 	{OFFSET(mii1_txd0), MODE(0)},			/* MII1_TXD0 */
 	{OFFSET(mii1_txclk), MODE(0) | RXACTIVE},	/* MII1_TXCLK */
 	{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE},	/* MII1_RXCLK */
 	{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE},	/* MII1_RXD3 */
 	{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE},	/* MII1_RXD2 */
 	{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE},	/* MII1_RXD1 */
 	{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE},	/* MII1_RXD0 */
 	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
 	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
 	{-1},
 };
 #ifdef CONFIG_NAND
 static struct module_pin_mux nand_pin_mux[] = {
 	{OFFSET(gpmc_ad0),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0  */
 	{OFFSET(gpmc_ad1),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1  */
 	{OFFSET(gpmc_ad2),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2  */
 	{OFFSET(gpmc_ad3),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3  */
 	{OFFSET(gpmc_ad4),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4  */
 	{OFFSET(gpmc_ad5),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5  */
 	{OFFSET(gpmc_ad6),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6  */
 	{OFFSET(gpmc_ad7),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7  */
 #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
 	{OFFSET(gpmc_ad8),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8  */
 	{OFFSET(gpmc_ad9),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9  */
 	{OFFSET(gpmc_ad10),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */
 	{OFFSET(gpmc_ad11),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */
 	{OFFSET(gpmc_ad12),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */
 	{OFFSET(gpmc_ad13),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */
 	{OFFSET(gpmc_ad14),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */
 	{OFFSET(gpmc_ad15),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */
 #endif
 	{OFFSET(gpmc_wait0),	(MODE(0) | PULLUP_EN | RXACTIVE)}, /* nWAIT */
 	{OFFSET(gpmc_wpn),	(MODE(7) | PULLUP_EN)},		   /* nWP */
 	{OFFSET(gpmc_csn0),	(MODE(0) | PULLUP_EN)},		   /* nCS */
 	{OFFSET(gpmc_wen),	(MODE(0) | PULLDOWN_EN)},	   /* WEN */
 	{OFFSET(gpmc_oen_ren),	(MODE(0) | PULLDOWN_EN)},	   /* OE */
 	{OFFSET(gpmc_advn_ale),	(MODE(0) | PULLDOWN_EN)},	   /* ADV_ALE */
 	{OFFSET(gpmc_be0n_cle),	(MODE(0) | PULLDOWN_EN)},	   /* BE_CLE */
 	{-1},
 };
 #elif defined(CONFIG_NOR)
 static struct module_pin_mux bone_norcape_pin_mux[] = {
 	{OFFSET(gpmc_a0), MODE(0) | PULLUDDIS},			/* NOR_A0 */
 	{OFFSET(gpmc_a1), MODE(0) | PULLUDDIS},			/* NOR_A1 */
 	{OFFSET(gpmc_a2), MODE(0) | PULLUDDIS},			/* NOR_A2 */
 	{OFFSET(gpmc_a3), MODE(0) | PULLUDDIS},			/* NOR_A3 */
 	{OFFSET(gpmc_a4), MODE(0) | PULLUDDIS},			/* NOR_A4 */
 	{OFFSET(gpmc_a5), MODE(0) | PULLUDDIS},			/* NOR_A5 */
 	{OFFSET(gpmc_a6), MODE(0) | PULLUDDIS},			/* NOR_A6 */
 	{OFFSET(gpmc_a7), MODE(0) | PULLUDDIS},			/* NOR_A7 */
 	{OFFSET(gpmc_ad0), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD0 */
 	{OFFSET(gpmc_ad1), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD1 */
 	{OFFSET(gpmc_ad2), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD2 */
 	{OFFSET(gpmc_ad3), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD3 */
 	{OFFSET(gpmc_ad4), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD4 */
 	{OFFSET(gpmc_ad5), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD5 */
 	{OFFSET(gpmc_ad6), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD6 */
 	{OFFSET(gpmc_ad7), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD7 */
 	{OFFSET(gpmc_ad8), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD8 */
 	{OFFSET(gpmc_ad9), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD9 */
 	{OFFSET(gpmc_ad10), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD10 */
 	{OFFSET(gpmc_ad11), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD11 */
 	{OFFSET(gpmc_ad12), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD12 */
 	{OFFSET(gpmc_ad13), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD13 */
 	{OFFSET(gpmc_ad14), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD14 */
 	{OFFSET(gpmc_ad15), MODE(0) | PULLUDDIS | RXACTIVE},	/* NOR_AD15 */
 	{OFFSET(gpmc_csn0), MODE(0) | PULLUDEN | PULLUP_EN},     /* CE */
 	{OFFSET(gpmc_advn_ale), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* ALE */
 	{OFFSET(gpmc_oen_ren), MODE(0) | PULLUDEN | PULLDOWN_EN},/* OEn_REN */
 	{OFFSET(gpmc_be0n_cle), MODE(0) | PULLUDEN | PULLDOWN_EN},/* unused */
 	{OFFSET(gpmc_wen), MODE(0) | PULLUDEN | PULLDOWN_EN},    /* WEN */
 	{OFFSET(gpmc_wait0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},/*WAIT*/
 	{-1},
 };
 #endif
 #if defined(CONFIG_NOR_BOOT)
 void enable_norboot_pin_mux(void)
 {
 	configure_module_pin_mux(bone_norcape_pin_mux);
 }
 #endif
 void enable_uart0_pin_mux(void)
 {
 	configure_module_pin_mux(uart0_pin_mux);
 }
 void enable_uart1_pin_mux(void)
 {
 	configure_module_pin_mux(uart1_pin_mux);
 }
 void enable_uart2_pin_mux(void)
 {
 	configure_module_pin_mux(uart2_pin_mux);
 }
 void enable_uart3_pin_mux(void)
 {
 	configure_module_pin_mux(uart3_pin_mux);
 }
 void enable_uart4_pin_mux(void)
 {
 	configure_module_pin_mux(uart4_pin_mux);
 }
 void enable_uart5_pin_mux(void)
 {
 	configure_module_pin_mux(uart5_pin_mux);
 }
 void enable_i2c0_pin_mux(void)
 {
 	configure_module_pin_mux(i2c0_pin_mux);
 }
 /*
  * The AM335x GP EVM, if daughter card(s) are connected, can have 8
  * different profiles.  These profiles determine what peripherals are
  * valid and need pinmux to be configured.
  */
 #define PROFILE_NONE	0x0
 #define PROFILE_0	(1 << 0)
 #define PROFILE_1	(1 << 1)
 #define PROFILE_2	(1 << 2)
 #define PROFILE_3	(1 << 3)
 #define PROFILE_4	(1 << 4)
 #define PROFILE_5	(1 << 5)
 #define PROFILE_6	(1 << 6)
 #define PROFILE_7	(1 << 7)
 #define PROFILE_MASK	0x7
 #define PROFILE_ALL	0xFF
 /* CPLD registers */
 #define I2C_CPLD_ADDR	0x35
 #define CFG_REG		0x10
 static unsigned short detect_daughter_board_profile(void)
 {
 	unsigned short val;
 	if (i2c_probe(I2C_CPLD_ADDR))
 		return PROFILE_NONE;
 	if (i2c_read(I2C_CPLD_ADDR, CFG_REG, 1, (unsigned char *)(&val), 2))
 		return PROFILE_NONE;
 	return (1 << (val & PROFILE_MASK));
 }
 void enable_board_pin_mux(struct am335x_baseboard_id *header)
 {
 	/* Do board-specific muxes. */
 	if (board_is_bone(header)) {
 		/* Beaglebone pinmux */
-		configure_module_pin_mux(i2c1_pin_mux);
 		configure_module_pin_mux(mii1_pin_mux);
 		configure_module_pin_mux(mmc0_pin_mux);
 #if defined(CONFIG_NAND)
 		configure_module_pin_mux(nand_pin_mux);
 #elif defined(CONFIG_NOR)
 		configure_module_pin_mux(bone_norcape_pin_mux);
 #else
 		configure_module_pin_mux(mmc1_pin_mux);
 #endif
 	} else if (board_is_gp_evm(header)) {
 		/* General Purpose EVM */
 		unsigned short profile = detect_daughter_board_profile();
 		configure_module_pin_mux(rgmii1_pin_mux);
 		configure_module_pin_mux(mmc0_pin_mux);
-		/* In profile #2 i2c1 and spi0 conflict. */
-		if (profile & ~PROFILE_2)
-			configure_module_pin_mux(i2c1_pin_mux);
 		/* Profiles 2 & 3 don't have NAND */
 #ifdef CONFIG_NAND
 		if (profile & ~(PROFILE_2 | PROFILE_3))
 			configure_module_pin_mux(nand_pin_mux);
 #endif
-		else if (profile == PROFILE_2) {
+		if (profile == PROFILE_2) {
 			configure_module_pin_mux(mmc1_pin_mux);
 			configure_module_pin_mux(spi0_pin_mux);
 		}
 	} else if (board_is_idk(header)) {
 		/* Industrial Motor Control (IDK) */
 		configure_module_pin_mux(mii1_pin_mux);
 		configure_module_pin_mux(mmc0_no_cd_pin_mux);
 	} else if (board_is_evm_sk(header)) {
 		/* Starter Kit EVM */
-		configure_module_pin_mux(i2c1_pin_mux);
 		configure_module_pin_mux(gpio0_7_pin_mux);
 		configure_module_pin_mux(rgmii1_pin_mux);
 		configure_module_pin_mux(mmc0_pin_mux_sk_evm);
 	} else if (board_is_bone_lt(header)) {
 		/* Beaglebone LT pinmux */
-		configure_module_pin_mux(i2c1_pin_mux);
 		configure_module_pin_mux(mii1_pin_mux);
 		configure_module_pin_mux(mmc0_pin_mux);
 #if defined(CONFIG_NAND) && defined(CONFIG_EMMC_BOOT)
 		configure_module_pin_mux(nand_pin_mux);
 #elif defined(CONFIG_NOR) && defined(CONFIG_EMMC_BOOT)
 		configure_module_pin_mux(bone_norcape_pin_mux);
 #else
 		configure_module_pin_mux(mmc1_pin_mux);
 #endif
         } else if (!strncmp(header->name, "SMARCT33", HDR_NAME_LEN)) {
                 /* SMARC T335X pinmux */
-                /* i2c1 (pin37 and pin38 on P1 connector) in SBC-SMART-MEN is set as GPIOs*/
-        /*      configure_module_pin_mux(i2c1_pin_mux);*/
                 configure_module_pin_mux(mmc0_pin_mux);
                 configure_module_pin_mux(mmc1_pin_mux);
+		configure_module_pin_mux(uart0_pin_mux);
+		configure_module_pin_mux(uart1_pin_mux);
                 configure_module_pin_mux(uart3_pin_mux);
                 configure_module_pin_mux(rmii1_pin_mux);
                 configure_module_pin_mux(rmii2_pin_mux);
                 configure_module_pin_mux(smarc_gpio_pin_mux);
                 configure_module_pin_mux(spi0_pin_mux);
+		configure_module_pin_mux(spi1_pin_mux);
                 configure_module_pin_mux(lcdc_pin_mux);
         } else if (!strncmp(header->name, "SMARCT80", HDR_NAME_LEN)) {
                 /* SMARC T335X 800MHz pinmux */
-                configure_module_pin_mux(i2c1_pin_mux);
                 configure_module_pin_mux(mmc0_pin_mux);
                 configure_module_pin_mux(mmc1_pin_mux);
+                configure_module_pin_mux(uart0_pin_mux);
+                configure_module_pin_mux(uart1_pin_mux);
                 configure_module_pin_mux(uart3_pin_mux);
                 configure_module_pin_mux(rmii1_pin_mux);
                 configure_module_pin_mux(rmii2_pin_mux);
                 configure_module_pin_mux(smarc_gpio_pin_mux);
                 configure_module_pin_mux(spi0_pin_mux);
+		configure_module_pin_mux(spi1_pin_mux);
                 configure_module_pin_mux(lcdc_pin_mux);

drivers/i2c/i2c_core.c

Diff comments View file @ 35e07b9

 /*
  * Copyright (C) 2009 Sergey Kubushyn <ksi@koi8.net>
  *
  * (C) Copyright 2012
  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  *
  * Multibus/multiadapter I2C core functions (wrappers)
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
 #include <i2c.h>
 struct i2c_adapter *i2c_get_adapter(int index)
 {
 	struct i2c_adapter *i2c_adap_p = ll_entry_start(struct i2c_adapter,
 						i2c);
 	int max = ll_entry_count(struct i2c_adapter, i2c);
 	int i;
 	if (index >= max) {
 		printf("Error, wrong i2c adapter %d max %d possible\n",
 		       index, max);
 		return i2c_adap_p;
 	}
 	if (index == 0)
 		return i2c_adap_p;
 	for (i = 0; i < index; i++)
 		i2c_adap_p++;
 	return i2c_adap_p;
 }
 #if !defined(CONFIG_SYS_I2C_DIRECT_BUS)
 struct i2c_bus_hose i2c_bus[CONFIG_SYS_NUM_I2C_BUSES] =
 			CONFIG_SYS_I2C_BUSES;
 #endif
 DECLARE_GLOBAL_DATA_PTR;
 void i2c_reloc_fixup(void)
 {
 #if defined(CONFIG_NEEDS_MANUAL_RELOC)
 	struct i2c_adapter *i2c_adap_p = ll_entry_start(struct i2c_adapter,
 						i2c);
 	struct i2c_adapter *tmp = i2c_adap_p;
 	int max = ll_entry_count(struct i2c_adapter, i2c);
 	int		i;
 	unsigned long	addr;
 	if (gd->reloc_off == 0)
 		return;
 	for (i = 0; i < max; i++) {
 		/* i2c_init() */
 		addr = (unsigned long)i2c_adap_p->init;
 		addr += gd->reloc_off;
 		i2c_adap_p->init = (void *)addr;
 		/* i2c_probe() */
 		addr = (unsigned long)i2c_adap_p->probe;
 		addr += gd->reloc_off;
 		i2c_adap_p->probe = (void *)addr;
 		/* i2c_read() */
 		addr = (unsigned long)i2c_adap_p->read;
 		addr += gd->reloc_off;
 		i2c_adap_p->read = (void *)addr;
 		/* i2c_write() */
 		addr = (unsigned long)i2c_adap_p->write;
 		addr += gd->reloc_off;
 		i2c_adap_p->write = (void *)addr;
 		/* i2c_set_bus_speed() */
 		addr = (unsigned long)i2c_adap_p->set_bus_speed;
 		addr += gd->reloc_off;
 		i2c_adap_p->set_bus_speed = (void *)addr;
 		/* name */
 		addr = (unsigned long)i2c_adap_p->name;
 		addr += gd->reloc_off;
 		i2c_adap_p->name = (char *)addr;
 		tmp++;
 		i2c_adap_p = tmp;
 	}
 #endif
 }
 #ifndef CONFIG_SYS_I2C_DIRECT_BUS
 /*
  * i2c_mux_set()
  * -------------
  *
  * This turns on the given channel on I2C multiplexer chip connected to
  * a given I2C adapter directly or via other multiplexers. In the latter
  * case the entire multiplexer chain must be initialized first starting
  * with the one connected directly to the adapter. When disabling a chain
  * muxes must be programmed in reverse order, starting with the one
  * farthest from the adapter.
  *
  * mux_id is the multiplexer chip type from defined in i2c.h. So far only
  * NXP (Philips) PCA954x multiplexers are supported. Switches are NOT
  * supported (anybody uses them?)
  */
 static int i2c_mux_set(struct i2c_adapter *adap, int mux_id, int chip,
 			int channel)
 {
 	uint8_t	buf;
 	int ret;
 	/* channel < 0 - turn off the mux */
 	if (channel < 0) {
 		buf = 0;
 		ret = adap->write(adap, chip, 0, 0, &buf, 1);
 		if (ret)
 			printf("%s: Could not turn off the mux.\n", __func__);
 		return ret;
 	}
 	switch (mux_id) {
 	case I2C_MUX_PCA9540_ID:
 	case I2C_MUX_PCA9542_ID:
 		if (channel > 1)
 			return -1;
 		buf = (uint8_t)((channel & 0x01) | (1 << 2));
 		break;
 	case I2C_MUX_PCA9544_ID:
 		if (channel > 3)
 			return -1;
 		buf = (uint8_t)((channel & 0x03) | (1 << 2));
 		break;
+       	case I2C_MUX_PCA9546_ID:
+               	if (channel > 4)
+                       	return -1;
+               	buf = (uint8_t)((channel & 0x04) | (1 << 3));
+               	break;
 	case I2C_MUX_PCA9547_ID:
 		if (channel > 7)
 			return -1;
 		buf = (uint8_t)((channel & 0x07) | (1 << 3));
 		break;
 	case I2C_MUX_PCA9548_ID:
 		if (channel > 7)
 			return -1;
 		buf = (uint8_t)(0x01 << channel);
 		break;
 	default:
 		printf("%s: wrong mux id: %d\n", __func__, mux_id);
 		return -1;
 	}
 	ret = adap->write(adap, chip, 0, 0, &buf, 1);
 	if (ret)
 		printf("%s: could not set mux: id: %d chip: %x channel: %d\n",
 		       __func__, mux_id, chip, channel);
 	return ret;
 }
 static int i2c_mux_set_all(void)
 {
 	struct i2c_bus_hose *i2c_bus_tmp = &i2c_bus[I2C_BUS];
 	int i;
 	/* Connect requested bus if behind muxes */
 	if (i2c_bus_tmp->next_hop[0].chip != 0) {
 		/* Set all muxes along the path to that bus */
 		for (i = 0; i < CONFIG_SYS_I2C_MAX_HOPS; i++) {
 			int	ret;
 			if (i2c_bus_tmp->next_hop[i].chip == 0)
 				break;
 			ret = i2c_mux_set(I2C_ADAP,
 					i2c_bus_tmp->next_hop[i].mux.id,
 					i2c_bus_tmp->next_hop[i].chip,
 					i2c_bus_tmp->next_hop[i].channel);
 			if (ret != 0)
 				return ret;
 		}
 	}
 	return 0;
 }
 static int i2c_mux_disconnect_all(void)
 {
 	struct	i2c_bus_hose *i2c_bus_tmp = &i2c_bus[I2C_BUS];
 	int	i;
 	uint8_t	buf = 0;
 	if (I2C_ADAP->init_done == 0)
 		return 0;
 	/* Disconnect current bus (turn off muxes if any) */
 	if ((i2c_bus_tmp->next_hop[0].chip != 0) &&
 	    (I2C_ADAP->init_done != 0)) {
 		i = CONFIG_SYS_I2C_MAX_HOPS;
 		do {
 			uint8_t	chip;
 			int ret;
 			chip = i2c_bus_tmp->next_hop[--i].chip;
 			if (chip == 0)
 				continue;
 			ret = I2C_ADAP->write(I2C_ADAP, chip, 0, 0, &buf, 1);
 			if (ret != 0) {
 				printf("i2c: mux disconnect error\n");
 				return ret;
 			}
 		} while (i > 0);
 	}
 	return 0;
 }
 #endif
 /*
  * i2c_init_bus():
  * ---------------
  *
  * Initializes one bus. Will initialize the parent adapter. No current bus
  * changes, no mux (if any) setup.
  */
 static void i2c_init_bus(unsigned int bus_no, int speed, int slaveaddr)
 {
 	if (bus_no >= CONFIG_SYS_NUM_I2C_BUSES)
 		return;
 	I2C_ADAP->init(I2C_ADAP, speed, slaveaddr);
 	if (gd->flags & GD_FLG_RELOC) {
 		I2C_ADAP->init_done = 1;
 		I2C_ADAP->speed = speed;
 		I2C_ADAP->slaveaddr = slaveaddr;
 	}
 }
 /* implement possible board specific board init */
 __weak void i2c_init_board(void)
 {
 }
 /*
  * i2c_init_all():
  *
  * not longer needed, will deleted. Actual init the SPD_BUS
  * for compatibility.
  * i2c_adap[] must be initialized beforehead with function pointers and
  * data, including speed and slaveaddr.
  */
 void i2c_init_all(void)
 {
 	i2c_init_board();
 	i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
 	return;
 }
 /*
  * i2c_get_bus_num():
  * ------------------
  *
  *  Returns index of currently active I2C bus.  Zero-based.
  */
 unsigned int i2c_get_bus_num(void)
 {
 	return gd->cur_i2c_bus;
 }
 /*
  * i2c_set_bus_num():
  * ------------------
  *
  *  Change the active I2C bus. Subsequent read/write calls will
  *  go to this one. Sets all of the muxes in a proper condition
  *  if that bus is behind muxes.
  *  If previously selected bus is behind the muxes turns off all the
  *  muxes along the path to that bus.
  *
  *	bus - bus index, zero based
  *
  *	Returns: 0 on success, not 0 on failure
  */
 int i2c_set_bus_num(unsigned int bus)
 {
 	int max;
 	if ((bus == I2C_BUS) && (I2C_ADAP->init_done > 0))
 		return 0;
 #ifndef CONFIG_SYS_I2C_DIRECT_BUS
 	if (bus >= CONFIG_SYS_NUM_I2C_BUSES)
 		return -1;
 #endif
 	max = ll_entry_count(struct i2c_adapter, i2c);
 	if (I2C_ADAPTER(bus) >= max) {
 		printf("Error, wrong i2c adapter %d max %d possible\n",
 		       I2C_ADAPTER(bus), max);
 		return -2;
 	}
 #ifndef CONFIG_SYS_I2C_DIRECT_BUS
 	i2c_mux_disconnect_all();
 #endif
 	gd->cur_i2c_bus = bus;
 	if (I2C_ADAP->init_done == 0)
 		i2c_init_bus(bus, I2C_ADAP->speed, I2C_ADAP->slaveaddr);
 #ifndef CONFIG_SYS_I2C_DIRECT_BUS
 	i2c_mux_set_all();
 #endif
 	return 0;
 }
 /*
  * Probe the given I2C chip address.  Returns 0 if a chip responded,
  * not 0 on failure.
  */
 int i2c_probe(uint8_t chip)
 {
 	return I2C_ADAP->probe(I2C_ADAP, chip);
 }
 /*
  * Read/Write interface:
  *   chip:    I2C chip address, range 0..127
  *   addr:    Memory (register) address within the chip
  *   alen:    Number of bytes to use for addr (typically 1, 2 for larger
  *              memories, 0 for register type devices with only one
  *              register)
  *   buffer:  Where to read/write the data
  *   len:     How many bytes to read/write
  *
  *   Returns: 0 on success, not 0 on failure
  */
 int i2c_read(uint8_t chip, unsigned int addr, int alen,
 				uint8_t *buffer, int len)
 {
 	return I2C_ADAP->read(I2C_ADAP, chip, addr, alen, buffer, len);
 }
 int i2c_write(uint8_t chip, unsigned int addr, int alen,
 				uint8_t *buffer, int len)
 {
 	return I2C_ADAP->write(I2C_ADAP, chip, addr, alen, buffer, len);
 }
 unsigned int i2c_set_bus_speed(unsigned int speed)
 {
 	unsigned int ret;
 	if (I2C_ADAP->set_bus_speed == NULL)
 		return 0;
 	ret = I2C_ADAP->set_bus_speed(I2C_ADAP, speed);
 	if (gd->flags & GD_FLG_RELOC)
 		I2C_ADAP->speed = (ret == 0) ? speed : 0;
 	return ret;
 }
 unsigned int i2c_get_bus_speed(void)
 {
 	struct i2c_adapter *cur = I2C_ADAP;
 	return cur->speed;
 }
 uint8_t i2c_reg_read(uint8_t addr, uint8_t reg)
 {
 	uint8_t buf;
 #ifdef CONFIG_8xx
 	/* MPC8xx needs this.  Maybe one day we can get rid of it. */
 	/* maybe it is now the time for it ... */
 	i2c_set_bus_num(i2c_get_bus_num());
 #endif
 	i2c_read(addr, reg, 1, &buf, 1);
 #ifdef DEBUG
 	printf("%s: bus=%d addr=0x%02x, reg=0x%02x, val=0x%02x\n",
 	       __func__, i2c_get_bus_num(), addr, reg, buf);
 #endif
 	return buf;
 }
 void i2c_reg_write(uint8_t addr, uint8_t reg, uint8_t val)
 {
 #ifdef CONFIG_8xx
 	/* MPC8xx needs this.  Maybe one day we can get rid of it. */
 	/* maybe it is now the time for it ... */
 	i2c_set_bus_num(i2c_get_bus_num());
 #endif
 #ifdef DEBUG
 	printf("%s: bus=%d addr=0x%02x, reg=0x%02x, val=0x%02x\n",
 	       __func__, i2c_get_bus_num(), addr, reg, val);
 #endif
 	i2c_write(addr, reg, 1, &val, 1);
 }
 __weak void i2c_init(int speed, int slaveaddr)
 {
 	i2c_init_bus(i2c_get_bus_num(), speed, slaveaddr);
 }

include/configs/smarct335x_evm.h

Diff comments View file @ 35e07b9

 /*
  * am335x_evm.h
  *
  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation version 2.
  *
  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  * kind, whether express or implied; without even the implied warranty
  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  */
 #ifndef __CONFIG_SMARCT335X_EVM_H
 #define __CONFIG_SMARCT335X_EVM_H
 #include <configs/embedian_am335x_common.h>
 #define CONFIG_ENV_IS_NOWHERE
 #ifndef CONFIG_SPL_BUILD
 # define CONFIG_TIMESTAMP
 # define CONFIG_LZO
 #endif
 #define CONFIG_SYS_BOOTM_LEN		(16 << 20)
 #define MACH_TYPE_SMARCT335XEVM		3600	/* Until the next sync */
 #define CONFIG_MACH_TYPE		MACH_TYPE_SMARCT335XEVM
 #define CONFIG_BOARD_LATE_INIT
 /* Clock Defines */
 #define V_OSCK				24000000  /* Clock output from T2 */
 #define V_SCLK				(V_OSCK)
 /* Custom script for NOR */
 #define CONFIG_SYS_LDSCRIPT		"board/embedian/smarct335x/u-boot.lds"
 /* Always 128 KiB env size */
 #define CONFIG_ENV_SIZE			(128 << 10)
 /* Enhance our eMMC support / experience. */
 #define CONFIG_CMD_GPT
 #define CONFIG_EFI_PARTITION
 /* Enable Atheros phy driver */
 /* #define CONFIG_PHY_ATHEROS */
 #ifdef CONFIG_NAND
 #define NANDARGS \
 	"mtdids=" MTDIDS_DEFAULT "\0" \
 	"mtdparts=" MTDPARTS_DEFAULT "\0" \
 	"nandargs=setenv bootargs console=${console} " \
 		"${optargs} " \
 		"root=${nandroot} " \
 		"rootfstype=${nandrootfstype}\0" \
 	"nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system,2048\0" \
 	"nandrootfstype=ubifs rootwait=1\0" \
 	"nandboot=echo Booting from nand ...; " \
 		"run nandargs; " \
 		"nand read ${fdtaddr} NAND.u-boot-spl-os; " \
 		"nand read ${loadaddr} NAND.kernel; " \
 		"bootz ${loadaddr} - ${fdtaddr}\0"
 #else
 #define NANDARGS ""
 #endif
 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 #define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \
 	"bootcmd_" #devtypel #instance "=" \
 	"setenv mmcdev " #instance"; "\
 	"setenv bootpart " #instance":2 ; "\
 	"run mmcboot\0"
 #define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \
 	#devtypel #instance " "
 #define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \
 	"bootcmd_" #devtypel "=" \
 	"run nandboot\0"
 #define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
 	#devtypel #instance " "
 #define BOOT_TARGET_DEVICES(func) \
 	func(MMC, mmc, 0) \
 	func(LEGACY_MMC, legacy_mmc, 0) \
 	func(MMC, mmc, 1) \
 	func(LEGACY_MMC, legacy_mmc, 1) \
 	func(NAND, nand, 0) \
 	func(PXE, pxe, na) \
 	func(DHCP, dhcp, na)
 #define CONFIG_BOOTCOMMAND \
+	"i2c mw 0x24 1 0x3e;" \
         "setenv umsmedia 0; "\
-        "i2c mw 0x24 1 0x3e; " \
         "run findfdt; " \
         "run finduuid; " \
         "run mmcboot;" \
         "run failumsboot;"
 #include <config_distro_bootcmd.h>
 #ifndef CONFIG_SPL_BUILD
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	DEFAULT_LINUX_BOOT_ENV \
 	DEFAULT_MMC_TI_ARGS \
 	"boot_fdt=try\0" \
         "mmcdev=0\0" \
         "bootpart=${mmcdev}:1\0" \
 	"bootdir=\0" \
         "fdtdir=/dtbs\0" \
 	"bootfile=zImage\0" \
 	"fdtfile=undefined\0" \
 	"console=ttyO3,115200n8\0" \
 	"partitions=" \
 		"uuid_disk=${uuid_gpt_disk};" \
 		"name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \
 	"optargs=\0" \
         "cape_disable=\0" \
         "cape_enable=\0" \
         "cmdline=\0" \
         "mmcpart=1\0" \
 	"ramroot=/dev/ram0 rw\0" \
 	"ramrootfstype=ext2\0" \
 	"spiroot=/dev/mtdblock4 rw\0" \
 	"spirootfstype=jffs2\0" \
 	"spisrcaddr=0xe0000\0" \
 	"spiimgsize=0x362000\0" \
 	"spibusno=0\0" \
 	"spiargs=setenv bootargs console=${console} " \
 		"${optargs} " \
 		"root=${spiroot} " \
 		"rootfstype=${spirootfstype}\0" \
         "bootenv=uEnv.txt\0" \
         "server_ip=192.168.1.110\0" \
         "gw_ip=192.168.1.254\0" \
         "netmask=255.255.255.0\0" \
         "hostname=smarct335x\0" \
         "device=eth0\0" \
         "autoconf=off\0" \
         "root_dir=/home/userid/targetNFS\0" \
         "tftp_dir=\0" \
         "nfs_options=,vers=3\0" \
         "nfsrootfstype=ext4 rootwait fixrtc\0" \
         "nfsargs=setenv bootargs console=${console} " \
                 "${optargs} " \
                 "${cape_disable} " \
                 "${cape_enable} " \
                 "root=/dev/nfs rw " \
                 "rootfstype=${nfsrootfstype} " \
                 "nfsroot=${nfsroot} " \
                 "ip=${ip} " \
                 "${cmdline}\0" \
         "spiroot=/dev/mtdblock4 rw\0" \
         "spirootfstype=jffs2\0" \
         "spisrcaddr=0xe0000\0" \
         "spiimgsize=0x362000\0" \
         "spibusno=0\0" \
                 "root=${spiroot} " \
                 "rootfstype=${spirootfstype}\0" \
         "bootenv=uEnv.txt\0" \
         "script=boot.scr\0" \
         "scriptfile=${script}\0" \
         "loadbootscript=load mmc ${bootpart} ${loadaddr} ${scriptfile};\0" \
         "bootscript=echo Running bootscript from mmc${bootpart} ...; " \
                 "source ${loadaddr}\0" \
         "loadbootenv=load mmc ${bootpart} ${loadaddr} ${bootenv}\0" \
         "importbootenv=echo Importing environment from mmc ...; " \
                 "env import -t -r $loadaddr $filesize\0" \
 	"ramargs=setenv bootargs console=${console} " \
 		"${optargs} " \
 		"root=${ramroot} " \
 		"rootfstype=${ramrootfstype}\0" \
 	"loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
 	"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
         "loadrd=load mmc ${bootpart} ${rdaddr} ${bootdir}/${rdfile}; setenv rdsize ${filesize}\0" \
         "loadfdt=echo loading ${fdtdir}/${fdtfile} ...; load mmc ${bootpart} ${fdtaddr} ${fdtdir}/${fdtfile}\0" \
         "failumsboot=echo; echo FAILSAFE: U-Boot UMS (USB Mass Storage) enabled, media now available over the usb slave port ...; " \
                "ums 0 mmc ${umsmedia};\0" \
 	"mmcloados=run args_mmc; " \
 		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
 			"if run loadfdt; then " \
 				"bootz ${loadaddr} - ${fdtaddr}; " \
 			"else " \
 				"if test ${boot_fdt} = try; then " \
 					"bootz; " \
 				"else " \
 					"echo WARN: Cannot load the DT; " \
 				"fi; " \
 			"fi; " \
 		"else " \
 			"bootz; " \
 		"fi;\0" \
         "mmcboot=mmc dev ${mmcdev}; " \
                 "if mmc rescan; then " \
                         "gpio set 51;" \
                         "setenv bootpart ${mmcdev}:1; " \
                         "if test -e mmc ${bootpart} /etc/fstab; then " \
                                "setenv mmcpart 1;" \
                        "fi; " \
                        "echo Checking for: /uEnv.txt ...;" \
                        "if test -e mmc ${bootpart} /uEnv.txt; then " \
                                 "if run loadbootenv; then " \
                                         "gpio set 54;" \
                                         "gpio set 55;" \
                                         "echo Loaded environment from ${bootenv};" \
                                         "run importbootenv;" \
                                         "gpio set 7;" \
                                 "fi;" \
                                 "if test -n ${cape}; then " \
                                         "if test -e mmc ${bootpart} ${fdtdir}/${fdtbase}-${cape}.dtb; then " \
                                                "setenv fdtfile ${fdtbase}-${cape}.dtb; " \
                                         "fi; " \
                                         "echo using: $fdtfile...; " \
                                 "fi; " \
                                 "echo Checking if uenvcmd is set ...;" \
                                 "if test -n ${uenvcmd}; then " \
                                         "echo Running uenvcmd ...;" \
                                         "run uenvcmd;" \
                                 "fi;" \
                                 "echo Checking if client_ip is set ...;" \
                                 "if test -n ${client_ip}; then " \
                                         "if test -n ${dtb}; then " \
                                                 "setenv fdtfile ${dtb};" \
                                                 "echo using ${fdtfile} ...;" \
                                         "fi;" \
                                         "if test -n ${uname_r}; then " \
                                                 "echo Running nfsboot_uname_r ...;" \
                                                 "run nfsboot_uname_r;" \
                                         "fi;" \
                                         "echo Running nfsboot ...;" \
                                         "run nfsboot;" \
                                 "fi;" \
                         "fi; " \
                         "echo Checking for: /${script} ...;" \
                         "if test -e mmc ${bootpart} /${script}; then " \
                                 "gpio set 54;" \
                                 "gpio set 55;" \
                                 "setenv scriptfile ${script};" \
                                 "run loadbootscript;" \
                                 "echo Loaded script from ${scriptfile};" \
                                 "gpio set 7; " \
                                 "run bootscript;" \
                         "fi; " \
                         "echo Checking for: /boot/${script} ...;" \
                         "if test -e mmc ${bootpart} /boot/${script}; then " \
                                 "gpio set 54;" \
                                 "gpio set 55;" \
                                 "setenv scriptfile /boot/${script};" \
                                 "run loadbootscript;" \
                                 "echo Loaded script from ${scriptfile};" \
                                 "gpio set 7; " \
                                 "run bootscript;" \
                         "fi; " \
                         "echo Checking for: /boot/uEnv.txt ...;" \
                         "for i in 1 2 3 4 5 6 7 ; do " \
                                 "setenv mmcpart ${i};" \
                                 "setenv bootpart ${mmcdev}:${mmcpart};" \
                                 "if test -e mmc ${bootpart} /boot/uEnv.txt; then " \
                                         "gpio set 54;" \
                                         "gpio set 55;" \
                                         "load mmc ${bootpart} ${loadaddr} /boot/uEnv.txt;" \
                                         "env import -t ${loadaddr} ${filesize};" \
                                         "echo Loaded environment from /boot/uEnv.txt;" \
                                         "if test -n ${dtb}; then " \
                                                 "setenv fdtfile ${dtb};" \
                                                 "echo Using: dtb=${fdtfile} ...;" \
                                         "fi;" \
                                         "echo Checking if uname_r is set in /boot/uEnv.txt...;" \
                                         "if test -n ${uname_r}; then " \
                                                 "gpio set 7; " \
                                                 "echo Running uname_boot ...;" \
                                                 "setenv mmcroot /dev/mmcblk${mmcdev}p${mmcpart} ro;" \
                                                "run uname_boot;" \
                                         "fi;" \
                                 "fi;" \
                         "done;" \
                 "fi;\0" \
 	"spiboot=echo Booting from spi ...; " \
 		"run spiargs; " \
 		"sf probe ${spibusno}:0; " \
 		"sf read ${loadaddr} ${spisrcaddr} ${spiimgsize}; " \
 		"bootz ${loadaddr}\0" \
         "nfsboot=echo Booting from ${server_ip} ...; " \
                 "setenv nfsroot ${server_ip}:${root_dir}${nfs_options}; " \
                 "setenv ip ${client_ip}:${server_ip}:${gw_ip}:${netmask}:${hostname}:${device}:${autoconf}; " \
                 "setenv autoload no; " \
                 "setenv serverip ${server_ip}; " \
                 "setenv ipaddr ${client_ip}; " \
                 "tftp ${loadaddr} ${tftp_dir}${bootfile}; " \
                 "tftp ${fdtaddr} ${tftp_dir}dtbs/${fdtfile}; " \
                 "run nfsargs; " \
                 "bootz ${loadaddr} - ${fdtaddr}\0" \
         "nfsboot_uname_r=echo Booting from ${server_ip} ...; " \
                 "setenv nfsroot ${server_ip}:${root_dir}${nfs_options}; " \
                 "setenv ip ${client_ip}:${server_ip}:${gw_ip}:${netmask}:${hostname}:${device}:${autoconf}; " \
                 "setenv autoload no; " \
                 "setenv serverip ${server_ip}; " \
                 "setenv ipaddr ${client_ip}; " \
                 "tftp ${loadaddr} ${tftp_dir}vmlinuz-${uname_r}; " \
                 "tftp ${fdtaddr} ${tftp_dir}dtbs/${uname_r}/${fdtfile}; " \
                 "run nfsargs; " \
                 "bootz ${loadaddr} - ${fdtaddr}\0" \
 	"ramboot=echo Booting from ramdisk ...; " \
 		"run ramargs; " \
 		"bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \
 	"findfdt="\
 		"if test $board_name = A335BONE; then " \
 			"setenv fdtfile am335x-bone.dtb; fi; " \
 		"if test $board_name = A335BNLT; then " \
 			"setenv fdtfile am335x-boneblack.dtb; fi; " \
 		"if test $board_name = BBG1; then " \
 			"setenv fdtfile am335x-bonegreen.dtb; fi; " \
 		"if test $board_name = A33515BB; then " \
 			"setenv fdtfile am335x-evm.dtb; fi; " \
 		"if test $board_name = A335X_SK; then " \
 			"setenv fdtfile am335x-evmsk.dtb; fi; " \
 		"if test $board_name = A335_ICE; then " \
 			"setenv fdtfile am335x-icev2.dtb; fi; " \
                 "if test $board_name = SMARCT33; then " \
                         "setenv fdtfile am335x-smarct335x.dtb; setenv fdtbase am335x-smarct335x; fi; " \
                 "if test $board_name = SMARCT80; then " \
                         "setenv fdtfile am335x-smarct335x.dtb; setenv fdtbase am335x-smarct335x; fi; " \
                 "if test $board_name = SMARCT1G; then " \
                         "setenv fdtfile am335x-smarct335x.dtb; setenv fdtbase am335x-smarct335x; fi; " \
 		"if test $fdtfile = undefined; then " \
 			"echo WARNING: Could not determine device tree to use; fi; \0" \
 	"init_console=" \
 		"if test $board_name = A335_ICE; then "\
 			"setenv console ttyO3,115200n8;" \
 		"else " \
 			"setenv console ttyS3,115200n8;" \
 		"fi;\0" \
         "uname_boot="\
                 "if test -e mmc ${bootpart} ${bootdir}/${bootfile}; then " \
                         "echo loading ${bootdir}/${bootfile} ...; "\
                         "run loadimage;" \
                         "setenv fdtdir /boot/dtbs/${uname_r}; " \
                         "if test -e mmc ${bootpart} ${fdtdir}/${fdtfile}; then " \
                                 "run loadfdt;" \
                         "else " \
                                 "setenv fdtdir /usr/lib/linux-image-${uname_r}; " \
                                 "if test -e mmc ${bootpart} ${fdtdir}/${fdtfile}; then " \
                                         "run loadfdt;" \
                                 "else " \
                                         "setenv fdtdir /lib/firmware/${uname_r}/device-tree; " \
                                         "if test -e mmc ${bootpart} ${fdtdir}/${fdtfile}; then " \
                                                 "run loadfdt;" \
                                         "else " \
                                                 "setenv fdtdir /boot/dtb-${uname_r}; " \
                                                 "if test -e mmc ${bootpart} ${fdtdir}/${fdtfile}; then " \
                                                         "run loadfdt;" \
                                                 "else " \
                                                         "setenv fdtdir /boot/dtbs; " \
                                                         "if test -e mmc ${bootpart} ${fdtdir}/${fdtfile}; then " \
                                                                 "run loadfdt;" \
                                                         "else " \
                                                                 "setenv fdtdir /boot/dtb; " \
                                                                 "if test -e mmc ${bootpart} ${fdtdir}/${fdtfile}; then " \
                                                                         "run loadfdt;" \
                                                                 "else " \
                                                                         "setenv fdtdir /boot; " \
                                                                         "if test -e mmc ${bootpart} ${fdtdir}/${fdtfile}; then " \
                                                                                 "run loadfdt;" \
                                                                         "else " \
                                                                                 "if test -e mmc ${bootpart} ${fdtfile}; then " \
                                                                                         "run loadfdt;" \
                                                                                 "else " \
                                                                                         "echo; echo unable to find [dtb=${fdtfile}] did you name it correctly? ...; " \
                                                                                         "run failumsboot;" \
                                                                                 "fi;" \
                                                                         "fi;" \
                                                                 "fi;" \
                                                         "fi;" \
                                                 "fi;" \
                                         "fi;" \
                                 "fi;" \
                         "fi; " \
                         "setenv rdfile initrd.img-${uname_r}; " \
                         "if test -e mmc ${bootpart} ${bootdir}/${rdfile}; then " \
                                 "echo loading ${bootdir}/${rdfile} ...; "\
                                 "run loadrd;" \
                                 "if test -n ${uuid}; then " \
                                         "setenv mmcroot UUID=${uuid} ro;" \
                                 "fi;" \
                                 "run args_mmc;" \
                                 "echo debug: [${bootargs}] ... ;" \
                                 "echo debug: [bootz ${loadaddr} ${rdaddr}:${rdsize} ${fdtaddr}] ... ;" \
                                 "bootz ${loadaddr} ${rdaddr}:${rdsize} ${fdtaddr}; " \
                                 "bootz ${loadaddr} ${rdaddr}:${rdsize} ${fdtaddr}; " \
                         "else " \
                                 "run args_mmc;" \
                                 "echo debug: [${bootargs}] ... ;" \
                                 "echo debug: [bootz ${loadaddr} - ${fdtaddr}] ... ;" \
                                 "bootz ${loadaddr} - ${fdtaddr}; " \
                         "fi;" \
                 "fi;\0" \
 	NANDARGS \
 	NETARGS \
 	DFUARGS \
 	BOOTENV
 #endif
 /* NS16550 Configuration */
 #define CONFIG_SYS_NS16550_COM1		0x44e09000	/* Base EVM has UART0 */
 #define CONFIG_SYS_NS16550_COM2		0x48022000	/* UART1 */
 #define CONFIG_SYS_NS16550_COM3		0x48024000	/* UART2 */
 #define CONFIG_SYS_NS16550_COM4		0x481a6000	/* UART3 */
 #define CONFIG_SYS_NS16550_COM5		0x481a8000	/* UART4 */
 #define CONFIG_SYS_NS16550_COM6		0x481aa000	/* UART5 */
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_CMD_EEPROM
 #define CONFIG_ENV_EEPROM_IS_ON_I2C
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* Main EEPROM */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
 #define CONFIG_SYS_I2C_MULTI_EEPROMS
+/* I2C SER definitions for DS90UH925 chip */
+#define CONFIG_SYS_I2C_SER_ADDR     	0x0e
+#define CONFIG_SYS_I2C_SER_PASSTROUGH   0xda    /* Enable SER I2C Pass Through */
+#define CONFIG_SYS_I2C_SER_PASSALL   	0xde    /* Enable SER I2C Pass All */
+#define CONFIG_SYS_I2C_SER_IRQ_ENABLE	0x21	/* Enable SER IRQ REQUEST */
+/* I2C switch definitions for PCA9546 chip */
+#define CONFIG_SYS_I2C_PCA9546_ADDR    	0x70
+#define CONFIG_SYS_I2C_PCA9546_ADDR_LEN	0       /* Single register. */
+#define CONFIG_SYS_I2C_PCA9546_ENABLE 	0x07    /* Enable channel 0,1,2. */
+#define CONFIG_SYS_NUM_I2C_BUSES       	4
+#define CONFIG_SYS_I2C_MAX_HOPS        	1
+#define CONFIG_SYS_I2C_BUSES   	{      	{0, {I2C_NULL_HOP}}, \
+					{0, {{I2C_MUX_PCA9546, 0x70, 1}}}, \
+                                       	{0, {{I2C_MUX_PCA9546, 0x70, 2}}}, \
+                                       	{0, {{I2C_MUX_PCA9546, 0x70, 3}}}, \
+                               	}
 /* PMIC support */
 #define CONFIG_POWER_TPS65217
 #define CONFIG_POWER_TPS65910
 /* SPL */
 #ifndef CONFIG_NOR_BOOT
 #define CONFIG_SPL_POWER_SUPPORT
 #define CONFIG_SPL_YMODEM_SUPPORT
 /* Bootcount using the RTC block */
 #define CONFIG_BOOTCOUNT_LIMIT
 #define CONFIG_BOOTCOUNT_AM33XX
 #define CONFIG_SYS_BOOTCOUNT_BE
 /* USB gadget RNDIS */
 #define CONFIG_SPL_MUSB_NEW_SUPPORT
 #define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/am33xx/u-boot-spl.lds"
 #endif
 #ifdef CONFIG_NAND
 /* NAND: device related configs */
 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 #define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
 					 CONFIG_SYS_NAND_PAGE_SIZE)
 #define CONFIG_SYS_NAND_PAGE_SIZE	2048
 #define CONFIG_SYS_NAND_OOBSIZE		64
 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
 /* NAND: driver related configs */
 #define CONFIG_NAND_OMAP_GPMC
 #define CONFIG_NAND_OMAP_GPMC_PREFETCH
 #define CONFIG_NAND_OMAP_ELM
 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
 #define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
 					 10, 11, 12, 13, 14, 15, 16, 17, \
 					 18, 19, 20, 21, 22, 23, 24, 25, \
 					 26, 27, 28, 29, 30, 31, 32, 33, \
 					 34, 35, 36, 37, 38, 39, 40, 41, \
 					 42, 43, 44, 45, 46, 47, 48, 49, \
 					 50, 51, 52, 53, 54, 55, 56, 57, }
 #define CONFIG_SYS_NAND_ECCSIZE		512
 #define CONFIG_SYS_NAND_ECCBYTES	14
 #define CONFIG_SYS_NAND_ONFI_DETECTION
 #define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW
 #define MTDIDS_DEFAULT			"nand0=nand.0"
 #define MTDPARTS_DEFAULT		"mtdparts=nand.0:" \
 					"128k(NAND.SPL)," \
 					"128k(NAND.SPL.backup1)," \
 					"128k(NAND.SPL.backup2)," \
 					"128k(NAND.SPL.backup3)," \
 					"256k(NAND.u-boot-spl-os)," \
 					"1m(NAND.u-boot)," \
 					"128k(NAND.u-boot-env)," \
 					"128k(NAND.u-boot-env.backup1)," \
 					"8m(NAND.kernel)," \
 					"-(NAND.file-system)"
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x000c0000
 /* NAND: SPL related configs */
 #ifdef CONFIG_SPL_NAND_SUPPORT
 #define CONFIG_SPL_NAND_AM33XX_BCH
 #endif
 #ifdef CONFIG_SPL_OS_BOOT
 #define CONFIG_CMD_SPL_NAND_OFS	0x00080000 /* os parameters */
 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x00200000 /* kernel offset */
 #define CONFIG_CMD_SPL_WRITE_SIZE	0x2000
 #endif
 #endif /* !CONFIG_NAND */
 /*
  * For NOR boot, we must set this to the start of where NOR is mapped
  * in memory.
  */
 #ifdef CONFIG_NOR_BOOT
 #define CONFIG_SYS_TEXT_BASE		0x08000000
 #endif
 /*
  * USB configuration.  We enable MUSB support, both for host and for
  * gadget.  We set USB0 as peripheral and USB1 as host, based on the
  * board schematic and physical port wired to each.  Then for host we
  * add mass storage support and for gadget we add both RNDIS ethernet
  * and DFU.
  */
 #define CONFIG_USB_MUSB_DSPS
 #define CONFIG_ARCH_MISC_INIT
 #define CONFIG_USB_MUSB_PIO_ONLY
 #define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
 #define CONFIG_USBDOWNLOAD_GADGET
 #define CONFIG_USB_GADGET_VBUS_DRAW     2
 #define CONFIG_AM335X_USB0
 #define CONFIG_AM335X_USB0_MODE	MUSB_PERIPHERAL
 #define CONFIG_AM335X_USB1
 #define CONFIG_AM335X_USB1_MODE MUSB_HOST
 #ifndef CONFIG_SPL_USBETH_SUPPORT
 /* Fastboot */
 #define CONFIG_USB_FUNCTION_FASTBOOT
 #define CONFIG_CMD_FASTBOOT
 #define CONFIG_ANDROID_BOOT_IMAGE
 #define CONFIG_FASTBOOT_BUF_ADDR	CONFIG_SYS_LOAD_ADDR
 #define CONFIG_FASTBOOT_BUF_SIZE	0x07000000
 /* To support eMMC booting */
 #define CONFIG_STORAGE_EMMC
 #define CONFIG_FASTBOOT_FLASH_MMC_DEV   1
 #endif
 #ifdef CONFIG_USB_MUSB_HOST
 #define CONFIG_USB_STORAGE
 #endif
 #ifdef CONFIG_USB_MUSB_GADGET
 #define CONFIG_USB_ETHER
 #define CONFIG_USB_ETH_RNDIS
 #define CONFIG_USBNET_HOST_ADDR	"de:ad:be:af:00:00"
 #endif /* CONFIG_USB_MUSB_GADGET */
 /*
  * Disable MMC DM for SPL build and can be re-enabled after adding
  * DM support in SPL
  */
 #ifdef CONFIG_SPL_BUILD
 #undef CONFIG_DM_MMC
 #undef CONFIG_TIMER
 #undef CONFIG_DM_NAND
 #undef CONFIG_DM_USB
 #endif
 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT)
 /* Remove other SPL modes. */
 #undef CONFIG_SPL_YMODEM_SUPPORT
 #undef CONFIG_SPL_NAND_SUPPORT
 #undef CONFIG_SPL_MMC_SUPPORT
 #define CONFIG_ENV_IS_NOWHERE
 #undef CONFIG_ENV_IS_IN_NAND
 /* disable host part of MUSB in SPL */
 /* disable EFI partitions and partition UUID support */
 #undef CONFIG_PARTITION_UUIDS
 #undef CONFIG_EFI_PARTITION
 /* General network SPL  */
 #define CONFIG_SPL_NET_SUPPORT
 #define CONFIG_SPL_ENV_SUPPORT
 #define CONFIG_SPL_NET_VCI_STRING	"AM335x U-Boot SPL"
 #endif
 /* USB Device Firmware Update support */
 #ifndef CONFIG_SPL_BUILD
 #define CONFIG_USB_FUNCTION_DFU
 #define CONFIG_DFU_MMC
 #define DFU_ALT_INFO_MMC \
 	"dfu_alt_info_mmc=" \
 	"boot part 0 1;" \
 	"rootfs part 0 2;" \
 	"MLO fat 0 1;" \
 	"MLO.raw raw 0x100 0x100;" \
 	"u-boot.img.raw raw 0x300 0x400;" \
 	"spl-os-args.raw raw 0x80 0x80;" \
 	"spl-os-image.raw raw 0x900 0x2000;" \
 	"spl-os-args fat 0 1;" \
 	"spl-os-image fat 0 1;" \
 	"u-boot.img fat 0 1;" \
 	"uEnv.txt fat 0 1\0"
 #ifdef CONFIG_NAND
 #define CONFIG_DFU_NAND
 #define DFU_ALT_INFO_NAND \
 	"dfu_alt_info_nand=" \
 	"SPL part 0 1;" \
 	"SPL.backup1 part 0 2;" \
 	"SPL.backup2 part 0 3;" \
 	"SPL.backup3 part 0 4;" \
 	"u-boot part 0 5;" \
 	"u-boot-spl-os part 0 6;" \
 	"kernel part 0 8;" \
 	"rootfs part 0 9\0"
 #else
 #define DFU_ALT_INFO_NAND ""
 #endif
 #define CONFIG_DFU_RAM
 #define DFU_ALT_INFO_RAM \
 	"dfu_alt_info_ram=" \
 	"kernel ram 0x80200000 0xD80000;" \
 	"fdt ram 0x80F80000 0x80000;" \
 	"ramdisk ram 0x81000000 0x4000000\0"
 #define DFUARGS \
 	"dfu_alt_info_emmc=rawemmc raw 0 3751936\0" \
 	DFU_ALT_INFO_MMC \
 	DFU_ALT_INFO_RAM \
 	DFU_ALT_INFO_NAND
 #endif
 /*
  * Default to using SPI for environment, etc.
  * 0x000000 - 0x020000 : SPL (128KiB)
  * 0x020000 - 0x0A0000 : U-Boot (512KiB)
  * 0x0A0000 - 0x0BFFFF : First copy of U-Boot Environment (128KiB)
  * 0x0C0000 - 0x0DFFFF : Second copy of U-Boot Environment (128KiB)
  * 0x0E0000 - 0x442000 : Linux Kernel
  * 0x442000 - 0x800000 : Userland
  */
 #if defined(CONFIG_SPI_BOOT)
 /* SPL related */
 #undef CONFIG_SPL_OS_BOOT		/* Not supported by existing map */
 #define CONFIG_SPL_SPI_SUPPORT
 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 #define CONFIG_SPL_SPI_LOAD
 #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x20000
 #define CONFIG_ENV_IS_IN_SPI_FLASH
 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
 #define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
 #define CONFIG_ENV_SECT_SIZE		(4 << 10) /* 4 KB sectors */
 #define CONFIG_ENV_OFFSET		(768 << 10) /* 768 KiB in */
 #define CONFIG_ENV_OFFSET_REDUND	(896 << 10) /* 896 KiB in */
 #define MTDIDS_DEFAULT			"nor0=m25p80-flash.0"
 #define MTDPARTS_DEFAULT		"mtdparts=m25p80-flash.0:128k(SPL)," \
 					"512k(u-boot),128k(u-boot-env1)," \
 					"128k(u-boot-env2),3464k(kernel)," \
 					"-(rootfs)"
 #elif defined(CONFIG_EMMC_BOOT)
 #undef CONFIG_SPL_OS_BOOT
 #undef CONFIG_ENV_IS_NOWHERE
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SPL_ENV_SUPPORT
 #define CONFIG_SYS_MMC_ENV_DEV		1
 #define CONFIG_SYS_MMC_ENV_PART		2
 #define CONFIG_ENV_OFFSET		0x0
 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
 #elif defined(CONFIG_NOR_BOOT)
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE		(128 << 10)	/* 128 KiB */
 #define CONFIG_ENV_OFFSET		(512 << 10)	/* 512 KiB */
 #define CONFIG_ENV_OFFSET_REDUND	(768 << 10)	/* 768 KiB */
 #define MTDIDS_DEFAULT			"nor0=physmap-flash.0"
 #define MTDPARTS_DEFAULT		"mtdparts=physmap-flash.0:" \
 					"512k(u-boot)," \
 					"128k(u-boot-env1)," \
 					"128k(u-boot-env2)," \
 					"4m(kernel),-(rootfs)"
 #elif defined(CONFIG_ENV_IS_IN_NAND)
 #define CONFIG_ENV_OFFSET		0x001c0000
 #define CONFIG_ENV_OFFSET_REDUND	0x001e0000
 #define CONFIG_SYS_ENV_SECT_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
 #elif !defined(CONFIG_ENV_IS_NOWHERE)
 /* Not NAND, SPI, NOR or eMMC env, so put ENV in a file on FAT */
 #define CONFIG_ENV_IS_IN_FAT
 #define FAT_ENV_INTERFACE		"mmc"
 #define FAT_ENV_DEVICE_AND_PART		"0:1"
 #define FAT_ENV_FILE			"uboot.env"
 #endif
 /* SPI flash. */
 #define CONFIG_SPI_FLASH_MACRONIX
 #define CONFIG_SF_DEFAULT_SPEED		24000000
 /* Network. */
 #define CONFIG_PHY_GIGE
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_SMSC
 /*
  * NOR Size = 16 MiB
  * Number of Sectors/Blocks = 128
  * Sector Size = 128 KiB
  * Word length = 16 bits
  * Default layout:
  * 0x000000 - 0x07FFFF : U-Boot (512 KiB)
  * 0x080000 - 0x09FFFF : First copy of U-Boot Environment (128 KiB)
  * 0x0A0000 - 0x0BFFFF : Second copy of U-Boot Environment (128 KiB)
  * 0x0C0000 - 0x4BFFFF : Linux Kernel (4 MiB)
  * 0x4C0000 - 0xFFFFFF : Userland (11 MiB + 256 KiB)
  */
 #if defined(CONFIG_NOR)
 #undef CONFIG_SYS_NO_FLASH
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 #define CONFIG_SYS_FLASH_PROTECTION
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_FLASH_CFI_MTD
 #define CONFIG_SYS_MAX_FLASH_SECT	128
 #define CONFIG_SYS_MAX_FLASH_BANKS	1
 #define CONFIG_SYS_FLASH_BASE		(0x08000000)
 #define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
 #define CONFIG_SYS_FLASH_SIZE		0x01000000
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
 #endif  /* NOR support */
 #ifdef CONFIG_DRIVER_TI_CPSW
 #define CONFIG_CLOCK_SYNTHESIZER
 #define CLK_SYNTHESIZER_I2C_ADDR 0x65
 #endif
 #endif	/* ! __CONFIG_SMARCT335X_EVM_H */

include/i2c.h

Diff comments View file @ 35e07b9

 /*
  * Copyright (C) 2009 Sergey Kubushyn <ksi@koi8.net>
  * Copyright (C) 2009 - 2013 Heiko Schocher <hs@denx.de>
  * Changes for multibus/multiadapter I2C support.
  *
  * (C) Copyright 2001
  * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  *
  * The original I2C interface was
  *   (C) 2000 by Paolo Scaffardi (arsenio@tin.it)
  *   AIRVENT SAM s.p.a - RIMINI(ITALY)
  * but has been changed substantially.
  */
 #ifndef _I2C_H_
 #define _I2C_H_
 /*
  * For now there are essentially two parts to this file - driver model
  * here at the top, and the older code below (with CONFIG_SYS_I2C being
  * most recent). The plan is to migrate everything to driver model.
  * The driver model structures and API are separate as they are different
  * enough as to be incompatible for compilation purposes.
  */
 enum dm_i2c_chip_flags {
 	DM_I2C_CHIP_10BIT	= 1 << 0, /* Use 10-bit addressing */
 	DM_I2C_CHIP_RD_ADDRESS	= 1 << 1, /* Send address for each read byte */
 	DM_I2C_CHIP_WR_ADDRESS	= 1 << 2, /* Send address for each write byte */
 };
 struct udevice;
 /**
  * struct dm_i2c_chip - information about an i2c chip
  *
  * An I2C chip is a device on the I2C bus. It sits at a particular address
  * and normally supports 7-bit or 10-bit addressing.
  *
  * To obtain this structure, use dev_get_parent_platdata(dev) where dev is
  * the chip to examine.
  *
  * @chip_addr:	Chip address on bus
  * @offset_len: Length of offset in bytes. A single byte offset can
  *		represent up to 256 bytes. A value larger than 1 may be
  *		needed for larger devices.
  * @flags:	Flags for this chip (dm_i2c_chip_flags)
  * @emul: Emulator for this chip address (only used for emulation)
  */
 struct dm_i2c_chip {
 	uint chip_addr;
 	uint offset_len;
 	uint flags;
 #ifdef CONFIG_SANDBOX
 	struct udevice *emul;
 	bool test_mode;
 #endif
 };
 /**
  * struct dm_i2c_bus- information about an i2c bus
  *
  * An I2C bus contains 0 or more chips on it, each at its own address. The
  * bus can operate at different speeds (measured in Hz, typically 100KHz
  * or 400KHz).
  *
  * To obtain this structure, use dev_get_uclass_priv(bus) where bus is the
  * I2C bus udevice.
  *
  * @speed_hz: Bus speed in hertz (typically 100000)
  */
 struct dm_i2c_bus {
 	int speed_hz;
 };
 /*
  * Not all of these flags are implemented in the U-Boot API
  */
 enum dm_i2c_msg_flags {
 	I2C_M_TEN		= 0x0010, /* ten-bit chip address */
 	I2C_M_RD		= 0x0001, /* read data, from slave to master */
 	I2C_M_STOP		= 0x8000, /* send stop after this message */
 	I2C_M_NOSTART		= 0x4000, /* no start before this message */
 	I2C_M_REV_DIR_ADDR	= 0x2000, /* invert polarity of R/W bit */
 	I2C_M_IGNORE_NAK	= 0x1000, /* continue after NAK */
 	I2C_M_NO_RD_ACK		= 0x0800, /* skip the Ack bit on reads */
 	I2C_M_RECV_LEN		= 0x0400, /* length is first received byte */
 };
 /**
  * struct i2c_msg - an I2C message
  *
  * @addr:	Slave address
  * @flags:	Flags (see enum dm_i2c_msg_flags)
  * @len:	Length of buffer in bytes, may be 0 for a probe
  * @buf:	Buffer to send/receive, or NULL if no data
  */
 struct i2c_msg {
 	uint addr;
 	uint flags;
 	uint len;
 	u8 *buf;
 };
 /**
  * struct i2c_msg_list - a list of I2C messages
  *
  * This is called i2c_rdwr_ioctl_data in Linux but the name does not seem
  * appropriate in U-Boot.
  *
  * @msg:	Pointer to i2c_msg array
  * @nmsgs:	Number of elements in the array
  */
 struct i2c_msg_list {
 	struct i2c_msg *msgs;
 	uint nmsgs;
 };
 /**
  * dm_i2c_read() - read bytes from an I2C chip
  *
  * To obtain an I2C device (called a 'chip') given the I2C bus address you
  * can use i2c_get_chip(). To obtain a bus by bus number use
  * uclass_get_device_by_seq(UCLASS_I2C, <bus number>).
  *
  * To set the address length of a devce use i2c_set_addr_len(). It
  * defaults to 1.
  *
  * @dev:	Chip to read from
  * @offset:	Offset within chip to start reading
  * @buffer:	Place to put data
  * @len:	Number of bytes to read
  *
  * @return 0 on success, -ve on failure
  */
 int dm_i2c_read(struct udevice *dev, uint offset, uint8_t *buffer, int len);
 /**
  * dm_i2c_write() - write bytes to an I2C chip
  *
  * See notes for dm_i2c_read() above.
  *
  * @dev:	Chip to write to
  * @offset:	Offset within chip to start writing
  * @buffer:	Buffer containing data to write
  * @len:	Number of bytes to write
  *
  * @return 0 on success, -ve on failure
  */
 int dm_i2c_write(struct udevice *dev, uint offset, const uint8_t *buffer,
 		 int len);
 /**
  * dm_i2c_probe() - probe a particular chip address
  *
  * This can be useful to check for the existence of a chip on the bus.
  * It is typically implemented by writing the chip address to the bus
  * and checking that the chip replies with an ACK.
  *
  * @bus:	Bus to probe
  * @chip_addr:	7-bit address to probe (10-bit and others are not supported)
  * @chip_flags:	Flags for the probe (see enum dm_i2c_chip_flags)
  * @devp:	Returns the device found, or NULL if none
  * @return 0 if a chip was found at that address, -ve if not
  */
 int dm_i2c_probe(struct udevice *bus, uint chip_addr, uint chip_flags,
 		 struct udevice **devp);
 /**
  * dm_i2c_reg_read() - Read a value from an I2C register
  *
  * This reads a single value from the given address in an I2C chip
  *
  * @dev:	Device to use for transfer
  * @addr:	Address to read from
  * @return value read, or -ve on error
  */
 int dm_i2c_reg_read(struct udevice *dev, uint offset);
 /**
  * dm_i2c_reg_write() - Write a value to an I2C register
  *
  * This writes a single value to the given address in an I2C chip
  *
  * @dev:	Device to use for transfer
  * @addr:	Address to write to
  * @val:	Value to write (normally a byte)
  * @return 0 on success, -ve on error
  */
 int dm_i2c_reg_write(struct udevice *dev, uint offset, unsigned int val);
 /**
  * dm_i2c_xfer() - Transfer messages over I2C
  *
  * This transfers a raw message. It is best to use dm_i2c_reg_read/write()
  * instead.
  *
  * @dev:	Device to use for transfer
  * @msg:	List of messages to transfer
  * @nmsgs:	Number of messages to transfer
  * @return 0 on success, -ve on error
  */
 int dm_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs);
 /**
  * dm_i2c_set_bus_speed() - set the speed of a bus
  *
  * @bus:	Bus to adjust
  * @speed:	Requested speed in Hz
  * @return 0 if OK, -EINVAL for invalid values
  */
 int dm_i2c_set_bus_speed(struct udevice *bus, unsigned int speed);
 /**
  * dm_i2c_get_bus_speed() - get the speed of a bus
  *
  * @bus:	Bus to check
  * @return speed of selected I2C bus in Hz, -ve on error
  */
 int dm_i2c_get_bus_speed(struct udevice *bus);
 /**
  * i2c_set_chip_flags() - set flags for a chip
  *
  * Typically addresses are 7 bits, but for 10-bit addresses you should set
  * flags to DM_I2C_CHIP_10BIT. All accesses will then use 10-bit addressing.
  *
  * @dev:	Chip to adjust
  * @flags:	New flags
  * @return 0 if OK, -EINVAL if value is unsupported, other -ve value on error
  */
 int i2c_set_chip_flags(struct udevice *dev, uint flags);
 /**
  * i2c_get_chip_flags() - get flags for a chip
  *
  * @dev:	Chip to check
  * @flagsp:	Place to put flags
  * @return 0 if OK, other -ve value on error
  */
 int i2c_get_chip_flags(struct udevice *dev, uint *flagsp);
 /**
  * i2c_set_offset_len() - set the offset length for a chip
  *
  * The offset used to access a chip may be up to 4 bytes long. Typically it
  * is only 1 byte, which is enough for chips with 256 bytes of memory or
  * registers. The default value is 1, but you can call this function to
  * change it.
  *
  * @offset_len:	New offset length value (typically 1 or 2)
  */
 int i2c_set_chip_offset_len(struct udevice *dev, uint offset_len);
 /**
  * i2c_get_offset_len() - get the offset length for a chip
  *
  * @return:	Current offset length value (typically 1 or 2)
  */
 int i2c_get_chip_offset_len(struct udevice *dev);
 /**
  * i2c_deblock() - recover a bus that is in an unknown state
  *
  * See the deblock() method in 'struct dm_i2c_ops' for full information
  *
  * @bus:	Bus to recover
  * @return 0 if OK, -ve on error
  */
 int i2c_deblock(struct udevice *bus);
 #ifdef CONFIG_DM_I2C_COMPAT
 /**
  * i2c_probe() - Compatibility function for driver model
  *
  * Calls dm_i2c_probe() on the current bus
  */
 int i2c_probe(uint8_t chip_addr);
 /**
  * i2c_read() - Compatibility function for driver model
  *
  * Calls dm_i2c_read() with the device corresponding to @chip_addr, and offset
  * set to @addr. @alen must match the current setting for the device.
  */
 int i2c_read(uint8_t chip_addr, unsigned int addr, int alen, uint8_t *buffer,
 	     int len);
 /**
  * i2c_write() - Compatibility function for driver model
  *
  * Calls dm_i2c_write() with the device corresponding to @chip_addr, and offset
  * set to @addr. @alen must match the current setting for the device.
  */
 int i2c_write(uint8_t chip_addr, unsigned int addr, int alen, uint8_t *buffer,
 	      int len);
 /**
  * i2c_get_bus_num_fdt() - Compatibility function for driver model
  *
  * @return the bus number associated with the given device tree node
  */
 int i2c_get_bus_num_fdt(int node);
 /**
  * i2c_get_bus_num() - Compatibility function for driver model
  *
  * @return the 'current' bus number
  */
 unsigned int i2c_get_bus_num(void);
 /**
  * i2c_set_bus_num() - Compatibility function for driver model
  *
  * Sets the 'current' bus
  */
 int i2c_set_bus_num(unsigned int bus);
 static inline void I2C_SET_BUS(unsigned int bus)
 {
 	i2c_set_bus_num(bus);
 }
 static inline unsigned int I2C_GET_BUS(void)
 {
 	return i2c_get_bus_num();
 }
 /**
  * i2c_init() - Compatibility function for driver model
  *
  * This function does nothing.
  */
 void i2c_init(int speed, int slaveaddr);
 /**
  * board_i2c_init() - Compatibility function for driver model
  *
  * @param blob  Device tree blbo
  * @return the number of I2C bus
  */
 void board_i2c_init(const void *blob);
 /*
  * Compatibility functions for driver model.
  */
 uint8_t i2c_reg_read(uint8_t addr, uint8_t reg);
 void i2c_reg_write(uint8_t addr, uint8_t reg, uint8_t val);
 #endif
 /**
  * struct dm_i2c_ops - driver operations for I2C uclass
  *
  * Drivers should support these operations unless otherwise noted. These
  * operations are intended to be used by uclass code, not directly from
  * other code.
  */
 struct dm_i2c_ops {
 	/**
 	 * xfer() - transfer a list of I2C messages
 	 *
 	 * @bus:	Bus to read from
 	 * @msg:	List of messages to transfer
 	 * @nmsgs:	Number of messages in the list
 	 * @return 0 if OK, -EREMOTEIO if the slave did not ACK a byte,
 	 *	-ECOMM if the speed cannot be supported, -EPROTO if the chip
 	 *	flags cannot be supported, other -ve value on some other error
 	 */
 	int (*xfer)(struct udevice *bus, struct i2c_msg *msg, int nmsgs);
 	/**
 	 * probe_chip() - probe for the presense of a chip address
 	 *
 	 * This function is optional. If omitted, the uclass will send a zero
 	 * length message instead.
 	 *
 	 * @bus:	Bus to probe
 	 * @chip_addr:	Chip address to probe
 	 * @chip_flags:	Probe flags (enum dm_i2c_chip_flags)
 	 * @return 0 if chip was found, -EREMOTEIO if not, -ENOSYS to fall back
 	 * to default probem other -ve value on error
 	 */
 	int (*probe_chip)(struct udevice *bus, uint chip_addr, uint chip_flags);
 	/**
 	 * set_bus_speed() - set the speed of a bus (optional)
 	 *
 	 * The bus speed value will be updated by the uclass if this function
 	 * does not return an error. This method is optional - if it is not
 	 * provided then the driver can read the speed from
 	 * dev_get_uclass_priv(bus)->speed_hz
 	 *
 	 * @bus:	Bus to adjust
 	 * @speed:	Requested speed in Hz
 	 * @return 0 if OK, -EINVAL for invalid values
 	 */
 	int (*set_bus_speed)(struct udevice *bus, unsigned int speed);
 	/**
 	 * get_bus_speed() - get the speed of a bus (optional)
 	 *
 	 * Normally this can be provided by the uclass, but if you want your
 	 * driver to check the bus speed by looking at the hardware, you can
 	 * implement that here. This method is optional. This method would
 	 * normally be expected to return dev_get_uclass_priv(bus)->speed_hz.
 	 *
 	 * @bus:	Bus to check
 	 * @return speed of selected I2C bus in Hz, -ve on error
 	 */
 	int (*get_bus_speed)(struct udevice *bus);
 	/**
 	 * set_flags() - set the flags for a chip (optional)
 	 *
 	 * This is generally implemented by the uclass, but drivers can
 	 * check the value to ensure that unsupported options are not used.
 	 * This method is optional. If provided, this method will always be
 	 * called when the flags change.
 	 *
 	 * @dev:	Chip to adjust
 	 * @flags:	New flags value
 	 * @return 0 if OK, -EINVAL if value is unsupported
 	 */
 	int (*set_flags)(struct udevice *dev, uint flags);
 	/**
 	 * deblock() - recover a bus that is in an unknown state
 	 *
 	 * I2C is a synchronous protocol and resets of the processor in the
 	 * middle of an access can block the I2C Bus until a powerdown of
 	 * the full unit is done. This is because slaves can be stuck
 	 * waiting for addition bus transitions for a transaction that will
 	 * never complete. Resetting the I2C master does not help. The only
 	 * way is to force the bus through a series of transitions to make
 	 * sure that all slaves are done with the transaction. This method
 	 * performs this 'deblocking' if support by the driver.
 	 *
 	 * This method is optional.
 	 */
 	int (*deblock)(struct udevice *bus);
 };
 #define i2c_get_ops(dev)	((struct dm_i2c_ops *)(dev)->driver->ops)
 /**
  * struct i2c_mux_ops - operations for an I2C mux
  *
  * The current mux state is expected to be stored in the mux itself since
  * it is the only thing that knows how to make things work. The mux can
  * record the current state and then avoid switching unless it is necessary.
  * So select() can be skipped if the mux is already in the correct state.
  * Also deselect() can be made a nop if required.
  */
 struct i2c_mux_ops {
 	/**
 	 * select() - select one of of I2C buses attached to a mux
 	 *
 	 * This will be called when there is no bus currently selected by the
 	 * mux. This method does not need to deselect the old bus since
 	 * deselect() will be already have been called if necessary.
 	 *
 	 * @mux:	Mux device
 	 * @bus:	I2C bus to select
 	 * @channel:	Channel number correponding to the bus to select
 	 * @return 0 if OK, -ve on error
 	 */
 	int (*select)(struct udevice *mux, struct udevice *bus, uint channel);
 	/**
 	 * deselect() - select one of of I2C buses attached to a mux
 	 *
 	 * This is used to deselect the currently selected I2C bus.
 	 *
 	 * @mux:	Mux device
 	 * @bus:	I2C bus to deselect
 	 * @channel:	Channel number correponding to the bus to deselect
 	 * @return 0 if OK, -ve on error
 	 */
 	int (*deselect)(struct udevice *mux, struct udevice *bus, uint channel);
 };
 #define i2c_mux_get_ops(dev)	((struct i2c_mux_ops *)(dev)->driver->ops)
 /**
  * i2c_get_chip() - get a device to use to access a chip on a bus
  *
  * This returns the device for the given chip address. The device can then
  * be used with calls to i2c_read(), i2c_write(), i2c_probe(), etc.
  *
  * @bus:	Bus to examine
  * @chip_addr:	Chip address for the new device
  * @offset_len:	Length of a register offset in bytes (normally 1)
  * @devp:	Returns pointer to new device if found or -ENODEV if not
  *		found
  */
 int i2c_get_chip(struct udevice *bus, uint chip_addr, uint offset_len,
 		 struct udevice **devp);
 /**
  * i2c_get_chip_for_busnum() - get a device to use to access a chip on
  *			       a bus number
  *
  * This returns the device for the given chip address on a particular bus
  * number.
  *
  * @busnum:	Bus number to examine
  * @chip_addr:	Chip address for the new device
  * @offset_len:	Length of a register offset in bytes (normally 1)
  * @devp:	Returns pointer to new device if found or -ENODEV if not
  *		found
  */
 int i2c_get_chip_for_busnum(int busnum, int chip_addr, uint offset_len,
 			    struct udevice **devp);
 /**
  * i2c_chip_ofdata_to_platdata() - Decode standard I2C platform data
  *
  * This decodes the chip address from a device tree node and puts it into
  * its dm_i2c_chip structure. This should be called in your driver's
  * ofdata_to_platdata() method.
  *
  * @blob:	Device tree blob
  * @node:	Node offset to read from
  * @spi:	Place to put the decoded information
  */
 int i2c_chip_ofdata_to_platdata(const void *blob, int node,
 				struct dm_i2c_chip *chip);
 /**
  * i2c_dump_msgs() - Dump a list of I2C messages
  *
  * This may be useful for debugging.
  *
  * @msg:	Message list to dump
  * @nmsgs:	Number of messages
  */
 void i2c_dump_msgs(struct i2c_msg *msg, int nmsgs);
 #ifndef CONFIG_DM_I2C
 /*
  * WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING
  *
  * The implementation MUST NOT use static or global variables if the
  * I2C routines are used to read SDRAM configuration information
  * because this is done before the memories are initialized. Limited
  * use of stack-based variables are OK (the initial stack size is
  * limited).
  *
  * WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING
  */
 /*
  * Configuration items.
  */
 #define I2C_RXTX_LEN	128	/* maximum tx/rx buffer length */
 #if !defined(CONFIG_SYS_I2C_MAX_HOPS)
 /* no muxes used bus = i2c adapters */
 #define CONFIG_SYS_I2C_DIRECT_BUS	1
 #define CONFIG_SYS_I2C_MAX_HOPS		0
 #define CONFIG_SYS_NUM_I2C_BUSES	ll_entry_count(struct i2c_adapter, i2c)
 #else
 /* we use i2c muxes */
 #undef CONFIG_SYS_I2C_DIRECT_BUS
 #endif
 /* define the I2C bus number for RTC and DTT if not already done */
 #if !defined(CONFIG_SYS_RTC_BUS_NUM)
 #define CONFIG_SYS_RTC_BUS_NUM		0
 #endif
 #if !defined(CONFIG_SYS_DTT_BUS_NUM)
 #define CONFIG_SYS_DTT_BUS_NUM		0
 #endif
 #if !defined(CONFIG_SYS_SPD_BUS_NUM)
 #define CONFIG_SYS_SPD_BUS_NUM		0
 #endif
 struct i2c_adapter {
 	void		(*init)(struct i2c_adapter *adap, int speed,
 				int slaveaddr);
 	int		(*probe)(struct i2c_adapter *adap, uint8_t chip);
 	int		(*read)(struct i2c_adapter *adap, uint8_t chip,
 				uint addr, int alen, uint8_t *buffer,
 				int len);
 	int		(*write)(struct i2c_adapter *adap, uint8_t chip,
 				uint addr, int alen, uint8_t *buffer,
 				int len);
 	uint		(*set_bus_speed)(struct i2c_adapter *adap,
 				uint speed);
 	int		speed;
 	int		waitdelay;
 	int		slaveaddr;
 	int		init_done;
 	int		hwadapnr;
 	char		*name;
 };
 #define U_BOOT_I2C_MKENT_COMPLETE(_init, _probe, _read, _write, \
 		_set_speed, _speed, _slaveaddr, _hwadapnr, _name) \
 	{ \
 		.init		=	_init, \
 		.probe		=	_probe, \
 		.read		=	_read, \
 		.write		=	_write, \
 		.set_bus_speed	=	_set_speed, \
 		.speed		=	_speed, \
 		.slaveaddr	=	_slaveaddr, \
 		.init_done	=	0, \
 		.hwadapnr	=	_hwadapnr, \
 		.name		=	#_name \
 };
 #define U_BOOT_I2C_ADAP_COMPLETE(_name, _init, _probe, _read, _write, \
 			_set_speed, _speed, _slaveaddr, _hwadapnr) \
 	ll_entry_declare(struct i2c_adapter, _name, i2c) = \
 	U_BOOT_I2C_MKENT_COMPLETE(_init, _probe, _read, _write, \
 		 _set_speed, _speed, _slaveaddr, _hwadapnr, _name);
 struct i2c_adapter *i2c_get_adapter(int index);
 #ifndef CONFIG_SYS_I2C_DIRECT_BUS
 struct i2c_mux {
 	int	id;
 	char	name[16];
 };
 struct i2c_next_hop {
 	struct i2c_mux		mux;
 	uint8_t		chip;
 	uint8_t		channel;
 };
 struct i2c_bus_hose {
 	int	adapter;
 	struct i2c_next_hop	next_hop[CONFIG_SYS_I2C_MAX_HOPS];
 };
 #define I2C_NULL_HOP	{{-1, ""}, 0, 0}
 extern struct i2c_bus_hose	i2c_bus[];
 #define I2C_ADAPTER(bus)	i2c_bus[bus].adapter
 #else
 #define I2C_ADAPTER(bus)	bus
 #endif
 #define	I2C_BUS			gd->cur_i2c_bus
 #define	I2C_ADAP_NR(bus)	i2c_get_adapter(I2C_ADAPTER(bus))
 #define	I2C_ADAP		I2C_ADAP_NR(gd->cur_i2c_bus)
 #define I2C_ADAP_HWNR		(I2C_ADAP->hwadapnr)
 #ifndef CONFIG_SYS_I2C_DIRECT_BUS
 #define I2C_MUX_PCA9540_ID	1
 #define I2C_MUX_PCA9540		{I2C_MUX_PCA9540_ID, "PCA9540B"}
 #define I2C_MUX_PCA9542_ID	2
 #define I2C_MUX_PCA9542		{I2C_MUX_PCA9542_ID, "PCA9542A"}
 #define I2C_MUX_PCA9544_ID	3
 #define I2C_MUX_PCA9544		{I2C_MUX_PCA9544_ID, "PCA9544A"}
+#define I2C_MUX_PCA9546_ID     	6
+#define I2C_MUX_PCA9546        	{I2C_MUX_PCA9546_ID, "PCA9546A"}
 #define I2C_MUX_PCA9547_ID	4
 #define I2C_MUX_PCA9547		{I2C_MUX_PCA9547_ID, "PCA9547A"}
 #define I2C_MUX_PCA9548_ID	5
 #define I2C_MUX_PCA9548		{I2C_MUX_PCA9548_ID, "PCA9548"}
 #endif
 #ifndef I2C_SOFT_DECLARATIONS
 # if defined(CONFIG_MPC8260)
 #  define I2C_SOFT_DECLARATIONS volatile ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT);
 # elif defined(CONFIG_8xx)
 #  define I2C_SOFT_DECLARATIONS	volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
 # elif (defined(CONFIG_AT91RM9200) || \
 	defined(CONFIG_AT91SAM9260) ||  defined(CONFIG_AT91SAM9261) || \
 	defined(CONFIG_AT91SAM9263))
 #  define I2C_SOFT_DECLARATIONS	at91_pio_t *pio	= (at91_pio_t *) ATMEL_BASE_PIOA;
 # else
 #  define I2C_SOFT_DECLARATIONS
 # endif
 #endif
 #ifdef CONFIG_8xx
 /* Set default value for the I2C bus speed on 8xx. In the
  * future, we'll define these in all 8xx board config files.
  */
 #ifndef	CONFIG_SYS_I2C_SPEED
 #define	CONFIG_SYS_I2C_SPEED	50000
 #endif
 #endif
 /*
  * Many boards/controllers/drivers don't support an I2C slave interface so
  * provide a default slave address for them for use in common code.  A real
  * value for CONFIG_SYS_I2C_SLAVE should be defined for any board which does
  * support a slave interface.
  */
 #ifndef	CONFIG_SYS_I2C_SLAVE
 #define	CONFIG_SYS_I2C_SLAVE	0xfe
 #endif
 /*
  * Initialization, must be called once on start up, may be called
  * repeatedly to change the speed and slave addresses.
  */
 void i2c_init(int speed, int slaveaddr);
 void i2c_init_board(void);
 #ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
 void i2c_board_late_init(void);
 #endif
 #ifdef CONFIG_SYS_I2C
 /*
  * i2c_get_bus_num:
  *
  *  Returns index of currently active I2C bus.  Zero-based.
  */
 unsigned int i2c_get_bus_num(void);
 /*
  * i2c_set_bus_num:
  *
  *  Change the active I2C bus.  Subsequent read/write calls will
  *  go to this one.
  *
  *	bus - bus index, zero based
  *
  *	Returns: 0 on success, not 0 on failure
  *
  */
 int i2c_set_bus_num(unsigned int bus);
 /*
  * i2c_init_all():
  *
  * Initializes all I2C adapters in the system. All i2c_adap structures must
  * be initialized beforehead with function pointers and data, including
  * speed and slaveaddr. Returns 0 on success, non-0 on failure.
  */
 void i2c_init_all(void);
 /*
  * Probe the given I2C chip address.  Returns 0 if a chip responded,
  * not 0 on failure.
  */
 int i2c_probe(uint8_t chip);
 /*
  * Read/Write interface:
  *   chip:    I2C chip address, range 0..127
  *   addr:    Memory (register) address within the chip
  *   alen:    Number of bytes to use for addr (typically 1, 2 for larger
  *              memories, 0 for register type devices with only one
  *              register)
  *   buffer:  Where to read/write the data
  *   len:     How many bytes to read/write
  *
  *   Returns: 0 on success, not 0 on failure
  */
 int i2c_read(uint8_t chip, unsigned int addr, int alen,
 				uint8_t *buffer, int len);
 int i2c_write(uint8_t chip, unsigned int addr, int alen,
 				uint8_t *buffer, int len);
 /*
  * Utility routines to read/write registers.
  */
 uint8_t i2c_reg_read(uint8_t addr, uint8_t reg);
 void i2c_reg_write(uint8_t addr, uint8_t reg, uint8_t val);
 /*
  * i2c_set_bus_speed:
  *
  *  Change the speed of the active I2C bus
  *
  *	speed - bus speed in Hz
  *
  *	Returns: new bus speed
  *
  */
 unsigned int i2c_set_bus_speed(unsigned int speed);
 /*
  * i2c_get_bus_speed:
  *
  *  Returns speed of currently active I2C bus in Hz
  */
 unsigned int i2c_get_bus_speed(void);
 /*
  * i2c_reloc_fixup:
  *
  * Adjusts I2C pointers after U-Boot is relocated to DRAM
  */
 void i2c_reloc_fixup(void);
 #if defined(CONFIG_SYS_I2C_SOFT)
 void i2c_soft_init(void);
 void i2c_soft_active(void);
 void i2c_soft_tristate(void);
 int i2c_soft_read(void);
 void i2c_soft_sda(int bit);
 void i2c_soft_scl(int bit);
 void i2c_soft_delay(void);
 #endif
 #else
 /*
  * Probe the given I2C chip address.  Returns 0 if a chip responded,
  * not 0 on failure.
  */
 int i2c_probe(uchar chip);
 /*
  * Read/Write interface:
  *   chip:    I2C chip address, range 0..127
  *   addr:    Memory (register) address within the chip
  *   alen:    Number of bytes to use for addr (typically 1, 2 for larger
  *              memories, 0 for register type devices with only one
  *              register)
  *   buffer:  Where to read/write the data
  *   len:     How many bytes to read/write
  *
  *   Returns: 0 on success, not 0 on failure
  */
 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len);
 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len);
 /*
  * Utility routines to read/write registers.
  */
 static inline u8 i2c_reg_read(u8 addr, u8 reg)
 {
 	u8 buf;
 #ifdef CONFIG_8xx
 	/* MPC8xx needs this.  Maybe one day we can get rid of it. */
 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 #endif
 #ifdef DEBUG
 	printf("%s: addr=0x%02x, reg=0x%02x\n", __func__, addr, reg);
 #endif
 	i2c_read(addr, reg, 1, &buf, 1);
 	return buf;
 }
 static inline void i2c_reg_write(u8 addr, u8 reg, u8 val)
 {
 #ifdef CONFIG_8xx
 	/* MPC8xx needs this.  Maybe one day we can get rid of it. */
 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 #endif
 #ifdef DEBUG
 	printf("%s: addr=0x%02x, reg=0x%02x, val=0x%02x\n",
 	       __func__, addr, reg, val);
 #endif
 	i2c_write(addr, reg, 1, &val, 1);
 }
 /*
  * Functions for setting the current I2C bus and its speed
  */
 /*
  * i2c_set_bus_num:
  *
  *  Change the active I2C bus.  Subsequent read/write calls will
  *  go to this one.
  *
  *	bus - bus index, zero based
  *
  *	Returns: 0 on success, not 0 on failure
  *
  */
 int i2c_set_bus_num(unsigned int bus);
 /*
  * i2c_get_bus_num:
  *
  *  Returns index of currently active I2C bus.  Zero-based.
  */
 unsigned int i2c_get_bus_num(void);
 /*
  * i2c_set_bus_speed:
  *
  *  Change the speed of the active I2C bus
  *
  *	speed - bus speed in Hz
  *
  *	Returns: 0 on success, not 0 on failure
  *
  */
 int i2c_set_bus_speed(unsigned int);
 /*
  * i2c_get_bus_speed:
  *
  *  Returns speed of currently active I2C bus in Hz
  */
 unsigned int i2c_get_bus_speed(void);
 #endif /* CONFIG_SYS_I2C */
 /*
  * only for backwardcompatibility, should go away if we switched
  * completely to new multibus support.
  */
 #if defined(CONFIG_SYS_I2C) || defined(CONFIG_I2C_MULTI_BUS)
 # if !defined(CONFIG_SYS_MAX_I2C_BUS)
 #  define CONFIG_SYS_MAX_I2C_BUS		2
 # endif
 # define I2C_MULTI_BUS				1
 #else
 # define CONFIG_SYS_MAX_I2C_BUS		1
 # define I2C_MULTI_BUS				0
 #endif
 /* NOTE: These two functions MUST be always_inline to avoid code growth! */
 static inline unsigned int I2C_GET_BUS(void) __attribute__((always_inline));
 static inline unsigned int I2C_GET_BUS(void)
 {
 	return I2C_MULTI_BUS ? i2c_get_bus_num() : 0;
 }
 static inline void I2C_SET_BUS(unsigned int bus) __attribute__((always_inline));
 static inline void I2C_SET_BUS(unsigned int bus)
 {
 	if (I2C_MULTI_BUS)
 		i2c_set_bus_num(bus);
 }
 /* Multi I2C definitions */
 enum {
 	I2C_0, I2C_1, I2C_2, I2C_3, I2C_4, I2C_5, I2C_6, I2C_7,
 	I2C_8, I2C_9, I2C_10,
 };
 /* Multi I2C busses handling */
 #ifdef CONFIG_SOFT_I2C_MULTI_BUS
 extern int get_multi_scl_pin(void);
 extern int get_multi_sda_pin(void);
 extern int multi_i2c_init(void);
 #endif
 /**
  * Get FDT values for i2c bus.
  *
  * @param blob  Device tree blbo
  * @return the number of I2C bus
  */
 void board_i2c_init(const void *blob);
 /**
  * Find the I2C bus number by given a FDT I2C node.
  *
  * @param blob  Device tree blbo
  * @param node  FDT I2C node to find
  * @return the number of I2C bus (zero based), or -1 on error
  */
 int i2c_get_bus_num_fdt(int node);
 /**
  * Reset the I2C bus represented by the given a FDT I2C node.
  *
  * @param blob  Device tree blbo
  * @param node  FDT I2C node to find
  * @return 0 if port was reset, -1 if not found
  */
 int i2c_reset_port_fdt(const void *blob, int node);
 #endif /* !CONFIG_DM_I2C */
 #endif	/* _I2C_H_ */