Eric Lee / smarc-uboot

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Commit 35e07b92f38436f04a0f8728cfc6a72f52aeddda

Authored by Eric Lee
1 parent cd7520d6af
Exists in v2016.05-dlt

initial commit for delta touch board

Showing 5 changed files with 96 additions and 36 deletions Side-by-side Diff

board/embedian/smarct335x/board.c
Diff comments   View file @ 35e07b9
... ... @@ -43,6 +43,12 @@
43 43 /* GPIO that controls LCD backlight PWM */
44 44 #define GPIO_LCD_PWM_EN 7
45 45  
  46 +/* GPIO that controls WDT */
  47 +#define GPIO_WDT_EN 66
  48 +
  49 +/* GPIO of SER_INT */
  50 +#define GPIO_SER_INT 100
  51 +
46 52 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
47 53  
48 54 /*
... ... @@ -551,10 +557,10 @@
551 557 * SMARC T335X rev. 00B0 and later use gpio0_7 as LCD backlight PWM and gpio1_22 as LCD backlight enable.
552 558 * This is safe enough to do on older revs.
553 559 */
554   - gpio_request(GPIO_LCD_BKLT_EN, "lcd_bklt_en");
555   - gpio_direction_output(GPIO_LCD_BKLT_EN, 1);
556   - gpio_request(GPIO_LCD_PWM_EN, "lcd_pwm_en");
557   - gpio_direction_output(GPIO_LCD_PWM_EN, 1);
  560 + gpio_request(GPIO_WDT_EN, "wdt_en");
  561 + gpio_direction_output(GPIO_WDT_EN, 0);
  562 + gpio_request(GPIO_SER_INT, "ser_int");
  563 + gpio_direction_input(GPIO_SER_INT);
558 564 config_ddr(400, &ioregs_smarct335x,
559 565 &ddr3_smarct335x_data,
560 566 &ddr3_smarct335x_cmd_ctrl_data,
... ... @@ -638,6 +644,28 @@
638 644 printf("Board Serial#: %.*s\n",
639 645 sizeof(header.serial), header.serial);
640 646 puts("-----------------------------------------\n");
  647 +
  648 + gpio_request(69, "i2c_multiplexer_reset");
  649 + /*gpio_direction_output(69, 0);*/
  650 + gpio_direction_output(69, 1);
  651 +
  652 + /* Turn on I2C switch PCA9546 channel */
  653 + i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR);
  654 + uint8_t i2cbuf;
  655 + i2cbuf = CONFIG_SYS_I2C_PCA9546_ENABLE;
  656 + i2c_write(CONFIG_SYS_I2C_PCA9546_ADDR, 1, CONFIG_SYS_I2C_PCA9546_ADDR_LEN, &i2cbuf, 1);
  657 +
  658 + /* Enable DS90UB925 I2C Pass Through */
  659 + i2cbuf = CONFIG_SYS_I2C_SER_PASSTROUGH;
  660 + i2c_write(CONFIG_SYS_I2C_SER_ADDR, 0x03, 1, &i2cbuf, 1);
  661 +
  662 + /* Enable DS90UB925 I2C Pass ALL */
  663 + i2cbuf = CONFIG_SYS_I2C_SER_PASSALL;
  664 + i2c_write(CONFIG_SYS_I2C_SER_ADDR, 0x17, 1, &i2cbuf, 1);
  665 +
  666 + /* Enable DS90UB925 IRQ */
  667 + i2cbuf = CONFIG_SYS_I2C_SER_IRQ_ENABLE;
  668 + i2c_write(CONFIG_SYS_I2C_SER_ADDR, 0xc6, 1, &i2cbuf, 1);
641 669  
642 670 /* Now set variables based on the header. */
643 671 strncpy(safe_string, (char *)header.name, sizeof(header.name));
board/embedian/smarct335x/mux.c
Diff comments   View file @ 35e07b9
... ... @@ -24,12 +24,16 @@
24 24 static struct module_pin_mux uart0_pin_mux[] = {
25 25 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
26 26 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
  27 + {OFFSET(uart0_ctsn), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_CTSN */
  28 + {OFFSET(uart0_rtsn), (MODE(0) | PULLUDEN)}, /* UART0_RTSN */
  29 +
27 30 {-1},
28 31 };
29 32  
30 33 static struct module_pin_mux uart1_pin_mux[] = {
31   - {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
32   - {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
  34 + {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
  35 + {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
  36 + {OFFSET(uart1_rtsn), (MODE(0) | PULLUDEN)}, /* UART1_RTSN */
33 37 {-1},
34 38 };
35 39  
... ... @@ -109,14 +113,6 @@
109 113 {-1},
110 114 };
111 115  
112   -static struct module_pin_mux i2c1_pin_mux[] = {
113   - {OFFSET(uart1_rxd), (MODE(3) | RXACTIVE |
114   - PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
115   - {OFFSET(uart1_txd), (MODE(3) | RXACTIVE |
116   - PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
117   - {-1},
118   -};
119   -
120 116 static struct module_pin_mux spi0_pin_mux[] = {
121 117 {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_SCLK */
122 118 {OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
123 119  
... ... @@ -124,9 +120,23 @@
124 120 {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_D1 */
125 121 {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
126 122 PULLUDEN | PULLUP_EN)}, /* SPI0_CS0 */
  123 + {OFFSET(spi0_cs1), (MODE(0) | RXACTIVE |
  124 + PULLUDEN | PULLUP_EN)}, /* SPI0_CS1 */
127 125 {-1},
128 126 };
129 127  
  128 +static struct module_pin_mux spi1_pin_mux[] = {
  129 + {OFFSET(mcasp0_aclkx), (MODE(3) | RXACTIVE | PULLUDEN)}, /* SPI1_SCLK */
  130 + {OFFSET(mcasp0_fsx), (MODE(3) | RXACTIVE |
  131 + PULLUDEN | PULLUP_EN)}, /* SPI1_D0 */
  132 + {OFFSET(mcasp0_axr0), (MODE(3) | RXACTIVE | PULLUDEN)}, /* SPI1_D1 */
  133 + {OFFSET(mcasp0_ahclkr), (MODE(3) | RXACTIVE |
  134 + PULLUDEN | PULLUP_EN)}, /* SPI1_CS0 */
  135 + {OFFSET(xdma_event_intr0), (MODE(4) | RXACTIVE |
  136 + PULLUDEN | PULLUP_EN)}, /* SPI1_CS1 */
  137 + {-1},
  138 +};
  139 +
130 140 static struct module_pin_mux gpio0_7_pin_mux[] = {
131 141 {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7 */
132 142 {-1},
133 143  
134 144  
135 145  
... ... @@ -138,21 +148,19 @@
138 148 {OFFSET(gpmc_a3), (MODE(7) | PULLUDEN | PULLUP_EN)}, /* GPIO1_19, MMC0_PWREN Enable*/
139 149 {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7, LCD_BKLT_PWM */
140 150 /* By SMARC Spec. GPIO0-5 is recommended for use as outputs and GPIO6-11 is recommended for use of inputs */
141   - {OFFSET(mii1_rxdv), MODE(7)}, /* GPIO3_4, GPIO0 */
142   - {OFFSET(gpmc_be0n_cle), MODE(7)}, /* GPIO2_5, GPIO1 */
  151 + {OFFSET(mii1_rxdv), MODE(7) | RXACTIVE}, /* GPIO3_4, GPIO0 */
143 152 {OFFSET(gpmc_a9), MODE(7)}, /* GPIO1_25, GPIO2 */
144   - {OFFSET(gpmc_a8), MODE(7)}, /* GPIO1_24, GPIO3 */
145   - {OFFSET(gpmc_wen), MODE(7)}, /* GPIO2_4, GPIO4 */
146   - {OFFSET(gpmc_oen_ren), MODE(7)}, /* GPIO2_3, GPIO5 */
  153 + {OFFSET(gpmc_a8), MODE(7) | RXACTIVE}, /* GPIO1_24, GPIO3 */
  154 + {OFFSET(gpmc_wen), MODE(7) | RXACTIVE}, /* GPIO2_4, GPIO4 */
  155 + {OFFSET(gpmc_oen_ren), MODE(7) | RXACTIVE}, /* GPIO2_3, GPIO5 */
147 156 {OFFSET(gpmc_be1n), MODE(7) | RXACTIVE}, /* GPIO1_28, GPIO6 */
148 157 {OFFSET(gpmc_csn0), MODE(7) | RXACTIVE}, /* GPIO1_29, GPIO7 */
149 158 {OFFSET(gpmc_csn3), MODE(7) | RXACTIVE}, /* GPIO2_0, GPIO8 */
150   - {OFFSET(gpmc_clk), MODE(7) | RXACTIVE}, /* GPIO2_1, GPIO9 */
151   - {OFFSET(emu0), MODE(7)}, /* GPIO3_7, GPIO10 for Buzzer */
  159 + {OFFSET(gpmc_clk), MODE(7)}, /* GPIO2_1, GPIO9 */
  160 + {OFFSET(emu0), MODE(7) | PULLUDEN}, /* GPIO3_7, GPIO10 for Buzzer */
152 161 {OFFSET(emu1), MODE(7) | RXACTIVE}, /* GPIO3_8, GPIO11 */
153   - /* i2c1 (pin37 and pin38 on P1 connector) in SBC-SMART-MEN is set as GPIOs*/
154   - {OFFSET(uart1_txd), MODE(7)}, /* uart1_txd.gpio0_15 */
155   - {OFFSET(uart1_rxd), MODE(7)}, /* uart1_rxd.gpio0_14 */
  162 + {OFFSET(gpmc_advn_ale), MODE(7) | PULLDOWN_EN}, /* GPIO2_2 WDT_TIMEOUT */
  163 + {OFFSET(gpmc_be0n_cle), MODE(7) | PULLUP_EN}, /* I2C Mux Reset */
156 164 {-1},
157 165 };
158 166  
... ... @@ -402,7 +410,6 @@
402 410 /* Do board-specific muxes. */
403 411 if (board_is_bone(header)) {
404 412 /* Beaglebone pinmux */
405   - configure_module_pin_mux(i2c1_pin_mux);
406 413 configure_module_pin_mux(mii1_pin_mux);
407 414 configure_module_pin_mux(mmc0_pin_mux);
408 415 #if defined(CONFIG_NAND)
409 416  
... ... @@ -417,15 +424,12 @@
417 424 unsigned short profile = detect_daughter_board_profile();
418 425 configure_module_pin_mux(rgmii1_pin_mux);
419 426 configure_module_pin_mux(mmc0_pin_mux);
420   - /* In profile #2 i2c1 and spi0 conflict. */
421   - if (profile & ~PROFILE_2)
422   - configure_module_pin_mux(i2c1_pin_mux);
423 427 /* Profiles 2 & 3 don't have NAND */
424 428 #ifdef CONFIG_NAND
425 429 if (profile & ~(PROFILE_2 | PROFILE_3))
426 430 configure_module_pin_mux(nand_pin_mux);
427 431 #endif
428   - else if (profile == PROFILE_2) {
  432 + if (profile == PROFILE_2) {
429 433 configure_module_pin_mux(mmc1_pin_mux);
430 434 configure_module_pin_mux(spi0_pin_mux);
431 435 }
432 436  
... ... @@ -435,13 +439,11 @@
435 439 configure_module_pin_mux(mmc0_no_cd_pin_mux);
436 440 } else if (board_is_evm_sk(header)) {
437 441 /* Starter Kit EVM */
438   - configure_module_pin_mux(i2c1_pin_mux);
439 442 configure_module_pin_mux(gpio0_7_pin_mux);
440 443 configure_module_pin_mux(rgmii1_pin_mux);
441 444 configure_module_pin_mux(mmc0_pin_mux_sk_evm);
442 445 } else if (board_is_bone_lt(header)) {
443 446 /* Beaglebone LT pinmux */
444   - configure_module_pin_mux(i2c1_pin_mux);
445 447 configure_module_pin_mux(mii1_pin_mux);
446 448 configure_module_pin_mux(mmc0_pin_mux);
447 449 #if defined(CONFIG_NAND) && defined(CONFIG_EMMC_BOOT)
448 450  
449 451  
450 452  
451 453  
452 454  
453 455  
454 456  
455 457  
... ... @@ -453,37 +455,42 @@
453 455 #endif
454 456 } else if (!strncmp(header->name, "SMARCT33", HDR_NAME_LEN)) {
455 457 /* SMARC T335X pinmux */
456   - /* i2c1 (pin37 and pin38 on P1 connector) in SBC-SMART-MEN is set as GPIOs*/
457   - /* configure_module_pin_mux(i2c1_pin_mux);*/
458 458 configure_module_pin_mux(mmc0_pin_mux);
459 459 configure_module_pin_mux(mmc1_pin_mux);
  460 + configure_module_pin_mux(uart0_pin_mux);
  461 + configure_module_pin_mux(uart1_pin_mux);
460 462 configure_module_pin_mux(uart3_pin_mux);
461 463 configure_module_pin_mux(rmii1_pin_mux);
462 464 configure_module_pin_mux(rmii2_pin_mux);
463 465 configure_module_pin_mux(smarc_gpio_pin_mux);
464 466 configure_module_pin_mux(spi0_pin_mux);
  467 + configure_module_pin_mux(spi1_pin_mux);
465 468 configure_module_pin_mux(lcdc_pin_mux);
466 469 } else if (!strncmp(header->name, "SMARCT80", HDR_NAME_LEN)) {
467 470 /* SMARC T335X 800MHz pinmux */
468   - configure_module_pin_mux(i2c1_pin_mux);
469 471 configure_module_pin_mux(mmc0_pin_mux);
470 472 configure_module_pin_mux(mmc1_pin_mux);
  473 + configure_module_pin_mux(uart0_pin_mux);
  474 + configure_module_pin_mux(uart1_pin_mux);
471 475 configure_module_pin_mux(uart3_pin_mux);
472 476 configure_module_pin_mux(rmii1_pin_mux);
473 477 configure_module_pin_mux(rmii2_pin_mux);
474 478 configure_module_pin_mux(smarc_gpio_pin_mux);
475 479 configure_module_pin_mux(spi0_pin_mux);
  480 + configure_module_pin_mux(spi1_pin_mux);
476 481 configure_module_pin_mux(lcdc_pin_mux);
477 482 } else if (!strncmp(header->name, "SMARCT1G", HDR_NAME_LEN)) {
478 483 /* SMARC T335X 1G pinmux */
479   - configure_module_pin_mux(i2c1_pin_mux);
480 484 configure_module_pin_mux(mmc0_pin_mux);
481 485 configure_module_pin_mux(mmc1_pin_mux);
  486 + configure_module_pin_mux(uart0_pin_mux);
  487 + configure_module_pin_mux(uart1_pin_mux);
482 488 configure_module_pin_mux(uart3_pin_mux);
483 489 configure_module_pin_mux(rmii1_pin_mux);
484 490 configure_module_pin_mux(rmii2_pin_mux);
485 491 configure_module_pin_mux(smarc_gpio_pin_mux);
486 492 configure_module_pin_mux(spi0_pin_mux);
  493 + configure_module_pin_mux(spi1_pin_mux);
487 494 configure_module_pin_mux(lcdc_pin_mux);
488 495 } else {
489 496 puts("Unknown board, cannot configure pinmux.");
drivers/i2c/i2c_core.c
Diff comments   View file @ 35e07b9
... ... @@ -127,6 +127,11 @@
127 127 return -1;
128 128 buf = (uint8_t)((channel & 0x03) | (1 << 2));
129 129 break;
  130 + case I2C_MUX_PCA9546_ID:
  131 + if (channel > 4)
  132 + return -1;
  133 + buf = (uint8_t)((channel & 0x04) | (1 << 3));
  134 + break;
130 135 case I2C_MUX_PCA9547_ID:
131 136 if (channel > 7)
132 137 return -1;
include/configs/smarct335x_evm.h
Diff comments   View file @ 35e07b9
... ... @@ -94,8 +94,8 @@
94 94 func(DHCP, dhcp, na)
95 95  
96 96 #define CONFIG_BOOTCOMMAND \
  97 + "i2c mw 0x24 1 0x3e;" \
97 98 "setenv umsmedia 0; "\
98   - "i2c mw 0x24 1 0x3e; " \
99 99 "run findfdt; " \
100 100 "run finduuid; " \
101 101 "run mmcboot;" \
... ... @@ -418,6 +418,24 @@
418 418 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
419 419 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
420 420 #define CONFIG_SYS_I2C_MULTI_EEPROMS
  421 +
  422 +/* I2C SER definitions for DS90UH925 chip */
  423 +#define CONFIG_SYS_I2C_SER_ADDR 0x0e
  424 +#define CONFIG_SYS_I2C_SER_PASSTROUGH 0xda /* Enable SER I2C Pass Through */
  425 +#define CONFIG_SYS_I2C_SER_PASSALL 0xde /* Enable SER I2C Pass All */
  426 +#define CONFIG_SYS_I2C_SER_IRQ_ENABLE 0x21 /* Enable SER IRQ REQUEST */
  427 +
  428 +/* I2C switch definitions for PCA9546 chip */
  429 +#define CONFIG_SYS_I2C_PCA9546_ADDR 0x70
  430 +#define CONFIG_SYS_I2C_PCA9546_ADDR_LEN 0 /* Single register. */
  431 +#define CONFIG_SYS_I2C_PCA9546_ENABLE 0x07 /* Enable channel 0,1,2. */
  432 +#define CONFIG_SYS_NUM_I2C_BUSES 4
  433 +#define CONFIG_SYS_I2C_MAX_HOPS 1
  434 +#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP}}, \
  435 + {0, {{I2C_MUX_PCA9546, 0x70, 1}}}, \
  436 + {0, {{I2C_MUX_PCA9546, 0x70, 2}}}, \
  437 + {0, {{I2C_MUX_PCA9546, 0x70, 3}}}, \
  438 + }
421 439  
422 440 /* PMIC support */
423 441 #define CONFIG_POWER_TPS65217
... ... @@ -657,6 +657,8 @@
657 657 #define I2C_MUX_PCA9542 {I2C_MUX_PCA9542_ID, "PCA9542A"}
658 658 #define I2C_MUX_PCA9544_ID 3
659 659 #define I2C_MUX_PCA9544 {I2C_MUX_PCA9544_ID, "PCA9544A"}
  660 +#define I2C_MUX_PCA9546_ID 6
  661 +#define I2C_MUX_PCA9546 {I2C_MUX_PCA9546_ID, "PCA9546A"}
660 662 #define I2C_MUX_PCA9547_ID 4
661 663 #define I2C_MUX_PCA9547 {I2C_MUX_PCA9547_ID, "PCA9547A"}
662 664 #define I2C_MUX_PCA9548_ID 5