Eric Lee / smarc-uboot

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Commit 36cc0de0b919c0e185739142742e0a76a7c5c30a

Authored by York Sun
1 parent 426337455e
Exists in smarc_8mq_lf_v2020.04 and in 17 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

armv8: layerscape: Rewrite memory reservation 

For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved
at the end of DDR. DDR is spit into two or three banks. This patch
reverts commit aabd7ddb and simplifies the calculation of reserved
memory, and moves the code into common SoC file. Secure memory is
carved out first. DDR bank size is reduced. Reserved memory is then
allocated on the top of available memory. U-Boot still has access
to reserved memory as data transferring is needed. Device tree is
fixed with reduced memory size to hide the reserved memory from OS.
The same region is reserved for efi_loader.

Signed-off-by: York Sun <york.sun@nxp.com>

Showing 17 changed files with 233 additions and 423 deletions Side-by-side Diff

arch/arm/cpu/armv8/fsl-layerscape/cpu.c
Diff comments   View file @ 36cc0de
... ... @@ -524,16 +524,202 @@
524 524 {
525 525 phys_size_t ram_top = ram_size;
526 526  
527   -#ifdef CONFIG_SYS_MEM_TOP_HIDE
528   -#error CONFIG_SYS_MEM_TOP_HIDE not to be used together with this function
529   -#endif
530   -
531   -/* Carve the MC private DRAM block from the end of DRAM */
532 527 #ifdef CONFIG_FSL_MC_ENET
  528 + /* The start address of MC reserved memory needs to be aligned. */
533 529 ram_top -= mc_get_dram_block_size();
534 530 ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);
535 531 #endif
536 532  
537   - return ram_top;
  533 + return ram_size - ram_top;
538 534 }
  535 +
  536 +phys_size_t get_effective_memsize(void)
  537 +{
  538 + phys_size_t ea_size, rem = 0;
  539 +
  540 + /*
  541 + * For ARMv8 SoCs, DDR memory is split into two or three regions. The
  542 + * first region is 2GB space at 0x8000_0000. If the memory extends to
  543 + * the second region (or the third region if applicable), the secure
  544 + * memory and Management Complex (MC) memory should be put into the
  545 + * highest region, i.e. the end of DDR memory. CONFIG_MAX_MEM_MAPPED
  546 + * is set to the size of first region so U-Boot doesn't relocate itself
  547 + * into higher address. Should DDR be configured to skip the first
  548 + * region, this function needs to be adjusted.
  549 + */
  550 + if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
  551 + ea_size = CONFIG_MAX_MEM_MAPPED;
  552 + rem = gd->ram_size - ea_size;
  553 + } else {
  554 + ea_size = gd->ram_size;
  555 + }
  556 +
  557 +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
  558 + /* Check if we have enough space for secure memory */
  559 + if (rem > CONFIG_SYS_MEM_RESERVE_SECURE) {
  560 + rem -= CONFIG_SYS_MEM_RESERVE_SECURE;
  561 + } else {
  562 + if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE) {
  563 + ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
  564 + rem = 0; /* Presume MC requires more memory */
  565 + } else {
  566 + printf("Error: No enough space for secure memory.\n");
  567 + }
  568 + }
  569 +#endif
  570 + /* Check if we have enough memory for MC */
  571 + if (rem < board_reserve_ram_top(rem)) {
  572 + /* Not enough memory in high region to reserve */
  573 + if (ea_size > board_reserve_ram_top(rem))
  574 + ea_size -= board_reserve_ram_top(rem);
  575 + else
  576 + printf("Error: No enough space for reserved memory.\n");
  577 + }
  578 +
  579 + return ea_size;
  580 +}
  581 +
  582 +void dram_init_banksize(void)
  583 +{
  584 +#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
  585 + phys_size_t dp_ddr_size;
  586 +#endif
  587 +
  588 + /*
  589 + * gd->ram_size has the total size of DDR memory, less reserved secure
  590 + * memory. The DDR extends from low region to high region(s) presuming
  591 + * no hole is created with DDR configuration. gd->arch.secure_ram tracks
  592 + * the location of secure memory. gd->arch.resv_ram tracks the location
  593 + * of reserved memory for Management Complex (MC).
  594 + */
  595 + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  596 + if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
  597 + gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
  598 + gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
  599 + gd->bd->bi_dram[1].size = gd->ram_size -
  600 + CONFIG_SYS_DDR_BLOCK1_SIZE;
  601 +#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
  602 + if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
  603 + gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
  604 + gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size -
  605 + CONFIG_SYS_DDR_BLOCK2_SIZE;
  606 + gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE;
  607 + }
  608 +#endif
  609 + } else {
  610 + gd->bd->bi_dram[0].size = gd->ram_size;
  611 + }
  612 +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
  613 +#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
  614 + if (gd->bd->bi_dram[2].size >= CONFIG_SYS_MEM_RESERVE_SECURE) {
  615 + gd->bd->bi_dram[2].size -= CONFIG_SYS_MEM_RESERVE_SECURE;
  616 + gd->arch.secure_ram = gd->bd->bi_dram[2].start +
  617 + gd->bd->bi_dram[2].size;
  618 + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
  619 + gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
  620 + } else
  621 +#endif
  622 + {
  623 + if (gd->bd->bi_dram[1].size >= CONFIG_SYS_MEM_RESERVE_SECURE) {
  624 + gd->bd->bi_dram[1].size -=
  625 + CONFIG_SYS_MEM_RESERVE_SECURE;
  626 + gd->arch.secure_ram = gd->bd->bi_dram[1].start +
  627 + gd->bd->bi_dram[1].size;
  628 + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
  629 + gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
  630 + } else if (gd->bd->bi_dram[0].size >
  631 + CONFIG_SYS_MEM_RESERVE_SECURE) {
  632 + gd->bd->bi_dram[0].size -=
  633 + CONFIG_SYS_MEM_RESERVE_SECURE;
  634 + gd->arch.secure_ram = gd->bd->bi_dram[0].start +
  635 + gd->bd->bi_dram[0].size;
  636 + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
  637 + gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
  638 + }
  639 + }
  640 +#endif /* CONFIG_SYS_MEM_RESERVE_SECURE */
  641 +
  642 +#ifdef CONFIG_FSL_MC_ENET
  643 + /* Assign memory for MC */
  644 +#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
  645 + if (gd->bd->bi_dram[2].size >=
  646 + board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
  647 + gd->arch.resv_ram = gd->bd->bi_dram[2].start +
  648 + gd->bd->bi_dram[2].size -
  649 + board_reserve_ram_top(gd->bd->bi_dram[2].size);
  650 + } else
  651 +#endif
  652 + {
  653 + if (gd->bd->bi_dram[1].size >=
  654 + board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
  655 + gd->arch.resv_ram = gd->bd->bi_dram[1].start +
  656 + gd->bd->bi_dram[1].size -
  657 + board_reserve_ram_top(gd->bd->bi_dram[1].size);
  658 + } else if (gd->bd->bi_dram[0].size >
  659 + board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
  660 + gd->arch.resv_ram = gd->bd->bi_dram[0].start +
  661 + gd->bd->bi_dram[0].size -
  662 + board_reserve_ram_top(gd->bd->bi_dram[0].size);
  663 + }
  664 + }
  665 +#endif /* CONFIG_FSL_MC_ENET */
  666 +
  667 +#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
  668 +#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
  669 +#error "This SoC shouldn't have DP DDR"
  670 +#endif
  671 + if (soc_has_dp_ddr()) {
  672 + /* initialize DP-DDR here */
  673 + puts("DP-DDR: ");
  674 + /*
  675 + * DDR controller use 0 as the base address for binding.
  676 + * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
  677 + */
  678 + dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
  679 + CONFIG_DP_DDR_CTRL,
  680 + CONFIG_DP_DDR_NUM_CTRLS,
  681 + CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
  682 + NULL, NULL, NULL);
  683 + if (dp_ddr_size) {
  684 + gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
  685 + gd->bd->bi_dram[2].size = dp_ddr_size;
  686 + } else {
  687 + puts("Not detected");
  688 + }
  689 + }
  690 +#endif
  691 +}
  692 +
  693 +#if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD)
  694 +void efi_add_known_memory(void)
  695 +{
  696 + int i;
  697 + phys_addr_t ram_start, start;
  698 + phys_size_t ram_size;
  699 + u64 pages;
  700 +
  701 + /* Add RAM */
  702 + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  703 +#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
  704 +#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
  705 +#error "This SoC shouldn't have DP DDR"
  706 +#endif
  707 + if (i == 2)
  708 + continue; /* skip DP-DDR */
  709 +#endif
  710 + ram_start = gd->bd->bi_dram[i].start;
  711 + ram_size = gd->bd->bi_dram[i].size;
  712 +#ifdef CONFIG_RESV_RAM
  713 + if (gd->arch.resv_ram >= ram_start &&
  714 + gd->arch.resv_ram < ram_start + ram_size)
  715 + ram_size = gd->arch.resv_ram - ram_start;
  716 +#endif
  717 + start = (ram_start + EFI_PAGE_MASK) & ~EFI_PAGE_MASK;
  718 + pages = (ram_size + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
  719 +
  720 + efi_add_memory_map(start, pages, EFI_CONVENTIONAL_MEMORY,
  721 + false);
  722 + }
  723 +}
  724 +#endif
arch/arm/include/asm/arch-fsl-layerscape/config.h
Diff comments   View file @ 36cc0de
... ... @@ -33,8 +33,8 @@
33 33 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
34 34  
35 35 /* DDR */
36   -#define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
37   -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
  36 +#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
  37 +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
38 38  
39 39 #define CONFIG_SYS_FSL_CCSR_GUR_LE
40 40 #define CONFIG_SYS_FSL_CCSR_SCFG_LE
board/freescale/ls1012afrdm/ls1012afrdm.c
Diff comments   View file @ 36cc0de
... ... @@ -91,33 +91,4 @@
91 91  
92 92 return 0;
93 93 }
94   -
95   -void dram_init_banksize(void)
96   -{
97   - /*
98   - * gd->arch.secure_ram tracks the location of secure memory.
99   - * It was set as if the memory starts from 0.
100   - * The address needs to add the offset of its bank.
101   - */
102   - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
103   - if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
104   - gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
105   - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
106   - gd->bd->bi_dram[1].size = gd->ram_size -
107   - CONFIG_SYS_DDR_BLOCK1_SIZE;
108   -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
109   - gd->arch.secure_ram = gd->bd->bi_dram[1].start +
110   - gd->arch.secure_ram -
111   - CONFIG_SYS_DDR_BLOCK1_SIZE;
112   - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
113   -#endif
114   - } else {
115   - gd->bd->bi_dram[0].size = gd->ram_size;
116   -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
117   - gd->arch.secure_ram = gd->bd->bi_dram[0].start +
118   - gd->arch.secure_ram;
119   - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
120   -#endif
121   - }
122   -}
board/freescale/ls1012aqds/ls1012aqds.c
Diff comments   View file @ 36cc0de
... ... @@ -166,33 +166,4 @@
166 166 return 0;
167 167 }
168 168 #endif
169   -
170   -void dram_init_banksize(void)
171   -{
172   - /*
173   - * gd->arch.secure_ram tracks the location of secure memory.
174   - * It was set as if the memory starts from 0.
175   - * The address needs to add the offset of its bank.
176   - */
177   - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
178   - if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
179   - gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
180   - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
181   - gd->bd->bi_dram[1].size = gd->ram_size -
182   - CONFIG_SYS_DDR_BLOCK1_SIZE;
183   -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
184   - gd->arch.secure_ram = gd->bd->bi_dram[1].start +
185   - gd->arch.secure_ram -
186   - CONFIG_SYS_DDR_BLOCK1_SIZE;
187   - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
188   -#endif
189   - } else {
190   - gd->bd->bi_dram[0].size = gd->ram_size;
191   -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
192   - gd->arch.secure_ram = gd->bd->bi_dram[0].start +
193   - gd->arch.secure_ram;
194   - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
195   -#endif
196   - }
197   -}
board/freescale/ls1012ardb/ls1012ardb.c
Diff comments   View file @ 36cc0de
... ... @@ -165,33 +165,4 @@
165 165  
166 166 return 0;
167 167 }
168   -
169   -void dram_init_banksize(void)
170   -{
171   - /*
172   - * gd->secure_ram tracks the location of secure memory.
173   - * It was set as if the memory starts from 0.
174   - * The address needs to add the offset of its bank.
175   - */
176   - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
177   - if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
178   - gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
179   - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
180   - gd->bd->bi_dram[1].size = gd->ram_size -
181   - CONFIG_SYS_DDR_BLOCK1_SIZE;
182   -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
183   - gd->arch.secure_ram = gd->bd->bi_dram[1].start +
184   - gd->arch.secure_ram -
185   - CONFIG_SYS_DDR_BLOCK1_SIZE;
186   - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
187   -#endif
188   - } else {
189   - gd->bd->bi_dram[0].size = gd->ram_size;
190   -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
191   - gd->arch.secure_ram = gd->bd->bi_dram[0].start +
192   - gd->arch.secure_ram;
193   - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
194   -#endif
195   - }
196   -}
board/freescale/ls1043aqds/ddr.c
Diff comments   View file @ 36cc0de
... ... @@ -127,33 +127,4 @@
127 127  
128 128 return dram_size;
129 129 }
130   -
131   -void dram_init_banksize(void)
132   -{
133   - /*
134   - * gd->arch.secure_ram tracks the location of secure memory.
135   - * It was set as if the memory starts from 0.
136   - * The address needs to add the offset of its bank.
137   - */
138   - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
139   - if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
140   - gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
141   - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
142   - gd->bd->bi_dram[1].size = gd->ram_size -
143   - CONFIG_SYS_DDR_BLOCK1_SIZE;
144   -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
145   - gd->arch.secure_ram = gd->bd->bi_dram[1].start +
146   - gd->arch.secure_ram -
147   - CONFIG_SYS_DDR_BLOCK1_SIZE;
148   - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
149   -#endif
150   - } else {
151   - gd->bd->bi_dram[0].size = gd->ram_size;
152   -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
153   - gd->arch.secure_ram = gd->bd->bi_dram[0].start +
154   - gd->arch.secure_ram;
155   - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
156   -#endif
157   - }
158   -}
board/freescale/ls1043ardb/ddr.c
Diff comments   View file @ 36cc0de
... ... @@ -188,33 +188,4 @@
188 188  
189 189 return dram_size;
190 190 }
191   -
192   -void dram_init_banksize(void)
193   -{
194   - /*
195   - * gd->arch.secure_ram tracks the location of secure memory.
196   - * It was set as if the memory starts from 0.
197   - * The address needs to add the offset of its bank.
198   - */
199   - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
200   - if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
201   - gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
202   - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
203   - gd->bd->bi_dram[1].size = gd->ram_size -
204   - CONFIG_SYS_DDR_BLOCK1_SIZE;
205   -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
206   - gd->arch.secure_ram = gd->bd->bi_dram[1].start +
207   - gd->arch.secure_ram -
208   - CONFIG_SYS_DDR_BLOCK1_SIZE;
209   - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
210   -#endif
211   - } else {
212   - gd->bd->bi_dram[0].size = gd->ram_size;
213   -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
214   - gd->arch.secure_ram = gd->bd->bi_dram[0].start +
215   - gd->arch.secure_ram;
216   - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
217   -#endif
218   - }
219   -}
board/freescale/ls1046aqds/ddr.c
Diff comments   View file @ 36cc0de
... ... @@ -112,33 +112,4 @@
112 112  
113 113 return dram_size;
114 114 }
115   -
116   -void dram_init_banksize(void)
117   -{
118   - /*
119   - * gd->arch.secure_ram tracks the location of secure memory.
120   - * It was set as if the memory starts from 0.
121   - * The address needs to add the offset of its bank.
122   - */
123   - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
124   - if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
125   - gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
126   - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
127   - gd->bd->bi_dram[1].size = gd->ram_size -
128   - CONFIG_SYS_DDR_BLOCK1_SIZE;
129   -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
130   - gd->arch.secure_ram = gd->bd->bi_dram[1].start +
131   - gd->arch.secure_ram -
132   - CONFIG_SYS_DDR_BLOCK1_SIZE;
133   - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
134   -#endif
135   - } else {
136   - gd->bd->bi_dram[0].size = gd->ram_size;
137   -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
138   - gd->arch.secure_ram = gd->bd->bi_dram[0].start +
139   - gd->arch.secure_ram;
140   - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
141   -#endif
142   - }
143   -}
board/freescale/ls1046ardb/ddr.c
Diff comments   View file @ 36cc0de
... ... @@ -112,33 +112,4 @@
112 112  
113 113 return dram_size;
114 114 }
115   -
116   -void dram_init_banksize(void)
117   -{
118   - /*
119   - * gd->arch.secure_ram tracks the location of secure memory.
120   - * It was set as if the memory starts from 0.
121   - * The address needs to add the offset of its bank.
122   - */
123   - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
124   - if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
125   - gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
126   - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
127   - gd->bd->bi_dram[1].size = gd->ram_size -
128   - CONFIG_SYS_DDR_BLOCK1_SIZE;
129   -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
130   - gd->arch.secure_ram = gd->bd->bi_dram[1].start +
131   - gd->arch.secure_ram -
132   - CONFIG_SYS_DDR_BLOCK1_SIZE;
133   - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
134   -#endif
135   - } else {
136   - gd->bd->bi_dram[0].size = gd->ram_size;
137   -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
138   - gd->arch.secure_ram = gd->bd->bi_dram[0].start +
139   - gd->arch.secure_ram;
140   - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
141   -#endif
142   - }
143   -}
board/freescale/ls2080a/ddr.c
Diff comments   View file @ 36cc0de
... ... @@ -169,59 +169,4 @@
169 169  
170 170 return dram_size;
171 171 }
172   -
173   -void dram_init_banksize(void)
174   -{
175   -#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
176   - phys_size_t dp_ddr_size;
177   -#endif
178   -
179   - /*
180   - * gd->arch.secure_ram tracks the location of secure memory.
181   - * It was set as if the memory starts from 0.
182   - * The address needs to add the offset of its bank.
183   - */
184   - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
185   - if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) {
186   - gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
187   - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
188   - gd->bd->bi_dram[1].size = gd->ram_size -
189   - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
190   -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
191   - gd->arch.secure_ram = gd->bd->bi_dram[1].start +
192   - gd->arch.secure_ram -
193   - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
194   - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
195   -#endif
196   - } else {
197   - gd->bd->bi_dram[0].size = gd->ram_size;
198   -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
199   - gd->arch.secure_ram = gd->bd->bi_dram[0].start +
200   - gd->arch.secure_ram;
201   - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
202   -#endif
203   - }
204   -
205   -#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
206   - if (soc_has_dp_ddr()) {
207   - /* initialize DP-DDR here */
208   - puts("DP-DDR: ");
209   - /*
210   - * DDR controller use 0 as the base address for binding.
211   - * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
212   - */
213   - dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
214   - CONFIG_DP_DDR_CTRL,
215   - CONFIG_DP_DDR_NUM_CTRLS,
216   - CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
217   - NULL, NULL, NULL);
218   - if (dp_ddr_size) {
219   - gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
220   - gd->bd->bi_dram[2].size = dp_ddr_size;
221   - } else {
222   - puts("Not detected");
223   - }
224   - }
225   -#endif
226   -}
board/freescale/ls2080a/ls2080a.c
Diff comments   View file @ 36cc0de
... ... @@ -123,6 +123,16 @@
123 123 base[1] = gd->bd->bi_dram[1].start;
124 124 size[1] = gd->bd->bi_dram[1].size;
125 125  
  126 +#ifdef CONFIG_RESV_RAM
  127 + /* reduce size if reserved memory is within this bank */
  128 + if (gd->arch.resv_ram >= base[0] &&
  129 + gd->arch.resv_ram < base[0] + size[0])
  130 + size[0] = gd->arch.resv_ram - base[0];
  131 + else if (gd->arch.resv_ram >= base[1] &&
  132 + gd->arch.resv_ram < base[1] + size[1])
  133 + size[1] = gd->arch.resv_ram - base[1];
  134 +#endif
  135 +
126 136 fdt_fixup_memory_banks(blob, base, size, 2);
127 137  
128 138 #ifdef CONFIG_FSL_MC_ENET
board/freescale/ls2080aqds/ddr.c
Diff comments   View file @ 36cc0de
... ... @@ -169,59 +169,4 @@
169 169  
170 170 return dram_size;
171 171 }
172   -
173   -void dram_init_banksize(void)
174   -{
175   -#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
176   - phys_size_t dp_ddr_size;
177   -#endif
178   -
179   - /*
180   - * gd->arch.secure_ram tracks the location of secure memory.
181   - * It was set as if the memory starts from 0.
182   - * The address needs to add the offset of its bank.
183   - */
184   - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
185   - if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) {
186   - gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
187   - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
188   - gd->bd->bi_dram[1].size = gd->ram_size -
189   - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
190   -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
191   - gd->arch.secure_ram = gd->bd->bi_dram[1].start +
192   - gd->arch.secure_ram -
193   - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
194   - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
195   -#endif
196   - } else {
197   - gd->bd->bi_dram[0].size = gd->ram_size;
198   -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
199   - gd->arch.secure_ram = gd->bd->bi_dram[0].start +
200   - gd->arch.secure_ram;
201   - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
202   -#endif
203   - }
204   -
205   -#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
206   - if (soc_has_dp_ddr()) {
207   - /* initialize DP-DDR here */
208   - puts("DP-DDR: ");
209   - /*
210   - * DDR controller use 0 as the base address for binding.
211   - * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
212   - */
213   - dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
214   - CONFIG_DP_DDR_CTRL,
215   - CONFIG_DP_DDR_NUM_CTRLS,
216   - CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
217   - NULL, NULL, NULL);
218   - if (dp_ddr_size) {
219   - gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
220   - gd->bd->bi_dram[2].size = dp_ddr_size;
221   - } else {
222   - puts("Not detected");
223   - }
224   - }
225   -#endif
226   -}
board/freescale/ls2080aqds/ls2080aqds.c
Diff comments   View file @ 36cc0de
... ... @@ -313,6 +313,16 @@
313 313 base[1] = gd->bd->bi_dram[1].start;
314 314 size[1] = gd->bd->bi_dram[1].size;
315 315  
  316 +#ifdef CONFIG_RESV_RAM
  317 + /* reduce size if reserved memory is within this bank */
  318 + if (gd->arch.resv_ram >= base[0] &&
  319 + gd->arch.resv_ram < base[0] + size[0])
  320 + size[0] = gd->arch.resv_ram - base[0];
  321 + else if (gd->arch.resv_ram >= base[1] &&
  322 + gd->arch.resv_ram < base[1] + size[1])
  323 + size[1] = gd->arch.resv_ram - base[1];
  324 +#endif
  325 +
316 326 fdt_fixup_memory_banks(blob, base, size, 2);
317 327  
318 328 fsl_fdt_fixup_dr_usb(blob, bd);
board/freescale/ls2080ardb/ddr.c
Diff comments   View file @ 36cc0de
... ... @@ -172,59 +172,4 @@
172 172  
173 173 return dram_size;
174 174 }
175   -
176   -void dram_init_banksize(void)
177   -{
178   -#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
179   - phys_size_t dp_ddr_size;
180   -#endif
181   -
182   - /*
183   - * gd->arch.secure_ram tracks the location of secure memory.
184   - * It was set as if the memory starts from 0.
185   - * The address needs to add the offset of its bank.
186   - */
187   - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
188   - if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) {
189   - gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
190   - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
191   - gd->bd->bi_dram[1].size = gd->ram_size -
192   - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
193   -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
194   - gd->arch.secure_ram = gd->bd->bi_dram[1].start +
195   - gd->arch.secure_ram -
196   - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
197   - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
198   -#endif
199   - } else {
200   - gd->bd->bi_dram[0].size = gd->ram_size;
201   -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
202   - gd->arch.secure_ram = gd->bd->bi_dram[0].start +
203   - gd->arch.secure_ram;
204   - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
205   -#endif
206   - }
207   -
208   -#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
209   - if (soc_has_dp_ddr()) {
210   - /* initialize DP-DDR here */
211   - puts("DP-DDR: ");
212   - /*
213   - * DDR controller use 0 as the base address for binding.
214   - * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
215   - */
216   - dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
217   - CONFIG_DP_DDR_CTRL,
218   - CONFIG_DP_DDR_NUM_CTRLS,
219   - CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
220   - NULL, NULL, NULL);
221   - if (dp_ddr_size) {
222   - gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
223   - gd->bd->bi_dram[2].size = dp_ddr_size;
224   - } else {
225   - puts("Not detected");
226   - }
227   - }
228   -#endif
229   -}
board/freescale/ls2080ardb/ls2080ardb.c
Diff comments   View file @ 36cc0de
... ... @@ -202,14 +202,6 @@
202 202 if (adjust_vdd(0))
203 203 printf("Warning: Adjusting core voltage failed.\n");
204 204  
205   -#if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD)
206   - if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
207   - efi_add_memory_map(gd->bd->bi_dram[2].start,
208   - gd->bd->bi_dram[2].size >> EFI_PAGE_SHIFT,
209   - EFI_RESERVED_MEMORY_TYPE, false);
210   - }
211   -#endif
212   -
213 205 return 0;
214 206 }
215 207  
... ... @@ -285,6 +277,16 @@
285 277 size[0] = gd->bd->bi_dram[0].size;
286 278 base[1] = gd->bd->bi_dram[1].start;
287 279 size[1] = gd->bd->bi_dram[1].size;
  280 +
  281 +#ifdef CONFIG_RESV_RAM
  282 + /* reduce size if reserved memory is within this bank */
  283 + if (gd->arch.resv_ram >= base[0] &&
  284 + gd->arch.resv_ram < base[0] + size[0])
  285 + size[0] = gd->arch.resv_ram - base[0];
  286 + else if (gd->arch.resv_ram >= base[1] &&
  287 + gd->arch.resv_ram < base[1] + size[1])
  288 + size[1] = gd->arch.resv_ram - base[1];
  289 +#endif
288 290  
289 291 fdt_fixup_memory_banks(blob, base, size, 2);
290 292  
... ... @@ -325,15 +325,6 @@
325 325 return gd->ram_top;
326 326 }
327 327  
328   -__weak phys_size_t board_reserve_ram_top(phys_size_t ram_size)
329   -{
330   -#ifdef CONFIG_SYS_MEM_TOP_HIDE
331   - return ram_size - CONFIG_SYS_MEM_TOP_HIDE;
332   -#else
333   - return ram_size;
334   -#endif
335   -}
336   -
337 328 static int setup_dest_addr(void)
338 329 {
339 330 debug("Monitor len: %08lX\n", gd->mon_len);
340 331  
341 332  
342 333  
... ... @@ -341,26 +332,19 @@
341 332 * Ram is setup, size stored in gd !!
342 333 */
343 334 debug("Ram size: %08lX\n", (ulong)gd->ram_size);
344   -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
345   - /* Reserve memory for secure MMU tables, and/or security monitor */
346   - gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
  335 +#if defined(CONFIG_SYS_MEM_TOP_HIDE)
347 336 /*
348   - * Record secure memory location. Need recalcuate if memory splits
349   - * into banks, or the ram base is not zero.
350   - */
351   - gd->arch.secure_ram = gd->ram_size;
352   -#endif
353   - /*
354 337 * Subtract specified amount of memory to hide so that it won't
355 338 * get "touched" at all by U-Boot. By fixing up gd->ram_size
356 339 * the Linux kernel should now get passed the now "corrected"
357   - * memory size and won't touch it either. This has been used
358   - * by arch/powerpc exclusively. Now ARMv8 takes advantage of
359   - * thie mechanism. If memory is split into banks, addresses
360   - * need to be calculated.
  340 + * memory size and won't touch it either. This should work
  341 + * for arch/ppc and arch/powerpc. Only Linux board ports in
  342 + * arch/powerpc with bootwrapper support, that recalculate the
  343 + * memory size from the SDRAM controller setup will have to
  344 + * get fixed.
361 345 */
362   - gd->ram_size = board_reserve_ram_top(gd->ram_size);
363   -
  346 + gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
  347 +#endif
364 348 #ifdef CONFIG_SYS_SDRAM_BASE
365 349 gd->ram_top = CONFIG_SYS_SDRAM_BASE;
366 350 #endif
drivers/net/fsl-mc/mc.c
Diff comments   View file @ 36cc0de
... ... @@ -714,21 +714,7 @@
714 714 */
715 715 u64 mc_get_dram_addr(void)
716 716 {
717   - u64 mc_ram_addr;
718   -
719   - /*
720   - * The MC private DRAM block was already carved at the end of DRAM
721   - * by board_init_f() using CONFIG_SYS_MEM_TOP_HIDE:
722   - */
723   - if (gd->bd->bi_dram[1].start) {
724   - mc_ram_addr =
725   - gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size;
726   - } else {
727   - mc_ram_addr =
728   - gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
729   - }
730   -
731   - return mc_ram_addr;
  717 + return gd->arch.resv_ram;
732 718 }
733 719  
734 720 /**