Eric Lee / smarc-uboot

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Commit 36da51ebacdc549b9d034a9241b6d88b06a951c5

Authored by Masahiro Yamada
Committed by Tom Rini
1 parent 814b661448
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

powerpc: mpc8xx: remove hermes board support 

This board sprinkles #ifdef(CONFIG_HERMES) over various global files
such as include/common.h, common/board_r.c, common/cmd_bdinfo.c.
Let's zap such an ill-behaved board.

It has not been converted to generic board yet and mpc8xx is old
enough.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>

Showing 17 changed files with 4 additions and 1664 deletions Side-by-side Diff

arch/powerpc/cpu/mpc8xx/Kconfig
Diff comments   View file @ 36da51e
... ... @@ -13,9 +13,6 @@
13 13 config TARGET_ESTEEM192E
14 14 bool "Support ESTEEM192E"
15 15  
16   -config TARGET_HERMES
17   - bool "Support hermes"
18   -
19 16 config TARGET_IP860
20 17 bool "Support IP860"
21 18  
... ... @@ -112,7 +109,6 @@
112 109 source "board/RRvision/Kconfig"
113 110 source "board/cogent/Kconfig"
114 111 source "board/esteem192e/Kconfig"
115   -source "board/hermes/Kconfig"
116 112 source "board/ip860/Kconfig"
117 113 source "board/ivm/Kconfig"
118 114 source "board/kup/kup4k/Kconfig"
arch/powerpc/cpu/mpc8xx/cpu_init.c
Diff comments   View file @ 36da51e
... ... @@ -125,8 +125,7 @@
125 125 * I owe him a free beer. - wd]
126 126 */
127 127  
128   -#if defined(CONFIG_HERMES) || \
129   - defined(CONFIG_IP860) || \
  128 +#if defined(CONFIG_IP860) || \
130 129 defined(CONFIG_IVML24) || \
131 130 defined(CONFIG_IVMS8) || \
132 131 defined(CONFIG_LWMON) || \
arch/powerpc/lib/board.c
Diff comments   View file @ 36da51e
... ... @@ -820,13 +820,6 @@
820 820 mac_read_from_eeprom();
821 821 #endif
822 822  
823   -#ifdef CONFIG_HERMES
824   - if ((gd->board_type >> 16) == 2)
825   - bd->bi_ethspeed = gd->board_type & 0xFFFF;
826   - else
827   - bd->bi_ethspeed = 0xFFFF;
828   -#endif
829   -
830 823 #ifdef CONFIG_CMD_NET
831 824 /* kept around for legacy kernels only ... ignore the next section */
832 825 eth_getenv_enetaddr("ethaddr", bd->bi_enetaddr);
... ... @@ -874,11 +867,6 @@
874 867 #if defined(CONFIG_MISC_INIT_R)
875 868 /* miscellaneous platform dependent initialisations */
876 869 misc_init_r();
877   -#endif
878   -
879   -#ifdef CONFIG_HERMES
880   - if (bd->bi_ethspeed != 0xFFFF)
881   - hermes_start_lxt980((int) bd->bi_ethspeed);
882 870 #endif
883 871  
884 872 #if defined(CONFIG_CMD_KGDB)
board/hermes/Kconfig
View file @ 36da51e
1   -if TARGET_HERMES
2   -
3   -config SYS_BOARD
4   - default "hermes"
5   -
6   -config SYS_CONFIG_NAME
7   - default "hermes"
8   -
9   -endif
board/hermes/MAINTAINERS
View file @ 36da51e
1   -HERMES BOARD
2   -M: Wolfgang Denk <wd@denx.de>
3   -S: Maintained
4   -F: board/hermes/
5   -F: include/configs/hermes.h
6   -F: configs/hermes_defconfig
board/hermes/Makefile
View file @ 36da51e
1   -#
2   -# (C) Copyright 2000-2006
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# SPDX-License-Identifier: GPL-2.0+
6   -#
7   -
8   -obj-y = hermes.o flash.o
board/hermes/flash.c
View file @ 36da51e
1   -/*
2   - * (C) Copyright 2000
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#include <common.h>
9   -#include <mpc8xx.h>
10   -
11   -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
12   -
13   -/*-----------------------------------------------------------------------
14   - * Functions
15   - */
16   -static ulong flash_get_size (vu_long *addr, flash_info_t *info);
17   -static int write_byte (flash_info_t *info, ulong dest, uchar data);
18   -static void flash_get_offsets (ulong base, flash_info_t *info);
19   -
20   -/*-----------------------------------------------------------------------
21   - */
22   -
23   -unsigned long flash_init (void)
24   -{
25   - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
26   - volatile memctl8xx_t *memctl = &immap->im_memctl;
27   - unsigned long size;
28   - int i;
29   -
30   - /* Init: no FLASHes known */
31   - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
32   - flash_info[i].flash_id = FLASH_UNKNOWN;
33   - }
34   -
35   - /* Static FLASH Bank configuration here - FIXME XXX */
36   -
37   - size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
38   -
39   - if (flash_info[0].flash_id == FLASH_UNKNOWN) {
40   - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
41   - size, size<<20);
42   - }
43   -
44   - /* Remap FLASH according to real size */
45   - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000);
46   - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) |
47   - (memctl->memc_br0 & ~(BR_BA_MSK));
48   -
49   - /* Re-do sizing to get full correct info */
50   - size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
51   -
52   - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
53   -
54   -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
55   - /* monitor protection ON by default */
56   - flash_protect(FLAG_PROTECT_SET,
57   - CONFIG_SYS_MONITOR_BASE,
58   - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
59   - &flash_info[0]);
60   -#endif
61   -
62   - flash_info[0].size = size;
63   -
64   - return (size);
65   -}
66   -
67   -/*-----------------------------------------------------------------------
68   - */
69   -static void flash_get_offsets (ulong base, flash_info_t *info)
70   -{
71   - int i;
72   -
73   - /* set up sector start address table */
74   - if (info->flash_id & FLASH_BTYPE) {
75   - /* set sector offsets for bottom boot block type */
76   - info->start[0] = base + 0x00000000;
77   - info->start[1] = base + 0x00004000;
78   - info->start[2] = base + 0x00006000;
79   - info->start[3] = base + 0x00008000;
80   - for (i = 4; i < info->sector_count; i++) {
81   - info->start[i] = base + (i * 0x00010000) - 0x00030000;
82   - }
83   - } else {
84   - /* set sector offsets for top boot block type */
85   - i = info->sector_count - 1;
86   - info->start[i--] = base + info->size - 0x00004000;
87   - info->start[i--] = base + info->size - 0x00006000;
88   - info->start[i--] = base + info->size - 0x00008000;
89   - for (; i >= 0; i--) {
90   - info->start[i] = base + i * 0x00010000;
91   - }
92   - }
93   -
94   -}
95   -
96   -/*-----------------------------------------------------------------------
97   - */
98   -void flash_print_info (flash_info_t *info)
99   -{
100   - int i;
101   -
102   - if (info->flash_id == FLASH_UNKNOWN) {
103   - printf ("missing or unknown FLASH type\n");
104   - return;
105   - }
106   -
107   - switch (info->flash_id & FLASH_VENDMASK) {
108   - case FLASH_MAN_AMD: printf ("AMD "); break;
109   - case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
110   - default: printf ("Unknown Vendor "); break;
111   - }
112   -
113   - switch (info->flash_id & FLASH_TYPEMASK) {
114   - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
115   - break;
116   - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
117   - break;
118   - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
119   - break;
120   - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
121   - break;
122   - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
123   - break;
124   - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
125   - break;
126   - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
127   - break;
128   - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
129   - break;
130   - default: printf ("Unknown Chip Type\n");
131   - break;
132   - }
133   -
134   - printf (" Size: %ld MB in %d Sectors\n",
135   - info->size >> 20, info->sector_count);
136   -
137   - printf (" Sector Start Addresses:");
138   - for (i=0; i<info->sector_count; ++i) {
139   - if ((i % 5) == 0)
140   - printf ("\n ");
141   - printf (" %08lX%s",
142   - info->start[i],
143   - info->protect[i] ? " (RO)" : " "
144   - );
145   - }
146   - printf ("\n");
147   - return;
148   -}
149   -
150   -/*-----------------------------------------------------------------------
151   - */
152   -
153   -
154   -/*-----------------------------------------------------------------------
155   - */
156   -
157   -/*
158   - * The following code cannot be run from FLASH!
159   - */
160   -
161   -static ulong flash_get_size (vu_long *addr, flash_info_t *info)
162   -{
163   - short i;
164   - uchar value;
165   - vu_char *caddr = (vu_char *)addr;
166   - ulong base = (ulong)addr;
167   -
168   -
169   - /* Write auto select command: read Manufacturer ID */
170   - caddr[0x0AAA] = 0xAA;
171   - caddr[0x0555] = 0x55;
172   - caddr[0x0AAA] = 0x90;
173   -
174   - value = caddr[0];
175   - switch (value) {
176   - case (AMD_MANUFACT & 0xFF):
177   - info->flash_id = FLASH_MAN_AMD;
178   - break;
179   - case (FUJ_MANUFACT & 0xFF):
180   - info->flash_id = FLASH_MAN_FUJ;
181   - break;
182   - default:
183   - info->flash_id = FLASH_UNKNOWN;
184   - info->sector_count = 0;
185   - info->size = 0;
186   - return (0); /* no or unknown flash */
187   - }
188   -
189   - value = caddr[2]; /* device ID */
190   -
191   - switch (value) {
192   - case (AMD_ID_LV400T & 0xFF):
193   - info->flash_id += FLASH_AM400T;
194   - info->sector_count = 11;
195   - info->size = 0x00080000;
196   - break; /* => 512 kB */
197   -
198   - case (AMD_ID_LV400B & 0xFF):
199   - info->flash_id += FLASH_AM400B;
200   - info->sector_count = 11;
201   - info->size = 0x00080000;
202   - break; /* => 512 kB */
203   -
204   - case (AMD_ID_LV800T & 0xFF):
205   - info->flash_id += FLASH_AM800T;
206   - info->sector_count = 19;
207   - info->size = 0x00100000;
208   - break; /* => 1 MB */
209   -
210   - case (AMD_ID_LV800B & 0xFF):
211   - info->flash_id += FLASH_AM800B;
212   - info->sector_count = 19;
213   - info->size = 0x00100000;
214   - break; /* => 1 MB */
215   -
216   - case (AMD_ID_LV160T & 0xFF):
217   - info->flash_id += FLASH_AM160T;
218   - info->sector_count = 35;
219   - info->size = 0x00200000;
220   - break; /* => 2 MB */
221   -
222   - case (AMD_ID_LV160B & 0xFF):
223   - info->flash_id += FLASH_AM160B;
224   - info->sector_count = 35;
225   - info->size = 0x00200000;
226   - break; /* => 2 MB */
227   -#if 0 /* enable when device IDs are available */
228   - case (AMD_ID_LV320T & 0xFF):
229   - info->flash_id += FLASH_AM320T;
230   - info->sector_count = 67;
231   - info->size = 0x00400000;
232   - break; /* => 4 MB */
233   -
234   - case (AMD_ID_LV320B & 0xFF):
235   - info->flash_id += FLASH_AM320B;
236   - info->sector_count = 67;
237   - info->size = 0x00400000;
238   - break; /* => 4 MB */
239   -#endif
240   - default:
241   - info->flash_id = FLASH_UNKNOWN;
242   - return (0); /* => no or unknown flash */
243   -
244   - }
245   -
246   - /* set up sector start address table */
247   - if (info->flash_id & FLASH_BTYPE) {
248   - /* set sector offsets for bottom boot block type */
249   - info->start[0] = base + 0x00000000;
250   - info->start[1] = base + 0x00004000;
251   - info->start[2] = base + 0x00006000;
252   - info->start[3] = base + 0x00008000;
253   - for (i = 4; i < info->sector_count; i++) {
254   - info->start[i] = base + (i * 0x00010000) - 0x00030000;
255   - }
256   - } else {
257   - /* set sector offsets for top boot block type */
258   - i = info->sector_count - 1;
259   - info->start[i--] = base + info->size - 0x00004000;
260   - info->start[i--] = base + info->size - 0x00006000;
261   - info->start[i--] = base + info->size - 0x00008000;
262   - for (; i >= 0; i--) {
263   - info->start[i] = base + i * 0x00010000;
264   - }
265   - }
266   -
267   - /* check for protected sectors */
268   - for (i = 0; i < info->sector_count; i++) {
269   - /* read sector protection: D0 = 1 if protected */
270   - caddr = (volatile unsigned char *)(info->start[i]);
271   - info->protect[i] = caddr[4] & 1;
272   - }
273   -
274   - /*
275   - * Prevent writes to uninitialized FLASH.
276   - */
277   - if (info->flash_id != FLASH_UNKNOWN) {
278   - caddr = (vu_char *)info->start[0];
279   -
280   - *caddr = 0xF0; /* reset bank */
281   - }
282   -
283   - return (info->size);
284   -}
285   -
286   -
287   -/*-----------------------------------------------------------------------
288   - */
289   -
290   -int flash_erase (flash_info_t *info, int s_first, int s_last)
291   -{
292   - vu_char *addr = (vu_char*)(info->start[0]);
293   - int flag, prot, sect, l_sect;
294   - ulong start, now, last;
295   -
296   - if ((s_first < 0) || (s_first > s_last)) {
297   - if (info->flash_id == FLASH_UNKNOWN) {
298   - printf ("- missing\n");
299   - } else {
300   - printf ("- no sectors to erase\n");
301   - }
302   - return 1;
303   - }
304   -
305   - if ((info->flash_id == FLASH_UNKNOWN) ||
306   - (info->flash_id > FLASH_AMD_COMP)) {
307   - printf ("Can't erase unknown flash type %08lx - aborted\n",
308   - info->flash_id);
309   - return 1;
310   - }
311   -
312   - prot = 0;
313   - for (sect=s_first; sect<=s_last; ++sect) {
314   - if (info->protect[sect]) {
315   - prot++;
316   - }
317   - }
318   -
319   - if (prot) {
320   - printf ("- Warning: %d protected sectors will not be erased!\n",
321   - prot);
322   - } else {
323   - printf ("\n");
324   - }
325   -
326   - l_sect = -1;
327   -
328   - /* Disable interrupts which might cause a timeout here */
329   - flag = disable_interrupts();
330   -
331   - addr[0x0AAA] = 0xAA;
332   - addr[0x0555] = 0x55;
333   - addr[0x0AAA] = 0x80;
334   - addr[0x0AAA] = 0xAA;
335   - addr[0x0555] = 0x55;
336   -
337   - /* Start erase on unprotected sectors */
338   - for (sect = s_first; sect<=s_last; sect++) {
339   - if (info->protect[sect] == 0) { /* not protected */
340   - addr = (vu_char*)(info->start[sect]);
341   - addr[0] = 0x30;
342   - l_sect = sect;
343   - }
344   - }
345   -
346   - /* re-enable interrupts if necessary */
347   - if (flag)
348   - enable_interrupts();
349   -
350   - /* wait at least 80us - let's wait 1 ms */
351   - udelay (1000);
352   -
353   - /*
354   - * We wait for the last triggered sector
355   - */
356   - if (l_sect < 0)
357   - goto DONE;
358   -
359   - start = get_timer (0);
360   - last = start;
361   - addr = (vu_char*)(info->start[l_sect]);
362   - while ((addr[0] & 0x80) != 0x80) {
363   - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
364   - printf ("Timeout\n");
365   - return 1;
366   - }
367   - /* show that we're waiting */
368   - if ((now - last) > 1000) { /* every second */
369   - putc ('.');
370   - last = now;
371   - }
372   - }
373   -
374   -DONE:
375   - /* reset to read mode */
376   - addr = (vu_char *)info->start[0];
377   - addr[0] = 0xF0; /* reset bank */
378   -
379   - printf (" done\n");
380   - return 0;
381   -}
382   -
383   -/*-----------------------------------------------------------------------
384   - * Copy memory to flash, returns:
385   - * 0 - OK
386   - * 1 - write timeout
387   - * 2 - Flash not erased
388   - */
389   -
390   -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
391   -{
392   - int rc;
393   -
394   - while (cnt > 0) {
395   - if ((rc = write_byte(info, addr++, *src++)) != 0) {
396   - return (rc);
397   - }
398   - --cnt;
399   - }
400   -
401   - return (0);
402   -}
403   -
404   -/*-----------------------------------------------------------------------
405   - * Write a word to Flash, returns:
406   - * 0 - OK
407   - * 1 - write timeout
408   - * 2 - Flash not erased
409   - */
410   -static int write_byte (flash_info_t *info, ulong dest, uchar data)
411   -{
412   - vu_char *addr = (vu_char*)(info->start[0]);
413   - ulong start;
414   - int flag;
415   -
416   - /* Check if Flash is (sufficiently) erased */
417   - if ((*((vu_char *)dest) & data) != data) {
418   - return (2);
419   - }
420   - /* Disable interrupts which might cause a timeout here */
421   - flag = disable_interrupts();
422   -
423   - addr[0x0AAA] = 0xAA;
424   - addr[0x0555] = 0x55;
425   - addr[0x0AAA] = 0xA0;
426   -
427   - *((vu_char *)dest) = data;
428   -
429   - /* re-enable interrupts if necessary */
430   - if (flag)
431   - enable_interrupts();
432   -
433   - /* data polling for D7 */
434   - start = get_timer (0);
435   - while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) {
436   - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
437   - return (1);
438   - }
439   - }
440   - return (0);
441   -}
442   -
443   -/*-----------------------------------------------------------------------
444   - */
board/hermes/hermes.c
View file @ 36da51e
1   -/*
2   - * (C) Copyright 2000
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#include <common.h>
9   -#include <commproc.h>
10   -#include <mpc8xx.h>
11   -
12   -#ifdef CONFIG_SHOW_BOOT_PROGRESS
13   -# include <status_led.h>
14   -# define SHOW_BOOT_PROGRESS(arg) bootstage_mark(arg)
15   -#else
16   -# define SHOW_BOOT_PROGRESS(arg)
17   -#endif
18   -
19   -DECLARE_GLOBAL_DATA_PTR;
20   -
21   -/* ------------------------------------------------------------------------- */
22   -
23   -static long int dram_size (long int, long int *, long int);
24   -static ulong board_init (void);
25   -static void send_smi_frame (volatile scc_t * sp, volatile cbd_t * bd,
26   - uchar * msg);
27   -
28   -/* ------------------------------------------------------------------------- */
29   -
30   -#define _NOT_USED_ 0xFFFFFFFF
31   -
32   -const uint sdram_table[] = {
33   - /*
34   - * Single Read. (Offset 0 in UPMA RAM)
35   - */
36   - 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
37   - 0x1ff77c47, /* last */
38   - /*
39   - * SDRAM Initialization (offset 5 in UPMA RAM)
40   - *
41   - * This is no UPM entry point. The following definition uses
42   - * the remaining space to establish an initialization
43   - * sequence, which is executed by a RUN command.
44   - *
45   - */
46   - 0x1fe77c35, 0xffaffc34, 0x1fa57c35, /* last */
47   - /*
48   - * Burst Read. (Offset 8 in UPMA RAM)
49   - */
50   - 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
51   - 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, /* last */
52   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
53   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
54   - /*
55   - * Single Write. (Offset 18 in UPMA RAM)
56   - */
57   - 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, /* last */
58   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
59   - /*
60   - * Burst Write. (Offset 20 in UPMA RAM)
61   - */
62   - 0x1f07fc04, 0xeeaebc00, 0x10ad4c00, 0xf0afcc00,
63   - 0xf0afcc00, 0xe1bb8c06, 0x1ff77c47, /* last */
64   - _NOT_USED_,
65   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
66   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
67   - /*
68   - * Refresh (Offset 30 in UPMA RAM)
69   - */
70   - 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
71   - 0xfffffc84, 0xfffffc07, /* last */
72   - _NOT_USED_, _NOT_USED_,
73   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
74   - /*
75   - * Exception. (Offset 3c in UPMA RAM)
76   - */
77   - 0x7ffffc07, /* last */
78   - _NOT_USED_, _NOT_USED_, _NOT_USED_,
79   -};
80   -
81   -/* ------------------------------------------------------------------------- */
82   -
83   -
84   -/*
85   - * Check Board Identity:
86   - *
87   - * Test ID string (HERMES...)
88   - *
89   - * Return code for board revision and network speed
90   - */
91   -
92   -int checkboard (void)
93   -{
94   - char buf[64];
95   - int i;
96   - int l = getenv_f("serial#", buf, sizeof(buf));
97   -
98   - puts ("Board: ");
99   -
100   - if (l < 0 || strncmp(buf, "HERMES", 6)) {
101   - puts ("### No HW ID - assuming HERMES-PRO");
102   - } else {
103   - for (i = 0; i < l; i++) {
104   - if (buf[i] == ' ')
105   - break;
106   - putc (buf[i]);
107   - }
108   - }
109   -
110   - gd->board_type = board_init ();
111   -
112   - printf (" Rev. %ld.x\n", (gd->board_type >> 16));
113   -
114   - return (0);
115   -}
116   -
117   -/* ------------------------------------------------------------------------- */
118   -
119   -phys_size_t initdram (int board_type)
120   -{
121   - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
122   - volatile memctl8xx_t *memctl = &immap->im_memctl;
123   - long int size, size8, size9;
124   -
125   - upmconfig (UPMA, (uint *) sdram_table,
126   - sizeof (sdram_table) / sizeof (uint));
127   -
128   - /*
129   - * Preliminary prescaler for refresh
130   - */
131   - memctl->memc_mptpr = 0x0400;
132   -
133   - memctl->memc_mar = 0x00000088;
134   -
135   - /*
136   - * Map controller banks 1 to the SDRAM banks at preliminary address
137   - */
138   - memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
139   - memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
140   -
141   - /* HERMES-PRO boards have only one bank SDRAM */
142   -
143   -
144   - udelay (200);
145   -
146   - /* perform SDRAM initializsation sequence */
147   -
148   - memctl->memc_mamr = 0xD0802114;
149   - memctl->memc_mcr = 0x80002105;
150   - udelay (1);
151   - memctl->memc_mamr = 0xD0802118;
152   - memctl->memc_mcr = 0x80002130;
153   - udelay (1);
154   - memctl->memc_mamr = 0xD0802114;
155   - memctl->memc_mcr = 0x80002106;
156   -
157   - udelay (1000);
158   -
159   - /*
160   - * Check Bank 0 Memory Size for re-configuration
161   - *
162   - * try 8 column mode
163   - */
164   - size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE_PRELIM,
165   - SDRAM_MAX_SIZE);
166   -
167   - udelay (1000);
168   -
169   - /*
170   - * try 9 column mode
171   - */
172   - size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE_PRELIM,
173   - SDRAM_MAX_SIZE);
174   -
175   - if (size8 < size9) { /* leave configuration at 9 columns */
176   - size = size9;
177   -/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
178   - } else { /* back to 8 columns */
179   - size = size8;
180   - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
181   - udelay (500);
182   -/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
183   - }
184   -
185   - udelay (1000);
186   -
187   - memctl->memc_or1 = ((-size) & 0xFFFF0000) | SDRAM_TIMING;
188   - memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
189   -
190   - udelay (10000);
191   -
192   - return (size);
193   -}
194   -
195   -/* ------------------------------------------------------------------------- */
196   -
197   -/*
198   - * Check memory range for valid RAM. A simple memory test determines
199   - * the actually available RAM size between addresses `base' and
200   - * `base + maxsize'. Some (not all) hardware errors are detected:
201   - * - short between address lines
202   - * - short between data lines
203   - */
204   -
205   -static long int dram_size (long int mamr_value, long int *base,
206   - long int maxsize)
207   -{
208   - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
209   - volatile memctl8xx_t *memctl = &immap->im_memctl;
210   -
211   - memctl->memc_mamr = mamr_value;
212   -
213   - return (get_ram_size(base, maxsize));
214   -}
215   -
216   -/* ------------------------------------------------------------------------- */
217   -
218   -#define PB_LED_3 0x00020000 /* Status LED's */
219   -#define PB_LED_2 0x00010000
220   -#define PB_LED_1 0x00008000
221   -#define PB_LED_0 0x00004000
222   -
223   -#define PB_LED_ALL (PB_LED_0 | PB_LED_1 | PB_LED_2 | PB_LED_3)
224   -
225   -#define PC_REP_SPD1 0x00000800
226   -#define PC_REP_SPD0 0x00000400
227   -
228   -#define PB_RESET_2081 0x00000020 /* Reset PEB2081 */
229   -
230   -#define PB_MAI_4 0x00000010 /* Configuration */
231   -#define PB_MAI_3 0x00000008
232   -#define PB_MAI_2 0x00000004
233   -#define PB_MAI_1 0x00000002
234   -#define PB_MAI_0 0x00000001
235   -
236   -#define PB_MAI_ALL (PB_MAI_0 | PB_MAI_1 | PB_MAI_2 | PB_MAI_3 | PB_MAI_4)
237   -
238   -
239   -#define PC_REP_MGRPRS 0x0200
240   -#define PC_REP_SPD 0x0040 /* Select 100 Mbps */
241   -#define PC_REP_RES 0x0004
242   -#define PC_BIT14 0x0002 /* ??? */
243   -#define PC_BIT15 0x0001 /* ??? ENDSL ?? */
244   -
245   -/* ------------------------------------------------------------------------- */
246   -
247   -static ulong board_init (void)
248   -{
249   - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
250   - ulong reg, revision, speed = 100;
251   - int ethspeed;
252   - char *s;
253   -
254   - if ((s = getenv ("ethspeed")) != NULL) {
255   - if (strcmp (s, "100") == 0) {
256   - ethspeed = 100;
257   - } else if (strcmp (s, "10") == 0) {
258   - ethspeed = 10;
259   - } else {
260   - ethspeed = 0;
261   - }
262   - } else {
263   - ethspeed = 0;
264   - }
265   -
266   - /* Configure Port B Output Pins => 0x0003cc3F */
267   - reg = PB_LED_ALL | PC_REP_SPD1 | PC_REP_SPD0 | PB_RESET_2081 |
268   - PB_MAI_ALL;
269   - immr->im_cpm.cp_pbpar &= ~reg;
270   - immr->im_cpm.cp_pbodr &= ~reg;
271   - immr->im_cpm.cp_pbdat &= ~reg; /* all 0 */
272   - immr->im_cpm.cp_pbdir |= reg;
273   -
274   - /* Check hardware revision */
275   - if ((immr->im_ioport.iop_pcdat & 0x0003) == 0x0003) {
276   - /*
277   - * Revision 3.x hardware
278   - */
279   - revision = 3;
280   -
281   - immr->im_ioport.iop_pcdat = 0x0240;
282   - immr->im_ioport.iop_pcdir = (PC_REP_MGRPRS | PC_REP_SPD | PC_REP_RES | PC_BIT14); /* = 0x0246 */
283   - immr->im_ioport.iop_pcdat |= PC_REP_RES;
284   - } else {
285   - immr->im_ioport.iop_pcdat = 0x0002;
286   - immr->im_ioport.iop_pcdir = (PC_REP_MGRPRS | PC_REP_RES | PC_BIT14 | PC_BIT15); /* = 0x0207 */
287   -
288   - if ((immr->im_ioport.iop_pcdat & PC_REP_SPD) == 0) {
289   - /*
290   - * Revision 2.x hardware: PC9 connected to PB21
291   - */
292   - revision = 2;
293   -
294   - if (ethspeed == 0) {
295   - /* both 10 and 100 Mbps allowed:
296   - * select 10 Mbps and autonegotiation
297   - */
298   - puts (" [10+100]");
299   - immr->im_cpm.cp_pbdat = 0; /* SPD1:SPD0 = 0:0 - autonegot. */
300   - speed = 10;
301   - } else if (ethspeed == 10) {
302   - /* we are asked for 10 Mbps,
303   - * so select 10 Mbps
304   - */
305   - puts (" [10]");
306   - immr->im_cpm.cp_pbdat = 0; /* ??? */
307   - speed = 10;
308   - } else {
309   - /* anything else:
310   - * select 100 Mbps
311   - */
312   - puts (" [100]");
313   - immr->im_cpm.cp_pbdat = PC_REP_SPD0 | PC_REP_SPD1;
314   - /* SPD1:SPD0 = 1:1 - 100 Mbps */
315   - speed = 100;
316   - }
317   - immr->im_ioport.iop_pcdat |= (PC_REP_RES | PC_BIT14);
318   -
319   - /* must be run from RAM */
320   - /* start_lxt980 (speed); */
321   - /*************************/
322   - } else {
323   - /*
324   - * Revision 1.x hardware
325   - */
326   - revision = 1;
327   -
328   - immr->im_ioport.iop_pcdat = PC_REP_MGRPRS | PC_BIT14; /* = 0x0202 */
329   - immr->im_ioport.iop_pcdir = (PC_REP_MGRPRS | PC_REP_SPD | PC_REP_RES | PC_BIT14 | PC_BIT15); /* = 0x0247 */
330   -
331   - if (ethspeed == 0) {
332   - /* both 10 and 100 Mbps allowed:
333   - * select 100 Mbps and autonegotiation
334   - */
335   - puts (" [10+100]");
336   - immr->im_cpm.cp_pbdat = 0; /* SPD1:SPD0 = 0:0 - autonegot. */
337   - immr->im_ioport.iop_pcdat |= PC_REP_SPD;
338   - } else if (ethspeed == 10) {
339   - /* we are asked for 10 Mbps,
340   - * so select 10 Mbps
341   - */
342   - puts (" [10]");
343   - immr->im_cpm.cp_pbdat = PC_REP_SPD0; /* SPD1:SPD0 = 0:1 - 10 Mbps */
344   - } else {
345   - /* anything else:
346   - * select 100 Mbps
347   - */
348   - puts (" [100]");
349   - immr->im_cpm.cp_pbdat = PC_REP_SPD0 | PC_REP_SPD1;
350   - /* SPD1:SPD0 = 1:1 - 100 Mbps */
351   - immr->im_ioport.iop_pcdat |= PC_REP_SPD;
352   - }
353   -
354   - immr->im_ioport.iop_pcdat |= PC_REP_RES;
355   - }
356   - }
357   - SHOW_BOOT_PROGRESS(BOOTSTAGE_ID_CHECK_MAGIC);
358   -
359   - return ((revision << 16) | (speed & 0xFFFF));
360   -}
361   -
362   -/* ------------------------------------------------------------------------- */
363   -
364   -#define SCC_SM 1 /* Index => SCC2 */
365   -#define PROFF PROFF_SCC2
366   -
367   -#define SMI_MSGLEN 8 /* Length of SMI Messages */
368   -
369   -#define PHYGPCR_ADDR 0x109 /* Port Enable */
370   -#define PHYPCR_ADDR 0x132 /* PHY Port Control Reg. (port 1) */
371   -#define LEDPCR_ADDR 0x141 /* LED Port Control Reg. */
372   -#define RPRESET_ADDR 0x144 /* Repeater Reset */
373   -
374   -#define PHYPCR_SPEED 0x2000 /* on for 100 Mbps, off for 10 Mbps */
375   -#define PHYPCR_AN 0x1000 /* on to enable Auto-Negotiation */
376   -#define PHYPCR_REST_AN 0x0200 /* on to restart Auto-Negotiation */
377   -#define PHYPCR_FDX 0x0100 /* on for Full Duplex, off for HDX */
378   -#define PHYPCR_COLT 0x0080 /* on to enable COL signal test */
379   -
380   -/* ------------------------------------------------------------------------- */
381   -
382   -/*
383   - * Must run from RAM:
384   - * uses parameter RAM area which is used for stack while running from ROM
385   - */
386   -void hermes_start_lxt980 (int speed)
387   -{
388   - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
389   - volatile cpm8xx_t *cp = (cpm8xx_t *) & (immr->im_cpm);
390   - volatile scc_t *sp = (scc_t *) & (cp->cp_scc[SCC_SM]);
391   - volatile cbd_t *bd;
392   - volatile hdlc_pram_t *hp;
393   - uchar smimsg[SMI_MSGLEN];
394   - ushort phypcrval;
395   - uint bd_off;
396   - int pnr;
397   -
398   - printf ("LXT9880: %3d Mbps\n", speed);
399   -
400   - immr->im_ioport.iop_paodr |= 0x0008; /* init PAODR: PA12 (TXD2) open drain */
401   - immr->im_ioport.iop_papar |= 0x400c; /* init PAPAR: TXD2, RXD2, BRGO4 */
402   - immr->im_ioport.iop_padir &= 0xbff3; /* init PADIR: BRGO4 */
403   - immr->im_ioport.iop_padir |= 0x4000;
404   -
405   - /* get temporary BD; no need for permanent alloc */
406   - bd_off = dpram_base_align (8);
407   -
408   - bd = (cbd_t *) (immr->im_cpm.cp_dpmem + bd_off);
409   -
410   - bd->cbd_bufaddr = 0;
411   - bd->cbd_datlen = 0;
412   - bd->cbd_sc = BD_SC_WRAP | BD_SC_LAST | BD_SC_INTRPT | BD_SC_TC;
413   -
414   - /* init. baudrate generator BRG4 */
415   - cp->cp_brgc4 = (0x00010000 | (50 << 1)); /* output 1 MHz */
416   -
417   - cp->cp_sicr &= 0xFFFF00FF; /* SICR: mask SCC2 */
418   - cp->cp_sicr |= 0x00001B00; /* SICR: SCC2 clk BRG4 */
419   -
420   - /* init SCC_SM register */
421   - sp->scc_psmr = 0x0000; /* init PSMR: no additional flags */
422   - sp->scc_todr = 0x0000;
423   - sp->scc_dsr = 0x7e7e;
424   -
425   - /* init. SCC_SM parameter area */
426   - hp = (hdlc_pram_t *) & cp->cp_dparam[PROFF];
427   -
428   - hp->tbase = bd_off; /* offset from beginning of DPRAM */
429   -
430   - hp->rfcr = 0x18;
431   - hp->tfcr = 0x18;
432   - hp->mrblr = 10;
433   -
434   - hp->c_mask = 0x0000f0b8;
435   - hp->c_pres = 0x0000ffff;
436   -
437   - hp->disfc = 0;
438   - hp->crcec = 0;
439   - hp->abtsc = 0;
440   - hp->nmarc = 0;
441   - hp->retrc = 0;
442   -
443   - hp->mflr = 10;
444   -
445   - hp->rfthr = 1;
446   -
447   - hp->hmask = 0;
448   - hp->haddr1 = 0;
449   - hp->haddr2 = 0;
450   - hp->haddr3 = 0;
451   - hp->haddr4 = 0;
452   -
453   - cp->cp_cpcr = SCC_SM << 6 | 0x0001; /* SCC_SM: init TX/RX params */
454   - while (cp->cp_cpcr & CPM_CR_FLG);
455   -
456   - /* clear all outstanding SCC events */
457   - sp->scc_scce = ~0;
458   -
459   - /* enable transmitter: GSMR_L: TPL=2(16bits), TPP=3(all ones), ENT */
460   - sp->scc_gsmrh = 0;
461   - sp->scc_gsmrl |= SCC_GSMRL_TPL_16 | SCC_GSMRL_TPP_ALL1 |
462   - SCC_GSMRL_ENT | SCC_GSMRL_MODE_HDLC;
463   -
464   -#if 0
465   - smimsg[0] = 0x00; /* CHIP/HUB ID */
466   - smimsg[1] = 0x38; /* WRITE CMD */
467   - smimsg[2] = (RPRESET_ADDR << 4) & 0xf0;
468   - smimsg[3] = RPRESET_ADDR >> 4;
469   - smimsg[4] = 0x01;
470   - smimsg[5] = 0x00;
471   - smimsg[6] = 0x00;
472   - smimsg[7] = 0x00;
473   -
474   - send_smi_frame (sp, bd, smimsg);
475   -#endif
476   -
477   - smimsg[0] = 0x7f; /* BROADCAST */
478   - smimsg[1] = 0x34; /* ASSIGN HUB ID */
479   - smimsg[2] = 0x00;
480   - smimsg[3] = 0x00;
481   - smimsg[4] = 0x00; /* HUB ID = 0 */
482   - smimsg[5] = 0x00;
483   - smimsg[6] = 0x00;
484   - smimsg[7] = 0x00;
485   -
486   - send_smi_frame (sp, bd, smimsg);
487   -
488   - smimsg[0] = 0x7f; /* BROADCAST */
489   - smimsg[1] = 0x3c; /* SET ARBOUT TO 0 */
490   - smimsg[2] = 0x00; /* ADDRESS = 0 */
491   - smimsg[3] = 0x00;
492   - smimsg[4] = 0x00; /* DATA = 0 */
493   - smimsg[5] = 0x00;
494   - smimsg[6] = 0x00;
495   - smimsg[7] = 0x00;
496   -
497   - send_smi_frame (sp, bd, smimsg);
498   -
499   - if (speed == 100) {
500   - phypcrval = PHYPCR_SPEED; /* 100 MBIT, disable autoneg. */
501   - } else {
502   - phypcrval = 0; /* 10 MBIT, disable autoneg. */
503   - }
504   -
505   - /* send MSGs */
506   - for (pnr = 0; pnr < 8; pnr++) {
507   - smimsg[0] = 0x00; /* CHIP/HUB ID */
508   - smimsg[1] = 0x38; /* WRITE CMD */
509   - smimsg[2] = ((PHYPCR_ADDR + pnr) << 4) & 0xf0;
510   - smimsg[3] = (PHYPCR_ADDR + pnr) >> 4;
511   - smimsg[4] = (unsigned char) (phypcrval & 0xff);
512   - smimsg[5] = (unsigned char) (phypcrval >> 8);
513   - smimsg[6] = 0x00;
514   - smimsg[7] = 0x00;
515   -
516   - send_smi_frame (sp, bd, smimsg);
517   - }
518   -
519   - smimsg[0] = 0x00; /* CHIP/HUB ID */
520   - smimsg[1] = 0x38; /* WRITE CMD */
521   - smimsg[2] = (PHYGPCR_ADDR << 4) & 0xf0;
522   - smimsg[3] = PHYGPCR_ADDR >> 4;
523   - smimsg[4] = 0xff; /* enable port 1-8 */
524   - smimsg[5] = 0x01; /* enable MII1 (0x01) */
525   - smimsg[6] = 0x00;
526   - smimsg[7] = 0x00;
527   -
528   - send_smi_frame (sp, bd, smimsg);
529   -
530   - smimsg[0] = 0x00; /* CHIP/HUB ID */
531   - smimsg[1] = 0x38; /* WRITE CMD */
532   - smimsg[2] = (LEDPCR_ADDR << 4) & 0xf0;
533   - smimsg[3] = LEDPCR_ADDR >> 4;
534   - smimsg[4] = 0xaa; /* Port 1-8 Conf.bits = 10 (Hardware control) */
535   - smimsg[5] = 0xaa;
536   - smimsg[6] = 0x00;
537   - smimsg[7] = 0x00;
538   -
539   - send_smi_frame (sp, bd, smimsg);
540   -
541   - /*
542   - * Disable Transmitter (so that we can free the BD, too)
543   - */
544   - sp->scc_gsmrl &= ~SCC_GSMRL_ENT;
545   -}
546   -
547   -/* ------------------------------------------------------------------------- */
548   -
549   -static void send_smi_frame (volatile scc_t * sp, volatile cbd_t * bd,
550   - uchar * msg)
551   -{
552   -#ifdef DEBUG
553   - unsigned hub, chip, cmd, length, addr;
554   -
555   - hub = msg[0] & 0x1F;
556   - chip = msg[0] >> 5;
557   - cmd = msg[1] & 0x1F;
558   - length = (msg[1] >> 5) | ((msg[2] & 0x0F) << 3);
559   - addr = (msg[2] >> 4) | (msg[3] << 4);
560   -
561   - printf ("SMI send: Hub %02x Chip %x Cmd %02x Len %d Addr %03x: "
562   - "%02x %02x %02x %02x\n",
563   - hub, chip, cmd, length, addr, msg[4], msg[5], msg[6], msg[7]);
564   -#endif /* DEBUG */
565   -
566   - bd->cbd_bufaddr = (uint) msg;
567   - bd->cbd_datlen = SMI_MSGLEN;
568   - bd->cbd_sc |= BD_SC_READY;
569   -
570   - /* wait for msg transmitted */
571   - while ((sp->scc_scce & 0x0002) == 0);
572   - /* clear all events */
573   - sp->scc_scce = ~0;
574   -}
575   -
576   -/* ------------------------------------------------------------------------- */
577   -
578   -void show_boot_progress (int status)
579   -{
580   - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
581   -
582   - /* let things compatible */
583   - if (status < -BOOTSTAGE_ID_POST_FAIL_R)
584   - status = -1;
585   - status ^= 0x0F;
586   - status = (status & 0x0F) << 14;
587   - immr->im_cpm.cp_pbdat = (immr->im_cpm.cp_pbdat & ~PB_LED_ALL) | status;
588   -}
589   -
590   -/* ------------------------------------------------------------------------- */
board/hermes/u-boot.lds
View file @ 36da51e
1   -/*
2   - * (C) Copyright 2000-2010
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -OUTPUT_ARCH(powerpc)
9   -
10   -SECTIONS
11   -{
12   - /* Read-only sections, merged into text segment: */
13   - . = + SIZEOF_HEADERS;
14   - .text :
15   - {
16   - /* WARNING - the following is hand-optimized to fit within */
17   - /* the sector layout of our flash chips! XXX FIXME XXX */
18   - arch/powerpc/cpu/mpc8xx/start.o (.text*)
19   - arch/powerpc/cpu/mpc8xx/traps.o (.text*)
20   - board/hermes/built-in.o (.text*)
21   -
22   - . = env_offset;
23   - common/env_embedded.o (.text*)
24   -
25   - *(.text*)
26   - }
27   - _etext = .;
28   - PROVIDE (etext = .);
29   - .rodata :
30   - {
31   - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
32   - }
33   -
34   - /* Read-write section, merged into data segment: */
35   - . = (. + 0x00FF) & 0xFFFFFF00;
36   - _erotext = .;
37   - PROVIDE (erotext = .);
38   - .reloc :
39   - {
40   - _GOT2_TABLE_ = .;
41   - KEEP(*(.got2))
42   - KEEP(*(.got))
43   - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
44   - _FIXUP_TABLE_ = .;
45   - KEEP(*(.fixup))
46   - }
47   - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
48   - __fixup_entries = (. - _FIXUP_TABLE_)>>2;
49   -
50   - .data :
51   - {
52   - *(.data*)
53   - *(.sdata*)
54   - }
55   - _edata = .;
56   - PROVIDE (edata = .);
57   -
58   - . = .;
59   -
60   - . = ALIGN(4);
61   - .u_boot_list : {
62   - KEEP(*(SORT(.u_boot_list*)));
63   - }
64   -
65   -
66   - . = .;
67   - __start___ex_table = .;
68   - __ex_table : { *(__ex_table) }
69   - __stop___ex_table = .;
70   -
71   - . = ALIGN(256);
72   - __init_begin = .;
73   - .text.init : { *(.text.init) }
74   - .data.init : { *(.data.init) }
75   - . = ALIGN(256);
76   - __init_end = .;
77   -
78   - __bss_start = .;
79   - .bss (NOLOAD) :
80   - {
81   - *(.bss*)
82   - *(.sbss*)
83   - *(COMMON)
84   - . = ALIGN(4);
85   - }
86   - __bss_end = . ;
87   - PROVIDE (end = .);
88   -}
board/hermes/u-boot.lds.debug
View file @ 36da51e
1   -/*
2   - * (C) Copyright 2000
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -OUTPUT_ARCH(powerpc)
9   -/* Do we need any of these for elf?
10   - __DYNAMIC = 0; */
11   -SECTIONS
12   -{
13   - /* Read-only sections, merged into text segment: */
14   - . = + SIZEOF_HEADERS;
15   - .interp : { *(.interp) }
16   - .hash : { *(.hash) }
17   - .dynsym : { *(.dynsym) }
18   - .dynstr : { *(.dynstr) }
19   - .rel.text : { *(.rel.text) }
20   - .rela.text : { *(.rela.text) }
21   - .rel.data : { *(.rel.data) }
22   - .rela.data : { *(.rela.data) }
23   - .rel.rodata : { *(.rel.rodata) }
24   - .rela.rodata : { *(.rela.rodata) }
25   - .rel.got : { *(.rel.got) }
26   - .rela.got : { *(.rela.got) }
27   - .rel.ctors : { *(.rel.ctors) }
28   - .rela.ctors : { *(.rela.ctors) }
29   - .rel.dtors : { *(.rel.dtors) }
30   - .rela.dtors : { *(.rela.dtors) }
31   - .rel.bss : { *(.rel.bss) }
32   - .rela.bss : { *(.rela.bss) }
33   - .rel.plt : { *(.rel.plt) }
34   - .rela.plt : { *(.rela.plt) }
35   - .init : { *(.init) }
36   - .plt : { *(.plt) }
37   - .text :
38   - {
39   - /* WARNING - the following is hand-optimized to fit within */
40   - /* the sector layout of our flash chips! XXX FIXME XXX */
41   -
42   - arch/powerpc/cpu/mpc8xx/start.o (.text)
43   - arch/powerpc/lib/ppcstring.o (.text)
44   - arch/powerpc/cpu/mpc8xx/interrupts.o (.text)
45   - arch/powerpc/lib/time.o (.text)
46   - arch/powerpc/lib/ticks.o (.text)
47   - . = env_offset;
48   - common/env_embedded.o(.text)
49   -
50   - *(.text)
51   - *(.got1)
52   - }
53   - _etext = .;
54   - PROVIDE (etext = .);
55   - .rodata :
56   - {
57   - *(.rodata)
58   - *(.rodata1)
59   - *(.rodata.str1.4)
60   - *(.eh_frame)
61   - }
62   - .fini : { *(.fini) } =0
63   - .ctors : { *(.ctors) }
64   - .dtors : { *(.dtors) }
65   -
66   - /* Read-write section, merged into data segment: */
67   - . = (. + 0x0FFF) & 0xFFFFF000;
68   - _erotext = .;
69   - PROVIDE (erotext = .);
70   - .reloc :
71   - {
72   - *(.got)
73   - _GOT2_TABLE_ = .;
74   - *(.got2)
75   - _FIXUP_TABLE_ = .;
76   - *(.fixup)
77   - }
78   - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
79   - __fixup_entries = (. - _FIXUP_TABLE_)>>2;
80   -
81   - .data :
82   - {
83   - *(.data)
84   - *(.data1)
85   - *(.sdata)
86   - *(.sdata2)
87   - *(.dynamic)
88   - CONSTRUCTORS
89   - }
90   - _edata = .;
91   - PROVIDE (edata = .);
92   -
93   -
94   - . = ALIGN(4);
95   - .u_boot_list : {
96   - KEEP(*(SORT(.u_boot_list*)));
97   - }
98   -
99   -
100   - __start___ex_table = .;
101   - __ex_table : { *(__ex_table) }
102   - __stop___ex_table = .;
103   -
104   - . = ALIGN(4096);
105   - __init_begin = .;
106   - .text.init : { *(.text.init) }
107   - .data.init : { *(.data.init) }
108   - . = ALIGN(4096);
109   - __init_end = .;
110   -
111   - __bss_start = .;
112   - .bss :
113   - {
114   - *(.sbss) *(.scommon)
115   - *(.dynbss)
116   - *(.bss)
117   - *(COMMON)
118   - }
119   - __bss_end = . ;
120   - PROVIDE (end = .);
121   -}
... ... @@ -454,24 +454,6 @@
454 454 return 0;
455 455 }
456 456  
457   -#ifdef CONFIG_HERMES
458   -static int initr_hermes(void)
459   -{
460   - if ((gd->board_type >> 16) == 2)
461   - gd->bd->bi_ethspeed = gd->board_type & 0xFFFF;
462   - else
463   - gd->bd->bi_ethspeed = 0xFFFF;
464   - return 0;
465   -}
466   -
467   -static int initr_hermes_start(void)
468   -{
469   - if (gd->bd->bi_ethspeed != 0xFFFF)
470   - hermes_start_lxt980((int) gd->bd->bi_ethspeed);
471   - return 0;
472   -}
473   -#endif
474   -
475 457 #ifdef CONFIG_SC3
476 458 /* TODO: with new initcalls, move this into the driver */
477 459 extern void sc3_read_eeprom(void);
... ... @@ -803,9 +785,6 @@
803 785 #ifdef CONFIG_SC3
804 786 initr_sc3_read_eeprom,
805 787 #endif
806   -#ifdef CONFIG_HERMES
807   - initr_hermes,
808   -#endif
809 788 #if defined(CONFIG_ID_EEPROM) || defined(CONFIG_SYS_I2C_MAC_OFFSET)
810 789 mac_read_from_eeprom,
811 790 #endif
... ... @@ -830,9 +809,6 @@
830 809 #endif
831 810 #ifdef CONFIG_MISC_INIT_R
832 811 misc_init_r, /* miscellaneous platform-dependent init */
833   -#endif
834   -#ifdef CONFIG_HERMES
835   - initr_hermes_start,
836 812 #endif
837 813 INIT_FUNC_WATCHDOG_RESET
838 814 #ifdef CONFIG_CMD_KGDB
... ... @@ -144,9 +144,6 @@
144 144 print_eth(5);
145 145 #endif
146 146  
147   -#ifdef CONFIG_HERMES
148   - print_mhz("ethspeed", bd->bi_ethspeed);
149   -#endif
150 147 printf("IP addr = %s\n", getenv("ipaddr"));
151 148 printf("baudrate = %6u bps\n", gd->baudrate);
152 149 print_num("relocaddr", gd->relocaddr);
configs/hermes_defconfig
View file @ 36da51e
1   -CONFIG_PPC=y
2   -CONFIG_8xx=y
3   -CONFIG_TARGET_HERMES=y
doc/README.scrapyard
Diff comments   View file @ 36da51e
... ... @@ -12,8 +12,9 @@
12 12  
13 13 Board Arch CPU Commit Removed Last known maintainer/contact
14 14 =================================================================================================
15   -PRS200 powerpc mpc5200 - -
16   -MCC200 powerpc mpc5200 - -
  15 +hermes powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
  16 +PRS200 powerpc mpc5200 ecfdcee 2014-11-12
  17 +MCC200 powerpc mpc5200 ecfdcee 2014-11-12
17 18 TOP5200 powerpc mpc5200 d58a945 2014-10-28 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
18 19 TOP860 powerpc mpc860 d58a945 2014-10-28 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
19 20 TOP9000 arm at91sam9xeXXX d58a945 2014-10-28 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
... ... @@ -445,11 +445,6 @@
445 445 extern ssize_t spi_write (uchar *, int, uchar *, int);
446 446 #endif
447 447  
448   -#ifdef CONFIG_HERMES
449   -/* $(BOARD)/hermes.c */
450   -void hermes_start_lxt980 (int speed);
451   -#endif
452   -
453 448 #ifdef CONFIG_EVB64260
454 449 void evb64260_init(void);
455 450 void debug_led(int, int);
... ... @@ -535,34 +535,6 @@
535 535 #define SICR_ENET_CLKRT ((uint)0x00002600)
536 536 #endif /* CONFIG_FPS850L, CONFIG_FPS860L */
537 537  
538   -/*** HERMES-PRO ******************************************************/
539   -
540   -/* The HERMES-PRO uses the FEC on a MPC860T for Ethernet */
541   -
542   -#ifdef CONFIG_HERMES
543   -
544   -#define FEC_ENET /* use FEC for EThernet */
545   -#undef SCC_ENET
546   -
547   -
548   -#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
549   -#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
550   -#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
551   -#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
552   -#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
553   -#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
554   -#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
555   -#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
556   -#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
557   -#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
558   -#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
559   -#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
560   -#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
561   -
562   -#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
563   -
564   -#endif /* CONFIG_HERMES */
565   -
566 538 /*** IP860 **********************************************************/
567 539  
568 540 #if defined(CONFIG_IP860)
include/configs/hermes.h
View file @ 36da51e
1   -/*
2   - * (C) Copyright 2000
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -/*
9   - * board/config.h - configuration options, board specific
10   - */
11   -
12   -#ifndef __CONFIG_H
13   -#define __CONFIG_H
14   -
15   -/*
16   - * High Level Configuration Options
17   - * (easy to change)
18   - */
19   -
20   -#define CONFIG_MPC860 1 /* This is a MPC860T CPU */
21   -#define CONFIG_HERMES 1 /* ...on a HERMES-PRO board */
22   -
23   -#define CONFIG_SYS_TEXT_BASE 0xFE000000
24   -
25   -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
26   -#undef CONFIG_8xx_CONS_SMC2
27   -#undef CONFIG_8xx_CONS_NONE
28   -#define CONFIG_BAUDRATE 9600
29   -#if 0
30   -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
31   -#else
32   -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
33   -#endif
34   -
35   -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
36   -
37   -#define CONFIG_BOARD_TYPES 1 /* support board types */
38   -
39   -#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
40   -
41   -#undef CONFIG_BOOTARGS
42   -#define CONFIG_BOOTCOMMAND \
43   - "bootp; " \
44   - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
45   - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
46   - "bootm"
47   -
48   -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
49   -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
50   -
51   -#undef CONFIG_WATCHDOG /* watchdog disabled */
52   -
53   -
54   -/*
55   - * Command line configuration.
56   - */
57   -#include <config_cmd_default.h>
58   -
59   -
60   -/*
61   - * BOOTP options
62   - */
63   -#define CONFIG_BOOTP_SUBNETMASK
64   -#define CONFIG_BOOTP_GATEWAY
65   -#define CONFIG_BOOTP_HOSTNAME
66   -#define CONFIG_BOOTP_BOOTPATH
67   -
68   -
69   -/*
70   - * Miscellaneous configurable options
71   - */
72   -#define CONFIG_SYS_LONGHELP /* undef to save memory */
73   -#if defined(CONFIG_CMD_KGDB)
74   -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
75   -#else
76   -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
77   -#endif
78   -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
79   -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
80   -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
81   -
82   -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
83   -#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
84   -
85   -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
86   -
87   -#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
88   -
89   -#define CONFIG_SYS_ALLOC_DPRAM 1 /* use allocation routines */
90   -/*
91   - * Low Level Configuration Settings
92   - * (address mappings, register initial values, etc.)
93   - * You should know what you are doing if you make changes here.
94   - */
95   -/*-----------------------------------------------------------------------
96   - * Internal Memory Mapped Register
97   - */
98   -#define CONFIG_SYS_IMMR 0xFF000000 /* Non-Standard value! */
99   -
100   -/*-----------------------------------------------------------------------
101   - * Definitions for initial stack pointer and data area (in DPRAM)
102   - */
103   -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
104   -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
105   -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
106   -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
107   -
108   -/*-----------------------------------------------------------------------
109   - * Start addresses for the final memory configuration
110   - * (Set up by the startup code)
111   - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
112   - */
113   -#define CONFIG_SYS_SDRAM_BASE 0x00000000
114   -#define CONFIG_SYS_FLASH_BASE 0xFE000000
115   -#ifdef DEBUG
116   -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
117   -#else
118   -#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
119   -#endif
120   -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
121   -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
122   -
123   -/*
124   - * For booting Linux, the board info and command line data
125   - * have to be in the first 8 MB of memory, since this is
126   - * the maximum mapped by the Linux kernel during initialization.
127   - */
128   -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
129   -/*-----------------------------------------------------------------------
130   - * FLASH organization
131   - */
132   -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
133   -#define CONFIG_SYS_MAX_FLASH_SECT 124 /* max number of sectors on one chip */
134   -
135   -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
136   -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
137   -
138   -#define CONFIG_ENV_IS_IN_FLASH 1
139   -#define CONFIG_ENV_OFFSET 0x4000 /* Offset of Environment Sector */
140   -#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
141   -/*-----------------------------------------------------------------------
142   - * Cache Configuration
143   - */
144   -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
145   -#if defined(CONFIG_CMD_KGDB)
146   -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
147   -#endif
148   -
149   -/*-----------------------------------------------------------------------
150   - * SYPCR - System Protection Control 11-9
151   - * SYPCR can only be written once after reset!
152   - *-----------------------------------------------------------------------
153   - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
154   - * +0x0004
155   - */
156   -#if defined(CONFIG_WATCHDOG)
157   -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
158   - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
159   -#else
160   -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
161   -#endif
162   -
163   -/*-----------------------------------------------------------------------
164   - * SIUMCR - SIU Module Configuration 11-6
165   - *-----------------------------------------------------------------------
166   - * +0x0000 => 0x000000C0
167   - */
168   -#define CONFIG_SYS_SIUMCR 0
169   -
170   -/*-----------------------------------------------------------------------
171   - * TBSCR - Time Base Status and Control 11-26
172   - *-----------------------------------------------------------------------
173   - * Clear Reference Interrupt Status, Timebase freezing enabled
174   - * +0x0200 => 0x00C2
175   - */
176   -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
177   -
178   -/*-----------------------------------------------------------------------
179   - * PISCR - Periodic Interrupt Status and Control 11-31
180   - *-----------------------------------------------------------------------
181   - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
182   - * +0x0240 => 0x0082
183   - */
184   -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
185   -
186   -/*-----------------------------------------------------------------------
187   - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
188   - *-----------------------------------------------------------------------
189   - * Reset PLL lock status sticky bit, timer expired status bit and timer
190   - * interrupt status bit, set PLL multiplication factor !
191   - */
192   -/* +0x0286 => 0x00B0D0C0 */
193   -#define CONFIG_SYS_PLPRCR \
194   - ( (11 << PLPRCR_MF_SHIFT) | \
195   - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \
196   - /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
197   - PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \
198   - )
199   -
200   -/*-----------------------------------------------------------------------
201   - * SCCR - System Clock and reset Control Register 15-27
202   - *-----------------------------------------------------------------------
203   - * Set clock output, timebase and RTC source and divider,
204   - * power management and some other internal clocks
205   - */
206   -#define SCCR_MASK SCCR_EBDF11
207   -/* +0x0282 => 0x03800000 */
208   -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_TBS | \
209   - SCCR_RTDIV | SCCR_RTSEL | \
210   - /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
211   - SCCR_EBDF00 | SCCR_DFSYNC00 | \
212   - SCCR_DFBRG00 | SCCR_DFNL000 | \
213   - SCCR_DFNH000)
214   -
215   -/*-----------------------------------------------------------------------
216   - * RTCSC - Real-Time Clock Status and Control Register 11-27
217   - *-----------------------------------------------------------------------
218   - */
219   -/* +0x0220 => 0x00C3 */
220   -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
221   -
222   -
223   -/*-----------------------------------------------------------------------
224   - * RCCR - RISC Controller Configuration Register 19-4
225   - *-----------------------------------------------------------------------
226   - */
227   -/* +0x09C4 => TIMEP=1 */
228   -#define CONFIG_SYS_RCCR 0x0100
229   -
230   -/*-----------------------------------------------------------------------
231   - * RMDS - RISC Microcode Development Support Control Register
232   - *-----------------------------------------------------------------------
233   - */
234   -#define CONFIG_SYS_RMDS 0
235   -
236   -/*-----------------------------------------------------------------------
237   - *
238   - *-----------------------------------------------------------------------
239   - *
240   - */
241   -#define CONFIG_SYS_DER 0
242   -
243   -/*
244   - * Init Memory Controller:
245   - *
246   - * BR0 and OR0 (FLASH)
247   - */
248   -
249   -#define FLASH_BASE0_PRELIM 0xFE000000 /* FLASH bank #0 */
250   -
251   -/* used to re-map FLASH
252   - * restrict access enough to keep SRAM working (if any)
253   - * but not too much to meddle with FLASH accesses
254   - */
255   -/* allow for max 4 MB of Flash */
256   -#define CONFIG_SYS_REMAP_OR_AM 0xFFC00000 /* OR addr mask */
257   -#define CONFIG_SYS_PRELIM_OR_AM 0xFFC00000 /* OR addr mask */
258   -
259   -/* FLASH timing: ACS = 11, TRLX = 1, CSNT = 1, SCY = 5, EHTR = 0 */
260   -#define CONFIG_SYS_OR_TIMING_FLASH ( OR_CSNT_SAM | /*OR_ACS_DIV4 |*/ OR_BI | \
261   - OR_SCY_5_CLK | OR_TRLX)
262   -
263   -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
264   -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
265   -/* 8 bit, bank valid */
266   -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
267   -
268   -/*
269   - * BR1/OR1 - SDRAM
270   - *
271   - * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
272   - */
273   -#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM bank */
274   -#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
275   -#define SDRAM_TIMING 0x00000A00 /* SDRAM-Timing */
276   -
277   -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
278   -
279   -#define CONFIG_SYS_OR1_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
280   -#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
281   -
282   -/*
283   - * BR2/OR2 - HPRO2: PEB2256 @ 0xE0000000, 8 Bit wide
284   - */
285   -#define HPRO2_BASE 0xE0000000
286   -#define HPRO2_OR_AM 0xFFFF8000
287   -#define HPRO2_TIMING 0x00000934
288   -
289   -#define CONFIG_SYS_OR2 (HPRO2_OR_AM | HPRO2_TIMING)
290   -#define CONFIG_SYS_BR2 ((HPRO2_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
291   -
292   -/*
293   - * BR3/OR3: not used
294   - * BR4/OR4: not used
295   - * BR5/OR5: not used
296   - * BR6/OR6: not used
297   - * BR7/OR7: not used
298   - */
299   -
300   -/*
301   - * MAMR settings for SDRAM
302   - */
303   -
304   -/* periodic timer for refresh */
305   -#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */
306   -
307   -/* 8 column SDRAM */
308   -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
309   - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
310   - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
311   -/* 9 column SDRAM */
312   -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
313   - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
314   - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
315   -#endif /* __CONFIG_H */