x86: Add support for the samus chromebook

This adds basic support for chromebook_samus. This is the 2015 Pixel and is based on an Intel broadwell platform. Supported so far are: - Serial - SPI flash - SDRAM init (with MRC cache) - SATA - Video (on the internal LCD panel) - Keyboard Various less-visible drivers are provided to make the above work (e.g. PCH, power control and LPC). The platform requires various binary blobs which are documented in the README. The major missing feature is USB3 since the existing U-Boot support does not work correctly with Intel XHCI controllers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

x86: Add support for the samus chromebook
This adds basic support for chromebook_samus. This is the 2015 Pixel and is based on an Intel broadwell platform. Supported so far are: - Serial - SPI flash - SDRAM init (with MRC cache) - SATA - Video (on the internal LCD panel) - Keyboard Various less-visible drivers are provided to make the above work (e.g. PCH, power control and LPC). The platform requires various binary blobs which are documented in the README. The major missing feature is USB3 since the existing U-Boot support does not work correctly with Intel XHCI controllers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass · Bin Meng
1 parent e5aa8a9b15
Showing 11 changed files with 876 additions and 1 deletions Side-by-side Diff
arch/x86/dts/Makefile
arch/x86/dts/chromebook_samus.dts
board/google/Kconfig
board/google/chromebook_samus/Kconfig
board/google/chromebook_samus/MAINTAINERS
board/google/chromebook_samus/Makefile
board/google/chromebook_samus/samus.c
configs/chromebook_samus_defconfig
doc/README.x86
include/configs/chromebook_samus.h
include/configs/x86-chromebook.h
@@ -5,6 +5,7 @@
 dtb-y += bayleybay.dtb \
 	chromebook_link.dtb \
 	chromebox_panther.dtb \
+	chromebook_samus.dtb \
 	cougarcanyon2.dtb \
 	crownbay.dtb \
 	efi.dtb \
+/dts-v1/;
+
+#include <dt-bindings/gpio/x86-gpio.h>
+
+/include/ "skeleton.dtsi"
+/include/ "keyboard.dtsi"
+/include/ "serial.dtsi"
+/include/ "rtc.dtsi"
+/include/ "tsc_timer.dtsi"
+
+/ {
+	model = "Google Samus";
+	compatible = "google,samus", "intel,broadwell";
+
+	aliases {
+		spi0 = &spi;
+		usb0 = &usb_0;
+		usb1 = &usb_1;
+	};
+
+	config {
+	       silent_console = <0>;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "intel,core-i3-gen5";
+			reg = <0>;
+			intel,apic-id = <0>;
+			intel,slow-ramp = <3>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "intel,core-i3-gen5";
+			reg = <1>;
+			intel,apic-id = <1>;
+		};
+
+		cpu@2 {
+			device_type = "cpu";
+			compatible = "intel,core-i3-gen5";
+			reg = <2>;
+			intel,apic-id = <2>;
+		};
+
+		cpu@3 {
+			device_type = "cpu";
+			compatible = "intel,core-i3-gen5";
+			reg = <3>;
+			intel,apic-id = <3>;
+		};
+
+	};
+
+	chosen {
+		stdout-path = "/serial";
+	};
+
+	keyboard {
+		intel,duplicate-por;
+	};
+
+	pch_pinctrl {
+		compatible = "intel,x86-broadwell-pinctrl";
+		u-boot,dm-pre-reloc;
+		reg = <0 0>;
+
+		/* Put this first: it is the default */
+		gpio_unused: gpio-unused {
+			mode-gpio;
+			direction = <PIN_INPUT>;
+			owner = <OWNER_GPIO>;
+			sense-disable;
+		};
+
+		gpio_acpi_sci: acpi-sci {
+			mode-gpio;
+			direction = <PIN_INPUT>;
+			invert;
+			route = <ROUTE_SCI>;
+		};
+
+		gpio_acpi_smi: acpi-smi {
+			mode-gpio;
+			direction = <PIN_INPUT>;
+			invert;
+			route = <ROUTE_SMI>;
+		};
+
+		gpio_input: gpio-input {
+			mode-gpio;
+			direction = <PIN_INPUT>;
+			owner = <OWNER_GPIO>;
+		};
+
+		gpio_input_invert: gpio-input-invert {
+			mode-gpio;
+			direction = <PIN_INPUT>;
+			owner = <OWNER_GPIO>;
+			invert;
+		};
+
+		gpio_native: gpio-native {
+		};
+
+		gpio_out_high: gpio-out-high {
+			mode-gpio;
+			direction = <PIN_OUTPUT>;
+			output-value = <1>;
+			owner = <OWNER_GPIO>;
+			sense-disable;
+		};
+
+		gpio_out_low: gpio-out-low {
+			mode-gpio;
+			direction = <PIN_OUTPUT>;
+			output-value = <0>;
+			owner = <OWNER_GPIO>;
+			sense-disable;
+		};
+
+		gpio_pirq: gpio-pirq {
+			mode-gpio;
+			direction = <PIN_INPUT>;
+			owner = <OWNER_GPIO>;
+			pirq-apic = <PIRQ_APIC_ROUTE>;
+		};
+
+		soc_gpio@0 {
+			config =
+				<0 &gpio_unused 0>,	/* unused */
+				<1 &gpio_unused 0>,	/* unused */
+				<2 &gpio_unused 0>,	/* unused */
+				<3 &gpio_unused 0>,	/* unused */
+				<4 &gpio_native 0>,	/* native: i2c0_sda_gpio4 */
+				<5 &gpio_native 0>,	/* native: i2c0_scl_gpio5 */
+				<6 &gpio_native 0>,	/* native: i2c1_sda_gpio6 */
+				<7 &gpio_native 0>,	/* native: i2c1_scl_gpio7 */
+				<8 &gpio_acpi_sci 0>,	/* pch_lte_wake_l */
+				<9 &gpio_input_invert 0>,	/* trackpad_int_l (wake) */
+				<10 &gpio_acpi_sci 0>,	/* pch_wlan_wake_l */
+				<11 &gpio_unused 0>,	/* unused */
+				<12 &gpio_unused 0>,	/* unused */
+				<13 &gpio_pirq 3>,	/* trackpad_int_l (pirql) */
+				<14 &gpio_pirq 4>,	/* touch_int_l (pirqm) */
+				<15 &gpio_unused 0>,	/* unused (strap) */
+				<16 &gpio_input 0>,	/* pch_wp */
+				<17 &gpio_unused 0>,	/* unused */
+				<18 &gpio_unused 0>,	/* unused */
+				<19 &gpio_unused 0>,	/* unused */
+				<20 &gpio_native 0>,	/* pcie_wlan_clkreq_l */
+				<21 &gpio_out_high 0>,	/* pp3300_ssd_en */
+				<22 &gpio_unused 0>,	/* unused */
+				<23 &gpio_out_low 0>,	/* pp3300_autobahn_en */
+				<24 &gpio_unused 0>,	/* unused */
+				<25 &gpio_input 0>,	/* ec_in_rw */
+				<26 &gpio_unused 0>,	/* unused */
+				<27 &gpio_acpi_sci 0>,	/* pch_wake_l */
+				<28 &gpio_unused 0>,	/* unused */
+				<29 &gpio_unused 0>,	/* unused */
+				<30 &gpio_native 0>,	/* native: pch_suswarn_l */
+				<31 &gpio_native 0>,	/* native: acok_buf */
+				<32 &gpio_native 0>,	/* native: lpc_clkrun_l */
+				<33 &gpio_native 0>,	/* native: ssd_devslp */
+				<34 &gpio_acpi_smi 0>,	/* ec_smi_l */
+				<35 &gpio_acpi_smi 0>,	/* pch_nmi_dbg_l (route in nmi_en) */
+				<36 &gpio_acpi_sci 0>,	/* ec_sci_l */
+				<37 &gpio_unused 0>,	/* unused */
+				<38 &gpio_unused 0>,	/* unused */
+				<39 &gpio_unused 0>,	/* unused */
+				<40 &gpio_native 0>,	/* native: pch_usb1_oc_l */
+				<41 &gpio_native 0>,	/* native: pch_usb2_oc_l */
+				<42 &gpio_unused 0>,	/* wlan_disable_l */
+				<43 &gpio_out_high 0>,	/* pp1800_codec_en */
+				<44 &gpio_unused 0>,	/* unused */
+				<45 &gpio_acpi_sci 0>,	/* dsp_int - codec wake */
+				<46 &gpio_pirq 6>,	/* hotword_det_l_3v3 (pirqo) - codec irq */
+				<47 &gpio_out_low 0>,	/* ssd_reset_l */
+				<48 &gpio_unused 0>,	/* unused */
+				<49 &gpio_unused 0>,	/* unused */
+				<50 &gpio_unused 0>,	/* unused */
+				<51 &gpio_unused 0>,	/* unused */
+				<52 &gpio_input 0>,	/* sim_det */
+				<53 &gpio_unused 0>,	/* unused */
+				<54 &gpio_unused 0>,	/* unused */
+				<55 &gpio_unused 0>,	/* unused */
+				<56 &gpio_unused 0>,	/* unused */
+				<57 &gpio_out_high 0>,	/* codec_reset_l */
+				<58 &gpio_unused 0>,	/* unused */
+				<59 &gpio_out_high 0>,	/* lte_disable_l */
+				<60 &gpio_unused 0>,	/* unused */
+				<61 &gpio_native 0>,	/* native: pch_sus_stat */
+				<62 &gpio_native 0>,	/* native: pch_susclk */
+				<63 &gpio_native 0>,	/* native: pch_slp_s5_l */
+				<64 &gpio_unused 0>,	/* unused */
+				<65 &gpio_input 0>,	/* ram_id3 */
+				<66 &gpio_input 0>,	/* ram_id3_old (strap) */
+				<67 &gpio_input 0>,	/* ram_id0 */
+				<68 &gpio_input 0>,	/* ram_id1 */
+				<69 &gpio_input 0>,	/* ram_id2 */
+				<70 &gpio_unused 0>,	/* unused */
+				<71 &gpio_native 0>,	/* native: modphy_en */
+				<72 &gpio_unused 0>,	/* unused */
+				<73 &gpio_unused 0>,	/* unused */
+				<74 &gpio_unused 0>,	/* unused */
+				<75 &gpio_unused 0>,	/* unused */
+				<76 &gpio_unused 0>,	/* unused */
+				<77 &gpio_unused 0>,	/* unused */
+				<78 &gpio_unused 0>,	/* unused */
+				<79 &gpio_unused 0>,	/* unused */
+				<80 &gpio_unused 0>,	/* unused */
+				<81 &gpio_unused 0>,	/* unused */
+				<82 &gpio_native 0>,	/* native: ec_rcin_l */
+				<83 &gpio_native 0>,	/* gspi0_cs */
+				<84 &gpio_native 0>,	/* gspi0_clk */
+				<85 &gpio_native 0>,	/* gspi0_miso */
+				<86 &gpio_native 0>,	/* gspi0_mosi (strap) */
+				<87 &gpio_unused 0>,	/* unused */
+				<88 &gpio_unused 0>,	/* unused */
+				<89 &gpio_out_high 0>,	/* pp3300_sd_en */
+				<90 &gpio_unused 0>,	/* unused */
+				<91 &gpio_unused 0>,	/* unused */
+				<92 &gpio_unused 0>,	/* unused */
+				<93 &gpio_unused 0>,	/* unused */
+				<94 &gpio_unused 0>;	/* unused */
+		};
+	};
+
+	pci {
+		compatible = "pci-x86";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		u-boot,dm-pre-reloc;
+		ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
+			0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
+			0x01000000 0x0 0x1000 0x1000 0 0xefff>;
+
+		northbridge@0,0 {
+			reg = <0x00000000 0 0 0 0>;
+			compatible = "intel,broadwell-northbridge";
+			board-id-gpios = <&gpio_c 5 0>, <&gpio_c 4 0>,
+					<&gpio_c 3 0>, <&gpio_c 1 0>;
+			u-boot,dm-pre-reloc;
+			spd {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				samsung_4 {
+					reg = <6>;
+					data = [91 20 f1 03 04 11 05 0b
+						03 11 01 08 0a 00 50 01
+						78 78 90 50 90 11 50 e0
+						10 04 3c 3c 01 90 00 00
+						00 80 00 00 00 00 00 a8
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 0f 11 02 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 80 ce 01
+						00 00 55 00 00 00 00 00
+						4b 34 45 38 45 33 30 34
+						45 44 2d 45 47 43 45 20
+						20 20 00 00 80 ce 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00];
+				};
+				hynix-h9ccnnnbltmlar-ntm-lpddr3-32 {
+					/*
+					 * banks 8, ranks 2, rows 14,
+					 * columns 10, density 4096 mb, x32
+					 */
+					reg = <8>;
+					data = [91 20 f1 03 04 11 05 0b
+						03 11 01 08 0a 00 50 01
+						78 78 90 50 90 11 50 e0
+						10 04 3c 3c 01 90 00 00
+						00 80 00 00 00 00 00 a8
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 0f 01 02 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 80 ad 00
+						00 00 55 00 00 00 00 00
+						48 39 43 43 4e 4e 4e 42
+						4c 54 4d 4c 41 52 2d 4e
+						54 4d 00 00 80 ad 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00];
+					};
+				samsung_8 {
+					reg = <10>;
+					data = [91 20 f1 03 04 12 05 0a
+						03 11 01 08 0a 00 50 01
+						78 78 90 50 90 11 50 e0
+						10 04 3c 3c 01 90 00 00
+						00 80 00 00 00 00 00 a8
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 0f 11 02 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 80 ce 01
+						00 00 55 00 00 00 00 00
+						4b 34 45 36 45 33 30 34
+						45 44 2d 45 47 43 45 20
+						20 20 00 00 80 ce 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00];
+				};
+				hynix-h9ccnnnbltmlar-ntm-lpddr3-16 {
+					/*
+					 * banks 8, ranks 2, rows 14,
+					 * columns 11, density 4096 mb, x16
+					 */
+					reg = <12>;
+					data = [91 20 f1 03 04 12 05 0a
+						03 11 01 08 0a 00 50 01
+						78 78 90 50 90 11 50 e0
+						10 04 3c 3c 01 90 00 00
+						00 80 00 00 00 00 00 a8
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 0f 01 02 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 80 ad 00
+						00 00 55 00 00 00 00 00
+						48 39 43 43 4e 4e 4e 42
+						4c 54 4d 4c 41 52 2d 4e
+						54 4d 00 00 80 ad 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00];
+				};
+				hynix-h9ccnnncltmlar-lpddr3 {
+					/*
+					 * banks 8, ranks 2, rows 15,
+					 * columns 11, density 8192 mb, x16
+					 */
+					reg = <13>;
+					data = [91 20 f1 03 05 1a 05 0a
+						03 11 01 08 0a 00 50 01
+						78 78 90 50 90 11 50 e0
+						90 06 3c 3c 01 90 00 00
+						00 80 00 00 00 00 00 a8
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 0f 01 02 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 80 ad 00
+						00 00 55 00 00 00 00 00
+						48 39 43 43 4e 4e 4e 43
+						4c 54 4d 4c 41 52 00 00
+						00 00 00 00 80 ad 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00];
+				};
+				elpida-edfb232a1ma {
+					/*
+					 * banks 8, ranks 2, rows 15,
+					 * columns 11, density 8192 mb, x16
+					 */
+					reg = <15>;
+					data = [91 20 f1 03 05 1a 05 0a
+						03 11 01 08 0a 00 50 01
+						78 78 90 50 90 11 50 e0
+						90 06 3c 3c 01 90 00 00
+						00 80 00 00 00 00 00 a8
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 0f 01 02 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 02 fe 00
+						00 00 00 00 00 00 00 00
+						45 44 46 42 32 33 32 41
+						31 4d 41 2d 47 44 2d 46
+						00 00 00 00 02 fe 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00];
+				};
+			};
+		};
+
+		gma@2,0 {
+			reg = <0x00001000 0 0 0 0>;
+			compatible = "intel,broadwell-igd";
+			intel,dp-hotplug = <6 6 6>;
+			intel,port-select = <1>;	/* eDP */
+			intel,power-cycle-delay = <6>;
+			intel,power-up-delay = <2000>;
+			intel,power-down-delay = <500>;
+			intel,power-backlight-on-delay = <2000>;
+			intel,power-backlight-off-delay = <2000>;
+			intel,cpu-backlight = <0x00000200>;
+			intel,pch-backlight = <0x04000200>;
+			intel,pre-graphics-delay = <200>;
+		};
+
+		me@16,0 {
+			reg = <0x0000b000 0 0 0 0>;
+			compatible = "intel,me";
+			u-boot,dm-pre-reloc;
+		};
+
+		usb_1: usb@14,0 {
+			reg = <0x0000a000 0 0 0 0>;
+			compatible = "xhci-pci";
+		};
+
+		usb_0: usb@1d,0 {
+			status = "disabled";
+			reg = <0x0000e800 0 0 0 0>;
+			compatible = "ehci-pci";
+		};
+
+		pch@1f,0 {
+			reg = <0x0000f800 0 0 0 0>;
+			compatible = "intel,broadwell-pch";
+			u-boot,dm-pre-reloc;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
+						0x80 0x80 0x80 0x80>;
+			intel,gpi-routing = <0 0 0 0 0 0 0 2
+						1 0 0 0 0 0 0 0>;
+			/* Enable EC SMI source */
+			intel,alt-gp-smi-enable = <0x0040>;
+
+			/* EC-SCI is GPIO36 */
+			intel,gpe0-en = <0 0x10 0 0>;
+
+			power-enable-gpio = <&gpio_a 23 0>;
+
+			spi: spi {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "intel,ich9-spi";
+				spi-flash@0 {
+					#size-cells = <1>;
+					#address-cells = <1>;
+					reg = <0>;
+					compatible = "winbond,w25q64",
+							"spi-flash";
+					memory-map = <0xff800000 0x00800000>;
+					rw-mrc-cache {
+						label = "rw-mrc-cache";
+						reg = <0x003e0000 0x00010000>;
+					};
+				};
+			};
+
+			gpio_a: gpioa {
+				compatible = "intel,broadwell-gpio";
+				u-boot,dm-pre-reloc;
+				#gpio-cells = <2>;
+				gpio-controller;
+				reg = <0 0>;
+				bank-name = "A";
+			};
+
+			gpio_b: gpiob {
+				compatible = "intel,broadwell-gpio";
+				u-boot,dm-pre-reloc;
+				#gpio-cells = <2>;
+				gpio-controller;
+				reg = <1 0>;
+				bank-name = "B";
+			};
+
+			gpio_c: gpioc {
+				compatible = "intel,broadwell-gpio";
+				u-boot,dm-pre-reloc;
+				#gpio-cells = <2>;
+				gpio-controller;
+				reg = <2 0>;
+				bank-name = "C";
+			};
+
+			lpc {
+				compatible = "intel,broadwell-lpc";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				u-boot,dm-pre-reloc;
+				intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
+				cros-ec@200 {
+					compatible = "google,cros-ec-lpc";
+					reg = <0x204 1 0x200 1 0x880 0x80>;
+
+					/*
+					 * Describes the flash memory within
+					 * the EC
+					 */
+					#address-cells = <1>;
+					#size-cells = <1>;
+					flash@8000000 {
+						reg = <0x08000000 0x20000>;
+						erase-value = <0xff>;
+					};
+				};
+			};
+		};
+
+		sata@1f,2 {
+			compatible = "intel,wildcatpoint-ahci";
+			reg = <0x0000fa00 0 0 0 0>;
+			u-boot,dm-pre-reloc;
+			intel,sata-mode = "ahci";
+			intel,sata-port-map = <1>;
+			intel,sata-port0-gen3-tx = <0x72>;
+			reset-gpio = <&gpio_b 15 GPIO_ACTIVE_LOW>;
+		};
+
+		smbus: smbus@1f,3 {
+			compatible = "intel,ich-i2c";
+			reg = <0x0000fb00 0 0 0 0>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	tpm {
+		reg = <0xfed40000 0x5000>;
+		compatible = "infineon,slb9635lpc";
+	};
+
+	microcode {
+		update@0 {
+#include "microcode/mc0306d4_00000018.dtsi"
+		};
+	};
+
+};
@@ -36,10 +36,23 @@
 	  video output and a 16GB SATA solid state drive. There is no Chrome
 	  OS EC on this model.
  
+config TARGET_CHROMEBOOK_SAMUS
+	bool "Chromebook samus"
+	help
+	  This is the Chromebook Pixel released in 2015. It uses an Intel
+	  Broadwell U Core i5 or Core i7 CPU with either 8GB or 16GB of
+	  LPDDR3 SDRAM. It has PCIe WiFi and Bluetooth. It also includes a
+	  720p webcam, USB SD reader, microphone and speakers, 2 USB 3 Type
+	  C ports which can support charging and up to a 4K external display.
+	  There is a solid state drive, either 32GB or 64GB. There is a
+	  Chrome OS EC connected on LPC, and it provides a 2560x1700 high
+	  resolution touch-enabled LCD display.
+
 endchoice
  
 source "board/google/chromebook_link/Kconfig"
 source "board/google/chromebox_panther/Kconfig"
+source "board/google/chromebook_samus/Kconfig"
  
 endif
+if TARGET_CHROMEBOOK_SAMUS
+
+config SYS_BOARD
+	default "chromebook_samus"
+
+config SYS_VENDOR
+	default "google"
+
+config SYS_SOC
+	default "broadwell"
+
+config SYS_CONFIG_NAME
+	default "chromebook_samus"
+
+config SYS_TEXT_BASE
+	default 0xffe00000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select X86_RESET_VECTOR
+	select INTEL_BROADWELL
+	select HAVE_INTEL_ME
+	select BOARD_ROMSIZE_KB_8192
+
+config PCIE_ECAM_BASE
+	default 0xf0000000
+
+config EARLY_POST_CROS_EC
+	bool "Enable early post to Chrome OS EC"
+	default y
+
+config SYS_CAR_ADDR
+	hex
+	default 0xff7c0000
+
+config SYS_CAR_SIZE
+	hex
+	default 0x40000
+
+endif
+CHROMEBOOK SAMUS BOARD
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/google/chromebook_samus/
+F:	include/configs/chromebook_samus.h
+F:	configs/chromebook_samus_defconfig
+#
+# Copyright (c) 2016 Google, Inc
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= samus.o
+/*
+ * Copyright (C) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/cpu.h>
+
+int arch_early_init_r(void)
+{
+	return cpu_run_reference_code();
+}
+
+int board_early_init_f(void)
+{
+	return 0;
+}
+CONFIG_X86=y
+CONFIG_SYS_MALLOC_F_LEN=0x1800
+CONFIG_VENDOR_GOOGLE=y
+CONFIG_DEFAULT_DEVICE_TREE="chromebook_samus"
+CONFIG_TARGET_CHROMEBOOK_SAMUS=y
+CONFIG_ENABLE_MRC_CACHE=y
+CONFIG_HAVE_MRC=y
+CONFIG_HAVE_REFCODE=y
+CONFIG_SMP=y
+CONFIG_HAVE_VGA_BIOS=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_CMD_BOOTSTAGE=y
+CONFIG_CMD_TPM=y
+CONFIG_CMD_TPM_TEST=y
+CONFIG_OF_CONTROL=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CPU=y
+CONFIG_INTEL_BROADWELL_GPIO=y
+CONFIG_CMD_CROS_EC=y
+CONFIG_CROS_EC=y
+CONFIG_CROS_EC_LPC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_PCI=y
+CONFIG_DM_RTC=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0x3f8
+CONFIG_DEBUG_UART_CLOCK=1843200
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_SYS_NS16550=y
+CONFIG_ICH_SPI=y
+CONFIG_TIMER=y
+CONFIG_TPM_TIS_LPC=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_DM_VIDEO=y
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
+CONFIG_VIDEO_BROADWELL_IGD=y
+CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_TPM=y
@@ -105,6 +105,87 @@
  
 ---
  
+Chromebook Samus (2015 Pixel) instructions for bare mode:
+
+First, you need the following binary blobs:
+
+* descriptor.bin - Intel flash descriptor
+* me.bin - Intel Management Engine
+* mrc.bin - Memory Reference Code, which sets up SDRAM
+* refcode.elf - Additional Reference code
+* vga.bin - video ROM, which sets up the display
+
+If you have a samus you can obtain them from your flash, for example, in
+developer mode on the Chromebook (use Ctrl-Alt-F2 to obtain a terminal and
+log in as 'root'):
+
+   cd /tmp
+   flashrom -w samus.bin
+   scp samus.bin username@ip_address:/path/to/somewhere
+
+If not see the coreboot tree [4] where you can use:
+
+   bash crosfirmware.sh samus
+
+to get the image. There is also an 'extract_blobs.sh' scripts that you can use
+on the 'coreboot-Google_Samus.*' file to short-circuit some of the below.
+
+Then 'ifdtool -x samus.bin' on your development machine will produce:
+
+   flashregion_0_flashdescriptor.bin
+   flashregion_1_bios.bin
+   flashregion_2_intel_me.bin
+
+Rename flashregion_0_flashdescriptor.bin to descriptor.bin
+Rename flashregion_2_intel_me.bin to me.bin
+You can ignore flashregion_1_bios.bin - it is not used.
+
+To get the rest, use 'cbfstool samus.bin print':
+
+samus.bin: 8192 kB, bootblocksize 2864, romsize 8388608, offset 0x700000
+alignment: 64 bytes, architecture: x86
+
+Name                           Offset     Type         Size
+cmos_layout.bin                0x700000   cmos_layout  1164
+pci8086,0406.rom               0x7004c0   optionrom    65536
+spd.bin                        0x710500   (unknown)    4096
+cpu_microcode_blob.bin         0x711540   microcode    70720
+fallback/romstage              0x722a00   stage        54210
+fallback/ramstage              0x72fe00   stage        96382
+config                         0x7476c0   raw          6075
+fallback/vboot                 0x748ec0   stage        15980
+fallback/refcode               0x74cd80   stage        75578
+fallback/payload               0x75f500   payload      62878
+u-boot.dtb                     0x76eb00   (unknown)    5318
+(empty)                        0x770000   null         196504
+mrc.bin                        0x79ffc0   (unknown)    222876
+(empty)                        0x7d66c0   null         167320
+
+You can extract what you need:
+
+   cbfstool samus.bin extract -n pci8086,0406.rom -f vga.bin
+   cbfstool samus.bin extract -n fallback/refcode -f refcode.rmod
+   cbfstool samus.bin extract -n mrc.bin -f mrc.bin
+   cbfstool samus.bin extract -n fallback/refcode -f refcode.bin -U
+
+Note that the -U flag is only supported by the latest cbfstool. It unpacks
+and decompresses the stage to produce a coreboot rmodule. This is a simple
+representation of an ELF file. You need the patch "Support decoding a stage
+with compression".
+
+Put all 5 files into board/google/chromebook_samus.
+
+Now you can build U-Boot and obtain u-boot.rom:
+
+$ make chromebook_link_defconfig
+$ make all
+
+If you are using em100, then this command will flash write -Boot:
+
+   em100 -s -d filename.rom -c W25Q64CV -r
+
+---
+
 Intel Crown Bay specific instructions for bare mode:
  
 U-Boot support of Intel Crown Bay board [4] relies on a binary blob called
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ@gmail.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+#include <configs/x86-chromebook.h>
+
+#undef CONFIG_CFB_CONSOLE
+
+#undef CONFIG_STD_DEVICES_SETTINGS
+#define CONFIG_STD_DEVICES_SETTINGS     "stdin=usbkbd,i8042-kbd,serial\0" \
+					"stdout=vidconsole,serial\0" \
+					"stderr=vidconsole,serial\0"
+
+#define CONFIG_ENV_SECT_SIZE		0x1000
+#define CONFIG_ENV_OFFSET		0x003f8000
+
+#endif	/* __CONFIG_H */
@@ -21,7 +21,8 @@
 	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
 	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
 	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}, \
-	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_AHCI}
+	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_AHCI}, \
+	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_AHCI}
  
 #define CONFIG_PCI_MEM_BUS	0xe0000000
 #define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
...	...	@@ -5,6 +5,7 @@
5	5	dtb-y += bayleybay.dtb \
6	6	chromebook_link.dtb \
7	7	chromebox_panther.dtb \
	8	+ chromebook_samus.dtb \
8	9	cougarcanyon2.dtb \
9	10	crownbay.dtb \
10	11	efi.dtb \
	1	+/dts-v1/;
	2	+
	3	+#include <dt-bindings/gpio/x86-gpio.h>
	4	+
	5	+/include/ "skeleton.dtsi"
	6	+/include/ "keyboard.dtsi"
	7	+/include/ "serial.dtsi"
	8	+/include/ "rtc.dtsi"
	9	+/include/ "tsc_timer.dtsi"
	10	+
	11	+/ {
	12	+ model = "Google Samus";
	13	+ compatible = "google,samus", "intel,broadwell";
	14	+
	15	+ aliases {
	16	+ spi0 = &spi;
	17	+ usb0 = &usb_0;
	18	+ usb1 = &usb_1;
	19	+ };
	20	+
	21	+ config {
	22	+ silent_console = <0>;
	23	+ };
	24	+
	25	+ cpus {
	26	+ #address-cells = <1>;
	27	+ #size-cells = <0>;
	28	+
	29	+ cpu@0 {
	30	+ device_type = "cpu";
	31	+ compatible = "intel,core-i3-gen5";
	32	+ reg = <0>;
	33	+ intel,apic-id = <0>;
	34	+ intel,slow-ramp = <3>;
	35	+ };
	36	+
	37	+ cpu@1 {
	38	+ device_type = "cpu";
	39	+ compatible = "intel,core-i3-gen5";
	40	+ reg = <1>;
	41	+ intel,apic-id = <1>;
	42	+ };
	43	+
	44	+ cpu@2 {
	45	+ device_type = "cpu";
	46	+ compatible = "intel,core-i3-gen5";
	47	+ reg = <2>;
	48	+ intel,apic-id = <2>;
	49	+ };
	50	+
	51	+ cpu@3 {
	52	+ device_type = "cpu";
	53	+ compatible = "intel,core-i3-gen5";
	54	+ reg = <3>;
	55	+ intel,apic-id = <3>;
	56	+ };
	57	+
	58	+ };
	59	+
	60	+ chosen {
	61	+ stdout-path = "/serial";
	62	+ };
	63	+
	64	+ keyboard {
	65	+ intel,duplicate-por;
	66	+ };
	67	+
	68	+ pch_pinctrl {
	69	+ compatible = "intel,x86-broadwell-pinctrl";
	70	+ u-boot,dm-pre-reloc;
	71	+ reg = <0 0>;
	72	+
	73	+ /* Put this first: it is the default */
	74	+ gpio_unused: gpio-unused {
	75	+ mode-gpio;
	76	+ direction = <PIN_INPUT>;
	77	+ owner = <OWNER_GPIO>;
	78	+ sense-disable;
	79	+ };
	80	+
	81	+ gpio_acpi_sci: acpi-sci {
	82	+ mode-gpio;
	83	+ direction = <PIN_INPUT>;
	84	+ invert;
	85	+ route = <ROUTE_SCI>;
	86	+ };
	87	+
	88	+ gpio_acpi_smi: acpi-smi {
	89	+ mode-gpio;
	90	+ direction = <PIN_INPUT>;
	91	+ invert;
	92	+ route = <ROUTE_SMI>;
	93	+ };
	94	+
	95	+ gpio_input: gpio-input {
	96	+ mode-gpio;
	97	+ direction = <PIN_INPUT>;
	98	+ owner = <OWNER_GPIO>;
	99	+ };
	100	+
	101	+ gpio_input_invert: gpio-input-invert {
	102	+ mode-gpio;
	103	+ direction = <PIN_INPUT>;
	104	+ owner = <OWNER_GPIO>;
	105	+ invert;
	106	+ };
	107	+
	108	+ gpio_native: gpio-native {
	109	+ };
	110	+
	111	+ gpio_out_high: gpio-out-high {
	112	+ mode-gpio;
	113	+ direction = <PIN_OUTPUT>;
	114	+ output-value = <1>;
	115	+ owner = <OWNER_GPIO>;
	116	+ sense-disable;
	117	+ };
	118	+
	119	+ gpio_out_low: gpio-out-low {
	120	+ mode-gpio;
	121	+ direction = <PIN_OUTPUT>;
	122	+ output-value = <0>;
	123	+ owner = <OWNER_GPIO>;
	124	+ sense-disable;
	125	+ };
	126	+
	127	+ gpio_pirq: gpio-pirq {
	128	+ mode-gpio;
	129	+ direction = <PIN_INPUT>;
	130	+ owner = <OWNER_GPIO>;
	131	+ pirq-apic = <PIRQ_APIC_ROUTE>;
	132	+ };
	133	+
	134	+ soc_gpio@0 {
	135	+ config =
	136	+ <0 &gpio_unused 0>, /* unused */
	137	+ <1 &gpio_unused 0>, /* unused */
	138	+ <2 &gpio_unused 0>, /* unused */
	139	+ <3 &gpio_unused 0>, /* unused */
	140	+ <4 &gpio_native 0>, /* native: i2c0_sda_gpio4 */
	141	+ <5 &gpio_native 0>, /* native: i2c0_scl_gpio5 */
	142	+ <6 &gpio_native 0>, /* native: i2c1_sda_gpio6 */
	143	+ <7 &gpio_native 0>, /* native: i2c1_scl_gpio7 */
	144	+ <8 &gpio_acpi_sci 0>, /* pch_lte_wake_l */
	145	+ <9 &gpio_input_invert 0>, /* trackpad_int_l (wake) */
	146	+ <10 &gpio_acpi_sci 0>, /* pch_wlan_wake_l */
	147	+ <11 &gpio_unused 0>, /* unused */
	148	+ <12 &gpio_unused 0>, /* unused */
	149	+ <13 &gpio_pirq 3>, /* trackpad_int_l (pirql) */
	150	+ <14 &gpio_pirq 4>, /* touch_int_l (pirqm) */
	151	+ <15 &gpio_unused 0>, /* unused (strap) */
	152	+ <16 &gpio_input 0>, /* pch_wp */
	153	+ <17 &gpio_unused 0>, /* unused */
	154	+ <18 &gpio_unused 0>, /* unused */
	155	+ <19 &gpio_unused 0>, /* unused */
	156	+ <20 &gpio_native 0>, /* pcie_wlan_clkreq_l */
	157	+ <21 &gpio_out_high 0>, /* pp3300_ssd_en */
	158	+ <22 &gpio_unused 0>, /* unused */
	159	+ <23 &gpio_out_low 0>, /* pp3300_autobahn_en */
	160	+ <24 &gpio_unused 0>, /* unused */
	161	+ <25 &gpio_input 0>, /* ec_in_rw */
	162	+ <26 &gpio_unused 0>, /* unused */
	163	+ <27 &gpio_acpi_sci 0>, /* pch_wake_l */
	164	+ <28 &gpio_unused 0>, /* unused */
	165	+ <29 &gpio_unused 0>, /* unused */
	166	+ <30 &gpio_native 0>, /* native: pch_suswarn_l */
	167	+ <31 &gpio_native 0>, /* native: acok_buf */
	168	+ <32 &gpio_native 0>, /* native: lpc_clkrun_l */
	169	+ <33 &gpio_native 0>, /* native: ssd_devslp */
	170	+ <34 &gpio_acpi_smi 0>, /* ec_smi_l */
	171	+ <35 &gpio_acpi_smi 0>, /* pch_nmi_dbg_l (route in nmi_en) */
	172	+ <36 &gpio_acpi_sci 0>, /* ec_sci_l */
	173	+ <37 &gpio_unused 0>, /* unused */
	174	+ <38 &gpio_unused 0>, /* unused */
	175	+ <39 &gpio_unused 0>, /* unused */
	176	+ <40 &gpio_native 0>, /* native: pch_usb1_oc_l */
	177	+ <41 &gpio_native 0>, /* native: pch_usb2_oc_l */
	178	+ <42 &gpio_unused 0>, /* wlan_disable_l */
	179	+ <43 &gpio_out_high 0>, /* pp1800_codec_en */
	180	+ <44 &gpio_unused 0>, /* unused */
	181	+ <45 &gpio_acpi_sci 0>, /* dsp_int - codec wake */
	182	+ <46 &gpio_pirq 6>, /* hotword_det_l_3v3 (pirqo) - codec irq */
	183	+ <47 &gpio_out_low 0>, /* ssd_reset_l */
	184	+ <48 &gpio_unused 0>, /* unused */
	185	+ <49 &gpio_unused 0>, /* unused */
	186	+ <50 &gpio_unused 0>, /* unused */
	187	+ <51 &gpio_unused 0>, /* unused */
	188	+ <52 &gpio_input 0>, /* sim_det */
	189	+ <53 &gpio_unused 0>, /* unused */
	190	+ <54 &gpio_unused 0>, /* unused */
	191	+ <55 &gpio_unused 0>, /* unused */
	192	+ <56 &gpio_unused 0>, /* unused */
	193	+ <57 &gpio_out_high 0>, /* codec_reset_l */
	194	+ <58 &gpio_unused 0>, /* unused */
	195	+ <59 &gpio_out_high 0>, /* lte_disable_l */
	196	+ <60 &gpio_unused 0>, /* unused */
	197	+ <61 &gpio_native 0>, /* native: pch_sus_stat */
	198	+ <62 &gpio_native 0>, /* native: pch_susclk */
	199	+ <63 &gpio_native 0>, /* native: pch_slp_s5_l */
	200	+ <64 &gpio_unused 0>, /* unused */
	201	+ <65 &gpio_input 0>, /* ram_id3 */
	202	+ <66 &gpio_input 0>, /* ram_id3_old (strap) */
	203	+ <67 &gpio_input 0>, /* ram_id0 */
	204	+ <68 &gpio_input 0>, /* ram_id1 */
	205	+ <69 &gpio_input 0>, /* ram_id2 */
	206	+ <70 &gpio_unused 0>, /* unused */
	207	+ <71 &gpio_native 0>, /* native: modphy_en */
	208	+ <72 &gpio_unused 0>, /* unused */
	209	+ <73 &gpio_unused 0>, /* unused */
	210	+ <74 &gpio_unused 0>, /* unused */
	211	+ <75 &gpio_unused 0>, /* unused */
	212	+ <76 &gpio_unused 0>, /* unused */
	213	+ <77 &gpio_unused 0>, /* unused */
	214	+ <78 &gpio_unused 0>, /* unused */
	215	+ <79 &gpio_unused 0>, /* unused */
	216	+ <80 &gpio_unused 0>, /* unused */
	217	+ <81 &gpio_unused 0>, /* unused */
	218	+ <82 &gpio_native 0>, /* native: ec_rcin_l */
	219	+ <83 &gpio_native 0>, /* gspi0_cs */
	220	+ <84 &gpio_native 0>, /* gspi0_clk */
	221	+ <85 &gpio_native 0>, /* gspi0_miso */
	222	+ <86 &gpio_native 0>, /* gspi0_mosi (strap) */
	223	+ <87 &gpio_unused 0>, /* unused */
	224	+ <88 &gpio_unused 0>, /* unused */
	225	+ <89 &gpio_out_high 0>, /* pp3300_sd_en */
	226	+ <90 &gpio_unused 0>, /* unused */
	227	+ <91 &gpio_unused 0>, /* unused */
	228	+ <92 &gpio_unused 0>, /* unused */
	229	+ <93 &gpio_unused 0>, /* unused */
	230	+ <94 &gpio_unused 0>; /* unused */
	231	+ };
	232	+ };
	233	+
	234	+ pci {
	235	+ compatible = "pci-x86";
	236	+ #address-cells = <3>;
	237	+ #size-cells = <2>;
	238	+ u-boot,dm-pre-reloc;
	239	+ ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
	240	+ 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
	241	+ 0x01000000 0x0 0x1000 0x1000 0 0xefff>;
	242	+
	243	+ northbridge@0,0 {
	244	+ reg = <0x00000000 0 0 0 0>;
	245	+ compatible = "intel,broadwell-northbridge";
	246	+ board-id-gpios = <&gpio_c 5 0>, <&gpio_c 4 0>,
	247	+ <&gpio_c 3 0>, <&gpio_c 1 0>;
	248	+ u-boot,dm-pre-reloc;
	249	+ spd {
	250	+ #address-cells = <1>;
	251	+ #size-cells = <0>;
	252	+ samsung_4 {
	253	+ reg = <6>;
	254	+ data = [91 20 f1 03 04 11 05 0b
	255	+ 03 11 01 08 0a 00 50 01
	256	+ 78 78 90 50 90 11 50 e0
	257	+ 10 04 3c 3c 01 90 00 00
	258	+ 00 80 00 00 00 00 00 a8
	259	+ 00 00 00 00 00 00 00 00
	260	+ 00 00 00 00 00 00 00 00
	261	+ 00 00 00 00 0f 11 02 00
	262	+ 00 00 00 00 00 00 00 00
	263	+ 00 00 00 00 00 00 00 00
	264	+ 00 00 00 00 00 00 00 00
	265	+ 00 00 00 00 00 00 00 00
	266	+ 00 00 00 00 00 00 00 00
	267	+ 00 00 00 00 00 00 00 00
	268	+ 00 00 00 00 00 80 ce 01
	269	+ 00 00 55 00 00 00 00 00
	270	+ 4b 34 45 38 45 33 30 34
	271	+ 45 44 2d 45 47 43 45 20
	272	+ 20 20 00 00 80 ce 00 00
	273	+ 00 00 00 00 00 00 00 00
	274	+ 00 00 00 00 00 00 00 00
	275	+ 00 00 00 00 00 00 00 00
	276	+ 00 00 00 00 00 00 00 00
	277	+ 00 00 00 00 00 00 00 00
	278	+ 00 00 00 00 00 00 00 00
	279	+ 00 00 00 00 00 00 00 00
	280	+ 00 00 00 00 00 00 00 00
	281	+ 00 00 00 00 00 00 00 00
	282	+ 00 00 00 00 00 00 00 00
	283	+ 00 00 00 00 00 00 00 00
	284	+ 00 00 00 00 00 00 00 00
	285	+ 00 00 00 00 00 00 00 00];
	286	+ };
	287	+ hynix-h9ccnnnbltmlar-ntm-lpddr3-32 {
	288	+ /*
	289	+ * banks 8, ranks 2, rows 14,
	290	+ * columns 10, density 4096 mb, x32
	291	+ */
	292	+ reg = <8>;
	293	+ data = [91 20 f1 03 04 11 05 0b
	294	+ 03 11 01 08 0a 00 50 01
	295	+ 78 78 90 50 90 11 50 e0
	296	+ 10 04 3c 3c 01 90 00 00
	297	+ 00 80 00 00 00 00 00 a8
	298	+ 00 00 00 00 00 00 00 00
	299	+ 00 00 00 00 00 00 00 00
	300	+ 00 00 00 00 0f 01 02 00
	301	+ 00 00 00 00 00 00 00 00
	302	+ 00 00 00 00 00 00 00 00
	303	+ 00 00 00 00 00 00 00 00
	304	+ 00 00 00 00 00 00 00 00
	305	+ 00 00 00 00 00 00 00 00
	306	+ 00 00 00 00 00 00 00 00
	307	+ 00 00 00 00 00 80 ad 00
	308	+ 00 00 55 00 00 00 00 00
	309	+ 48 39 43 43 4e 4e 4e 42
	310	+ 4c 54 4d 4c 41 52 2d 4e
	311	+ 54 4d 00 00 80 ad 00 00
	312	+ 00 00 00 00 00 00 00 00
	313	+ 00 00 00 00 00 00 00 00
	314	+ 00 00 00 00 00 00 00 00
	315	+ 00 00 00 00 00 00 00 00
	316	+ 00 00 00 00 00 00 00 00
	317	+ 00 00 00 00 00 00 00 00
	318	+ 00 00 00 00 00 00 00 00
	319	+ 00 00 00 00 00 00 00 00
	320	+ 00 00 00 00 00 00 00 00
	321	+ 00 00 00 00 00 00 00 00
	322	+ 00 00 00 00 00 00 00 00
	323	+ 00 00 00 00 00 00 00 00
	324	+ 00 00 00 00 00 00 00 00];
	325	+ };
	326	+ samsung_8 {
	327	+ reg = <10>;
	328	+ data = [91 20 f1 03 04 12 05 0a
	329	+ 03 11 01 08 0a 00 50 01
	330	+ 78 78 90 50 90 11 50 e0
	331	+ 10 04 3c 3c 01 90 00 00
	332	+ 00 80 00 00 00 00 00 a8
	333	+ 00 00 00 00 00 00 00 00
	334	+ 00 00 00 00 00 00 00 00
	335	+ 00 00 00 00 0f 11 02 00
	336	+ 00 00 00 00 00 00 00 00
	337	+ 00 00 00 00 00 00 00 00
	338	+ 00 00 00 00 00 00 00 00
	339	+ 00 00 00 00 00 00 00 00
	340	+ 00 00 00 00 00 00 00 00
	341	+ 00 00 00 00 00 00 00 00
	342	+ 00 00 00 00 00 80 ce 01
	343	+ 00 00 55 00 00 00 00 00
	344	+ 4b 34 45 36 45 33 30 34
	345	+ 45 44 2d 45 47 43 45 20
	346	+ 20 20 00 00 80 ce 00 00
	347	+ 00 00 00 00 00 00 00 00
	348	+ 00 00 00 00 00 00 00 00
	349	+ 00 00 00 00 00 00 00 00
	350	+ 00 00 00 00 00 00 00 00
	351	+ 00 00 00 00 00 00 00 00
	352	+ 00 00 00 00 00 00 00 00
	353	+ 00 00 00 00 00 00 00 00
	354	+ 00 00 00 00 00 00 00 00
	355	+ 00 00 00 00 00 00 00 00
	356	+ 00 00 00 00 00 00 00 00
	357	+ 00 00 00 00 00 00 00 00
	358	+ 00 00 00 00 00 00 00 00
	359	+ 00 00 00 00 00 00 00 00];
	360	+ };
	361	+ hynix-h9ccnnnbltmlar-ntm-lpddr3-16 {
	362	+ /*
	363	+ * banks 8, ranks 2, rows 14,
	364	+ * columns 11, density 4096 mb, x16
	365	+ */
	366	+ reg = <12>;
	367	+ data = [91 20 f1 03 04 12 05 0a
	368	+ 03 11 01 08 0a 00 50 01
	369	+ 78 78 90 50 90 11 50 e0
	370	+ 10 04 3c 3c 01 90 00 00
	371	+ 00 80 00 00 00 00 00 a8
	372	+ 00 00 00 00 00 00 00 00
	373	+ 00 00 00 00 00 00 00 00
	374	+ 00 00 00 00 0f 01 02 00
	375	+ 00 00 00 00 00 00 00 00
	376	+ 00 00 00 00 00 00 00 00
	377	+ 00 00 00 00 00 00 00 00
	378	+ 00 00 00 00 00 00 00 00
	379	+ 00 00 00 00 00 00 00 00
	380	+ 00 00 00 00 00 00 00 00
	381	+ 00 00 00 00 00 80 ad 00
	382	+ 00 00 55 00 00 00 00 00
	383	+ 48 39 43 43 4e 4e 4e 42
	384	+ 4c 54 4d 4c 41 52 2d 4e
	385	+ 54 4d 00 00 80 ad 00 00
	386	+ 00 00 00 00 00 00 00 00
	387	+ 00 00 00 00 00 00 00 00
	388	+ 00 00 00 00 00 00 00 00
	389	+ 00 00 00 00 00 00 00 00
	390	+ 00 00 00 00 00 00 00 00
	391	+ 00 00 00 00 00 00 00 00
	392	+ 00 00 00 00 00 00 00 00
	393	+ 00 00 00 00 00 00 00 00
	394	+ 00 00 00 00 00 00 00 00
	395	+ 00 00 00 00 00 00 00 00
	396	+ 00 00 00 00 00 00 00 00
	397	+ 00 00 00 00 00 00 00 00
	398	+ 00 00 00 00 00 00 00 00];
	399	+ };
	400	+ hynix-h9ccnnncltmlar-lpddr3 {
	401	+ /*
	402	+ * banks 8, ranks 2, rows 15,
	403	+ * columns 11, density 8192 mb, x16
	404	+ */
	405	+ reg = <13>;
	406	+ data = [91 20 f1 03 05 1a 05 0a
	407	+ 03 11 01 08 0a 00 50 01
	408	+ 78 78 90 50 90 11 50 e0
	409	+ 90 06 3c 3c 01 90 00 00
	410	+ 00 80 00 00 00 00 00 a8
	411	+ 00 00 00 00 00 00 00 00
	412	+ 00 00 00 00 00 00 00 00
	413	+ 00 00 00 00 0f 01 02 00
	414	+ 00 00 00 00 00 00 00 00
	415	+ 00 00 00 00 00 00 00 00
	416	+ 00 00 00 00 00 00 00 00
	417	+ 00 00 00 00 00 00 00 00
	418	+ 00 00 00 00 00 00 00 00
	419	+ 00 00 00 00 00 00 00 00
	420	+ 00 00 00 00 00 80 ad 00
	421	+ 00 00 55 00 00 00 00 00
	422	+ 48 39 43 43 4e 4e 4e 43
	423	+ 4c 54 4d 4c 41 52 00 00
	424	+ 00 00 00 00 80 ad 00 00
	425	+ 00 00 00 00 00 00 00 00
	426	+ 00 00 00 00 00 00 00 00
	427	+ 00 00 00 00 00 00 00 00
	428	+ 00 00 00 00 00 00 00 00
	429	+ 00 00 00 00 00 00 00 00
	430	+ 00 00 00 00 00 00 00 00
	431	+ 00 00 00 00 00 00 00 00
	432	+ 00 00 00 00 00 00 00 00
	433	+ 00 00 00 00 00 00 00 00
	434	+ 00 00 00 00 00 00 00 00
	435	+ 00 00 00 00 00 00 00 00
	436	+ 00 00 00 00 00 00 00 00
	437	+ 00 00 00 00 00 00 00 00];
	438	+ };
	439	+ elpida-edfb232a1ma {
	440	+ /*
	441	+ * banks 8, ranks 2, rows 15,
	442	+ * columns 11, density 8192 mb, x16
	443	+ */
	444	+ reg = <15>;
	445	+ data = [91 20 f1 03 05 1a 05 0a
	446	+ 03 11 01 08 0a 00 50 01
	447	+ 78 78 90 50 90 11 50 e0
	448	+ 90 06 3c 3c 01 90 00 00
	449	+ 00 80 00 00 00 00 00 a8
	450	+ 00 00 00 00 00 00 00 00
	451	+ 00 00 00 00 00 00 00 00
	452	+ 00 00 00 00 0f 01 02 00
	453	+ 00 00 00 00 00 00 00 00
	454	+ 00 00 00 00 00 00 00 00
	455	+ 00 00 00 00 00 00 00 00
	456	+ 00 00 00 00 00 00 00 00
	457	+ 00 00 00 00 00 00 00 00
	458	+ 00 00 00 00 00 00 00 00
	459	+ 00 00 00 00 00 02 fe 00
	460	+ 00 00 00 00 00 00 00 00
	461	+ 45 44 46 42 32 33 32 41
	462	+ 31 4d 41 2d 47 44 2d 46
	463	+ 00 00 00 00 02 fe 00 00
	464	+ 00 00 00 00 00 00 00 00
	465	+ 00 00 00 00 00 00 00 00
	466	+ 00 00 00 00 00 00 00 00
	467	+ 00 00 00 00 00 00 00 00
	468	+ 00 00 00 00 00 00 00 00
	469	+ 00 00 00 00 00 00 00 00
	470	+ 00 00 00 00 00 00 00 00
	471	+ 00 00 00 00 00 00 00 00
	472	+ 00 00 00 00 00 00 00 00
	473	+ 00 00 00 00 00 00 00 00
	474	+ 00 00 00 00 00 00 00 00
	475	+ 00 00 00 00 00 00 00 00
	476	+ 00 00 00 00 00 00 00 00];
	477	+ };
	478	+ };
	479	+ };
	480	+
	481	+ gma@2,0 {
	482	+ reg = <0x00001000 0 0 0 0>;
	483	+ compatible = "intel,broadwell-igd";
	484	+ intel,dp-hotplug = <6 6 6>;
	485	+ intel,port-select = <1>; /* eDP */
	486	+ intel,power-cycle-delay = <6>;
	487	+ intel,power-up-delay = <2000>;
	488	+ intel,power-down-delay = <500>;
	489	+ intel,power-backlight-on-delay = <2000>;
	490	+ intel,power-backlight-off-delay = <2000>;
	491	+ intel,cpu-backlight = <0x00000200>;
	492	+ intel,pch-backlight = <0x04000200>;
	493	+ intel,pre-graphics-delay = <200>;
	494	+ };
	495	+
	496	+ me@16,0 {
	497	+ reg = <0x0000b000 0 0 0 0>;
	498	+ compatible = "intel,me";
	499	+ u-boot,dm-pre-reloc;
	500	+ };
	501	+
	502	+ usb_1: usb@14,0 {
	503	+ reg = <0x0000a000 0 0 0 0>;
	504	+ compatible = "xhci-pci";
	505	+ };
	506	+
	507	+ usb_0: usb@1d,0 {
	508	+ status = "disabled";
	509	+ reg = <0x0000e800 0 0 0 0>;
	510	+ compatible = "ehci-pci";
	511	+ };
	512	+
	513	+ pch@1f,0 {
	514	+ reg = <0x0000f800 0 0 0 0>;
	515	+ compatible = "intel,broadwell-pch";
	516	+ u-boot,dm-pre-reloc;
	517	+ #address-cells = <1>;
	518	+ #size-cells = <1>;
	519	+ intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
	520	+ 0x80 0x80 0x80 0x80>;
	521	+ intel,gpi-routing = <0 0 0 0 0 0 0 2
	522	+ 1 0 0 0 0 0 0 0>;
	523	+ /* Enable EC SMI source */
	524	+ intel,alt-gp-smi-enable = <0x0040>;
	525	+
	526	+ /* EC-SCI is GPIO36 */
	527	+ intel,gpe0-en = <0 0x10 0 0>;
	528	+
	529	+ power-enable-gpio = <&gpio_a 23 0>;
	530	+
	531	+ spi: spi {
	532	+ #address-cells = <1>;
	533	+ #size-cells = <0>;
	534	+ compatible = "intel,ich9-spi";
	535	+ spi-flash@0 {
	536	+ #size-cells = <1>;
	537	+ #address-cells = <1>;
	538	+ reg = <0>;
	539	+ compatible = "winbond,w25q64",
	540	+ "spi-flash";
	541	+ memory-map = <0xff800000 0x00800000>;
	542	+ rw-mrc-cache {
	543	+ label = "rw-mrc-cache";
	544	+ reg = <0x003e0000 0x00010000>;
	545	+ };
	546	+ };
	547	+ };
	548	+
	549	+ gpio_a: gpioa {
	550	+ compatible = "intel,broadwell-gpio";
	551	+ u-boot,dm-pre-reloc;
	552	+ #gpio-cells = <2>;
	553	+ gpio-controller;
	554	+ reg = <0 0>;
	555	+ bank-name = "A";
	556	+ };
	557	+
	558	+ gpio_b: gpiob {
	559	+ compatible = "intel,broadwell-gpio";
	560	+ u-boot,dm-pre-reloc;
	561	+ #gpio-cells = <2>;
	562	+ gpio-controller;
	563	+ reg = <1 0>;
	564	+ bank-name = "B";
	565	+ };
	566	+
	567	+ gpio_c: gpioc {
	568	+ compatible = "intel,broadwell-gpio";
	569	+ u-boot,dm-pre-reloc;
	570	+ #gpio-cells = <2>;
	571	+ gpio-controller;
	572	+ reg = <2 0>;
	573	+ bank-name = "C";
	574	+ };
	575	+
	576	+ lpc {
	577	+ compatible = "intel,broadwell-lpc";
	578	+ #address-cells = <1>;
	579	+ #size-cells = <0>;
	580	+ u-boot,dm-pre-reloc;
	581	+ intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
	582	+ cros-ec@200 {
	583	+ compatible = "google,cros-ec-lpc";
	584	+ reg = <0x204 1 0x200 1 0x880 0x80>;
	585	+
	586	+ /*
	587	+ * Describes the flash memory within
	588	+ * the EC
	589	+ */
	590	+ #address-cells = <1>;
	591	+ #size-cells = <1>;
	592	+ flash@8000000 {
	593	+ reg = <0x08000000 0x20000>;
	594	+ erase-value = <0xff>;
	595	+ };
	596	+ };
	597	+ };
	598	+ };
	599	+
	600	+ sata@1f,2 {
	601	+ compatible = "intel,wildcatpoint-ahci";
	602	+ reg = <0x0000fa00 0 0 0 0>;
	603	+ u-boot,dm-pre-reloc;
	604	+ intel,sata-mode = "ahci";
	605	+ intel,sata-port-map = <1>;
	606	+ intel,sata-port0-gen3-tx = <0x72>;
	607	+ reset-gpio = <&gpio_b 15 GPIO_ACTIVE_LOW>;
	608	+ };
	609	+
	610	+ smbus: smbus@1f,3 {
	611	+ compatible = "intel,ich-i2c";
	612	+ reg = <0x0000fb00 0 0 0 0>;
	613	+ u-boot,dm-pre-reloc;
	614	+ };
	615	+ };
	616	+
	617	+ tpm {
	618	+ reg = <0xfed40000 0x5000>;
	619	+ compatible = "infineon,slb9635lpc";
	620	+ };
	621	+
	622	+ microcode {
	623	+ update@0 {
	624	+#include "microcode/mc0306d4_00000018.dtsi"
	625	+ };
	626	+ };
	627	+
	628	+};
...	...	@@ -36,10 +36,23 @@
36	36	video output and a 16GB SATA solid state drive. There is no Chrome
37	37	OS EC on this model.
38	38
	39	+config TARGET_CHROMEBOOK_SAMUS
	40	+ bool "Chromebook samus"
	41	+ help
	42	+ This is the Chromebook Pixel released in 2015. It uses an Intel
	43	+ Broadwell U Core i5 or Core i7 CPU with either 8GB or 16GB of
	44	+ LPDDR3 SDRAM. It has PCIe WiFi and Bluetooth. It also includes a
	45	+ 720p webcam, USB SD reader, microphone and speakers, 2 USB 3 Type
	46	+ C ports which can support charging and up to a 4K external display.
	47	+ There is a solid state drive, either 32GB or 64GB. There is a
	48	+ Chrome OS EC connected on LPC, and it provides a 2560x1700 high
	49	+ resolution touch-enabled LCD display.
	50	+
39	51	endchoice
40	52
41	53	source "board/google/chromebook_link/Kconfig"
42	54	source "board/google/chromebox_panther/Kconfig"
	55	+source "board/google/chromebook_samus/Kconfig"
43	56
44	57	endif
	1	+if TARGET_CHROMEBOOK_SAMUS
	2	+
	3	+config SYS_BOARD
	4	+ default "chromebook_samus"
	5	+
	6	+config SYS_VENDOR
	7	+ default "google"
	8	+
	9	+config SYS_SOC
	10	+ default "broadwell"
	11	+
	12	+config SYS_CONFIG_NAME
	13	+ default "chromebook_samus"
	14	+
	15	+config SYS_TEXT_BASE
	16	+ default 0xffe00000
	17	+
	18	+config BOARD_SPECIFIC_OPTIONS # dummy
	19	+ def_bool y
	20	+ select X86_RESET_VECTOR
	21	+ select INTEL_BROADWELL
	22	+ select HAVE_INTEL_ME
	23	+ select BOARD_ROMSIZE_KB_8192
	24	+
	25	+config PCIE_ECAM_BASE
	26	+ default 0xf0000000
	27	+
	28	+config EARLY_POST_CROS_EC
	29	+ bool "Enable early post to Chrome OS EC"
	30	+ default y
	31	+
	32	+config SYS_CAR_ADDR
	33	+ hex
	34	+ default 0xff7c0000
	35	+
	36	+config SYS_CAR_SIZE
	37	+ hex
	38	+ default 0x40000
	39	+
	40	+endif
	1	+CHROMEBOOK SAMUS BOARD
	2	+M: Simon Glass <sjg@chromium.org>
	3	+S: Maintained
	4	+F: board/google/chromebook_samus/
	5	+F: include/configs/chromebook_samus.h
	6	+F: configs/chromebook_samus_defconfig
	1	+#
	2	+# Copyright (c) 2016 Google, Inc
	3	+#
	4	+# SPDX-License-Identifier: GPL-2.0+
	5	+#
	6	+
	7	+obj-y += samus.o
	1	+/*
	2	+ * Copyright (C) 2016 Google, Inc
	3	+ *
	4	+ * SPDX-License-Identifier: GPL-2.0+
	5	+ */
	6	+
	7	+#include <common.h>
	8	+#include <asm/cpu.h>
	9	+
	10	+int arch_early_init_r(void)
	11	+{
	12	+ return cpu_run_reference_code();
	13	+}
	14	+
	15	+int board_early_init_f(void)
	16	+{
	17	+ return 0;
	18	+}
	1	+CONFIG_X86=y
	2	+CONFIG_SYS_MALLOC_F_LEN=0x1800
	3	+CONFIG_VENDOR_GOOGLE=y
	4	+CONFIG_DEFAULT_DEVICE_TREE="chromebook_samus"
	5	+CONFIG_TARGET_CHROMEBOOK_SAMUS=y
	6	+CONFIG_ENABLE_MRC_CACHE=y
	7	+CONFIG_HAVE_MRC=y
	8	+CONFIG_HAVE_REFCODE=y
	9	+CONFIG_SMP=y
	10	+CONFIG_HAVE_VGA_BIOS=y
	11	+CONFIG_CMD_CPU=y
	12	+# CONFIG_CMD_IMLS is not set
	13	+# CONFIG_CMD_FLASH is not set
	14	+CONFIG_CMD_GPIO=y
	15	+# CONFIG_CMD_SETEXPR is not set
	16	+# CONFIG_CMD_NFS is not set
	17	+CONFIG_BOOTSTAGE=y
	18	+CONFIG_BOOTSTAGE_REPORT=y
	19	+CONFIG_CMD_BOOTSTAGE=y
	20	+CONFIG_CMD_TPM=y
	21	+CONFIG_CMD_TPM_TEST=y
	22	+CONFIG_OF_CONTROL=y
	23	+CONFIG_REGMAP=y
	24	+CONFIG_SYSCON=y
	25	+CONFIG_CPU=y
	26	+CONFIG_INTEL_BROADWELL_GPIO=y
	27	+CONFIG_CMD_CROS_EC=y
	28	+CONFIG_CROS_EC=y
	29	+CONFIG_CROS_EC_LPC=y
	30	+CONFIG_SPI_FLASH=y
	31	+CONFIG_SPI_FLASH_GIGADEVICE=y
	32	+CONFIG_SPI_FLASH_MACRONIX=y
	33	+CONFIG_SPI_FLASH_WINBOND=y
	34	+CONFIG_DM_PCI=y
	35	+CONFIG_DM_RTC=y
	36	+CONFIG_DEBUG_UART=y
	37	+CONFIG_DEBUG_UART_BASE=0x3f8
	38	+CONFIG_DEBUG_UART_CLOCK=1843200
	39	+CONFIG_DEBUG_UART_BOARD_INIT=y
	40	+CONFIG_SYS_NS16550=y
	41	+CONFIG_ICH_SPI=y
	42	+CONFIG_TIMER=y
	43	+CONFIG_TPM_TIS_LPC=y
	44	+CONFIG_USB=y
	45	+CONFIG_DM_USB=y
	46	+CONFIG_DM_VIDEO=y
	47	+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
	48	+CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
	49	+CONFIG_VIDEO_BROADWELL_IGD=y
	50	+CONFIG_USE_PRIVATE_LIBGCC=y
	51	+CONFIG_TPM=y
...	...	@@ -105,6 +105,87 @@
105	105
106	106	---
107	107
	108	+Chromebook Samus (2015 Pixel) instructions for bare mode:
	109	+
	110	+First, you need the following binary blobs:
	111	+
	112	+* descriptor.bin - Intel flash descriptor
	113	+* me.bin - Intel Management Engine
	114	+* mrc.bin - Memory Reference Code, which sets up SDRAM
	115	+* refcode.elf - Additional Reference code
	116	+* vga.bin - video ROM, which sets up the display
	117	+
	118	+If you have a samus you can obtain them from your flash, for example, in
	119	+developer mode on the Chromebook (use Ctrl-Alt-F2 to obtain a terminal and
	120	+log in as 'root'):
	121	+
	122	+ cd /tmp
	123	+ flashrom -w samus.bin
	124	+ scp samus.bin username@ip_address:/path/to/somewhere
	125	+
	126	+If not see the coreboot tree [4] where you can use:
	127	+
	128	+ bash crosfirmware.sh samus
	129	+
	130	+to get the image. There is also an 'extract_blobs.sh' scripts that you can use
	131	+on the 'coreboot-Google_Samus.*' file to short-circuit some of the below.
	132	+
	133	+Then 'ifdtool -x samus.bin' on your development machine will produce:
	134	+
	135	+ flashregion_0_flashdescriptor.bin
	136	+ flashregion_1_bios.bin
	137	+ flashregion_2_intel_me.bin
	138	+
	139	+Rename flashregion_0_flashdescriptor.bin to descriptor.bin
	140	+Rename flashregion_2_intel_me.bin to me.bin
	141	+You can ignore flashregion_1_bios.bin - it is not used.
	142	+
	143	+To get the rest, use 'cbfstool samus.bin print':
	144	+
	145	+samus.bin: 8192 kB, bootblocksize 2864, romsize 8388608, offset 0x700000
	146	+alignment: 64 bytes, architecture: x86
	147	+
	148	+Name Offset Type Size
	149	+cmos_layout.bin 0x700000 cmos_layout 1164
	150	+pci8086,0406.rom 0x7004c0 optionrom 65536
	151	+spd.bin 0x710500 (unknown) 4096
	152	+cpu_microcode_blob.bin 0x711540 microcode 70720
	153	+fallback/romstage 0x722a00 stage 54210
	154	+fallback/ramstage 0x72fe00 stage 96382
	155	+config 0x7476c0 raw 6075
	156	+fallback/vboot 0x748ec0 stage 15980
	157	+fallback/refcode 0x74cd80 stage 75578
	158	+fallback/payload 0x75f500 payload 62878
	159	+u-boot.dtb 0x76eb00 (unknown) 5318
	160	+(empty) 0x770000 null 196504
	161	+mrc.bin 0x79ffc0 (unknown) 222876
	162	+(empty) 0x7d66c0 null 167320
	163	+
	164	+You can extract what you need:
	165	+
	166	+ cbfstool samus.bin extract -n pci8086,0406.rom -f vga.bin
	167	+ cbfstool samus.bin extract -n fallback/refcode -f refcode.rmod
	168	+ cbfstool samus.bin extract -n mrc.bin -f mrc.bin
	169	+ cbfstool samus.bin extract -n fallback/refcode -f refcode.bin -U
	170	+
	171	+Note that the -U flag is only supported by the latest cbfstool. It unpacks
	172	+and decompresses the stage to produce a coreboot rmodule. This is a simple
	173	+representation of an ELF file. You need the patch "Support decoding a stage
	174	+with compression".
	175	+
	176	+Put all 5 files into board/google/chromebook_samus.
	177	+
	178	+Now you can build U-Boot and obtain u-boot.rom:
	179	+
	180	+$ make chromebook_link_defconfig
	181	+$ make all
	182	+
	183	+If you are using em100, then this command will flash write -Boot:
	184	+
	185	+ em100 -s -d filename.rom -c W25Q64CV -r
	186	+
	187	+---
	188	+
108	189	Intel Crown Bay specific instructions for bare mode:
109	190
110	191	U-Boot support of Intel Crown Bay board [4] relies on a binary blob called
	1	+/*
	2	+ * Copyright (c) 2011 The Chromium OS Authors.
	3	+ * (C) Copyright 2008
	4	+ * Graeme Russ, graeme.russ@gmail.com.
	5	+ *
	6	+ * SPDX-License-Identifier: GPL-2.0+
	7	+ */
	8	+
	9	+/*
	10	+ * board/config.h - configuration options, board specific
	11	+ */
	12	+
	13	+#ifndef __CONFIG_H
	14	+#define __CONFIG_H
	15	+
	16	+#include <configs/x86-common.h>
	17	+#include <configs/x86-chromebook.h>
	18	+
	19	+#undef CONFIG_CFB_CONSOLE
	20	+
	21	+#undef CONFIG_STD_DEVICES_SETTINGS
	22	+#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,i8042-kbd,serial\0" \
	23	+ "stdout=vidconsole,serial\0" \
	24	+ "stderr=vidconsole,serial\0"
	25	+
	26	+#define CONFIG_ENV_SECT_SIZE 0x1000
	27	+#define CONFIG_ENV_OFFSET 0x003f8000
	28	+
	29	+#endif /* __CONFIG_H */