Eric Lee / smarc-uboot

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Commit 375a4496ff250baf6e4b845c1ebf40e4b3c409a3

Authored by Albert ARIBAUD
2 parents c35cf8dc9f 55f2118c11
Exists in master and in 50 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'

Showing 16 changed files Side-by-side Diff

arch/arm/cpu/armv7/exynos/clock.c
Diff comments   View file @ 375a449
... ... @@ -1410,7 +1410,8 @@
1410 1410 else {
1411 1411 if (proid_is_exynos4412())
1412 1412 exynos4x12_set_mmc_clk(dev_index, div);
1413   - exynos4_set_mmc_clk(dev_index, div);
  1413 + else
  1414 + exynos4_set_mmc_clk(dev_index, div);
1414 1415 }
1415 1416 }
1416 1417  
arch/arm/cpu/armv7/exynos/pinmux.c
Diff comments   View file @ 375a449
... ... @@ -462,7 +462,7 @@
462 462 case PERIPH_ID_SDMMC1:
463 463 case PERIPH_ID_SDMMC3:
464 464 case PERIPH_ID_SDMMC4:
465   - printf("SDMMC device %d not implemented\n", peripheral);
  465 + debug("SDMMC device %d not implemented\n", peripheral);
466 466 return -1;
467 467 default:
468 468 debug("%s: invalid peripheral %d", __func__, peripheral);
arch/arm/cpu/armv7/exynos/spl_boot.c
Diff comments   View file @ 375a449
... ... @@ -10,8 +10,11 @@
10 10 #include <asm/arch/clock.h>
11 11 #include <asm/arch/clk.h>
12 12 #include <asm/arch/dmc.h>
  13 +#include <asm/arch/periph.h>
  14 +#include <asm/arch/pinmux.h>
13 15 #include <asm/arch/power.h>
14 16 #include <asm/arch/spl.h>
  17 +#include <asm/arch/spi.h>
15 18  
16 19 #include "common_setup.h"
17 20 #include "clock_init.h"
18 21  
... ... @@ -59,7 +62,122 @@
59 62 }
60 63 #endif
61 64  
  65 +#ifdef CONFIG_SPI_BOOTING
  66 +static void spi_rx_tx(struct exynos_spi *regs, int todo,
  67 + void *dinp, void const *doutp, int i)
  68 +{
  69 + uint *rxp = (uint *)(dinp + (i * (32 * 1024)));
  70 + int rx_lvl, tx_lvl;
  71 + uint out_bytes, in_bytes;
  72 +
  73 + out_bytes = todo;
  74 + in_bytes = todo;
  75 + setbits_le32(&regs->ch_cfg, SPI_CH_RST);
  76 + clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
  77 + writel(((todo * 8) / 32) | SPI_PACKET_CNT_EN, &regs->pkt_cnt);
  78 +
  79 + while (in_bytes) {
  80 + uint32_t spi_sts;
  81 + int temp;
  82 +
  83 + spi_sts = readl(&regs->spi_sts);
  84 + rx_lvl = ((spi_sts >> 15) & 0x7f);
  85 + tx_lvl = ((spi_sts >> 6) & 0x7f);
  86 + while (tx_lvl < 32 && out_bytes) {
  87 + temp = 0xffffffff;
  88 + writel(temp, &regs->tx_data);
  89 + out_bytes -= 4;
  90 + tx_lvl += 4;
  91 + }
  92 + while (rx_lvl >= 4 && in_bytes) {
  93 + temp = readl(&regs->rx_data);
  94 + if (rxp)
  95 + *rxp++ = temp;
  96 + in_bytes -= 4;
  97 + rx_lvl -= 4;
  98 + }
  99 + }
  100 +}
  101 +
62 102 /*
  103 + * Copy uboot from spi flash to RAM
  104 + *
  105 + * @parma uboot_size size of u-boot to copy
  106 + * @param uboot_addr address in u-boot to copy
  107 + */
  108 +static void exynos_spi_copy(unsigned int uboot_size, unsigned int uboot_addr)
  109 +{
  110 + int upto, todo;
  111 + int i, timeout = 100;
  112 + struct exynos_spi *regs = (struct exynos_spi *)CONFIG_ENV_SPI_BASE;
  113 +
  114 + set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */
  115 + /* set the spi1 GPIO */
  116 + exynos_pinmux_config(PERIPH_ID_SPI1, PINMUX_FLAG_NONE);
  117 +
  118 + /* set pktcnt and enable it */
  119 + writel(4 | SPI_PACKET_CNT_EN, &regs->pkt_cnt);
  120 + /* set FB_CLK_SEL */
  121 + writel(SPI_FB_DELAY_180, &regs->fb_clk);
  122 + /* set CH_WIDTH and BUS_WIDTH as word */
  123 + setbits_le32(&regs->mode_cfg, SPI_MODE_CH_WIDTH_WORD |
  124 + SPI_MODE_BUS_WIDTH_WORD);
  125 + clrbits_le32(&regs->ch_cfg, SPI_CH_CPOL_L); /* CPOL: active high */
  126 +
  127 + /* clear rx and tx channel if set priveously */
  128 + clrbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON);
  129 +
  130 + setbits_le32(&regs->swap_cfg, SPI_RX_SWAP_EN |
  131 + SPI_RX_BYTE_SWAP |
  132 + SPI_RX_HWORD_SWAP);
  133 +
  134 + /* do a soft reset */
  135 + setbits_le32(&regs->ch_cfg, SPI_CH_RST);
  136 + clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
  137 +
  138 + /* now set rx and tx channel ON */
  139 + setbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON | SPI_CH_HS_EN);
  140 + clrbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */
  141 +
  142 + /* Send read instruction (0x3h) followed by a 24 bit addr */
  143 + writel((SF_READ_DATA_CMD << 24) | SPI_FLASH_UBOOT_POS, &regs->tx_data);
  144 +
  145 + /* waiting for TX done */
  146 + while (!(readl(&regs->spi_sts) & SPI_ST_TX_DONE)) {
  147 + if (!timeout) {
  148 + debug("SPI TIMEOUT\n");
  149 + break;
  150 + }
  151 + timeout--;
  152 + }
  153 +
  154 + for (upto = 0, i = 0; upto < uboot_size; upto += todo, i++) {
  155 + todo = min(uboot_size - upto, (1 << 15));
  156 + spi_rx_tx(regs, todo, (void *)(uboot_addr),
  157 + (void *)(SPI_FLASH_UBOOT_POS), i);
  158 + }
  159 +
  160 + setbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT);/* make the CS high */
  161 +
  162 + /*
  163 + * Let put controller mode to BYTE as
  164 + * SPI driver does not support WORD mode yet
  165 + */
  166 + clrbits_le32(&regs->mode_cfg, SPI_MODE_CH_WIDTH_WORD |
  167 + SPI_MODE_BUS_WIDTH_WORD);
  168 + writel(0, &regs->swap_cfg);
  169 +
  170 + /*
  171 + * Flush spi tx, rx fifos and reset the SPI controller
  172 + * and clear rx/tx channel
  173 + */
  174 + clrsetbits_le32(&regs->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST);
  175 + clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
  176 + clrbits_le32(&regs->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON);
  177 +}
  178 +#endif
  179 +
  180 +/*
63 181 * Copy U-boot from mmc to RAM:
64 182 * COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains
65 183 * Pointer to API (Data transfer from mmc to ram)
... ... @@ -70,6 +188,9 @@
70 188  
71 189 u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst) = NULL;
72 190 u32 offset = 0, size = 0;
  191 +#ifdef CONFIG_SPI_BOOTING
  192 + struct spl_machine_param *param = spl_get_machine_params();
  193 +#endif
73 194 #ifdef CONFIG_SUPPORT_EMMC_BOOT
74 195 u32 (*copy_bl2_from_emmc)(u32 nblock, u32 dst);
75 196 void (*end_bootop_from_emmc)(void);
... ... @@ -91,9 +212,8 @@
91 212 switch (bootmode) {
92 213 #ifdef CONFIG_SPI_BOOTING
93 214 case BOOT_MODE_SERIAL:
94   - offset = SPI_FLASH_UBOOT_POS;
95   - size = CONFIG_BL2_SIZE;
96   - copy_bl2 = get_irom_func(SPI_INDEX);
  215 + /* Customised function to copy u-boot from SF */
  216 + exynos_spi_copy(param->uboot_size, CONFIG_SYS_TEXT_BASE);
97 217 break;
98 218 #endif
99 219 case BOOT_MODE_MMC:
arch/arm/include/asm/arch-exynos/dwmmc.h
Diff comments   View file @ 375a449
... ... @@ -6,10 +6,6 @@
6 6 */
7 7  
8 8 #define DWMCI_CLKSEL 0x09C
9   -#define DWMCI_SHIFT_0 0x0
10   -#define DWMCI_SHIFT_1 0x1
11   -#define DWMCI_SHIFT_2 0x2
12   -#define DWMCI_SHIFT_3 0x3
13 9 #define DWMCI_SET_SAMPLE_CLK(x) (x)
14 10 #define DWMCI_SET_DRV_CLK(x) ((x) << 16)
15 11 #define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
arch/arm/include/asm/arch-exynos/mmc.h
Diff comments   View file @ 375a449
... ... @@ -55,7 +55,7 @@
55 55  
56 56 int s5p_sdhci_init(u32 regbase, int index, int bus_width);
57 57  
58   -static inline unsigned int s5p_mmc_init(int index, int bus_width)
  58 +static inline int s5p_mmc_init(int index, int bus_width)
59 59 {
60 60 unsigned int base = samsung_get_base_mmc() +
61 61 (S5P_MMC_DEV_OFFSET * index);
arch/arm/include/asm/arch-exynos/power.h
Diff comments   View file @ 375a449
... ... @@ -16,7 +16,7 @@
16 16 unsigned int gnss_rtc_out_ctrl;
17 17 unsigned char res2[0x1ec];
18 18 unsigned int system_power_down_ctrl;
19   - unsigned char res3[0x1];
  19 + unsigned int res3;
20 20 unsigned int system_power_down_option;
21 21 unsigned char res4[0x1f4];
22 22 unsigned int swreset;
arch/arm/include/asm/arch-exynos/spi.h
Diff comments   View file @ 375a449
... ... @@ -30,6 +30,7 @@
30 30 #define EXYNOS_SPI_MAX_FREQ 50000000
31 31  
32 32 #define SPI_TIMEOUT_MS 10
  33 +#define SF_READ_DATA_CMD 0x3
33 34  
34 35 /* SPI_CHCFG */
35 36 #define SPI_CH_HS_EN (1 << 6)
arch/arm/include/asm/arch-s5pc1xx/mmc.h
Diff comments   View file @ 375a449
... ... @@ -55,7 +55,7 @@
55 55  
56 56 int s5p_sdhci_init(u32 regbase, int index, int bus_width);
57 57  
58   -static inline unsigned int s5p_mmc_init(int index, int bus_width)
  58 +static inline int s5p_mmc_init(int index, int bus_width)
59 59 {
60 60 unsigned int base = samsung_get_base_mmc() +
61 61 (S5P_MMC_DEV_OFFSET * index);
board/samsung/trats/trats.c
Diff comments   View file @ 375a449
... ... @@ -501,6 +501,17 @@
501 501 debug("USB_udc_probe\n");
502 502 return s3c_udc_probe(&s5pc210_otg_data);
503 503 }
  504 +
  505 +#ifdef CONFIG_USB_CABLE_CHECK
  506 +int usb_cable_connected(void)
  507 +{
  508 + struct pmic *muic = pmic_get("MAX8997_MUIC");
  509 + if (!muic)
  510 + return 0;
  511 +
  512 + return !!muic->chrg->chrg_type(muic);
  513 +}
  514 +#endif
504 515 #endif
505 516  
506 517 static void pmic_reset(void)
board/samsung/trats2/trats2.c
Diff comments   View file @ 375a449
... ... @@ -25,6 +25,9 @@
25 25 #include <power/max77693_fg.h>
26 26 #include <libtizen.h>
27 27 #include <errno.h>
  28 +#include <usb.h>
  29 +#include <usb/s3c_udc.h>
  30 +#include <usb_mass_storage.h>
28 31  
29 32 DECLARE_GLOBAL_DATA_PTR;
30 33  
... ... @@ -40,7 +43,7 @@
40 43 int modelrev = 0;
41 44 int i;
42 45  
43   - gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE;
  46 + gpio2 = (struct exynos4x12_gpio_part2 *)samsung_get_base_gpio_part2();
44 47  
45 48 /*
46 49 * GPM1[1:0]: MODEL_REV[1:0]
... ... @@ -90,7 +93,7 @@
90 93  
91 94 static void board_external_gpio_init(void)
92 95 {
93   - gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE;
  96 + gpio2 = (struct exynos4x12_gpio_part2 *)samsung_get_base_gpio_part2();
94 97  
95 98 /*
96 99 * some pins which in alive block are connected with external pull-up
... ... @@ -115,8 +118,8 @@
115 118 #ifdef CONFIG_SYS_I2C_INIT_BOARD
116 119 static void board_init_i2c(void)
117 120 {
118   - gpio1 = (struct exynos4x12_gpio_part1 *)EXYNOS4X12_GPIO_PART1_BASE;
119   - gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE;
  121 + gpio1 = (struct exynos4x12_gpio_part1 *)samsung_get_base_gpio_part1();
  122 + gpio2 = (struct exynos4x12_gpio_part2 *)samsung_get_base_gpio_part2();
120 123  
121 124 /* I2C_7 */
122 125 s5p_gpio_direction_output(&gpio1->d0, 2, 1);
... ... @@ -147,7 +150,7 @@
147 150 int board_init(void)
148 151 {
149 152 struct exynos4_power *pwr =
150   - (struct exynos4_power *)EXYNOS4X12_POWER_BASE;
  153 + (struct exynos4_power *)samsung_get_base_power();
151 154  
152 155 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
153 156  
... ... @@ -254,7 +257,7 @@
254 257 {
255 258 int err0, err2 = 0;
256 259  
257   - gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE;
  260 + gpio2 = (struct exynos4x12_gpio_part2 *)samsung_get_base_gpio_part2();
258 261  
259 262 /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
260 263 s5p_gpio_direction_output(&gpio2->k0, 2, 1);
... ... @@ -308,6 +311,95 @@
308 311 return err0 & err2;
309 312 }
310 313  
  314 +#ifdef CONFIG_USB_GADGET
  315 +static int s5pc210_phy_control(int on)
  316 +{
  317 + int ret = 0;
  318 + unsigned int val;
  319 + struct pmic *p, *p_pmic, *p_muic;
  320 +
  321 + p_pmic = pmic_get("MAX77686_PMIC");
  322 + if (!p_pmic)
  323 + return -ENODEV;
  324 +
  325 + if (pmic_probe(p_pmic))
  326 + return -1;
  327 +
  328 + p_muic = pmic_get("MAX77693_MUIC");
  329 + if (!p_muic)
  330 + return -ENODEV;
  331 +
  332 + if (pmic_probe(p_muic))
  333 + return -1;
  334 +
  335 + if (on) {
  336 + ret = max77686_set_ldo_mode(p_pmic, 12, OPMODE_ON);
  337 + if (ret)
  338 + return -1;
  339 +
  340 + p = pmic_get("MAX77693_PMIC");
  341 + if (!p)
  342 + return -ENODEV;
  343 +
  344 + if (pmic_probe(p))
  345 + return -1;
  346 +
  347 + /* SAFEOUT */
  348 + ret = pmic_reg_read(p, MAX77693_SAFEOUT, &val);
  349 + if (ret)
  350 + return -1;
  351 +
  352 + val |= MAX77693_ENSAFEOUT1;
  353 + ret = pmic_reg_write(p, MAX77693_SAFEOUT, val);
  354 + if (ret)
  355 + return -1;
  356 +
  357 + /* PATH: USB */
  358 + ret = pmic_reg_write(p_muic, MAX77693_MUIC_CONTROL1,
  359 + MAX77693_MUIC_CTRL1_DN1DP2);
  360 +
  361 + } else {
  362 + ret = max77686_set_ldo_mode(p_pmic, 12, OPMODE_LPM);
  363 + if (ret)
  364 + return -1;
  365 +
  366 + /* PATH: UART */
  367 + ret = pmic_reg_write(p_muic, MAX77693_MUIC_CONTROL1,
  368 + MAX77693_MUIC_CTRL1_UT1UR2);
  369 + }
  370 +
  371 + if (ret)
  372 + return -1;
  373 +
  374 + return 0;
  375 +}
  376 +
  377 +struct s3c_plat_otg_data s5pc210_otg_data = {
  378 + .phy_control = s5pc210_phy_control,
  379 + .regs_phy = EXYNOS4X12_USBPHY_BASE,
  380 + .regs_otg = EXYNOS4X12_USBOTG_BASE,
  381 + .usb_phy_ctrl = EXYNOS4X12_USBPHY_CONTROL,
  382 + .usb_flags = PHY0_SLEEP,
  383 +};
  384 +
  385 +int board_usb_init(int index, enum usb_init_type init)
  386 +{
  387 + debug("USB_udc_probe\n");
  388 + return s3c_udc_probe(&s5pc210_otg_data);
  389 +}
  390 +
  391 +#ifdef CONFIG_USB_CABLE_CHECK
  392 +int usb_cable_connected(void)
  393 +{
  394 + struct pmic *muic = pmic_get("MAX77693_MUIC");
  395 + if (!muic)
  396 + return 0;
  397 +
  398 + return !!muic->chrg->chrg_type(muic);
  399 +}
  400 +#endif
  401 +#endif
  402 +
311 403 static int pmic_init_max77686(void)
312 404 {
313 405 struct pmic *p = pmic_get("MAX77686_PMIC");
... ... @@ -421,7 +513,7 @@
421 513 {
422 514 struct pmic *p = pmic_get("MAX77686_PMIC");
423 515  
424   - gpio1 = (struct exynos4x12_gpio_part1 *)EXYNOS4X12_GPIO_PART1_BASE;
  516 + gpio1 = (struct exynos4x12_gpio_part1 *)samsung_get_base_gpio_part1();
425 517  
426 518 /* LCD_2.2V_EN: GPC0[1] */
427 519 s5p_gpio_set_pull(&gpio1->c0, 1, GPIO_PULL_UP);
... ... @@ -435,7 +527,7 @@
435 527  
436 528 void exynos_reset_lcd(void)
437 529 {
438   - gpio1 = (struct exynos4x12_gpio_part1 *)EXYNOS4X12_GPIO_PART1_BASE;
  530 + gpio1 = (struct exynos4x12_gpio_part1 *)samsung_get_base_gpio_part1();
439 531  
440 532 /* reset lcd */
441 533 s5p_gpio_direction_output(&gpio1->f2, 1, 0);
drivers/usb/gadget/regs-otg.h
Diff comments   View file @ 375a449
... ... @@ -226,6 +226,11 @@
226 226 #define CLK_SEL_12MHZ (0x2 << 0)
227 227 #define CLK_SEL_48MHZ (0x0 << 0)
228 228  
  229 +#define EXYNOS4X12_ID_PULLUP0 (0x01 << 3)
  230 +#define EXYNOS4X12_COMMON_ON_N0 (0x01 << 4)
  231 +#define EXYNOS4X12_CLK_SEL_12MHZ (0x02 << 0)
  232 +#define EXYNOS4X12_CLK_SEL_24MHZ (0x05 << 0)
  233 +
229 234 /* Device Configuration Register DCFG */
230 235 #define DEV_SPEED_HIGH_SPEED_20 (0x0 << 0)
231 236 #define DEV_SPEED_FULL_SPEED_20 (0x1 << 0)
drivers/usb/gadget/s3c_udc_otg.c
Diff comments   View file @ 375a449
... ... @@ -167,8 +167,13 @@
167 167 writel((readl(&phy->phypwr) &~(OTG_DISABLE_0 | ANALOG_PWRDOWN)
168 168 &~FORCE_SUSPEND_0), &phy->phypwr);
169 169  
170   - writel((readl(&phy->phyclk) &~(ID_PULLUP0 | COMMON_ON_N0)) |
171   - CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */
  170 + if (s5p_cpu_id == 0x4412)
  171 + writel((readl(&phy->phyclk) & ~(EXYNOS4X12_ID_PULLUP0 |
  172 + EXYNOS4X12_COMMON_ON_N0)) | EXYNOS4X12_CLK_SEL_24MHZ,
  173 + &phy->phyclk); /* PLL 24Mhz */
  174 + else
  175 + writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)) |
  176 + CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */
172 177  
173 178 writel((readl(&phy->rstcon) &~(LINK_SW_RST | PHYLNK_SW_RST))
174 179 | PHY_SW_RST0, &phy->rstcon);
include/configs/arndale.h
Diff comments   View file @ 375a449
... ... @@ -198,10 +198,6 @@
198 198 #define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512)
199 199 #define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)
200 200  
201   -#define CONFIG_SPI_BOOTING
202   -#define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058
203   -#define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
204   -
205 201 #define CONFIG_DOS_PARTITION
206 202 #define CONFIG_EFI_PARTITION
207 203 #define CONFIG_CMD_PART
include/configs/exynos5250-dt.h
Diff comments   View file @ 375a449
... ... @@ -157,6 +157,7 @@
157 157 #define COPY_BL2_FNPTR_ADDR 0x02020030
158 158  
159 159 #define CONFIG_SPL_LIBCOMMON_SUPPORT
  160 +#define CONFIG_SPL_GPIO_SUPPORT
160 161  
161 162 /* specific .lds file */
162 163 #define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds"
... ... @@ -255,7 +256,7 @@
255 256 #define CONFIG_DRIVER_S3C24X0_I2C
256 257 #define CONFIG_I2C_MULTI_BUS
257 258 #define CONFIG_MAX_I2C_NUM 8
258   -#define CONFIG_SYS_I2C_SLAVE 0x0
  259 +#define CONFIG_SYS_I2C_SLAVE 0x0
259 260 #define CONFIG_I2C_EDID
260 261  
261 262 /* PMIC */
... ... @@ -266,6 +267,7 @@
266 267 /* SPI */
267 268 #define CONFIG_ENV_IS_IN_SPI_FLASH
268 269 #define CONFIG_SPI_FLASH
  270 +#define CONFIG_ENV_SPI_BASE 0x12D30000
269 271  
270 272 #ifdef CONFIG_SPI_FLASH
271 273 #define CONFIG_EXYNOS_SPI
... ... @@ -289,27 +291,6 @@
289 291 #define CONFIG_POWER
290 292 #define CONFIG_POWER_I2C
291 293 #define CONFIG_POWER_MAX77686
292   -
293   -/* SPI */
294   -#define CONFIG_ENV_IS_IN_SPI_FLASH
295   -#define CONFIG_SPI_FLASH
296   -
297   -#ifdef CONFIG_SPI_FLASH
298   -#define CONFIG_EXYNOS_SPI
299   -#define CONFIG_CMD_SF
300   -#define CONFIG_CMD_SPI
301   -#define CONFIG_SPI_FLASH_WINBOND
302   -#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
303   -#define CONFIG_SF_DEFAULT_SPEED 50000000
304   -#define EXYNOS5_SPI_NUM_CONTROLLERS 5
305   -#endif
306   -
307   -#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
308   -#define CONFIG_ENV_SPI_MODE SPI_MODE_0
309   -#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
310   -#define CONFIG_ENV_SPI_BUS 1
311   -#define CONFIG_ENV_SPI_MAX_HZ 50000000
312   -#endif
313 294  
314 295 /* Ethernet Controllor Driver */
315 296 #ifdef CONFIG_CMD_NET
include/configs/trats.h
Diff comments   View file @ 375a449
... ... @@ -308,6 +308,7 @@
308 308 #define CONFIG_USB_GADGET_S3C_UDC_OTG
309 309 #define CONFIG_USB_GADGET_DUALSPEED
310 310 #define CONFIG_USB_GADGET_VBUS_DRAW 2
  311 +#define CONFIG_USB_CABLE_CHECK
311 312  
312 313 /* LCD */
313 314 #define CONFIG_EXYNOS_FB
include/configs/trats2.h
Diff comments   View file @ 375a449
... ... @@ -20,8 +20,6 @@
20 20 #define CONFIG_EXYNOS4 /* which is in a EXYNOS4XXX */
21 21 #define CONFIG_TIZEN /* TIZEN lib */
22 22  
23   -#define PLATFORM_NO_UNALIGNED
24   -
25 23 #include <asm/arch/cpu.h> /* get chip and board defs */
26 24  
27 25 #define CONFIG_ARCH_CPU_INIT
... ... @@ -65,10 +63,9 @@
65 63  
66 64 #define CONFIG_DISPLAY_CPUINFO
67 65  
68   -/*
69   - * Size of malloc() pool
70   - */
71   -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (2 << 20))
  66 +#include <asm/sizes.h>
  67 +/* Size of malloc() pool */
  68 +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M))
72 69  
73 70 /* select serial console configuration */
74 71 #define CONFIG_SERIAL2
... ... @@ -100,6 +97,7 @@
100 97 #define CONFIG_CMD_CACHE
101 98 #define CONFIG_CMD_I2C
102 99 #define CONFIG_CMD_MMC
  100 +#define CONFIG_CMD_DFU
103 101 #define CONFIG_CMD_GPT
104 102 #define CONFIG_CMD_PMIC
105 103  
... ... @@ -113,6 +111,23 @@
113 111 #define CONFIG_CMD_EXT4
114 112 #define CONFIG_CMD_EXT4_WRITE
115 113  
  114 +/* USB Composite download gadget - g_dnl */
  115 +#define CONFIG_USBDOWNLOAD_GADGET
  116 +#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M
  117 +#define CONFIG_DFU_FUNCTION
  118 +#define CONFIG_DFU_MMC
  119 +
  120 +/* TIZEN THOR downloader support */
  121 +#define CONFIG_CMD_THOR_DOWNLOAD
  122 +#define CONFIG_THOR_FUNCTION
  123 +
  124 +/* USB Samsung's IDs */
  125 +#define CONFIG_G_DNL_VENDOR_NUM 0x04E8
  126 +#define CONFIG_G_DNL_PRODUCT_NUM 0x6601
  127 +#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM
  128 +#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D
  129 +#define CONFIG_G_DNL_MANUFACTURER "Samsung"
  130 +
116 131 /* To use the TFTPBOOT over USB, Please enable the CONFIG_CMD_NET */
117 132 #undef CONFIG_CMD_NET
118 133  
119 134  
120 135  
121 136  
122 137  
123 138  
... ... @@ -136,25 +151,29 @@
136 151 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
137 152  
138 153 /* Tizen - partitions definitions */
139   -#define PARTS_CSA "csa-mmc"
140   -#define PARTS_BOOTLOADER "u-boot"
  154 +#define PARTS_CSA "csa"
141 155 #define PARTS_BOOT "boot"
  156 +#define PARTS_MODEM "modem"
  157 +#define PARTS_CSC "csc"
142 158 #define PARTS_ROOT "platform"
143 159 #define PARTS_DATA "data"
144   -#define PARTS_CSC "csc"
145 160 #define PARTS_UMS "ums"
146 161  
147 162 #define PARTS_DEFAULT \
148   - "uuid_disk=${uuid_gpt_disk};" \
149   - "name="PARTS_CSA",size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
150   - "name="PARTS_BOOTLOADER",size=60MiB," \
151   - "uuid=${uuid_gpt_"PARTS_BOOTLOADER"};" \
152   - "name="PARTS_BOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
153   - "name="PARTS_ROOT",size=1GiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
154   - "name="PARTS_DATA",size=3GiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
  163 + "name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
  164 + "name="PARTS_BOOT",size=64MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
  165 + "name="PARTS_MODEM",size=100MiB,uuid=${uuid_gpt_"PARTS_MODEM"};" \
155 166 "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
  167 + "name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
  168 + "name="PARTS_DATA",size=512MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
156 169 "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
157 170  
  171 +#define CONFIG_DFU_ALT \
  172 + "u-boot mmc 80 800;" \
  173 + "uImage ext4 0 2;" \
  174 + "exynos4412-trats2.dtb ext4 0 2;" \
  175 + ""PARTS_ROOT" part 0 5\0"
  176 +
158 177 #define CONFIG_EXTRA_ENV_SETTINGS \
159 178 "bootk=" \
160 179 "run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \
161 180  
162 181  
... ... @@ -178,15 +197,16 @@
178 197 "rootfstype=ext4\0" \
179 198 "console=" CONFIG_DEFAULT_CONSOLE \
180 199 "kernelname=uImage\0" \
181   - "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \
182   - "0x40007FC0 ${kernelname}\0" \
  200 + "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 " \
  201 + "${kernelname}\0" \
183 202 "loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \
184 203 "${fdtfile}\0" \
185   - "mmcdev=0\0" \" \
  204 + "mmcdev=CONFIG_MMC_DEFAULT_DEV\0" \" \
186 205 "mmcbootpart=2\0" \
187 206 "mmcrootpart=5\0" \
188 207 "opts=always_resume=1\0" \
189 208 "partitions=" PARTS_DEFAULT \
  209 + "dfu_alt_info=" CONFIG_DFU_ALT \
190 210 "uartpath=ap\0" \
191 211 "usbpath=ap\0" \
192 212 "consoleon=set console console=ttySAC2,115200n8; save; reset\0" \
... ... @@ -233,8 +253,6 @@
233 253 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \
234 254 - GENERATED_GBL_DATA_SIZE)
235 255  
236   -#define CONFIG_SYS_HZ 1000
237   -
238 256 /* valid baudrates */
239 257 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
240 258  
... ... @@ -293,6 +311,11 @@
293 311 #define CONFIG_POWER_MUIC_MAX77693
294 312 #define CONFIG_POWER_FG_MAX77693
295 313 #define CONFIG_POWER_BATTERY_TRATS2
  314 +#define CONFIG_USB_GADGET
  315 +#define CONFIG_USB_GADGET_S3C_UDC_OTG
  316 +#define CONFIG_USB_GADGET_DUALSPEED
  317 +#define CONFIG_USB_GADGET_VBUS_DRAW 2
  318 +#define CONFIG_USB_CABLE_CHECK
296 319  
297 320 /* LCD */
298 321 #define CONFIG_EXYNOS_FB
... ... @@ -304,6 +327,9 @@
304 327 #define CONFIG_EXYNOS_MIPI_DSIM
305 328 #define CONFIG_VIDEO_BMP_GZIP
306 329 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 250 * 4) + (1 << 12))
  330 +
  331 +#define CONFIG_CMD_USB_MASS_STORAGE
  332 +#define CONFIG_USB_GADGET_MASS_STORAGE
307 333  
308 334 /* Pass open firmware flat tree */
309 335 #define CONFIG_OF_LIBFDT 1