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Commit 37a9b4d0b7457f6d1c1998fff2372b7f92bc1d8c

Authored by Wolfgang Denk
Committed by Albert ARIBAUD
1 parent b550834458
Exists in master and in 55 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

ARM: remove broken "cmc_pu2" board 

Signed-off-by: Wolfgang Denk <wd@denx.de>

Showing 8 changed files with 1 additions and 1066 deletions Side-by-side Diff

board/cmc_pu2/Makefile
View file @ 37a9b4d
1   -#
2   -# (C) Copyright 2003-2006
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# See file CREDITS for list of people who contributed to this
6   -# project.
7   -#
8   -# This program is free software; you can redistribute it and/or
9   -# modify it under the terms of the GNU General Public License as
10   -# published by the Free Software Foundation; either version 2 of
11   -# the License, or (at your option) any later version.
12   -#
13   -# This program is distributed in the hope that it will be useful,
14   -# but WITHOUT ANY WARRANTY; without even the implied warranty of
15   -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16   -# GNU General Public License for more details.
17   -#
18   -# You should have received a copy of the GNU General Public License
19   -# along with this program; if not, write to the Free Software
20   -# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21   -# MA 02111-1307 USA
22   -#
23   -
24   -include $(TOPDIR)/config.mk
25   -
26   -LIB = $(obj)lib$(BOARD).o
27   -
28   -COBJS := cmc_pu2.o flash.o load_sernum_ethaddr.o
29   -
30   -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
31   -OBJS := $(addprefix $(obj),$(COBJS))
32   -SOBJS := $(addprefix $(obj),$(SOBJS))
33   -
34   -$(LIB): $(obj).depend $(OBJS) $(SOBJS)
35   - $(call cmd_link_o_target, $(OBJS) $(SOBJS))
36   -
37   -clean:
38   - rm -f $(SOBJS) $(OBJS)
39   -
40   -distclean: clean
41   - rm -f $(LIB) core *.bak $(obj).depend
42   -
43   -#########################################################################
44   -
45   -# defines $(obj).depend target
46   -include $(SRCTREE)/rules.mk
47   -
48   -sinclude $(obj).depend
49   -
50   -#########################################################################
board/cmc_pu2/cmc_pu2.c
View file @ 37a9b4d
1   -/*
2   - * (C) Copyright 2002
3   - * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4   - * Marius Groeger <mgroeger@sysgo.de>
5   - *
6   - * Modified for CMC_PU2 (removed Smart Media support) by Gary Jennejohn
7   - * (2004) garyj@denx.de
8   - *
9   - * Modified for CMC_BASIC by Martin Krause (2005), TQ-Systems GmbH
10   - *
11   - * See file CREDITS for list of people who contributed to this
12   - * project.
13   - *
14   - * This program is free software; you can redistribute it and/or
15   - * modify it under the terms of the GNU General Public License as
16   - * published by the Free Software Foundation; either version 2 of
17   - * the License, or (at your option) any later version.
18   - *
19   - * This program is distributed in the hope that it will be useful,
20   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
21   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22   - * GNU General Public License for more details.
23   - *
24   - * You should have received a copy of the GNU General Public License
25   - * along with this program; if not, write to the Free Software
26   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27   - * MA 02111-1307 USA
28   - */
29   -
30   -#include <common.h>
31   -#include <asm/mach-types.h>
32   -#include <asm/arch/AT91RM9200.h>
33   -#include <asm/io.h>
34   -#include <netdev.h>
35   -#if defined(CONFIG_DRIVER_ETHER)
36   -#include <at91rm9200_net.h>
37   -#include <dm9161.h>
38   -#endif
39   -
40   -DECLARE_GLOBAL_DATA_PTR;
41   -
42   -/* ------------------------------------------------------------------------- */
43   -/*
44   - * Miscelaneous platform dependent initialisations
45   - */
46   -#define CMC_HP_BASIC 1
47   -#define CMC_PU2 2
48   -#define CMC_BASIC 4
49   -
50   -int hw_detect (void);
51   -
52   -int board_init (void)
53   -{
54   - AT91PS_PIO piob = AT91C_BASE_PIOB;
55   - AT91PS_PIO pioc = AT91C_BASE_PIOC;
56   -
57   - /* Enable Ctrlc */
58   - console_init_f ();
59   -
60   - /* Correct IRDA resistor problem */
61   - /* Set PA23_TXD in Output */
62   - /* (AT91PS_PIO) AT91C_BASE_PIOA->PIO_OER = AT91C_PA23_TXD2; */
63   -
64   - /* memory and cpu-speed are setup before relocation */
65   - /* so we do _nothing_ here */
66   -
67   - /* PIOB and PIOC clock enabling */
68   - *AT91C_PMC_PCER = 1 << AT91C_ID_PIOB;
69   - *AT91C_PMC_PCER = 1 << AT91C_ID_PIOC;
70   -
71   - /*
72   - * configure PC0-PC3 as input without pull ups, so RS485 driver enable
73   - * (CMC-PU2) and digital outputs (CMC-BASIC) are deactivated.
74   - */
75   - pioc->PIO_ODR = AT91C_PIO_PC0 | AT91C_PIO_PC1 |
76   - AT91C_PIO_PC2 | AT91C_PIO_PC3;
77   - pioc->PIO_PPUDR = AT91C_PIO_PC0 | AT91C_PIO_PC1 |
78   - AT91C_PIO_PC2 | AT91C_PIO_PC3;
79   - pioc->PIO_PER = AT91C_PIO_PC0 | AT91C_PIO_PC1 |
80   - AT91C_PIO_PC2 | AT91C_PIO_PC3;
81   -
82   - /*
83   - * On CMC-PU2 board configure PB3-PB6 to input without pull ups to
84   - * clear the duo LEDs (the external pull downs assure a proper
85   - * signal). On CMC-BASIC and CMC-HP-BASIC set PB3-PB6 to output and
86   - * drive it high, to configure current measurement on AINx.
87   - */
88   - if (hw_detect() & CMC_PU2) {
89   - piob->PIO_ODR = AT91C_PIO_PB3 | AT91C_PIO_PB4 |
90   - AT91C_PIO_PB5 | AT91C_PIO_PB6;
91   - }
92   - else if ((hw_detect() & CMC_BASIC) || (hw_detect() & CMC_HP_BASIC)) {
93   - piob->PIO_SODR = AT91C_PIO_PB3 | AT91C_PIO_PB4 |
94   - AT91C_PIO_PB5 | AT91C_PIO_PB6;
95   - piob->PIO_OER = AT91C_PIO_PB3 | AT91C_PIO_PB4 |
96   - AT91C_PIO_PB5 | AT91C_PIO_PB6;
97   - }
98   - piob->PIO_PPUDR = AT91C_PIO_PB3 | AT91C_PIO_PB4 |
99   - AT91C_PIO_PB5 | AT91C_PIO_PB6;
100   - piob->PIO_PER = AT91C_PIO_PB3 | AT91C_PIO_PB4 |
101   - AT91C_PIO_PB5 | AT91C_PIO_PB6;
102   -
103   - /*
104   - * arch number of CMC_PU2-Board. MACH_TYPE_CMC_PU2 is not supported in
105   - * the linuxarm kernel, yet.
106   - */
107   - /* gd->bd->bi_arch_number = MACH_TYPE_CMC_PU2; */
108   - gd->bd->bi_arch_number = 251;
109   - /* adress of boot parameters */
110   - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
111   -
112   - return 0;
113   -}
114   -
115   -int dram_init (void)
116   -{
117   - gd->bd->bi_dram[0].start = PHYS_SDRAM;
118   - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
119   - return 0;
120   -}
121   -
122   -int checkboard (void)
123   -{
124   - if (hw_detect() & CMC_PU2)
125   - puts ("Board: CMC-PU2 (Rittal GmbH)\n");
126   - else if (hw_detect() & CMC_BASIC)
127   - puts ("Board: CMC-BASIC (Rittal GmbH)\n");
128   - else if (hw_detect() & CMC_HP_BASIC)
129   - puts ("Board: CMC-HP-BASIC (Rittal GmbH)\n");
130   - else
131   - puts ("Board: unknown\n");
132   - return 0;
133   -}
134   -
135   -int hw_detect (void)
136   -{
137   - AT91PS_PIO pio = AT91C_BASE_PIOB;
138   -
139   - /* PIOB clock enabling */
140   - *AT91C_PMC_PCER = 1 << AT91C_ID_PIOB;
141   -
142   - /* configure PB12 as input without pull up */
143   - pio->PIO_ODR = AT91C_PIO_PB12;
144   - pio->PIO_PPUDR = AT91C_PIO_PB12;
145   - pio->PIO_PER = AT91C_PIO_PB12;
146   -
147   - /* configure PB13 as input without pull up */
148   - pio->PIO_ODR = AT91C_PIO_PB13;
149   - pio->PIO_PPUDR = AT91C_PIO_PB13;
150   - pio->PIO_PER = AT91C_PIO_PB13;
151   -
152   - /* read board identification pin */
153   - if (pio->PIO_PDSR & AT91C_PIO_PB12)
154   - return ((pio->PIO_PDSR & AT91C_PIO_PB13)
155   - ? CMC_PU2 : 0);
156   - else
157   - return ((pio->PIO_PDSR & AT91C_PIO_PB13)
158   - ? CMC_HP_BASIC : CMC_BASIC);
159   -}
160   -
161   -#ifdef CONFIG_DRIVER_ETHER
162   -#if defined(CONFIG_CMD_NET)
163   -
164   -/*
165   - * Name:
166   - * at91rm9200_GetPhyInterface
167   - * Description:
168   - * Initialise the interface functions to the PHY
169   - * Arguments:
170   - * None
171   - * Return value:
172   - * None
173   - */
174   -void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
175   -{
176   - p_phyops->Init = dm9161_InitPhy;
177   - p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
178   - p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
179   - p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
180   -}
181   -
182   -#endif
183   -#endif /* CONFIG_DRIVER_ETHER */
184   -
185   -#ifdef CONFIG_DRIVER_AT91EMAC
186   -int board_eth_init(bd_t *bis)
187   -{
188   - int rc = 0;
189   - rc = at91emac_register(bis, 0);
190   - return rc;
191   -}
192   -#endif
board/cmc_pu2/config.mk
View file @ 37a9b4d
1   -CONFIG_SYS_TEXT_BASE = 0x20F00000
2   -## For testing: load at 0x20100000 and "go" at 0x201000A4
3   -#CONFIG_SYS_TEXT_BASE = 0x20100000
board/cmc_pu2/flash.c
View file @ 37a9b4d
1   -/*
2   - * (C) Copyright 2003-2004
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * (C) Copyright 2004
6   - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
7   - *
8   - * Modified for the CMC PU2 by (C) Copyright 2004 Gary Jennejohn
9   - * garyj@denx.de
10   - *
11   - * See file CREDITS for list of people who contributed to this
12   - * project.
13   - *
14   - * This program is free software; you can redistribute it and/or
15   - * modify it under the terms of the GNU General Public License as
16   - * published by the Free Software Foundation; either version 2 of
17   - * the License, or (at your option) any later version.
18   - *
19   - * This program is distributed in the hope that it will be useful,
20   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
21   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22   - * GNU General Public License for more details.
23   - *
24   - * You should have received a copy of the GNU General Public License
25   - * along with this program; if not, write to the Free Software
26   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27   - * MA 02111-1307 USA
28   - */
29   -
30   -#include <common.h>
31   -
32   -#ifndef CONFIG_ENV_ADDR
33   -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
34   -#endif
35   -
36   -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
37   -
38   -#define FLASH_CYCLE1 0x0555
39   -#define FLASH_CYCLE2 0x02AA
40   -
41   -/*-----------------------------------------------------------------------
42   - * Functions
43   - */
44   -static ulong flash_get_size(vu_short *addr, flash_info_t *info);
45   -static void flash_reset(flash_info_t *info);
46   -static int write_word_amd(flash_info_t *info, vu_short *dest, ushort data);
47   -static flash_info_t *flash_get_info(ulong base);
48   -
49   -/*-----------------------------------------------------------------------
50   - * flash_init()
51   - *
52   - * sets up flash_info and returns size of FLASH (bytes)
53   - */
54   -unsigned long flash_init (void)
55   -{
56   - unsigned long size = 0;
57   - ulong flashbase = CONFIG_SYS_FLASH_BASE;
58   -
59   - /* Init: no FLASHes known */
60   - memset(&flash_info[0], 0, sizeof(flash_info_t));
61   -
62   - flash_info[0].size = flash_get_size((vu_short *)flashbase, &flash_info[0]);
63   -
64   - size = flash_info[0].size;
65   -
66   -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
67   - /* monitor protection ON by default */
68   - flash_protect(FLAG_PROTECT_SET,
69   - CONFIG_SYS_MONITOR_BASE,
70   - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
71   - flash_get_info(CONFIG_SYS_MONITOR_BASE));
72   -#endif
73   -
74   -#ifdef CONFIG_ENV_IS_IN_FLASH
75   - /* ENV protection ON by default */
76   - flash_protect(FLAG_PROTECT_SET,
77   - CONFIG_ENV_ADDR,
78   - CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
79   - flash_get_info(CONFIG_ENV_ADDR));
80   -#endif
81   -
82   - return size ? size : 1;
83   -}
84   -
85   -/*-----------------------------------------------------------------------
86   - */
87   -static void flash_reset(flash_info_t *info)
88   -{
89   - vu_short *base = (vu_short *)(info->start[0]);
90   -
91   - /* Put FLASH back in read mode */
92   - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
93   - *base = 0x00FF; /* Intel Read Mode */
94   - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
95   - *base = 0x00F0; /* AMD Read Mode */
96   -}
97   -
98   -/*-----------------------------------------------------------------------
99   - */
100   -
101   -static flash_info_t *flash_get_info(ulong base)
102   -{
103   - int i;
104   - flash_info_t * info;
105   -
106   - info = NULL;
107   - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
108   - info = & flash_info[i];
109   - if (info->size && info->start[0] <= base &&
110   - base <= info->start[0] + info->size - 1)
111   - break;
112   - }
113   -
114   - return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info;
115   -}
116   -
117   -/*-----------------------------------------------------------------------
118   - */
119   -
120   -void flash_print_info (flash_info_t *info)
121   -{
122   - int i;
123   -
124   - if (info->flash_id == FLASH_UNKNOWN) {
125   - printf ("missing or unknown FLASH type\n");
126   - return;
127   - }
128   -
129   - switch (info->flash_id & FLASH_VENDMASK) {
130   - case FLASH_MAN_AMD: printf ("AMD "); break;
131   - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
132   - case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
133   - case FLASH_MAN_SST: printf ("SST "); break;
134   - case FLASH_MAN_STM: printf ("STM "); break;
135   - case FLASH_MAN_INTEL: printf ("INTEL "); break;
136   - default: printf ("Unknown Vendor "); break;
137   - }
138   -
139   - switch (info->flash_id & FLASH_TYPEMASK) {
140   - case FLASH_S29GL064M:
141   - printf ("S29GL064M-R6 (64Mbit, uniform sector size)\n");
142   - break;
143   - default:
144   - printf ("Unknown Chip Type\n");
145   - break;
146   - }
147   -
148   - printf (" Size: %ld MB in %d Sectors\n",
149   - info->size >> 20,
150   - info->sector_count);
151   -
152   - printf (" Sector Start Addresses:");
153   -
154   - for (i=0; i<info->sector_count; ++i) {
155   - if ((i % 5) == 0) {
156   - printf ("\n ");
157   - }
158   - printf (" %08lX%s",
159   - info->start[i],
160   - info->protect[i] ? " (RO)" : " ");
161   - }
162   - printf ("\n");
163   - return;
164   -}
165   -
166   -/*-----------------------------------------------------------------------
167   - */
168   -
169   -/*
170   - * The following code cannot be run from FLASH!
171   - */
172   -
173   -ulong flash_get_size (vu_short *addr, flash_info_t *info)
174   -{
175   - int i;
176   - ushort value;
177   - ulong base = (ulong)addr;
178   -
179   - /* Write auto select command sequence */
180   - addr[FLASH_CYCLE1] = 0x00AA; /* for AMD, Intel ignores this */
181   - addr[FLASH_CYCLE2] = 0x0055; /* for AMD, Intel ignores this */
182   - addr[FLASH_CYCLE1] = 0x0090; /* selects Intel or AMD */
183   -
184   - /* read Manufacturer ID */
185   - udelay(100);
186   - value = addr[0];
187   - debug ("Manufacturer ID: %04X\n", value);
188   -
189   - switch (value) {
190   -
191   - case (AMD_MANUFACT & 0xFFFF):
192   - debug ("Manufacturer: AMD (Spansion)\n");
193   - info->flash_id = FLASH_MAN_AMD;
194   - break;
195   -
196   - case (INTEL_MANUFACT & 0xFFFF):
197   - debug ("Manufacturer: Intel (not supported yet)\n");
198   - info->flash_id = FLASH_MAN_INTEL;
199   - break;
200   -
201   - default:
202   - printf ("Unknown Manufacturer ID: %04X\n", value);
203   - info->flash_id = FLASH_UNKNOWN;
204   - info->sector_count = 0;
205   - info->size = 0;
206   - goto out;
207   - }
208   -
209   - value = addr[1];
210   - debug ("Device ID: %04X\n", value);
211   -
212   - switch (addr[1]) {
213   -
214   - case (AMD_ID_MIRROR & 0xFFFF):
215   - debug ("Mirror Bit flash: addr[14] = %08X addr[15] = %08X\n",
216   - addr[14], addr[15]);
217   -
218   - switch(addr[14]) {
219   - case (AMD_ID_GL064M_2 & 0xFFFF):
220   - if (addr[15] != (AMD_ID_GL064M_3 & 0xffff)) {
221   - printf ("Chip: S29GLxxxM -> unknown\n");
222   - info->flash_id = FLASH_UNKNOWN;
223   - info->sector_count = 0;
224   - info->size = 0;
225   - } else {
226   - debug ("Chip: S29GL064M-R6\n");
227   - info->flash_id += FLASH_S29GL064M;
228   - info->sector_count = 128;
229   - info->size = 0x00800000;
230   - for (i = 0; i < info->sector_count; i++) {
231   - info->start[i] = base;
232   - base += 0x10000;
233   - }
234   - }
235   - break; /* => 16 MB */
236   - default:
237   - printf ("Chip: *** unknown ***\n");
238   - info->flash_id = FLASH_UNKNOWN;
239   - info->sector_count = 0;
240   - info->size = 0;
241   - break;
242   - }
243   - break;
244   -
245   - default:
246   - printf ("Unknown Device ID: %04X\n", value);
247   - info->flash_id = FLASH_UNKNOWN;
248   - info->sector_count = 0;
249   - info->size = 0;
250   - break;
251   - }
252   -
253   -out:
254   - /* Put FLASH back in read mode */
255   - flash_reset(info);
256   -
257   - return (info->size);
258   -}
259   -
260   -/*-----------------------------------------------------------------------
261   - */
262   -
263   -int flash_erase (flash_info_t *info, int s_first, int s_last)
264   -{
265   - vu_short *addr = (vu_short *)(info->start[0]);
266   - int flag, prot, sect, ssect, l_sect;
267   - ulong now, last, start;
268   -
269   - debug ("flash_erase: first: %d last: %d\n", s_first, s_last);
270   -
271   - if ((s_first < 0) || (s_first > s_last)) {
272   - if (info->flash_id == FLASH_UNKNOWN) {
273   - printf ("- missing\n");
274   - } else {
275   - printf ("- no sectors to erase\n");
276   - }
277   - return 1;
278   - }
279   -
280   - if ((info->flash_id == FLASH_UNKNOWN) ||
281   - (info->flash_id > FLASH_AMD_COMP)) {
282   - printf ("Can't erase unknown flash type %08lx - aborted\n",
283   - info->flash_id);
284   - return 1;
285   - }
286   -
287   - prot = 0;
288   - for (sect=s_first; sect<=s_last; ++sect) {
289   - if (info->protect[sect]) {
290   - prot++;
291   - }
292   - }
293   -
294   - if (prot) {
295   - printf ("- Warning: %d protected sectors will not be erased!\n",
296   - prot);
297   - } else {
298   - printf ("\n");
299   - }
300   -
301   - /* Disable interrupts which might cause a timeout here */
302   - flag = disable_interrupts();
303   -
304   - /*
305   - * Start erase on unprotected sectors.
306   - * Since the flash can erase multiple sectors with one command
307   - * we take advantage of that by doing the erase in chunks of
308   - * 3 sectors.
309   - */
310   - for (sect = s_first; sect <= s_last; ) {
311   - l_sect = -1;
312   -
313   - addr[FLASH_CYCLE1] = 0x00AA;
314   - addr[FLASH_CYCLE2] = 0x0055;
315   - addr[FLASH_CYCLE1] = 0x0080;
316   - addr[FLASH_CYCLE1] = 0x00AA;
317   - addr[FLASH_CYCLE2] = 0x0055;
318   -
319   - /* do the erase in chunks of at most 3 sectors */
320   - for (ssect = 0; ssect < 3; ssect++) {
321   - if ((sect + ssect) > s_last)
322   - break;
323   - if (info->protect[sect + ssect] == 0) { /* not protected */
324   - addr = (vu_short *)(info->start[sect + ssect]);
325   - addr[0] = 0x0030;
326   - l_sect = sect + ssect;
327   - }
328   - }
329   - /* wait at least 80us - let's wait 1 ms */
330   - udelay (1000);
331   -
332   - /*
333   - * We wait for the last triggered sector
334   - */
335   - if (l_sect < 0)
336   - goto DONE;
337   -
338   - start = get_timer(0);
339   - last = 0;
340   - addr = (vu_short *)(info->start[l_sect]);
341   - while ((addr[0] & 0x0080) != 0x0080) {
342   - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
343   - printf ("Timeout\n");
344   - return 1;
345   - }
346   - /* show that we're waiting */
347   - if ((now - last) > 1000) { /* every second */
348   - putc ('.');
349   - last = now;
350   - }
351   - }
352   - addr = (vu_short *)info->start[0];
353   - addr[0] = 0x00F0; /* reset bank */
354   - sect += ssect;
355   - }
356   -
357   - /* re-enable interrupts if necessary */
358   - if (flag)
359   - enable_interrupts();
360   -
361   -DONE:
362   - /* reset to read mode */
363   - addr = (vu_short *)info->start[0];
364   - addr[0] = 0x00F0; /* reset bank */
365   -
366   - printf (" done\n");
367   - return 0;
368   -}
369   -
370   -/*-----------------------------------------------------------------------
371   - * Copy memory to flash, returns:
372   - * 0 - OK
373   - * 1 - write timeout
374   - * 2 - Flash not erased
375   - */
376   -
377   -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
378   -{
379   - ulong wp, data;
380   - int rc;
381   -
382   - if (addr & 1) {
383   - printf ("unaligned destination not supported\n");
384   - return ERR_ALIGN;
385   - };
386   -
387   - if ((int) src & 1) {
388   - printf ("unaligned source not supported\n");
389   - return ERR_ALIGN;
390   - };
391   -
392   - wp = addr;
393   -
394   - while (cnt >= 2) {
395   - data = *((vu_short *)src);
396   - if ((rc = write_word_amd(info, (vu_short *)wp, data)) != 0) {
397   -printf ("write_buff 1: write_word_amd() rc=%d\n", rc);
398   - return (rc);
399   - }
400   - src += 2;
401   - wp += 2;
402   - cnt -= 2;
403   - }
404   -
405   - if (cnt == 0) {
406   - return (ERR_OK);
407   - }
408   -
409   - if (cnt == 1) {
410   - data = (*((volatile u8 *) src)) | (*((volatile u8 *) (wp + 1)) << 8);
411   - if ((rc = write_word_amd(info, (vu_short *)wp, data)) != 0) {
412   -printf ("write_buff 1: write_word_amd() rc=%d\n", rc);
413   - return (rc);
414   - }
415   - src += 1;
416   - wp += 1;
417   - cnt -= 1;
418   - }
419   -
420   - return ERR_OK;
421   -}
422   -
423   -/*-----------------------------------------------------------------------
424   - * Write a word to Flash for AMD FLASH
425   - * A word is 16 or 32 bits, whichever the bus width of the flash bank
426   - * (not an individual chip) is.
427   - *
428   - * returns:
429   - * 0 - OK
430   - * 1 - write timeout
431   - * 2 - Flash not erased
432   - */
433   -static int write_word_amd (flash_info_t *info, vu_short *dest, ushort data)
434   -{
435   - int flag;
436   - vu_short *base; /* first address in flash bank */
437   - ulong start;
438   -
439   - /* Check if Flash is (sufficiently) erased */
440   - if ((*dest & data) != data) {
441   - return (2);
442   - }
443   -
444   - base = (vu_short *)(info->start[0]);
445   -
446   - /* Disable interrupts which might cause a timeout here */
447   - flag = disable_interrupts();
448   -
449   - base[FLASH_CYCLE1] = 0x00AA; /* unlock */
450   - base[FLASH_CYCLE2] = 0x0055; /* unlock */
451   - base[FLASH_CYCLE1] = 0x00A0; /* selects program mode */
452   -
453   - *dest = data; /* start programming the data */
454   -
455   - /* re-enable interrupts if necessary */
456   - if (flag)
457   - enable_interrupts();
458   -
459   - start = get_timer(0);
460   -
461   - /* data polling for D7 */
462   - while ((*dest & 0x0080) != (data & 0x0080)) {
463   - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
464   - *dest = 0x00F0; /* reset bank */
465   - return (1);
466   - }
467   - }
468   - return (0);
469   -}
board/cmc_pu2/load_sernum_ethaddr.c
View file @ 37a9b4d
1   -/*
2   - * (C) Copyright 2000, 2001, 2002
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * (C) Copyright 2005
6   - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
7   - *
8   - * See file CREDITS for list of people who contributed to this
9   - * project.
10   - *
11   - * This program is free software; you can redistribute it and/or
12   - * modify it under the terms of the GNU General Public License as
13   - * published by the Free Software Foundation; either version 2 of
14   - * the License, or (at your option) any later version.
15   - *
16   - * This program is distributed in the hope that it will be useful,
17   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
18   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19   - * GNU General Public License for more details.
20   - *
21   - * You should have received a copy of the GNU General Public License
22   - * along with this program; if not, write to the Free Software
23   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24   - * MA 02111-1307 USA
25   - */
26   -
27   -/* #define DEBUG */
28   -
29   -#include <common.h>
30   -#include <net.h>
31   -
32   -#define I2C_CHIP 0x50 /* I2C bus address of onboard EEPROM */
33   -#define I2C_ALEN 1 /* length of EEPROM addresses in bytes */
34   -#define I2C_OFFSET 0x0 /* start address of manufacturere data block
35   - * in EEPROM */
36   -
37   -/* 64 Byte manufacturer data block in EEPROM */
38   -struct manufacturer_data {
39   - unsigned int serial_number; /* serial number (0...999999) */
40   - unsigned short hardware; /* hardware version (e.g. V1.02) */
41   - unsigned short manuf_date; /* manufacture date (e.g. 25/02) */
42   - unsigned char name[20]; /* device name (in CHIP.INI) */
43   - unsigned char macadr[6]; /* MAC address */
44   - signed char a_kal[4]; /* calibration value for U */
45   - signed char i_kal[4]; /* calibration value for I */
46   - unsigned char reserve[18]; /* reserved */
47   - unsigned short save_nr; /* save count */
48   - unsigned short chksum; /* checksum */
49   -};
50   -
51   -
52   -int i2c_read (unsigned char chip, unsigned int addr, int alen,
53   - unsigned char *buffer, int len);
54   -
55   -/*-----------------------------------------------------------------------
56   - * Process manufacturer data block in EEPROM:
57   - *
58   - * If we boot on a system fresh from factory, check if the manufacturer data
59   - * in the EEPROM is valid and save some information it contains.
60   - *
61   - * CMC manufacturer data is defined as follows:
62   - *
63   - * - located in the onboard EEPROM
64   - * - starts at offset 0x0
65   - * - size 0x00000040
66   - *
67   - * Internal structure: see struct definition
68   - */
69   -
70   -int misc_init_r(void)
71   -{
72   - struct manufacturer_data data;
73   - char serial [9];
74   - unsigned short chksum;
75   - unsigned char *p;
76   - unsigned short i;
77   -
78   -#if !defined(CONFIG_HARD_I2C) && !defined(CONFIG_SOFT_I2C)
79   -#error you must define some I2C support (CONFIG_HARD_I2C or CONFIG_SOFT_I2C)
80   -#endif
81   - if (i2c_read(I2C_CHIP, I2C_OFFSET, I2C_ALEN, (unsigned char *)&data,
82   - sizeof(data)) != 0) {
83   - puts ("Error reading manufacturer data from EEPROM\n");
84   - return -1;
85   - }
86   -
87   - /* check if manufacturer data block is valid */
88   - p = (unsigned char *)&data;
89   - chksum = 0;
90   - for (i = 0; i < (sizeof(data) - sizeof(data.chksum)); i++)
91   - chksum += *p++;
92   -
93   - debug ("checksum of manufacturer data block: %#.4x\n", chksum);
94   -
95   - if (chksum != data.chksum) {
96   - puts ("Error: manufacturer data block has invalid checksum\n");
97   - return -1;
98   - }
99   -
100   - /* copy serial number */
101   - sprintf (serial, "%d", data.serial_number);
102   -
103   - /* set serial# and ethaddr if not yet defined */
104   - if (getenv("serial#") == NULL) {
105   - setenv ("serial#", serial);
106   - }
107   -
108   - if (getenv("ethaddr") == NULL) {
109   - eth_setenv_enetaddr("ethaddr", data.macadr);
110   - }
111   -
112   - return 0;
113   -}
... ... @@ -57,7 +57,6 @@
57 57 eb_cpux9k2 arm arm920t - BuS at91
58 58 cpuat91 arm arm920t cpuat91 eukrea at91 cpuat91
59 59 cpuat91_ram arm arm920t cpuat91 eukrea at91 cpuat91:RAMBOOT
60   -cmc_pu2 arm arm920t - - at91rm9200
61 60 csb637 arm arm920t - - at91rm9200
62 61 kb9202 arm arm920t - - at91rm9200
63 62 m501sk arm arm920t - - at91rm9200
doc/README.scrapyard
Diff comments   View file @ 37a9b4d
... ... @@ -11,6 +11,7 @@
11 11  
12 12 Board Arch CPU removed Commit last known maintainer/contact
13 13 =============================================================================
  14 +cmc_pu2 arm arm920t - 2011-07-17
14 15 at91cap9adk arm arm926ejs - 2011-07-17 Stelian Pop <stelian.pop@leadtechdesign.com>
15 16 voiceblue arm arm925t - 2011-07-17
16 17 smdk2400 arm arm920t - 2011-07-17 Gary Jennejohn <garyj@denx.de>
include/configs/cmc_pu2.h
View file @ 37a9b4d
1   -/*
2   - * 2004-2005 Gary Jennejohn <garyj@denx.de>
3   - *
4   - * Configuration settings for the CMC PU2 board.
5   - *
6   - * See file CREDITS for list of people who contributed to this
7   - * project.
8   - *
9   - * This program is free software; you can redistribute it and/or
10   - * modify it under the terms of the GNU General Public License as
11   - * published by the Free Software Foundation; either version 2 of
12   - * the License, or (at your option) any later version.
13   - *
14   - * This program is distributed in the hope that it will be useful,
15   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
16   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17   - * GNU General Public License for more details.
18   - *
19   - * You should have received a copy of the GNU General Public License
20   - * along with this program; if not, write to the Free Software
21   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22   - * MA 02111-1307 USA
23   - */
24   -
25   -#ifndef __CONFIG_H
26   -#define __CONFIG_H
27   -
28   -#define CONFIG_AT91_LEGACY
29   -
30   -/* ARM asynchronous clock */
31   -#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */
32   -#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK/3) /* peripheral clock */
33   -
34   -#define AT91_SLOW_CLOCK 32768 /* slow clock */
35   -
36   -#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
37   -#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
38   -#define CONFIG_CMC_PU2 1 /* on an CMC_PU2 Board */
39   -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
40   -#define USE_920T_MMU 1
41   -
42   -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
43   -#define CONFIG_SETUP_MEMORY_TAGS 1
44   -#define CONFIG_INITRD_TAG 1
45   -
46   -#ifndef CONFIG_SKIP_LOWLEVEL_INIT
47   -#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
48   -/* flash */
49   -#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
50   -#define CONFIG_SYS_SMC_CSR0_VAL 0x100032ad /* 16bit, 2 TDF, 4 WS */
51   -
52   -/* clocks */
53   -#define CONFIG_SYS_PLLAR_VAL 0x2026BE04 /* 179,712 MHz for PCK */
54   -#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
55   -#define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 69.120MHz from PLLA */
56   -
57   -/* sdram */
58   -#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
59   -#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
60   -#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
61   -#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
62   -#define CONFIG_SYS_SDRC_CR_VAL 0x3399c1d4 /* set up the CONFIG_SYS_SDRAM */
63   -#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */
64   -#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */
65   -#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */
66   -#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
67   -#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
68   -#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
69   -#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
70   -#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
71   -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
72   -
73   -/*
74   - * Size of malloc() pool
75   - */
76   -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
77   -
78   -#define CONFIG_BAUDRATE 9600
79   -
80   -/*
81   - * Hardware drivers
82   - */
83   -
84   -/* define one of these to choose the DBGU, USART0 or USART1 as console */
85   -#define CONFIG_AT91RM9200_USART
86   -#undef CONFIG_DBGU
87   -#define CONFIG_USART0
88   -#undef CONFIG_USART1
89   -
90   -#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
91   -
92   -#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
93   -
94   -#define CONFIG_HARD_I2C
95   -
96   -#ifdef CONFIG_HARD_I2C
97   -#define CONFIG_SYS_I2C_SPEED 0 /* not used */
98   -#define CONFIG_SYS_I2C_SLAVE 0 /* not used */
99   -#define CONFIG_RTC_RS5C372A /* RICOH I2C RTC */
100   -#define CONFIG_SYS_I2C_RTC_ADDR 0x32
101   -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
102   -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
103   -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
104   -#else
105   -#define CONFIG_TIMESTAMP
106   -#endif
107   -/* still about 20 kB free with this defined */
108   -#define CONFIG_SYS_LONGHELP
109   -
110   -#define CONFIG_BOOTDELAY 1
111   -
112   -
113   -/*
114   - * BOOTP options
115   - */
116   -#define CONFIG_BOOTP_BOOTFILESIZE
117   -#define CONFIG_BOOTP_BOOTPATH
118   -#define CONFIG_BOOTP_GATEWAY
119   -#define CONFIG_BOOTP_HOSTNAME
120   -
121   -
122   -/*
123   - * Command line configuration.
124   - */
125   -#include <config_cmd_default.h>
126   -
127   -#define CONFIG_CMD_DHCP
128   -#define CONFIG_CMD_NFS
129   -#define CONFIG_CMD_SNTP
130   -
131   -#undef CONFIG_CMD_FPGA
132   -#undef CONFIG_CMD_MISC
133   -
134   -#if defined(CONFIG_HARD_I2C)
135   - #define CONFIG_CMD_DATE
136   - #define CONFIG_CMD_EEPROM
137   - #define CONFIG_CMD_I2C
138   -#endif
139   -
140   -
141   -#define CONFIG_MISC_INIT_R
142   -#define CONFIG_SYS_LONGHELP
143   -
144   -#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
145   -#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */
146   -
147   -#define CONFIG_NR_DRAM_BANKS 1
148   -#define PHYS_SDRAM 0x20000000
149   -#define PHYS_SDRAM_SIZE 0x1000000 /* 16 megs */
150   -
151   -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
152   -#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
153   -
154   -#define CONFIG_NET_MULTI 1
155   -#ifdef CONFIG_NET_MULTI
156   -#define CONFIG_DRIVER_AT91EMAC 1
157   -#define CONFIG_SYS_RX_ETH_BUFFER 8
158   -#else
159   -#define CONFIG_DRIVER_ETHER 1
160   -#endif
161   -#define CONFIG_NET_RETRY_COUNT 20
162   -#define CONFIG_AT91C_USE_RMII
163   -
164   -#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ)
165   -#define CONFIG_SYS_MAX_DATAFLASH_BANKS 2
166   -#define CONFIG_SYS_MAX_DATAFLASH_PAGES 16384
167   -#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */
168   -#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */
169   -
170   -#define PHYS_FLASH_1 0x10000000
171   -#define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */
172   -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
173   -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
174   -#define CONFIG_SYS_MAX_FLASH_BANKS 1
175   -#define CONFIG_SYS_MAX_FLASH_SECT 256
176   -#define CONFIG_SYS_FLASH_ERASE_TOUT (11 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
177   -#define CONFIG_SYS_FLASH_WRITE_TOUT ( 2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
178   -
179   -#define CONFIG_ENV_IS_IN_FLASH 1
180   -#define CONFIG_ENV_OFFSET 0x20000 /* after u-boot.bin */
181   -#define CONFIG_ENV_SECT_SIZE (64 << 10) /* sectors are 64 kB */
182   -#define CONFIG_ENV_SIZE (16 << 10) /* Use only 16 kB */
183   -
184   -#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
185   -
186   -#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 }
187   -
188   -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
189   -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
190   -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
191   -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
192   -
193   -#define CONFIG_SYS_HZ 1000
194   -#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK/2) /* AT91C_TC0_CMR is implicitly set to */
195   - /* AT91C_TC_TIMER_DIV1_CLOCK */
196   -
197   -#define CONFIG_STACKSIZE (32*1024) /* regular stack */
198   -
199   -#ifdef CONFIG_USE_IRQ
200   -#error CONFIG_USE_IRQ not supported
201   -#endif
202   -
203   -#define CONFIG_EXTRA_ENV_SETTINGS \
204   - "net_nfs=tftp ${loadaddr} ${bootfile};run nfsargs addip addcons " \
205   - "addmtd;bootm\0" \
206   - "nfsargs=setenv bootargs root=/dev/nfs rw " \
207   - "nfsroot=${serverip}:${rootpath}\0" \
208   - "net_cramfs=tftp ${loadaddr} ${bootfile}; run flashargs addip " \
209   - "addcons addmtd; bootm\0" \
210   - "flash_cramfs=run flashargs addip addcons addmtd; bootm 10030000\0" \
211   - "flashargs=setenv bootargs root=/dev/mtdblock3 ro\0" \
212   - "addip=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \
213   - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
214   - "${hostname}::off\0" \
215   - "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
216   - "addmtd=setenv bootargs ${bootargs} mtdparts=cmc_pu2:128k(uboot)ro," \
217   - "64k(environment),768k(linux),4096k(root),-\0" \
218   - "load=tftp ${loadaddr} ${loadfile}\0" \
219   - "update=protect off 10000000 1001ffff;erase 10000000 1001ffff; " \
220   - "cp.b ${loadaddr} 10000000 ${filesize};" \
221   - "protect on 10000000 1001ffff\0" \
222   - "updatel=era 10030000 100effff;tftp ${loadaddr} ${bootfile}; " \
223   - "cp.b ${loadaddr} 10030000 ${filesize}\0" \
224   - "updatec=era 100f0000 104effff;tftp ${loadaddr} ${cramfsimage}; " \
225   - "cp.b ${loadaddr} 100f0000 ${filesize}\0" \
226   - "updatej=era 104f0000 107fffff;tftp ${loadaddr} ${jffsimage}; " \
227   - "cp.b ${loadaddr} 104f0000 ${filesize}\0" \
228   - "cramfsimage=cramfs_cmc-pu2.img\0" \
229   - "jffsimage=jffs2_cmc-pu2.img\0" \
230   - "loadfile=u-boot_cmc-pu2.bin\0" \
231   - "bootfile=uImage_cmc-pu2\0" \
232   - "loadaddr=0x20800000\0" \
233   - "hostname=CMC-TC-PU2\0" \
234   - "bootcmd=run dhcp_start;run flash_cramfs\0" \
235   - "autoload=n\0" \
236   - "dhcp_start=echo no DHCP\0" \
237   - "ipaddr=192.168.0.190\0"
238   -#endif /* __CONFIG_H */