Eric Lee / smarc-uboot

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Commit 37b499c43fbf91b65520d7e2bd7bb998c7ba38e2

Authored by Simon Glass
Committed by Tom Rini
1 parent 8f3086aaac
Exists in smarc_8mq_lf_v2020.04 and in 22 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

Drop CONFIG_WINBOND_83C553 

This is not used in U-Boot. Drop this option and associated dead code.

Signed-off-by: Simon Glass <sjg@chromium.org>

Showing 4 changed files with 0 additions and 222 deletions Side-by-side Diff

... ... @@ -262,17 +262,6 @@
262 262 }
263 263 #endif
264 264  
265   -#ifdef CONFIG_WINBOND_83C553
266   -static int initr_w83c553f(void)
267   -{
268   - /*
269   - * Initialise the ISA bridge
270   - */
271   - initialise_w83c553f();
272   - return 0;
273   -}
274   -#endif
275   -
276 265 static int initr_barrier(void)
277 266 {
278 267 #ifdef CONFIG_PPC
... ... @@ -833,9 +822,6 @@
833 822 * because PCU ressources are crucial for flash access on some boards.
834 823 */
835 824 initr_pci,
836   -#endif
837   -#ifdef CONFIG_WINBOND_83C553
838   - initr_w83c553f,
839 825 #endif
840 826 #ifdef CONFIG_ARCH_EARLY_INIT_R
841 827 arch_early_init_r,
drivers/pci/Makefile
Diff comments   View file @ 37b499c
... ... @@ -29,7 +29,6 @@
29 29 obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o
30 30 obj-$(CONFIG_PCI_TEGRA) += pci_tegra.o
31 31 obj-$(CONFIG_TSI108_PCI) += tsi108_pci.o
32   -obj-$(CONFIG_WINBOND_83C553) += w83c553f.o
33 32 obj-$(CONFIG_PCIE_DW_MVEBU) += pcie_dw_mvebu.o
34 33 obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o
35 34 obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o
drivers/pci/w83c553f.c
View file @ 37b499c
1   -/*
2   - * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
3   - * Andreas Heppel <aheppel@sysgo.de>
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -/*
9   - * Initialisation of the PCI-to-ISA bridge and disabling the BIOS
10   - * write protection (for flash) in function 0 of the chip.
11   - * Enabling function 1 (IDE controller of the chip.
12   - */
13   -
14   -#include <common.h>
15   -#include <config.h>
16   -
17   -#include <asm/io.h>
18   -#include <pci.h>
19   -
20   -#include <w83c553f.h>
21   -
22   -#define out8(addr,val) do { \
23   - out_8((u8*) (addr),(val)); udelay(1); \
24   - } while (0)
25   -#define out16(addr,val) do { \
26   - out_be16((u16*) (addr),(val)); udelay(1); \
27   - } while (0)
28   -
29   -extern uint ide_bus_offset[CONFIG_SYS_IDE_MAXBUS];
30   -
31   -void initialise_pic(void);
32   -void initialise_dma(void);
33   -
34   -void initialise_w83c553f(void)
35   -{
36   - pci_dev_t devbusfn;
37   - unsigned char reg8;
38   - unsigned short reg16;
39   - unsigned int reg32;
40   -
41   - devbusfn = pci_find_device(W83C553F_VID, W83C553F_DID, 0);
42   - if (devbusfn == -1)
43   - {
44   - printf("Error: Cannot find W83C553F controller on any PCI bus.");
45   - return;
46   - }
47   -
48   - pci_read_config_word(devbusfn, PCI_COMMAND, &reg16);
49   - reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
50   - pci_write_config_word(devbusfn, PCI_COMMAND, reg16);
51   -
52   - pci_read_config_byte(devbusfn, WINBOND_IPADCR, &reg8);
53   - /* 16 MB ISA memory space */
54   - reg8 |= (IPADCR_IPATOM4 | IPADCR_IPATOM5 | IPADCR_IPATOM6 | IPADCR_IPATOM7);
55   - reg8 &= ~IPADCR_MBE512;
56   - pci_write_config_byte(devbusfn, WINBOND_IPADCR, reg8);
57   -
58   - pci_read_config_byte(devbusfn, WINBOND_CSCR, &reg8);
59   - /* switch off BIOS write protection */
60   - reg8 |= CSCR_UBIOSCSE;
61   - reg8 &= ~CSCR_BIOSWP;
62   - pci_write_config_byte(devbusfn, WINBOND_CSCR, reg8);
63   -
64   - /*
65   - * Interrupt routing:
66   - * - IDE -> IRQ 9/0
67   - * - INTA -> IRQ 10
68   - * - INTB -> IRQ 11
69   - * - INTC -> IRQ 14
70   - * - INTD -> IRQ 15
71   - */
72   - pci_write_config_byte(devbusfn, WINBOND_IDEIRCR, 0x90);
73   - pci_write_config_word(devbusfn, WINBOND_PCIIRCR, 0xABEF);
74   -
75   - /*
76   - * Read IDE bus offsets from function 1 device.
77   - * We must unmask the LSB indicating that ist is an IO address.
78   - */
79   - devbusfn |= PCI_BDF(0,0,1);
80   -
81   - /*
82   - * Switch off legacy IRQ for IDE and IDE port 1.
83   - */
84   - pci_write_config_byte(devbusfn, 0x09, 0x8F);
85   -
86   - pci_read_config_dword(devbusfn, WINDOND_IDECSR, &reg32);
87   - reg32 &= ~(IDECSR_LEGIRQ | IDECSR_P1EN | IDECSR_P1F16);
88   - pci_write_config_dword(devbusfn, WINDOND_IDECSR, reg32);
89   -
90   - pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &ide_bus_offset[0]);
91   - ide_bus_offset[0] &= ~1;
92   -#if CONFIG_SYS_IDE_MAXBUS > 1
93   - pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_2, &ide_bus_offset[1]);
94   - ide_bus_offset[1] &= ~1;
95   -#endif
96   -
97   - /*
98   - * Enable function 1, IDE -> busmastering and IO space access
99   - */
100   - pci_read_config_word(devbusfn, PCI_COMMAND, &reg16);
101   - reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
102   - pci_write_config_word(devbusfn, PCI_COMMAND, reg16);
103   -
104   - /*
105   - * Initialise ISA interrupt controller
106   - */
107   - initialise_pic();
108   -
109   - /*
110   - * Initialise DMA controller
111   - */
112   - initialise_dma();
113   -}
114   -
115   -void initialise_pic(void)
116   -{
117   - out8(W83C553F_PIC1_ICW1, 0x11);
118   - out8(W83C553F_PIC1_ICW2, 0x08);
119   - out8(W83C553F_PIC1_ICW3, 0x04);
120   - out8(W83C553F_PIC1_ICW4, 0x01);
121   - out8(W83C553F_PIC1_OCW1, 0xfb);
122   - out8(W83C553F_PIC1_ELC, 0x20);
123   -
124   - out8(W83C553F_PIC2_ICW1, 0x11);
125   - out8(W83C553F_PIC2_ICW2, 0x08);
126   - out8(W83C553F_PIC2_ICW3, 0x02);
127   - out8(W83C553F_PIC2_ICW4, 0x01);
128   - out8(W83C553F_PIC2_OCW1, 0xff);
129   - out8(W83C553F_PIC2_ELC, 0xce);
130   -
131   - out8(W83C553F_TMR1_CMOD, 0x74);
132   -
133   - out8(W83C553F_PIC2_OCW1, 0x20);
134   - out8(W83C553F_PIC1_OCW1, 0x20);
135   -
136   - out8(W83C553F_PIC2_OCW1, 0x2b);
137   - out8(W83C553F_PIC1_OCW1, 0x2b);
138   -}
139   -
140   -void initialise_dma(void)
141   -{
142   - unsigned int channel;
143   - unsigned int rvalue1, rvalue2;
144   -
145   - /* perform a H/W reset of the devices */
146   -
147   - out8(W83C553F_DMA1 + W83C553F_DMA1_MC, 0x00);
148   - out16(W83C553F_DMA2 + W83C553F_DMA2_MC, 0x0000);
149   -
150   - /* initialise all channels to a sane state */
151   -
152   - for (channel = 0; channel < 4; channel++) {
153   - /*
154   - * dependent upon the channel, setup the specifics:
155   - *
156   - * demand
157   - * address-increment
158   - * autoinitialize-disable
159   - * verify-transfer
160   - */
161   -
162   - switch (channel) {
163   - case 0:
164   - rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH0SEL|W83C553F_MODE_TT_VERIFY);
165   - rvalue2 = (W83C553F_MODE_TM_CASCADE|W83C553F_MODE_CH0SEL);
166   - break;
167   - case 1:
168   - rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY);
169   - rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY);
170   - break;
171   - case 2:
172   - rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY);
173   - rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY);
174   - break;
175   - case 3:
176   - rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY);
177   - rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY);
178   - break;
179   - default:
180   - rvalue1 = 0x00;
181   - rvalue2 = 0x00;
182   - break;
183   - }
184   -
185   - /* write to write mode registers */
186   -
187   - out8(W83C553F_DMA1 + W83C553F_DMA1_WM, rvalue1 & 0xFF);
188   - out16(W83C553F_DMA2 + W83C553F_DMA2_WM, rvalue2 & 0x00FF);
189   - }
190   -
191   - /* enable all channels */
192   -
193   - out8(W83C553F_DMA1 + W83C553F_DMA1_CM, 0x00);
194   - out16(W83C553F_DMA2 + W83C553F_DMA2_CM, 0x0000);
195   - /*
196   - * initialize the global DMA configuration
197   - *
198   - * DACK# active low
199   - * DREQ active high
200   - * fixed priority
201   - * channel group enable
202   - */
203   -
204   - out8(W83C553F_DMA1 + W83C553F_DMA1_CS, 0x00);
205   - out16(W83C553F_DMA2 + W83C553F_DMA2_CS, 0x0000);
206   -}
scripts/config_whitelist.txt
Diff comments   View file @ 37b499c
... ... @@ -6891,7 +6891,6 @@
6891 6891 CONFIG_WDOG_GPIO_PIN
6892 6892 CONFIG_WD_MAX_RATE
6893 6893 CONFIG_WD_PERIOD
6894   -CONFIG_WINBOND_83C553
6895 6894 CONFIG_X600
6896 6895 CONFIG_X86EMU_DEBUG
6897 6896 CONFIG_X86EMU_RAW_IO