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Commit 37b608a52dcb13312a4f7ccea199cd6bac76d298

Authored by Masahiro Yamada
Committed by Tom Rini
1 parent a258e732a7
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

powerpc: remove icecube_5200, Lite5200, cpci5200, mecp5200, pf5200 

These boards are still non-generic boards.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>

Showing 49 changed files with 5 additions and 4752 deletions Side-by-side Diff

arch/powerpc/cpu/mpc5xxx/Kconfig
Diff comments   View file @ 37b608a
... ... @@ -26,9 +26,6 @@
26 26 config TARGET_GALAXY5200
27 27 bool "Support galaxy5200"
28 28  
29   -config TARGET_ICECUBE
30   - bool "Support IceCube"
31   -
32 29 config TARGET_INKA4X0
33 30 bool "Support inka4x0"
34 31  
... ... @@ -47,15 +44,6 @@
47 44 config TARGET_V38B
48 45 bool "Support v38b"
49 46  
50   -config TARGET_CPCI5200
51   - bool "Support cpci5200"
52   -
53   -config TARGET_MECP5200
54   - bool "Support mecp5200"
55   -
56   -config TARGET_PF5200
57   - bool "Support pf5200"
58   -
59 47 config TARGET_O2D
60 48 bool "Support O2D"
61 49  
62 50  
... ... @@ -99,11 +87,7 @@
99 87 source "board/bc3450/Kconfig"
100 88 source "board/canmb/Kconfig"
101 89 source "board/cm5200/Kconfig"
102   -source "board/esd/cpci5200/Kconfig"
103   -source "board/esd/mecp5200/Kconfig"
104   -source "board/esd/pf5200/Kconfig"
105 90 source "board/galaxy5200/Kconfig"
106   -source "board/icecube/Kconfig"
107 91 source "board/ifm/o2dnt2/Kconfig"
108 92 source "board/inka4x0/Kconfig"
109 93 source "board/intercontrol/digsy_mtc/Kconfig"
arch/powerpc/cpu/mpc5xxx/pci_mpc5200.c
Diff comments   View file @ 37b608a
... ... @@ -33,21 +33,7 @@
33 33 *(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
34 34 eieio();
35 35 udelay(10);
36   -#if (defined CONFIG_PF5200 || defined CONFIG_CPCI5200)
37   - if (dev & 0x00ff0000) {
38   - u32 val;
39   - val = in_le16((volatile u16 *)(CONFIG_PCI_IO_PHYS+2));
40   - udelay(10);
41   - val = val << 16;
42   - val |= in_le16((volatile u16 *)(CONFIG_PCI_IO_PHYS+0));
43   - *value = val;
44   - } else {
45   - *value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS);
46   - }
47   - udelay(10);
48   -#else
49 36 *value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS);
50   -#endif
51 37 eieio();
52 38 *(volatile u32 *)MPC5XXX_PCI_CAR = 0;
53 39 udelay(10);
board/esd/cpci5200/Kconfig
View file @ 37b608a
1   -if TARGET_CPCI5200
2   -
3   -config SYS_BOARD
4   - default "cpci5200"
5   -
6   -config SYS_VENDOR
7   - default "esd"
8   -
9   -config SYS_CONFIG_NAME
10   - default "cpci5200"
11   -
12   -endif
board/esd/cpci5200/MAINTAINERS
View file @ 37b608a
1   -CPCI5200 BOARD
2   -M: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
3   -S: Maintained
4   -F: board/esd/cpci5200/
5   -F: include/configs/cpci5200.h
6   -F: configs/cpci5200_defconfig
board/esd/cpci5200/Makefile
View file @ 37b608a
1   -#
2   -# (C) Copyright 2003-2006
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# SPDX-License-Identifier: GPL-2.0+
6   -#
7   -
8   -# Objects for Xilinx JTAG programming (CPLD)
9   -# CPLD = ../common/xilinx_jtag/lenval.o \
10   -# ../common/xilinx_jtag/micro.o \
11   -# ../common/xilinx_jtag/ports.o
12   -
13   -# obj-y = cpci5200.o flash.o $(CPLD)
14   -obj-y = cpci5200.o strataflash.o
board/esd/cpci5200/cpci5200.c
View file @ 37b608a
1   -/*
2   - * (C) Copyright 2003
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * (C) Copyright 2004
6   - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
7   - *
8   - * SPDX-License-Identifier: GPL-2.0+
9   - */
10   -
11   -/*
12   - * cpci5200.c - main board support/init for the esd cpci5200.
13   - */
14   -
15   -#include <common.h>
16   -#include <mpc5xxx.h>
17   -#include <pci.h>
18   -#include <command.h>
19   -#include <netdev.h>
20   -
21   -#include "mt46v16m16-75.h"
22   -
23   -void init_ata_reset(void);
24   -
25   -static void sdram_start(int hi_addr)
26   -{
27   - long hi_addr_bit = hi_addr ? 0x01000000 : 0;
28   -
29   - /* unlock mode register */
30   - *(vu_long *) MPC5XXX_SDRAM_CTRL =
31   - SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
32   - __asm__ volatile ("sync");
33   -
34   - /* precharge all banks */
35   - *(vu_long *) MPC5XXX_SDRAM_CTRL =
36   - SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
37   - __asm__ volatile ("sync");
38   -
39   - /* set mode register: extended mode */
40   - *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
41   - __asm__ volatile ("sync");
42   -
43   - /* set mode register: reset DLL */
44   - *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
45   - __asm__ volatile ("sync");
46   -
47   - /* precharge all banks */
48   - *(vu_long *) MPC5XXX_SDRAM_CTRL =
49   - SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
50   - __asm__ volatile ("sync");
51   -
52   - /* auto refresh */
53   - *(vu_long *) MPC5XXX_SDRAM_CTRL =
54   - SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
55   - __asm__ volatile ("sync");
56   -
57   - /* set mode register */
58   - *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
59   - __asm__ volatile ("sync");
60   -
61   - /* normal operation */
62   - *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
63   - __asm__ volatile ("sync");
64   -}
65   -
66   -/*
67   - * ATTENTION: Although partially referenced initdram does NOT make real use
68   - * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
69   - * is something else than 0x00000000.
70   - */
71   -
72   -phys_size_t initdram(int board_type)
73   -{
74   - ulong dramsize = 0;
75   - ulong test1, test2;
76   -
77   - /* setup SDRAM chip selects */
78   - *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
79   - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
80   - __asm__ volatile ("sync");
81   -
82   - /* setup config registers */
83   - *(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
84   - *(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
85   - __asm__ volatile ("sync");
86   -
87   - /* set tap delay */
88   - *(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
89   - __asm__ volatile ("sync");
90   -
91   - /* find RAM size using SDRAM CS0 only */
92   - sdram_start(0);
93   - test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
94   - sdram_start(1);
95   - test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
96   -
97   - if (test1 > test2) {
98   - sdram_start(0);
99   - dramsize = test1;
100   - } else {
101   - dramsize = test2;
102   - }
103   -
104   - /* memory smaller than 1MB is impossible */
105   - if (dramsize < (1 << 20)) {
106   - dramsize = 0;
107   - }
108   -
109   - /* set SDRAM CS0 size according to the amount of RAM found */
110   - if (dramsize > 0) {
111   - *(vu_long *) MPC5XXX_SDRAM_CS0CFG =
112   - 0x13 + __builtin_ffs(dramsize >> 20) - 1;
113   - /* let SDRAM CS1 start right after CS0 */
114   - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */
115   - } else {
116   -#if 0
117   - *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
118   - /* let SDRAM CS1 start right after CS0 */
119   - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */
120   -#else
121   - *(vu_long *) MPC5XXX_SDRAM_CS0CFG =
122   - 0x13 + __builtin_ffs(0x08000000 >> 20) - 1;
123   - /* let SDRAM CS1 start right after CS0 */
124   - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e; /* 2G */
125   -#endif
126   - }
127   -
128   -#if 0
129   - /* find RAM size using SDRAM CS1 only */
130   - sdram_start(0);
131   - get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
132   - sdram_start(1);
133   - get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
134   - sdram_start(0);
135   -#endif
136   - /* set SDRAM CS1 size according to the amount of RAM found */
137   -
138   - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
139   -
140   - init_ata_reset();
141   - return (dramsize);
142   -}
143   -
144   -int checkboard(void)
145   -{
146   - puts("Board: esd CPCI5200 (cpci5200)\n");
147   - return 0;
148   -}
149   -
150   -void flash_preinit(void)
151   -{
152   - /*
153   - * Now, when we are in RAM, enable flash write
154   - * access for detection process.
155   - * Note that CS_BOOT cannot be cleared when
156   - * executing in flash.
157   - */
158   - *(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
159   -}
160   -
161   -void flash_afterinit(ulong size)
162   -{
163   - if (size == 0x02000000) {
164   - /* adjust mapping */
165   - *(vu_long *) MPC5XXX_BOOTCS_START =
166   - *(vu_long *) MPC5XXX_CS0_START =
167   - START_REG(CONFIG_SYS_BOOTCS_START | size);
168   - *(vu_long *) MPC5XXX_BOOTCS_STOP =
169   - *(vu_long *) MPC5XXX_CS0_STOP =
170   - STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
171   - }
172   -}
173   -
174   -#ifdef CONFIG_PCI
175   -static struct pci_controller hose;
176   -
177   -extern void pci_mpc5xxx_init(struct pci_controller *);
178   -
179   -void pci_init_board(void) {
180   - pci_mpc5xxx_init(&hose);
181   -}
182   -#endif
183   -
184   -#if defined(CONFIG_CMD_IDE) && defined (CONFIG_IDE_RESET)
185   -
186   -void init_ide_reset(void)
187   -{
188   - debug("init_ide_reset\n");
189   -
190   - /* Configure PSC1_4 as GPIO output for ATA reset */
191   - *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
192   - *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
193   -}
194   -
195   -void ide_set_reset(int idereset)
196   -{
197   - debug("ide_reset(%d)\n", idereset);
198   -
199   - if (idereset) {
200   - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
201   - } else {
202   - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
203   - }
204   -}
205   -#endif
206   -
207   -#define MPC5XXX_SIMPLEIO_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004)
208   -#define MPC5XXX_SIMPLEIO_GPIO_DIR (MPC5XXX_GPIO + 0x000C)
209   -#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x0010)
210   -#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT (MPC5XXX_GPIO + 0x0014)
211   -
212   -#define MPC5XXX_INTERRUPT_GPIO_ENABLE (MPC5XXX_GPIO + 0x0020)
213   -#define MPC5XXX_INTERRUPT_GPIO_DIR (MPC5XXX_GPIO + 0x0028)
214   -#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C)
215   -#define MPC5XXX_INTERRUPT_GPIO_STATUS (MPC5XXX_GPIO + 0x003C)
216   -
217   -#define GPIO_WU6 0x40000000UL
218   -#define GPIO_USB0 0x00010000UL
219   -#define GPIO_USB9 0x08000000UL
220   -#define GPIO_USB9S 0x00080000UL
221   -
222   -void init_ata_reset(void)
223   -{
224   - debug("init_ata_reset\n");
225   -
226   - /* Configure GPIO_WU6 as GPIO output for ATA reset */
227   - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6;
228   - *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6;
229   - *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6;
230   - __asm__ volatile ("sync");
231   -
232   - *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0;
233   - *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0;
234   - *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0;
235   - __asm__ volatile ("sync");
236   -
237   - *(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
238   - *(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9;
239   - __asm__ volatile ("sync");
240   -
241   - if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) {
242   - *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0;
243   - __asm__ volatile ("sync");
244   - }
245   -}
246   -
247   -int board_eth_init(bd_t *bis)
248   -{
249   - return pci_eth_init(bis);
250   -}
251   -
252   -int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
253   -{
254   - unsigned int addr;
255   - unsigned int size;
256   - int i;
257   - volatile unsigned long *ptr;
258   -
259   - addr = simple_strtol(argv[1], NULL, 16);
260   - size = simple_strtol(argv[2], NULL, 16);
261   -
262   - printf("\nWriting at addr %08x, size %08x.\n", addr, size);
263   -
264   - while (1) {
265   - ptr = (volatile unsigned long *)addr;
266   - for (i = 0; i < (size >> 2); i++) {
267   - *ptr++ = i;
268   - }
269   -
270   - /* Abort if ctrl-c was pressed */
271   - if (ctrlc()) {
272   - puts("\nAbort\n");
273   - return 0;
274   - }
275   - putc('.');
276   - }
277   - return 0;
278   -}
279   -
280   -U_BOOT_CMD(writepci, 3, 1, do_writepci,
281   - "Write some data to pcibus",
282   - "<addr> <size>\n"
283   - ""
284   -);
board/esd/cpci5200/mt46v16m16-75.h
View file @ 37b608a
1   -/*
2   - * (C) Copyright 2004
3   - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#define SDRAM_DDR 1 /* is DDR */
9   -
10   -/* Settings for XLB = 132 MHz */
11   -#define SDRAM_MODE 0x018D0000
12   -#define SDRAM_EMODE 0x40090000
13   -#define SDRAM_CONTROL 0x705f0f00
14   -#define SDRAM_CONFIG1 0x73722930
15   -#define SDRAM_CONFIG2 0x47770000
16   -#define SDRAM_TAPDELAY 0x10000000
board/esd/cpci5200/strataflash.c
View file @ 37b608a
1   -/*
2   - * (C) Copyright 2002
3   - * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#include <common.h>
9   -#include <asm/processor.h>
10   -#include <asm/cache.h>
11   -
12   -#undef DEBUG_FLASH
13   -/*
14   - * This file implements a Common Flash Interface (CFI) driver for U-Boot.
15   - * The width of the port and the width of the chips are determined at initialization.
16   - * These widths are used to calculate the address for access CFI data structures.
17   - * It has been tested on an Intel Strataflash implementation.
18   - *
19   - * References
20   - * JEDEC Standard JESD68 - Common Flash Interface (CFI)
21   - * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
22   - * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
23   - * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
24   - *
25   - * TODO
26   - * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available
27   - * Add support for other command sets Use the PRI and ALT to determine command set
28   - * Verify erase and program timeouts.
29   - */
30   -
31   -#define FLASH_CMD_CFI 0x98
32   -#define FLASH_CMD_READ_ID 0x90
33   -#define FLASH_CMD_RESET 0xff
34   -#define FLASH_CMD_BLOCK_ERASE 0x20
35   -#define FLASH_CMD_ERASE_CONFIRM 0xD0
36   -#define FLASH_CMD_WRITE 0x40
37   -#define FLASH_CMD_PROTECT 0x60
38   -#define FLASH_CMD_PROTECT_SET 0x01
39   -#define FLASH_CMD_PROTECT_CLEAR 0xD0
40   -#define FLASH_CMD_CLEAR_STATUS 0x50
41   -#define FLASH_CMD_WRITE_TO_BUFFER 0xE8
42   -#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0
43   -
44   -#define FLASH_STATUS_DONE 0x80
45   -#define FLASH_STATUS_ESS 0x40
46   -#define FLASH_STATUS_ECLBS 0x20
47   -#define FLASH_STATUS_PSLBS 0x10
48   -#define FLASH_STATUS_VPENS 0x08
49   -#define FLASH_STATUS_PSS 0x04
50   -#define FLASH_STATUS_DPS 0x02
51   -#define FLASH_STATUS_R 0x01
52   -#define FLASH_STATUS_PROTECT 0x01
53   -
54   -#define FLASH_OFFSET_CFI 0x55
55   -#define FLASH_OFFSET_CFI_RESP 0x10
56   -#define FLASH_OFFSET_WTOUT 0x1F
57   -#define FLASH_OFFSET_WBTOUT 0x20
58   -#define FLASH_OFFSET_ETOUT 0x21
59   -#define FLASH_OFFSET_CETOUT 0x22
60   -#define FLASH_OFFSET_WMAX_TOUT 0x23
61   -#define FLASH_OFFSET_WBMAX_TOUT 0x24
62   -#define FLASH_OFFSET_EMAX_TOUT 0x25
63   -#define FLASH_OFFSET_CEMAX_TOUT 0x26
64   -#define FLASH_OFFSET_SIZE 0x27
65   -#define FLASH_OFFSET_INTERFACE 0x28
66   -#define FLASH_OFFSET_BUFFER_SIZE 0x2A
67   -#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C
68   -#define FLASH_OFFSET_ERASE_REGIONS 0x2D
69   -#define FLASH_OFFSET_PROTECT 0x02
70   -#define FLASH_OFFSET_USER_PROTECTION 0x85
71   -#define FLASH_OFFSET_INTEL_PROTECTION 0x81
72   -
73   -#define FLASH_MAN_CFI 0x01000000
74   -
75   -typedef union {
76   - unsigned char c;
77   - unsigned short w;
78   - unsigned long l;
79   -} cfiword_t;
80   -
81   -typedef union {
82   - unsigned char *cp;
83   - unsigned short *wp;
84   - unsigned long *lp;
85   -} cfiptr_t;
86   -
87   -#define NUM_ERASE_REGIONS 4
88   -
89   -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
90   -
91   -/*-----------------------------------------------------------------------
92   - * Functions
93   - */
94   -
95   -static void flash_add_byte(flash_info_t * info, cfiword_t * cword, uchar c);
96   -static void flash_make_cmd(flash_info_t * info, uchar cmd, void *cmdbuf);
97   -static void flash_write_cmd(flash_info_t * info, int sect, uchar offset,
98   - uchar cmd);
99   -static int flash_isequal(flash_info_t * info, int sect, uchar offset,
100   - uchar cmd);
101   -static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd);
102   -static int flash_detect_cfi(flash_info_t * info);
103   -static ulong flash_get_size(ulong base, int banknum);
104   -static int flash_write_cfiword(flash_info_t * info, ulong dest,
105   - cfiword_t cword);
106   -static int flash_full_status_check(flash_info_t * info, ulong sector,
107   - ulong tout, char *prompt);
108   -#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
109   -static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp,
110   - int len);
111   -#endif
112   -/*-----------------------------------------------------------------------
113   - * create an address based on the offset and the port width
114   - */
115   -inline uchar *flash_make_addr(flash_info_t * info, int sect, int offset)
116   -{
117   - return ((uchar *) (info->start[sect] + (offset * info->portwidth)));
118   -}
119   -
120   -/*-----------------------------------------------------------------------
121   - * read a character at a port width address
122   - */
123   -inline uchar flash_read_uchar(flash_info_t * info, uchar offset)
124   -{
125   - uchar *cp;
126   - cp = flash_make_addr(info, 0, offset);
127   - return (cp[info->portwidth - 1]);
128   -}
129   -
130   -/*-----------------------------------------------------------------------
131   - * read a short word by swapping for ppc format.
132   - */
133   -ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset)
134   -{
135   - uchar *addr;
136   -
137   - addr = flash_make_addr(info, sect, offset);
138   - return ((addr[(2 * info->portwidth) - 1] << 8) |
139   - addr[info->portwidth - 1]);
140   -
141   -}
142   -
143   -/*-----------------------------------------------------------------------
144   - * read a long word by picking the least significant byte of each maiximum
145   - * port size word. Swap for ppc format.
146   - */
147   -ulong flash_read_long(flash_info_t * info, int sect, uchar offset)
148   -{
149   - uchar *addr;
150   -
151   - addr = flash_make_addr(info, sect, offset);
152   - return ((addr[(2 * info->portwidth) - 1] << 24) |
153   - (addr[(info->portwidth) - 1] << 16) |
154   - (addr[(4 * info->portwidth) - 1] << 8) |
155   - addr[(3 * info->portwidth) - 1]);
156   -
157   -}
158   -
159   -/*-----------------------------------------------------------------------
160   - */
161   -unsigned long flash_init(void)
162   -{
163   - unsigned long size;
164   - int i;
165   - unsigned long address;
166   -
167   - /* The flash is positioned back to back, with the demultiplexing of the chip
168   - * based on the A24 address line.
169   - *
170   - */
171   -
172   - address = CONFIG_SYS_FLASH_BASE;
173   - size = 0;
174   -
175   - /* Init: no FLASHes known */
176   - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
177   - flash_info[i].flash_id = FLASH_UNKNOWN;
178   - size += flash_info[i].size = flash_get_size(address, i);
179   - address += CONFIG_SYS_FLASH_INCREMENT;
180   - if (flash_info[i].flash_id == FLASH_UNKNOWN) {
181   - printf
182   - ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
183   - i, flash_info[0].size, flash_info[i].size << 20);
184   - }
185   - }
186   -
187   -#if 0 /* test-only */
188   - /* Monitor protection ON by default */
189   -#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
190   - for (i = 0;
191   - flash_info[0].start[i] < CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1;
192   - i++)
193   - (void)flash_real_protect(&flash_info[0], i, 1);
194   -#endif
195   -#endif
196   -
197   - return (size);
198   -}
199   -
200   -/*-----------------------------------------------------------------------
201   - */
202   -int flash_erase(flash_info_t * info, int s_first, int s_last)
203   -{
204   - int rcode = 0;
205   - int prot;
206   - int sect;
207   -
208   - if (info->flash_id != FLASH_MAN_CFI) {
209   - printf("Can't erase unknown flash type - aborted\n");
210   - return 1;
211   - }
212   - if ((s_first < 0) || (s_first > s_last)) {
213   - printf("- no sectors to erase\n");
214   - return 1;
215   - }
216   -
217   - prot = 0;
218   - for (sect = s_first; sect <= s_last; ++sect) {
219   - if (info->protect[sect]) {
220   - prot++;
221   - }
222   - }
223   - if (prot) {
224   - printf("- Warning: %d protected sectors will not be erased!\n",
225   - prot);
226   - } else {
227   - printf("\n");
228   - }
229   -
230   - for (sect = s_first; sect <= s_last; sect++) {
231   - if (info->protect[sect] == 0) { /* not protected */
232   - flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS);
233   - flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE);
234   - flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
235   -
236   - if (flash_full_status_check
237   - (info, sect, info->erase_blk_tout, "erase")) {
238   - rcode = 1;
239   - } else
240   - printf(".");
241   - }
242   - }
243   - printf(" done\n");
244   - return rcode;
245   -}
246   -
247   -/*-----------------------------------------------------------------------
248   - */
249   -void flash_print_info(flash_info_t * info)
250   -{
251   - int i;
252   -
253   - if (info->flash_id != FLASH_MAN_CFI) {
254   - printf("missing or unknown FLASH type\n");
255   - return;
256   - }
257   -
258   - printf("CFI conformant FLASH (%d x %d)",
259   - (info->portwidth << 3), (info->chipwidth << 3));
260   - printf(" Size: %ld MB in %d Sectors\n",
261   - info->size >> 20, info->sector_count);
262   - printf
263   - (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
264   - info->erase_blk_tout, info->write_tout, info->buffer_write_tout,
265   - info->buffer_size);
266   -
267   - printf(" Sector Start Addresses:");
268   - for (i = 0; i < info->sector_count; ++i) {
269   - if ((i % 5) == 0)
270   - printf("\n");
271   - printf(" %08lX%5s",
272   - info->start[i], info->protect[i] ? " (RO)" : " ");
273   - }
274   - printf("\n");
275   - return;
276   -}
277   -
278   -/*-----------------------------------------------------------------------
279   - * Copy memory to flash, returns:
280   - * 0 - OK
281   - * 1 - write timeout
282   - * 2 - Flash not erased
283   - */
284   -int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
285   -{
286   - ulong wp;
287   - ulong cp;
288   - int aln;
289   - cfiword_t cword;
290   - int i, rc;
291   -
292   - /* get lower aligned address */
293   - wp = (addr & ~(info->portwidth - 1));
294   -
295   - /* handle unaligned start */
296   - if ((aln = addr - wp) != 0) {
297   - cword.l = 0;
298   - cp = wp;
299   - for (i = 0; i < aln; ++i, ++cp)
300   - flash_add_byte(info, &cword, (*(uchar *) cp));
301   -
302   - for (; (i < info->portwidth) && (cnt > 0); i++) {
303   - flash_add_byte(info, &cword, *src++);
304   - cnt--;
305   - cp++;
306   - }
307   - for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
308   - flash_add_byte(info, &cword, (*(uchar *) cp));
309   - if ((rc = flash_write_cfiword(info, wp, cword)) != 0)
310   - return rc;
311   - wp = cp;
312   - }
313   -#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
314   - while (cnt >= info->portwidth) {
315   - i = info->buffer_size > cnt ? cnt : info->buffer_size;
316   - if ((rc = flash_write_cfibuffer(info, wp, src, i)) != ERR_OK)
317   - return rc;
318   - wp += i;
319   - src += i;
320   - cnt -= i;
321   - }
322   -#else
323   - /* handle the aligned part */
324   - while (cnt >= info->portwidth) {
325   - cword.l = 0;
326   - for (i = 0; i < info->portwidth; i++) {
327   - flash_add_byte(info, &cword, *src++);
328   - }
329   - if ((rc = flash_write_cfiword(info, wp, cword)) != 0)
330   - return rc;
331   - wp += info->portwidth;
332   - cnt -= info->portwidth;
333   - }
334   -#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
335   - if (cnt == 0) {
336   - return (0);
337   - }
338   -
339   - /*
340   - * handle unaligned tail bytes
341   - */
342   - cword.l = 0;
343   - for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i, ++cp) {
344   - flash_add_byte(info, &cword, *src++);
345   - --cnt;
346   - }
347   - for (; i < info->portwidth; ++i, ++cp) {
348   - flash_add_byte(info, &cword, (*(uchar *) cp));
349   - }
350   -
351   - return flash_write_cfiword(info, wp, cword);
352   -}
353   -
354   -/*-----------------------------------------------------------------------
355   - */
356   -int flash_real_protect(flash_info_t * info, long sector, int prot)
357   -{
358   - int retcode = 0;
359   -
360   - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
361   - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
362   - if (prot)
363   - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET);
364   - else
365   - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
366   -
367   - if ((retcode =
368   - flash_full_status_check(info, sector, info->erase_blk_tout,
369   - prot ? "protect" : "unprotect")) == 0) {
370   -
371   - info->protect[sector] = prot;
372   - /* Intel's unprotect unprotects all locking */
373   - if (prot == 0) {
374   - int i;
375   - for (i = 0; i < info->sector_count; i++) {
376   - if (info->protect[i])
377   - flash_real_protect(info, i, 1);
378   - }
379   - }
380   - }
381   -
382   - return retcode;
383   -}
384   -
385   -/*-----------------------------------------------------------------------
386   - * wait for XSR.7 to be set. Time out with an error if it does not.
387   - * This routine does not set the flash to read-array mode.
388   - */
389   -static int flash_status_check(flash_info_t * info, ulong sector, ulong tout,
390   - char *prompt)
391   -{
392   - ulong start;
393   -
394   - /* Wait for command completion */
395   - start = get_timer(0);
396   - while (!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
397   - if (get_timer(start) > info->erase_blk_tout) {
398   - printf("Flash %s timeout at address %lx\n", prompt,
399   - info->start[sector]);
400   - flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
401   - return ERR_TIMOUT;
402   - }
403   - }
404   - return ERR_OK;
405   -}
406   -
407   -/*-----------------------------------------------------------------------
408   - * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
409   - * This routine sets the flash to read-array mode.
410   - */
411   -static int flash_full_status_check(flash_info_t * info, ulong sector,
412   - ulong tout, char *prompt)
413   -{
414   - int retcode;
415   - retcode = flash_status_check(info, sector, tout, prompt);
416   - if ((retcode == ERR_OK)
417   - && !flash_isequal(info, sector, 0, FLASH_STATUS_DONE)) {
418   - retcode = ERR_INVAL;
419   - printf("Flash %s error at address %lx\n", prompt,
420   - info->start[sector]);
421   - if (flash_isset
422   - (info, sector, 0,
423   - FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) {
424   - printf("Command Sequence Error.\n");
425   - } else if (flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)) {
426   - printf("Block Erase Error.\n");
427   - retcode = ERR_NOT_ERASED;
428   - } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) {
429   - printf("Locking Error\n");
430   - }
431   - if (flash_isset(info, sector, 0, FLASH_STATUS_DPS)) {
432   - printf("Block locked.\n");
433   - retcode = ERR_PROTECTED;
434   - }
435   - if (flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
436   - printf("Vpp Low Error.\n");
437   - }
438   - flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
439   - return retcode;
440   -}
441   -
442   -/*-----------------------------------------------------------------------
443   - */
444   -static void flash_add_byte(flash_info_t * info, cfiword_t * cword, uchar c)
445   -{
446   - switch (info->portwidth) {
447   - case FLASH_CFI_8BIT:
448   - cword->c = c;
449   - break;
450   - case FLASH_CFI_16BIT:
451   - cword->w = (cword->w << 8) | c;
452   - break;
453   - case FLASH_CFI_32BIT:
454   - cword->l = (cword->l << 8) | c;
455   - }
456   -}
457   -
458   -/*-----------------------------------------------------------------------
459   - * make a proper sized command based on the port and chip widths
460   - */
461   -static void flash_make_cmd(flash_info_t * info, uchar cmd, void *cmdbuf)
462   -{
463   - int i;
464   - uchar *cp = (uchar *) cmdbuf;
465   - for (i = 0; i < info->portwidth; i++)
466   - *cp++ = ((i + 1) % info->chipwidth) ? '\0' : cmd;
467   -}
468   -
469   -/*
470   - * Write a proper sized command to the correct address
471   - */
472   -static void flash_write_cmd(flash_info_t * info, int sect, uchar offset,
473   - uchar cmd)
474   -{
475   -
476   - volatile cfiptr_t addr;
477   - cfiword_t cword;
478   - addr.cp = flash_make_addr(info, sect, offset);
479   - flash_make_cmd(info, cmd, &cword);
480   - switch (info->portwidth) {
481   - case FLASH_CFI_8BIT:
482   - *addr.cp = cword.c;
483   - break;
484   - case FLASH_CFI_16BIT:
485   - *addr.wp = cword.w;
486   - break;
487   - case FLASH_CFI_32BIT:
488   - *addr.lp = cword.l;
489   - break;
490   - }
491   -}
492   -
493   -/*-----------------------------------------------------------------------
494   - */
495   -static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd)
496   -{
497   - cfiptr_t cptr;
498   - cfiword_t cword;
499   - int retval;
500   - cptr.cp = flash_make_addr(info, sect, offset);
501   - flash_make_cmd(info, cmd, &cword);
502   - switch (info->portwidth) {
503   - case FLASH_CFI_8BIT:
504   - retval = (cptr.cp[0] == cword.c);
505   - break;
506   - case FLASH_CFI_16BIT:
507   - retval = (cptr.wp[0] == cword.w);
508   - break;
509   - case FLASH_CFI_32BIT:
510   - retval = (cptr.lp[0] == cword.l);
511   - break;
512   - default:
513   - retval = 0;
514   - break;
515   - }
516   - return retval;
517   -}
518   -
519   -/*-----------------------------------------------------------------------
520   - */
521   -static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd)
522   -{
523   - cfiptr_t cptr;
524   - cfiword_t cword;
525   - int retval;
526   - cptr.cp = flash_make_addr(info, sect, offset);
527   - flash_make_cmd(info, cmd, &cword);
528   - switch (info->portwidth) {
529   - case FLASH_CFI_8BIT:
530   - retval = ((cptr.cp[0] & cword.c) == cword.c);
531   - break;
532   - case FLASH_CFI_16BIT:
533   - retval = ((cptr.wp[0] & cword.w) == cword.w);
534   - break;
535   - case FLASH_CFI_32BIT:
536   - retval = ((cptr.lp[0] & cword.l) == cword.l);
537   - break;
538   - default:
539   - retval = 0;
540   - break;
541   - }
542   - return retval;
543   -}
544   -
545   -/*-----------------------------------------------------------------------
546   - * detect if flash is compatible with the Common Flash Interface (CFI)
547   - * http://www.jedec.org/download/search/jesd68.pdf
548   - *
549   - */
550   -static int flash_detect_cfi(flash_info_t * info)
551   -{
552   -
553   - for (info->portwidth = FLASH_CFI_8BIT;
554   - info->portwidth <= FLASH_CFI_32BIT; info->portwidth <<= 1) {
555   - for (info->chipwidth = FLASH_CFI_BY8;
556   - info->chipwidth <= info->portwidth;
557   - info->chipwidth <<= 1) {
558   - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
559   - flash_write_cmd(info, 0, FLASH_OFFSET_CFI,
560   - FLASH_CMD_CFI);
561   - if (flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP, 'Q')
562   - && flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1,
563   - 'R')
564   - && flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2,
565   - 'Y'))
566   - return 1;
567   - }
568   - }
569   - return 0;
570   -}
571   -
572   -/*
573   - * The following code cannot be run from FLASH!
574   - *
575   - */
576   -static ulong flash_get_size(ulong base, int banknum)
577   -{
578   - flash_info_t *info = &flash_info[banknum];
579   - int i, j;
580   - int sect_cnt;
581   - unsigned long sector;
582   - unsigned long tmp;
583   - int size_ratio = 0;
584   - uchar num_erase_regions;
585   - int erase_region_size;
586   - int erase_region_count;
587   -
588   - info->start[0] = base;
589   -#if 0
590   - invalidate_dcache_range(base, base + 0x400);
591   -#endif
592   - if (flash_detect_cfi(info)) {
593   -
594   - size_ratio = info->portwidth / info->chipwidth;
595   - num_erase_regions =
596   - flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
597   -
598   - sect_cnt = 0;
599   - sector = base;
600   - for (i = 0; i < num_erase_regions; i++) {
601   - if (i > NUM_ERASE_REGIONS) {
602   - printf("%d erase regions found, only %d used\n",
603   - num_erase_regions, NUM_ERASE_REGIONS);
604   - break;
605   - }
606   - tmp =
607   - flash_read_long(info, 0,
608   - FLASH_OFFSET_ERASE_REGIONS);
609   - erase_region_size =
610   - (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128;
611   - tmp >>= 16;
612   - erase_region_count = (tmp & 0xffff) + 1;
613   - for (j = 0; j < erase_region_count; j++) {
614   - info->start[sect_cnt] = sector;
615   - sector += (erase_region_size * size_ratio);
616   - info->protect[sect_cnt] =
617   - flash_isset(info, sect_cnt,
618   - FLASH_OFFSET_PROTECT,
619   - FLASH_STATUS_PROTECT);
620   - sect_cnt++;
621   - }
622   - }
623   -
624   - info->sector_count = sect_cnt;
625   - /* multiply the size by the number of chips */
626   - info->size =
627   - (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) *
628   - size_ratio;
629   - info->buffer_size =
630   - (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE));
631   - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT);
632   - info->erase_blk_tout =
633   - (tmp *
634   - (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT)));
635   - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT);
636   - info->buffer_write_tout =
637   - (tmp *
638   - (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT)));
639   - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT);
640   - info->write_tout =
641   - (tmp *
642   - (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT))) /
643   - 1000;
644   - info->flash_id = FLASH_MAN_CFI;
645   - }
646   -
647   - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
648   -#ifdef DEBUG_FLASH
649   - printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */
650   -#endif
651   -#ifdef DEBUG_FLASH
652   - printf("found %d erase regions\n", num_erase_regions);
653   -#endif
654   -#ifdef DEBUG_FLASH
655   - printf("size=%08x sectors=%08x \n", info->size, info->sector_count);
656   -#endif
657   - return (info->size);
658   -}
659   -
660   -/*-----------------------------------------------------------------------
661   - */
662   -static int flash_write_cfiword(flash_info_t * info, ulong dest, cfiword_t cword)
663   -{
664   -
665   - cfiptr_t cptr;
666   - int flag;
667   -
668   - cptr.cp = (uchar *)dest;
669   -
670   - /* Check if Flash is (sufficiently) erased */
671   - switch (info->portwidth) {
672   - case FLASH_CFI_8BIT:
673   - flag = ((cptr.cp[0] & cword.c) == cword.c);
674   - break;
675   - case FLASH_CFI_16BIT:
676   - flag = ((cptr.wp[0] & cword.w) == cword.w);
677   - break;
678   - case FLASH_CFI_32BIT:
679   - flag = ((cptr.lp[0] & cword.l) == cword.l);
680   - break;
681   - default:
682   - return 2;
683   - }
684   - if (!flag)
685   - return 2;
686   -
687   - /* Disable interrupts which might cause a timeout here */
688   - flag = disable_interrupts();
689   -
690   - flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
691   - flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
692   -
693   - switch (info->portwidth) {
694   - case FLASH_CFI_8BIT:
695   - cptr.cp[0] = cword.c;
696   - break;
697   - case FLASH_CFI_16BIT:
698   - cptr.wp[0] = cword.w;
699   - break;
700   - case FLASH_CFI_32BIT:
701   - cptr.lp[0] = cword.l;
702   - break;
703   - }
704   -
705   - /* re-enable interrupts if necessary */
706   - if (flag)
707   - enable_interrupts();
708   -
709   - return flash_full_status_check(info, 0, info->write_tout, "write");
710   -}
711   -
712   -#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
713   -
714   -/* loop through the sectors from the highest address
715   - * when the passed address is greater or equal to the sector address
716   - * we have a match
717   - */
718   -static int find_sector(flash_info_t * info, ulong addr)
719   -{
720   - int sector;
721   - for (sector = info->sector_count - 1; sector >= 0; sector--) {
722   - if (addr >= info->start[sector])
723   - break;
724   - }
725   - return sector;
726   -}
727   -
728   -static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp,
729   - int len)
730   -{
731   -
732   - int sector;
733   - int cnt;
734   - int retcode;
735   - volatile cfiptr_t src;
736   - volatile cfiptr_t dst;
737   -
738   - src.cp = cp;
739   - dst.cp = (uchar *) dest;
740   - sector = find_sector(info, dest);
741   - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
742   - flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
743   - if ((retcode = flash_status_check(info, sector, info->buffer_write_tout,
744   - "write to buffer")) == ERR_OK) {
745   - switch (info->portwidth) {
746   - case FLASH_CFI_8BIT:
747   - cnt = len;
748   - break;
749   - case FLASH_CFI_16BIT:
750   - cnt = len >> 1;
751   - break;
752   - case FLASH_CFI_32BIT:
753   - cnt = len >> 2;
754   - break;
755   - default:
756   - return ERR_INVAL;
757   - break;
758   - }
759   - flash_write_cmd(info, sector, 0, (uchar) cnt - 1);
760   - while (cnt-- > 0) {
761   - switch (info->portwidth) {
762   - case FLASH_CFI_8BIT:
763   - *dst.cp++ = *src.cp++;
764   - break;
765   - case FLASH_CFI_16BIT:
766   - *dst.wp++ = *src.wp++;
767   - break;
768   - case FLASH_CFI_32BIT:
769   - *dst.lp++ = *src.lp++;
770   - break;
771   - default:
772   - return ERR_INVAL;
773   - break;
774   - }
775   - }
776   - flash_write_cmd(info, sector, 0,
777   - FLASH_CMD_WRITE_BUFFER_CONFIRM);
778   - retcode =
779   - flash_full_status_check(info, sector,
780   - info->buffer_write_tout,
781   - "buffer write");
782   - }
783   - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
784   - return retcode;
785   -}
786   -#endif /* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */
board/esd/mecp5200/Kconfig
View file @ 37b608a
1   -if TARGET_MECP5200
2   -
3   -config SYS_BOARD
4   - default "mecp5200"
5   -
6   -config SYS_VENDOR
7   - default "esd"
8   -
9   -config SYS_CONFIG_NAME
10   - default "mecp5200"
11   -
12   -endif
board/esd/mecp5200/MAINTAINERS
View file @ 37b608a
1   -MECP5200 BOARD
2   -M: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
3   -S: Maintained
4   -F: board/esd/mecp5200/
5   -F: include/configs/mecp5200.h
6   -F: configs/mecp5200_defconfig
board/esd/mecp5200/Makefile
View file @ 37b608a
1   -#
2   -# (C) Copyright 2003-2006
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# SPDX-License-Identifier: GPL-2.0+
6   -#
7   -
8   -obj-y = mecp5200.o
board/esd/mecp5200/mecp5200.c
View file @ 37b608a
1   -/*
2   - * (C) Copyright 2003
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * (C) Copyright 2004
6   - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
7   - *
8   - * SPDX-License-Identifier: GPL-2.0+
9   - */
10   -
11   -/*
12   - * pf5200.c - main board support/init for the esd pf5200.
13   - */
14   -
15   -#include <common.h>
16   -#include <mpc5xxx.h>
17   -#include <pci.h>
18   -#include <command.h>
19   -#include <netdev.h>
20   -
21   -#include "mt46v16m16-75.h"
22   -
23   -void init_power_switch(void);
24   -
25   -static void sdram_start(int hi_addr)
26   -{
27   - long hi_addr_bit = hi_addr ? 0x01000000 : 0;
28   -
29   - /* unlock mode register */
30   - *(vu_long *) MPC5XXX_SDRAM_CTRL =
31   - SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
32   - __asm__ volatile ("sync");
33   -
34   - /* precharge all banks */
35   - *(vu_long *) MPC5XXX_SDRAM_CTRL =
36   - SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
37   - __asm__ volatile ("sync");
38   -
39   - /* set mode register: extended mode */
40   - *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
41   - __asm__ volatile ("sync");
42   -
43   - /* set mode register: reset DLL */
44   - *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
45   - __asm__ volatile ("sync");
46   -
47   - /* precharge all banks */
48   - *(vu_long *) MPC5XXX_SDRAM_CTRL =
49   - SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
50   - __asm__ volatile ("sync");
51   -
52   - /* auto refresh */
53   - *(vu_long *) MPC5XXX_SDRAM_CTRL =
54   - SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
55   - __asm__ volatile ("sync");
56   -
57   - /* set mode register */
58   - *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
59   - __asm__ volatile ("sync");
60   -
61   - /* normal operation */
62   - *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
63   - __asm__ volatile ("sync");
64   -}
65   -
66   -/*
67   - * ATTENTION: Although partially referenced initdram does NOT make real use
68   - * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
69   - * is something else than 0x00000000.
70   - */
71   -
72   -phys_size_t initdram(int board_type)
73   -{
74   - ulong dramsize = 0;
75   - ulong test1, test2;
76   -
77   - /* setup SDRAM chip selects */
78   - *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
79   - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
80   - __asm__ volatile ("sync");
81   -
82   - /* setup config registers */
83   - *(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
84   - *(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
85   - __asm__ volatile ("sync");
86   -
87   - /* set tap delay */
88   - *(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
89   - __asm__ volatile ("sync");
90   -
91   - /* find RAM size using SDRAM CS0 only */
92   - sdram_start(0);
93   - test1 = get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x80000000);
94   - sdram_start(1);
95   - test2 = get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x80000000);
96   -
97   - if (test1 > test2) {
98   - sdram_start(0);
99   - dramsize = test1;
100   - } else {
101   - dramsize = test2;
102   - }
103   -
104   - /* memory smaller than 1MB is impossible */
105   - if (dramsize < (1 << 20))
106   - dramsize = 0;
107   -
108   - /* set SDRAM CS0 size according to the amount of RAM found */
109   - if (dramsize > 0) {
110   - *(vu_long *) MPC5XXX_SDRAM_CS0CFG =
111   - 0x13 + __builtin_ffs(dramsize >> 20) - 1;
112   - /* let SDRAM CS1 start right after CS0 */
113   - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */
114   - } else {
115   -#if 0
116   - *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
117   - /* let SDRAM CS1 start right after CS0 */
118   - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */
119   -#else
120   - *(vu_long *) MPC5XXX_SDRAM_CS0CFG =
121   - 0x13 + __builtin_ffs(0x08000000 >> 20) - 1;
122   - /* let SDRAM CS1 start right after CS0 */
123   - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e; /* 2G */
124   -#endif
125   - }
126   -
127   -#if 0
128   - /* find RAM size using SDRAM CS1 only */
129   - sdram_start(0);
130   - get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
131   - sdram_start(1);
132   - get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
133   - sdram_start(0);
134   -#endif
135   - /* set SDRAM CS1 size according to the amount of RAM found */
136   -
137   - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
138   -
139   - init_power_switch();
140   - return (dramsize);
141   -}
142   -
143   -int checkboard(void)
144   -{
145   - puts("Board: esd CPX CPU5200 (mecp5200)\n");
146   - return 0;
147   -}
148   -
149   -void flash_preinit(void)
150   -{
151   - /*
152   - * Now, when we are in RAM, enable flash write
153   - * access for detection process.
154   - * Note that CS_BOOT cannot be cleared when
155   - * executing in flash.
156   - */
157   - *(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
158   -}
159   -
160   -void flash_afterinit(ulong size)
161   -{
162   - if (size == CONFIG_SYS_FLASH_SIZE) {
163   - /* adjust mapping */
164   - *(vu_long *) MPC5XXX_BOOTCS_START =
165   - *(vu_long *) MPC5XXX_CS0_START =
166   - START_REG(CONFIG_SYS_BOOTCS_START | size);
167   - *(vu_long *) MPC5XXX_BOOTCS_STOP =
168   - *(vu_long *) MPC5XXX_CS0_STOP =
169   - STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
170   - }
171   -}
172   -
173   -#ifdef CONFIG_PCI
174   -static struct pci_controller hose;
175   -
176   -extern void pci_mpc5xxx_init(struct pci_controller *);
177   -
178   -void pci_init_board(void)
179   -{
180   - pci_mpc5xxx_init(&hose);
181   -}
182   -#endif
183   -
184   -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
185   -
186   -#define GPIO_PSC1_4 0x01000000UL
187   -
188   -void init_ide_reset(void)
189   -{
190   - debug("init_ide_reset\n");
191   -
192   - /* Configure PSC1_4 as GPIO output for ATA reset */
193   - *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
194   - *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
195   -}
196   -
197   -void ide_set_reset(int idereset)
198   -{
199   - debug("ide_reset(%d)\n", idereset);
200   -
201   - if (idereset)
202   - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
203   - else
204   - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
205   -}
206   -#endif
207   -
208   -#define MPC5XXX_SIMPLEIO_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004)
209   -#define MPC5XXX_SIMPLEIO_GPIO_DIR (MPC5XXX_GPIO + 0x000C)
210   -#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x0010)
211   -#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT (MPC5XXX_GPIO + 0x0014)
212   -
213   -#define MPC5XXX_INTERRUPT_GPIO_ENABLE (MPC5XXX_GPIO + 0x0020)
214   -#define MPC5XXX_INTERRUPT_GPIO_DIR (MPC5XXX_GPIO + 0x0028)
215   -#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C)
216   -#define MPC5XXX_INTERRUPT_GPIO_STATUS (MPC5XXX_GPIO + 0x003C)
217   -
218   -#define GPIO_WU6 0x40000000UL
219   -#define GPIO_USB0 0x00010000UL
220   -#define GPIO_USB9 0x08000000UL
221   -#define GPIO_USB9S 0x00080000UL
222   -
223   -void init_power_switch(void)
224   -{
225   - debug("init_power_switch\n");
226   -
227   - /* Configure GPIO_WU6 as GPIO output for ATA reset */
228   - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6;
229   - *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6;
230   - *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6;
231   - __asm__ volatile ("sync");
232   -
233   - *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0;
234   - *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0;
235   - *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0;
236   - __asm__ volatile ("sync");
237   -
238   - *(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
239   - *(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9;
240   - __asm__ volatile ("sync");
241   -
242   - if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) {
243   - *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0;
244   - __asm__ volatile ("sync");
245   - }
246   -}
247   -
248   -int board_eth_init(bd_t *bis)
249   -{
250   - return pci_eth_init(bis);
251   -}
board/esd/mecp5200/mt46v16m16-75.h
View file @ 37b608a
1   -/*
2   - * (C) Copyright 2004
3   - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#define SDRAM_DDR 1 /* is DDR */
9   -
10   -/* Settings for XLB = 132 MHz */
11   -#define SDRAM_MODE 0x018D0000
12   -#define SDRAM_EMODE 0x40090000
13   -#define SDRAM_CONTROL 0x705f0f00
14   -#define SDRAM_CONFIG1 0x73722930
15   -#define SDRAM_CONFIG2 0x47770000
16   -#define SDRAM_TAPDELAY 0x10000000
board/esd/pf5200/Kconfig
View file @ 37b608a
1   -if TARGET_PF5200
2   -
3   -config SYS_BOARD
4   - default "pf5200"
5   -
6   -config SYS_VENDOR
7   - default "esd"
8   -
9   -config SYS_CONFIG_NAME
10   - default "pf5200"
11   -
12   -endif
board/esd/pf5200/MAINTAINERS
View file @ 37b608a
1   -PF5200 BOARD
2   -M: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
3   -S: Maintained
4   -F: board/esd/pf5200/
5   -F: include/configs/pf5200.h
6   -F: configs/pf5200_defconfig
board/esd/pf5200/Makefile
View file @ 37b608a
1   -#
2   -# (C) Copyright 2003-2006
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# SPDX-License-Identifier: GPL-2.0+
6   -#
7   -
8   -# Objects for Xilinx JTAG programming (CPLD)
9   -# CPLD = ../common/xilinx_jtag/lenval.o \
10   -# ../common/xilinx_jtag/micro.o \
11   -# ../common/xilinx_jtag/ports.o
12   -
13   -# obj-y = pf5200.o flash.o $(CPLD)
14   -obj-y = pf5200.o flash.o
board/esd/pf5200/flash.c
View file @ 37b608a
1   -/*
2   - * (C) Copyright 2003
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#include <common.h>
9   -
10   -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
11   -
12   -typedef unsigned short FLASH_PORT_WIDTH;
13   -typedef volatile unsigned short FLASH_PORT_WIDTHV;
14   -
15   -#define FLASH_ID_MASK 0x00FF
16   -
17   -#define FPW FLASH_PORT_WIDTH
18   -#define FPWV FLASH_PORT_WIDTHV
19   -
20   -#define FLASH_CYCLE1 0x0555
21   -#define FLASH_CYCLE2 0x0aaa
22   -#define FLASH_ID1 0x00
23   -#define FLASH_ID2 0x01
24   -#define FLASH_ID3 0x0E
25   -#define FLASH_ID4 0x0F
26   -
27   -/*-----------------------------------------------------------------------
28   - * Functions
29   - */
30   -static ulong flash_get_size(FPWV * addr, flash_info_t * info);
31   -static void flash_reset(flash_info_t * info);
32   -static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data);
33   -static flash_info_t *flash_get_info(ulong base);
34   -
35   -/*-----------------------------------------------------------------------
36   - * flash_init()
37   - *
38   - * sets up flash_info and returns size of FLASH (bytes)
39   - */
40   -unsigned long flash_init(void)
41   -{
42   - unsigned long size = 0;
43   - int i = 0;
44   - extern void flash_preinit(void);
45   - extern void flash_afterinit(uint, ulong, ulong);
46   -
47   - ulong flashbase = CONFIG_SYS_FLASH_BASE;
48   -
49   - flash_preinit();
50   -
51   - /* There is only ONE FLASH device */
52   - memset(&flash_info[i], 0, sizeof(flash_info_t));
53   - flash_info[i].size = flash_get_size((FPW *) flashbase, &flash_info[i]);
54   - size += flash_info[i].size;
55   -
56   -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
57   - /* monitor protection ON by default */
58   - flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
59   - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
60   - flash_get_info(CONFIG_SYS_MONITOR_BASE));
61   -#endif
62   -
63   -#ifdef CONFIG_ENV_IS_IN_FLASH
64   - /* ENV protection ON by default */
65   - flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
66   - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
67   - flash_get_info(CONFIG_ENV_ADDR));
68   -#endif
69   -
70   - flash_afterinit(i, flash_info[i].start[0], flash_info[i].size);
71   - return size ? size : 1;
72   -}
73   -
74   -/*-----------------------------------------------------------------------
75   - */
76   -static void flash_reset(flash_info_t * info) {
77   - FPWV *base = (FPWV *) (info->start[0]);
78   -
79   - /* Put FLASH back in read mode */
80   - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
81   - *base = (FPW) 0x00FF00FF; /* Intel Read Mode */
82   - } else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) {
83   - *base = (FPW) 0x00F000F0; /* AMD Read Mode */
84   - }
85   -}
86   -
87   -/*-----------------------------------------------------------------------
88   - */
89   -
90   -static flash_info_t *flash_get_info(ulong base) {
91   - int i;
92   - flash_info_t *info;
93   -
94   - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
95   - info = &flash_info[i];
96   - if ((info->size) && (info->start[0] <= base)
97   - && (base <= info->start[0] + info->size - 1)) {
98   - break;
99   - }
100   - }
101   - return (i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info);
102   -}
103   -
104   -/*-----------------------------------------------------------------------
105   - */
106   -
107   -void flash_print_info(flash_info_t * info) {
108   - int i;
109   - char *fmt;
110   -
111   - if (info->flash_id == FLASH_UNKNOWN) {
112   - printf("missing or unknown FLASH type\n");
113   - return;
114   - }
115   -
116   - switch (info->flash_id & FLASH_VENDMASK) {
117   - case FLASH_MAN_AMD:
118   - printf("AMD ");
119   - break;
120   - default:
121   - printf("Unknown Vendor ");
122   - break;
123   - }
124   -
125   - switch (info->flash_id & FLASH_TYPEMASK) {
126   - case FLASH_AMLV256U:
127   - fmt = "29LV256M (256 Mbit)\n";
128   - break;
129   - default:
130   - fmt = "Unknown Chip Type\n";
131   - break;
132   - }
133   -
134   - printf(fmt);
135   - printf(" Size: %ld MB in %d Sectors\n", info->size >> 20,
136   - info->sector_count);
137   - printf(" Sector Start Addresses:");
138   -
139   - for (i = 0; i < info->sector_count; ++i) {
140   - ulong size;
141   - int erased;
142   - ulong *flash = (unsigned long *)info->start[i];
143   -
144   - if ((i % 5) == 0) {
145   - printf("\n ");
146   - }
147   -
148   - /*
149   - * Check if whole sector is erased
150   - */
151   - size =
152   - (i !=
153   - (info->sector_count - 1)) ? (info->start[i + 1] -
154   - info->start[i]) >> 2 : (info->
155   - start
156   - [0] +
157   - info->
158   - size -
159   - info->
160   - start
161   - [i])
162   - >> 2;
163   -
164   - for (flash = (unsigned long *)info->start[i], erased = 1;
165   - (flash != (unsigned long *)info->start[i] + size)
166   - && erased; flash++) {
167   - erased = *flash == ~0x0UL;
168   - }
169   - printf(" %08lX %s %s", info->start[i], erased ? "E" : " ",
170   - info->protect[i] ? "(RO)" : " ");
171   - }
172   -
173   - printf("\n");
174   -}
175   -
176   -/*-----------------------------------------------------------------------
177   - */
178   -
179   -/*
180   - * The following code cannot be run from FLASH!
181   - */
182   -
183   -ulong flash_get_size(FPWV * addr, flash_info_t * info) {
184   - int i;
185   -
186   - /* Write auto select command: read Manufacturer ID */
187   - /* Write auto select command sequence and test FLASH answer */
188   - addr[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* for AMD, Intel ignores this */
189   - addr[FLASH_CYCLE2] = (FPW) 0x00550055; /* for AMD, Intel ignores this */
190   - addr[FLASH_CYCLE1] = (FPW) 0x00900090; /* selects Intel or AMD */
191   -
192   - /* The manufacturer codes are only 1 byte, so just use 1 byte. */
193   - /* This works for any bus width and any FLASH device width. */
194   - udelay(100);
195   - switch (addr[FLASH_ID1] & 0x00ff) {
196   - case (uchar) AMD_MANUFACT:
197   - info->flash_id = FLASH_MAN_AMD;
198   - break;
199   - default:
200   - printf("unknown vendor=%x ", addr[FLASH_ID1] & 0xff);
201   - info->flash_id = FLASH_UNKNOWN;
202   - info->sector_count = 0;
203   - info->size = 0;
204   - break;
205   - }
206   -
207   - /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
208   - if (info->flash_id != FLASH_UNKNOWN) {
209   - switch ((FPW) addr[FLASH_ID2]) {
210   - case (FPW) AMD_ID_MIRROR:
211   - /* MIRROR BIT FLASH, read more ID bytes */
212   - if ((FPW) addr[FLASH_ID3] == (FPW) AMD_ID_LV256U_2
213   - && (FPW) addr[FLASH_ID4] == (FPW) AMD_ID_LV256U_3) {
214   - /* attention: only the first 16 MB will be used in u-boot */
215   - info->flash_id += FLASH_AMLV256U;
216   - info->sector_count = 512;
217   - info->size = 0x02000000;
218   - for (i = 0; i < info->sector_count; i++) {
219   - info->start[i] =
220   - (ulong) addr + 0x10000 * i;
221   - }
222   - break;
223   - }
224   - /* fall thru to here ! */
225   - default:
226   - printf("unknown AMD device=%x %x %x",
227   - (FPW) addr[FLASH_ID2], (FPW) addr[FLASH_ID3],
228   - (FPW) addr[FLASH_ID4]);
229   - info->flash_id = FLASH_UNKNOWN;
230   - info->sector_count = 0;
231   - info->size = 0x800000;
232   - break;
233   - }
234   -
235   - /* Put FLASH back in read mode */
236   - flash_reset(info);
237   - }
238   - return (info->size);
239   -}
240   -
241   -/*-----------------------------------------------------------------------
242   - */
243   -
244   -int flash_erase(flash_info_t * info, int s_first, int s_last) {
245   - FPWV *addr;
246   - int flag, prot, sect;
247   - int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
248   - ulong start, now, last;
249   - int rcode = 0;
250   -
251   - if ((s_first < 0) || (s_first > s_last)) {
252   - if (info->flash_id == FLASH_UNKNOWN) {
253   - printf("- missing\n");
254   - } else {
255   - printf("- no sectors to erase\n");
256   - }
257   - return 1;
258   - }
259   -
260   - switch (info->flash_id & FLASH_TYPEMASK) {
261   - case FLASH_AMLV256U:
262   - break;
263   - case FLASH_UNKNOWN:
264   - default:
265   - printf("Can't erase unknown flash type %08lx - aborted\n",
266   - info->flash_id);
267   - return 1;
268   - }
269   -
270   - prot = 0;
271   - for (sect = s_first; sect <= s_last; ++sect) {
272   - if (info->protect[sect]) {
273   - prot++;
274   - }
275   - }
276   -
277   - if (prot) {
278   - printf("- Warning: %d protected sectors will not be erased!\n",
279   - prot);
280   - } else {
281   - printf("\n");
282   - }
283   -
284   - last = get_timer(0);
285   -
286   - /* Start erase on unprotected sectors */
287   - for (sect = s_first; sect <= s_last && rcode == 0; sect++) {
288   - if (info->protect[sect] != 0) { /* protected, skip it */
289   - continue;
290   - }
291   - /* Disable interrupts which might cause a timeout here */
292   - flag = disable_interrupts();
293   -
294   - addr = (FPWV *) (info->start[sect]);
295   - if (intel) {
296   - *addr = (FPW) 0x00500050; /* clear status register */
297   - *addr = (FPW) 0x00200020; /* erase setup */
298   - *addr = (FPW) 0x00D000D0; /* erase confirm */
299   - } else {
300   - /* must be AMD style if not Intel */
301   - FPWV *base; /* first address in bank */
302   -
303   - base = (FPWV *) (info->start[0]);
304   - base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */
305   - base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */
306   - base[FLASH_CYCLE1] = (FPW) 0x00800080; /* erase mode */
307   - base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */
308   - base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */
309   - *addr = (FPW) 0x00300030; /* erase sector */
310   - }
311   -
312   - /* re-enable interrupts if necessary */
313   - if (flag) {
314   - enable_interrupts();
315   - }
316   - start = get_timer(0);
317   -
318   - /* wait at least 50us for AMD, 80us for Intel. */
319   - /* Let's wait 1 ms. */
320   - udelay(1000);
321   -
322   - while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) {
323   - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
324   - printf("Timeout\n");
325   - if (intel) {
326   - /* suspend erase */
327   - *addr = (FPW) 0x00B000B0;
328   - }
329   - flash_reset(info); /* reset to read mode */
330   - rcode = 1; /* failed */
331   - break;
332   - }
333   - /* show that we're waiting */
334   - if ((get_timer(last)) > CONFIG_SYS_HZ) {
335   - /* every second */
336   - putc('.');
337   - last = get_timer(0);
338   - }
339   - }
340   - /* show that we're waiting */
341   - if ((get_timer(last)) > CONFIG_SYS_HZ) {
342   - /* every second */
343   - putc('.');
344   - last = get_timer(0);
345   - }
346   - flash_reset(info); /* reset to read mode */
347   - }
348   - printf(" done\n");
349   - return (rcode);
350   -}
351   -
352   -/*-----------------------------------------------------------------------
353   - * Copy memory to flash, returns:
354   - * 0 - OK
355   - * 1 - write timeout
356   - * 2 - Flash not erased
357   - */
358   -int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
359   -{
360   - FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
361   - int bytes; /* number of bytes to program in current word */
362   - int left; /* number of bytes left to program */
363   - int i, res;
364   -
365   - for (left = cnt, res = 0;
366   - left > 0 && res == 0;
367   - addr += sizeof(data), left -= sizeof(data) - bytes) {
368   -
369   - bytes = addr & (sizeof(data) - 1);
370   - addr &= ~(sizeof(data) - 1);
371   -
372   - /* combine source and destination data so can program
373   - * an entire word of 16 or 32 bits
374   - */
375   - for (i = 0; i < sizeof(data); i++) {
376   - data <<= 8;
377   - if (i < bytes || i - bytes >= left)
378   - data += *((uchar *) addr + i);
379   - else
380   - data += *src++;
381   - }
382   -
383   - /* write one word to the flash */
384   - switch (info->flash_id & FLASH_VENDMASK) {
385   - case FLASH_MAN_AMD:
386   - res = write_word_amd(info, (FPWV *) addr, data);
387   - break;
388   - default:
389   - /* unknown flash type, error! */
390   - printf("missing or unknown FLASH type\n");
391   - res = 1; /* not really a timeout, but gives error */
392   - break;
393   - }
394   - }
395   - return (res);
396   -}
397   -
398   -/*-----------------------------------------------------------------------
399   - * Write a word to Flash for AMD FLASH
400   - * A word is 16 or 32 bits, whichever the bus width of the flash bank
401   - * (not an individual chip) is.
402   - *
403   - * returns:
404   - * 0 - OK
405   - * 1 - write timeout
406   - * 2 - Flash not erased
407   - */
408   -static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data) {
409   - ulong start;
410   - int flag;
411   - int res = 0; /* result, assume success */
412   - FPWV *base; /* first address in flash bank */
413   -
414   - /* Check if Flash is (sufficiently) erased */
415   - if ((*dest & data) != data) {
416   - return (2);
417   - }
418   -
419   - base = (FPWV *) (info->start[0]);
420   -
421   - /* Disable interrupts which might cause a timeout here */
422   - flag = disable_interrupts();
423   -
424   - base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */
425   - base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */
426   - base[FLASH_CYCLE1] = (FPW) 0x00A000A0; /* selects program mode */
427   -
428   - *dest = data; /* start programming the data */
429   -
430   - /* re-enable interrupts if necessary */
431   - if (flag) {
432   - enable_interrupts();
433   - }
434   - start = get_timer(0);
435   -
436   - /* data polling for D7 */
437   - while (res == 0
438   - && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) {
439   - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
440   - *dest = (FPW) 0x00F000F0; /* reset bank */
441   - res = 1;
442   - }
443   - }
444   - return (res);
445   -}
board/esd/pf5200/mt46v16m16-75.h
View file @ 37b608a
1   -/*
2   - * (C) Copyright 2004
3   - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#define SDRAM_DDR 1 /* is DDR */
9   -
10   -/* Settings for XLB = 132 MHz */
11   -#define SDRAM_MODE 0x018D0000
12   -#define SDRAM_EMODE 0x40090000
13   -#define SDRAM_CONTROL 0x705f0f00
14   -#define SDRAM_CONFIG1 0x73722930
15   -#define SDRAM_CONFIG2 0x47770000
16   -#define SDRAM_TAPDELAY 0x10000000
board/esd/pf5200/pf5200.c
View file @ 37b608a
1   -/*
2   - * (C) Copyright 2003
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * (C) Copyright 2004
6   - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
7   - *
8   - * SPDX-License-Identifier: GPL-2.0+
9   - */
10   -
11   -/*
12   - * pf5200.c - main board support/init for the esd pf5200.
13   - */
14   -
15   -#include <common.h>
16   -#include <mpc5xxx.h>
17   -#include <pci.h>
18   -#include <command.h>
19   -#include <netdev.h>
20   -
21   -#include "mt46v16m16-75.h"
22   -
23   -void init_power_switch(void);
24   -
25   -static void sdram_start(int hi_addr)
26   -{
27   - long hi_addr_bit = hi_addr ? 0x01000000 : 0;
28   -
29   - /* unlock mode register */
30   - *(vu_long *) MPC5XXX_SDRAM_CTRL =
31   - SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
32   - __asm__ volatile ("sync");
33   -
34   - /* precharge all banks */
35   - *(vu_long *) MPC5XXX_SDRAM_CTRL =
36   - SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
37   - __asm__ volatile ("sync");
38   -
39   - /* set mode register: extended mode */
40   - *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
41   - __asm__ volatile ("sync");
42   -
43   - /* set mode register: reset DLL */
44   - *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
45   - __asm__ volatile ("sync");
46   -
47   - /* precharge all banks */
48   - *(vu_long *) MPC5XXX_SDRAM_CTRL =
49   - SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
50   - __asm__ volatile ("sync");
51   -
52   - /* auto refresh */
53   - *(vu_long *) MPC5XXX_SDRAM_CTRL =
54   - SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
55   - __asm__ volatile ("sync");
56   -
57   - /* set mode register */
58   - *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
59   - __asm__ volatile ("sync");
60   -
61   - /* normal operation */
62   - *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
63   - __asm__ volatile ("sync");
64   -}
65   -
66   -/*
67   - * ATTENTION: Although partially referenced initdram does NOT make real use
68   - * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
69   - * is something else than 0x00000000.
70   - */
71   -
72   -phys_size_t initdram(int board_type)
73   -{
74   - ulong dramsize = 0;
75   - ulong test1, test2;
76   -
77   - /* setup SDRAM chip selects */
78   - *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
79   - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
80   - __asm__ volatile ("sync");
81   -
82   - /* setup config registers */
83   - *(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
84   - *(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
85   - __asm__ volatile ("sync");
86   -
87   - /* set tap delay */
88   - *(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
89   - __asm__ volatile ("sync");
90   -
91   - /* find RAM size using SDRAM CS0 only */
92   - sdram_start(0);
93   - test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
94   - sdram_start(1);
95   - test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
96   -
97   - if (test1 > test2) {
98   - sdram_start(0);
99   - dramsize = test1;
100   - } else {
101   - dramsize = test2;
102   - }
103   -
104   - /* memory smaller than 1MB is impossible */
105   - if (dramsize < (1 << 20)) {
106   - dramsize = 0;
107   - }
108   -
109   - /* set SDRAM CS0 size according to the amount of RAM found */
110   - if (dramsize > 0) {
111   - *(vu_long *) MPC5XXX_SDRAM_CS0CFG =
112   - 0x13 + __builtin_ffs(dramsize >> 20) - 1;
113   - /* let SDRAM CS1 start right after CS0 */
114   - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */
115   - } else {
116   -#if 0
117   - *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
118   - /* let SDRAM CS1 start right after CS0 */
119   - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */
120   -#else
121   - *(vu_long *) MPC5XXX_SDRAM_CS0CFG =
122   - 0x13 + __builtin_ffs(0x08000000 >> 20) - 1;
123   - /* let SDRAM CS1 start right after CS0 */
124   - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e; /* 2G */
125   -#endif
126   - }
127   -
128   -#if 0
129   - /* find RAM size using SDRAM CS1 only */
130   - sdram_start(0);
131   - get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
132   - sdram_start(1);
133   - get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
134   - sdram_start(0);
135   -#endif
136   - /* set SDRAM CS1 size according to the amount of RAM found */
137   -
138   - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
139   -
140   - init_power_switch();
141   - return (dramsize);
142   -}
143   -
144   -int checkboard(void)
145   -{
146   - puts("Board: esd ParaFinder (pf5200)\n");
147   - return 0;
148   -}
149   -
150   -void flash_preinit(void)
151   -{
152   - /*
153   - * Now, when we are in RAM, enable flash write
154   - * access for detection process.
155   - * Note that CS_BOOT cannot be cleared when
156   - * executing in flash.
157   - */
158   - *(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
159   -}
160   -
161   -void flash_afterinit(ulong size)
162   -{
163   - if (size == 0x02000000) {
164   - /* adjust mapping */
165   - *(vu_long *) MPC5XXX_BOOTCS_START =
166   - *(vu_long *) MPC5XXX_CS0_START =
167   - START_REG(CONFIG_SYS_BOOTCS_START | size);
168   - *(vu_long *) MPC5XXX_BOOTCS_STOP =
169   - *(vu_long *) MPC5XXX_CS0_STOP =
170   - STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
171   - }
172   -}
173   -
174   -#ifdef CONFIG_PCI
175   -static struct pci_controller hose;
176   -
177   -extern void pci_mpc5xxx_init(struct pci_controller *);
178   -
179   -void pci_init_board(void) {
180   - pci_mpc5xxx_init(&hose);
181   -}
182   -#endif
183   -
184   -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
185   -
186   -void init_ide_reset(void)
187   -{
188   - debug("init_ide_reset\n");
189   -
190   - /* Configure PSC1_4 as GPIO output for ATA reset */
191   - *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
192   - *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
193   -}
194   -
195   -void ide_set_reset(int idereset)
196   -{
197   - debug("ide_reset(%d)\n", idereset);
198   -
199   - if (idereset) {
200   - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
201   - } else {
202   - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
203   - }
204   -}
205   -#endif
206   -
207   -#define MPC5XXX_SIMPLEIO_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004)
208   -#define MPC5XXX_SIMPLEIO_GPIO_DIR (MPC5XXX_GPIO + 0x000C)
209   -#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x0010)
210   -#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT (MPC5XXX_GPIO + 0x0014)
211   -
212   -#define MPC5XXX_INTERRUPT_GPIO_ENABLE (MPC5XXX_GPIO + 0x0020)
213   -#define MPC5XXX_INTERRUPT_GPIO_DIR (MPC5XXX_GPIO + 0x0028)
214   -#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C)
215   -#define MPC5XXX_INTERRUPT_GPIO_STATUS (MPC5XXX_GPIO + 0x003C)
216   -
217   -#define GPIO_WU6 0x40000000UL
218   -#define GPIO_USB0 0x00010000UL
219   -#define GPIO_USB9 0x08000000UL
220   -#define GPIO_USB9S 0x00080000UL
221   -
222   -void init_power_switch(void)
223   -{
224   - debug("init_power_switch\n");
225   -
226   - /* Configure GPIO_WU6 as GPIO output for ATA reset */
227   - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6;
228   - *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6;
229   - *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6;
230   - __asm__ volatile ("sync");
231   -
232   - *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0;
233   - *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0;
234   - *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0;
235   - __asm__ volatile ("sync");
236   -
237   - *(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
238   - *(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9;
239   - __asm__ volatile ("sync");
240   -
241   - if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) {
242   - *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0;
243   - __asm__ volatile ("sync");
244   - }
245   - *(vu_char *) CONFIG_SYS_CS1_START = 0x02; /* Red Power LED on */
246   - __asm__ volatile ("sync");
247   -
248   - *(vu_char *) (CONFIG_SYS_CS1_START + 1) = 0x02; /* Disable driver for KB11 */
249   - __asm__ volatile ("sync");
250   -}
251   -
252   -int board_eth_init(bd_t *bis)
253   -{
254   - return pci_eth_init(bis);
255   -}
256   -
257   -void power_set_reset(int power)
258   -{
259   - debug("ide_set_reset(%d)\n", power);
260   -
261   - if (power) {
262   - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_WU6;
263   - *(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
264   - } else {
265   - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6;
266   - if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) ==
267   - 0) {
268   - *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |=
269   - GPIO_USB0;
270   - }
271   -
272   - }
273   -}
274   -
275   -int do_poweroff(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
276   -{
277   - power_set_reset(1);
278   - return (0);
279   -}
280   -
281   -U_BOOT_CMD(poweroff, 1, 1, do_poweroff, "Switch off power", "");
282   -
283   -int phypower(int flag)
284   -{
285   - u32 addr;
286   - vu_long *reg;
287   - int status;
288   - pci_dev_t dev;
289   -
290   - dev = PCI_BDF(0, 0x18, 0);
291   - status = pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &addr);
292   - if (status == 0) {
293   - reg = (vu_long *) (addr + 0x00000040);
294   - *reg |= 0x40000000;
295   - __asm__ volatile ("sync");
296   -
297   - reg = (vu_long *) (addr + 0x001000c);
298   - *reg |= 0x20000000;
299   - __asm__ volatile ("sync");
300   -
301   - reg = (vu_long *) (addr + 0x0010004);
302   - if (flag != 0) {
303   - *reg &= ~0x20000000;
304   - } else {
305   - *reg |= 0x20000000;
306   - }
307   - __asm__ volatile ("sync");
308   - }
309   - return (status);
310   -}
311   -
312   -int do_phypower(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
313   -{
314   - if (argv[1][0] == '0')
315   - (void)phypower(0);
316   - else
317   - (void)phypower(1);
318   -
319   - return (0);
320   -}
321   -
322   -U_BOOT_CMD(phypower, 2, 2, do_phypower,
323   - "Switch power of ethernet phy", "");
324   -
325   -int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
326   -{
327   - unsigned int addr;
328   - unsigned int size;
329   - int i;
330   - volatile unsigned long *ptr;
331   -
332   - addr = simple_strtol(argv[1], NULL, 16);
333   - size = simple_strtol(argv[2], NULL, 16);
334   -
335   - printf("\nWriting at addr %08x, size %08x.\n", addr, size);
336   -
337   - while (1) {
338   - ptr = (volatile unsigned long *)addr;
339   - for (i = 0; i < (size >> 2); i++) {
340   - *ptr++ = i;
341   - }
342   -
343   - /* Abort if ctrl-c was pressed */
344   - if (ctrlc()) {
345   - puts("\nAbort\n");
346   - return 0;
347   - }
348   - putc('.');
349   - }
350   - return 0;
351   -}
352   -
353   -U_BOOT_CMD(writepci, 3, 1, do_writepci,
354   - "Write some data to pcibus",
355   - "<addr> <size>\n"
356   - ""
357   -);
board/icecube/Kconfig
View file @ 37b608a
1   -if TARGET_ICECUBE
2   -
3   -config SYS_BOARD
4   - default "icecube"
5   -
6   -config SYS_CONFIG_NAME
7   - default "IceCube"
8   -
9   -endif
board/icecube/MAINTAINERS
View file @ 37b608a
1   -ICECUBE BOARD
2   -M: Wolfgang Denk <wd@denx.de>
3   -S: Maintained
4   -F: board/icecube/
5   -F: include/configs/IceCube.h
6   -F: configs/icecube_5200_defconfig
7   -
8   -ICECUBE_5200_DDR BOARD
9   -#M: -
10   -S: Maintained
11   -F: configs/icecube_5200_DDR_defconfig
12   -F: configs/icecube_5200_DDR_LOWBOOT_defconfig
13   -F: configs/icecube_5200_DDR_LOWBOOT08_defconfig
14   -F: configs/icecube_5200_LOWBOOT_defconfig
15   -F: configs/icecube_5200_LOWBOOT08_defconfig
16   -F: configs/Lite5200_defconfig
17   -F: configs/Lite5200_LOWBOOT_defconfig
18   -F: configs/Lite5200_LOWBOOT08_defconfig
19   -F: configs/lite5200b_defconfig
20   -F: configs/lite5200b_LOWBOOT_defconfig
21   -F: configs/lite5200b_PM_defconfig
board/icecube/Makefile
View file @ 37b608a
1   -#
2   -# (C) Copyright 2003-2006
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# SPDX-License-Identifier: GPL-2.0+
6   -#
7   -
8   -obj-y := icecube.o flash.o
board/icecube/README
View file @ 37b608a
1   ----------------------------------------------------------------------------
2   -Build target Flash address | BDI "go" command | Reset Vector
3   ----------------------------------------------------------------------------
4   -Lite5200 0xFFF00000 | 0xFFF00100 | 0xFFF00100
5   -Lite5200_LOWBOOT 0xFF000000 | 0xFF000100 | 0x00000100
6   -Lite5200_LOWBOOT08 0xFF800000 | 0xFF800100 | 0x00000100
7   -icecube_5200 0xFFF00000 | 0xFFF00100 | 0xFFF00100
8   -icecube_5200_LOWBOOT 0xFF000000 | 0xFF000100 | 0x00000100
9   -icecube_5200_LOWBOOT08 0xFF800000 | 0xFF800100 | 0x00000100
10   -icecube_5200_DDR 0xFFF00000 | 0xFFF00100 | 0xFFF00100
11   -icecube_5200_DDR_LOWBOOT 0xFF800000 | 0xFF800100 | 0x00000100
12   -icecube_5200_DDR_LOWBOOT08 0xFF800000 | 0xFF800100 | 0x00000100
13   ----------------------------------------------------------------------------
board/icecube/README.Lite5200B_low_power
View file @ 37b608a
1   -Lite5200B wakeup from low-power mode (CONFIG_LITE5200B_PM)
2   -----------------------------------------------------------
3   -
4   -Low-power mode as described in Lite5200B User's Manual, means that
5   -with support of MC68HLC908QT1 microcontroller (refered to as QT),
6   -everything but the SDRAM can be powered down. This brings
7   -maximum power saving, while one can still restore previous state
8   -quickly.
9   -
10   -Quick overview where U-Boot comes into the picture:
11   -- OS saves device states
12   -- OS saves wakeup handler address to physical 0x0, puts SDRAM into
13   - self-refresh and signals to QT, it should power down the board
14   -- / board is sleeping here /
15   -- someone presses SW4 (connected to QT)
16   -- U-Boot checks PSC2_4 pin, if QT drives it down, then we woke up,
17   - so get SDRAM out of self-refresh and transfer control to OS
18   - wakeup handler
19   -- OS restores device states
20   -
21   -This was tested on Linux with USB and Ethernet in use. Adding
22   -support for other devices is an OS issue.
board/icecube/flash.c
View file @ 37b608a
1   -/*
2   - * (C) Copyright 2003
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#include <common.h>
9   -
10   -#ifndef CONFIG_FLASH_CFI_DRIVER
11   -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
12   -
13   -/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
14   - * has nothing to do with the flash chip being 8-bit or 16-bit.
15   - */
16   -#ifdef CONFIG_FLASH_16BIT
17   -typedef unsigned short FLASH_PORT_WIDTH;
18   -typedef volatile unsigned short FLASH_PORT_WIDTHV;
19   -#define FLASH_ID_MASK 0xFFFF
20   -#else
21   -typedef unsigned char FLASH_PORT_WIDTH;
22   -typedef volatile unsigned char FLASH_PORT_WIDTHV;
23   -#define FLASH_ID_MASK 0xFF
24   -#endif
25   -
26   -#define FPW FLASH_PORT_WIDTH
27   -#define FPWV FLASH_PORT_WIDTHV
28   -
29   -#define ORMASK(size) ((-size) & OR_AM_MSK)
30   -
31   -#define FLASH_CYCLE1 0x0555
32   -#define FLASH_CYCLE2 0x02aa
33   -
34   -/*-----------------------------------------------------------------------
35   - * Functions
36   - */
37   -static ulong flash_get_size(FPWV *addr, flash_info_t *info);
38   -static void flash_reset(flash_info_t *info);
39   -static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
40   -static flash_info_t *flash_get_info(ulong base);
41   -
42   -/*-----------------------------------------------------------------------
43   - * flash_init()
44   - *
45   - * sets up flash_info and returns size of FLASH (bytes)
46   - */
47   -unsigned long flash_init (void)
48   -{
49   - unsigned long size = 0;
50   - int i;
51   - extern void flash_preinit(void);
52   - extern void flash_afterinit(ulong);
53   - ulong flashbase = CONFIG_SYS_FLASH_BASE;
54   -
55   - flash_preinit();
56   -
57   - /* Init: no FLASHes known */
58   - for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
59   - memset(&flash_info[i], 0, sizeof(flash_info_t));
60   -
61   - flash_info[i].size =
62   - flash_get_size((FPW *)flashbase, &flash_info[i]);
63   -
64   - size += flash_info[i].size;
65   - flashbase += 0x800000;
66   - }
67   -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
68   - /* monitor protection ON by default */
69   - flash_protect(FLAG_PROTECT_SET,
70   - CONFIG_SYS_MONITOR_BASE,
71   - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
72   - flash_get_info(CONFIG_SYS_MONITOR_BASE));
73   -#endif
74   -
75   -#ifdef CONFIG_ENV_IS_IN_FLASH
76   - /* ENV protection ON by default */
77   - flash_protect(FLAG_PROTECT_SET,
78   - CONFIG_ENV_ADDR,
79   - CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
80   - flash_get_info(CONFIG_ENV_ADDR));
81   -#endif
82   -
83   -
84   - flash_afterinit(size);
85   - return size ? size : 1;
86   -}
87   -
88   -/*-----------------------------------------------------------------------
89   - */
90   -static void flash_reset(flash_info_t *info)
91   -{
92   - FPWV *base = (FPWV *)(info->start[0]);
93   -
94   - /* Put FLASH back in read mode */
95   - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
96   - *base = (FPW)0x00FF00FF; /* Intel Read Mode */
97   - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
98   - *base = (FPW)0x00F000F0; /* AMD Read Mode */
99   -}
100   -
101   -/*-----------------------------------------------------------------------
102   - */
103   -
104   -static flash_info_t *flash_get_info(ulong base)
105   -{
106   - int i;
107   - flash_info_t * info;
108   -
109   - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
110   - info = & flash_info[i];
111   - if (info->size &&
112   - info->start[0] <= base && base <= info->start[0] + info->size - 1)
113   - break;
114   - }
115   -
116   - return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info;
117   -}
118   -
119   -/*-----------------------------------------------------------------------
120   - */
121   -
122   -void flash_print_info (flash_info_t *info)
123   -{
124   - int i;
125   - uchar *boottype;
126   - uchar *bootletter;
127   - char *fmt;
128   - uchar botbootletter[] = "B";
129   - uchar topbootletter[] = "T";
130   - uchar botboottype[] = "bottom boot sector";
131   - uchar topboottype[] = "top boot sector";
132   -
133   - if (info->flash_id == FLASH_UNKNOWN) {
134   - printf ("missing or unknown FLASH type\n");
135   - return;
136   - }
137   -
138   - switch (info->flash_id & FLASH_VENDMASK) {
139   - case FLASH_MAN_AMD: printf ("AMD "); break;
140   - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
141   - case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
142   - case FLASH_MAN_SST: printf ("SST "); break;
143   - case FLASH_MAN_STM: printf ("STM "); break;
144   - case FLASH_MAN_INTEL: printf ("INTEL "); break;
145   - default: printf ("Unknown Vendor "); break;
146   - }
147   -
148   - /* check for top or bottom boot, if it applies */
149   - if (info->flash_id & FLASH_BTYPE) {
150   - boottype = botboottype;
151   - bootletter = botbootletter;
152   - }
153   - else {
154   - boottype = topboottype;
155   - bootletter = topbootletter;
156   - }
157   -
158   - switch (info->flash_id & FLASH_TYPEMASK) {
159   - case FLASH_AMDLV065D:
160   - fmt = "29LV065 (64 Mbit, uniform sectors)\n";
161   - break;
162   - default:
163   - fmt = "Unknown Chip Type\n";
164   - break;
165   - }
166   -
167   - printf (fmt, bootletter, boottype);
168   -
169   - printf (" Size: %ld MB in %d Sectors\n",
170   - info->size >> 20,
171   - info->sector_count);
172   -
173   - printf (" Sector Start Addresses:");
174   -
175   - for (i=0; i<info->sector_count; ++i) {
176   - if ((i % 5) == 0) {
177   - printf ("\n ");
178   - }
179   -
180   - printf (" %08lX%s", info->start[i],
181   - info->protect[i] ? " (RO)" : " ");
182   - }
183   -
184   - printf ("\n");
185   -}
186   -
187   -/*-----------------------------------------------------------------------
188   - */
189   -
190   -/*
191   - * The following code cannot be run from FLASH!
192   - */
193   -
194   -ulong flash_get_size (FPWV *addr, flash_info_t *info)
195   -{
196   - int i;
197   - FPWV* addr2;
198   -
199   - /* Write auto select command: read Manufacturer ID */
200   - /* Write auto select command sequence and test FLASH answer */
201   - addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */
202   - addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */
203   - addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */
204   -
205   - /* The manufacturer codes are only 1 byte, so just use 1 byte.
206   - * This works for any bus width and any FLASH device width.
207   - */
208   - udelay(100);
209   - switch (addr[0] & 0xff) {
210   -
211   - case (uchar)AMD_MANUFACT:
212   - info->flash_id = FLASH_MAN_AMD;
213   - break;
214   -
215   - case (uchar)INTEL_MANUFACT:
216   - info->flash_id = FLASH_MAN_INTEL;
217   - break;
218   -
219   - default:
220   - info->flash_id = FLASH_UNKNOWN;
221   - info->sector_count = 0;
222   - info->size = 0;
223   - break;
224   - }
225   -
226   - /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
227   - if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[1]) {
228   -
229   - case (FPW)AMD_ID_LV065D:
230   - info->flash_id += FLASH_AMDLV065D;
231   - info->sector_count = 128;
232   - info->size = 0x00800000;
233   - for( i = 0; i < info->sector_count; i++ )
234   - info->start[i] = (ulong)addr + (i * 0x10000);
235   - break; /* => 8 or 16 MB */
236   -
237   - default:
238   - info->flash_id = FLASH_UNKNOWN;
239   - info->sector_count = 0;
240   - info->size = 0;
241   - return (0); /* => no or unknown flash */
242   - }
243   -
244   - /* test for real flash at bank 1 */
245   - addr2 = (FPW *)((ulong)addr | 0x800000);
246   - if (addr2 != addr &&
247   - ((addr2[0] & 0xff) == (addr[0] & 0xff)) && ((FPW)addr2[1] == (FPW)addr[1])) {
248   - /* Seems 2 banks are the same space (8Mb chip is installed,
249   - * J24 in default position (CS0)). Disable this (first) bank.
250   - */
251   - info->flash_id = FLASH_UNKNOWN;
252   - info->sector_count = 0;
253   - info->size = 0;
254   - }
255   - /* Put FLASH back in read mode */
256   - flash_reset(info);
257   -
258   - return (info->size);
259   -}
260   -
261   -/*-----------------------------------------------------------------------
262   - */
263   -
264   -int flash_erase (flash_info_t *info, int s_first, int s_last)
265   -{
266   - FPWV *addr;
267   - int flag, prot, sect;
268   - int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
269   - ulong start, now, last;
270   - int rcode = 0;
271   -
272   - if ((s_first < 0) || (s_first > s_last)) {
273   - if (info->flash_id == FLASH_UNKNOWN) {
274   - printf ("- missing\n");
275   - } else {
276   - printf ("- no sectors to erase\n");
277   - }
278   - return 1;
279   - }
280   -
281   - switch (info->flash_id & FLASH_TYPEMASK) {
282   - case FLASH_AMDLV065D:
283   - break;
284   - case FLASH_UNKNOWN:
285   - default:
286   - printf ("Can't erase unknown flash type %08lx - aborted\n",
287   - info->flash_id);
288   - return 1;
289   - }
290   -
291   - prot = 0;
292   - for (sect=s_first; sect<=s_last; ++sect) {
293   - if (info->protect[sect]) {
294   - prot++;
295   - }
296   - }
297   -
298   - if (prot) {
299   - printf ("- Warning: %d protected sectors will not be erased!\n",
300   - prot);
301   - } else {
302   - printf ("\n");
303   - }
304   -
305   - last = get_timer(0);
306   -
307   - /* Start erase on unprotected sectors */
308   - for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
309   -
310   - if (info->protect[sect] != 0) /* protected, skip it */
311   - continue;
312   -
313   - /* Disable interrupts which might cause a timeout here */
314   - flag = disable_interrupts();
315   -
316   - addr = (FPWV *)(info->start[sect]);
317   - if (intel) {
318   - *addr = (FPW)0x00500050; /* clear status register */
319   - *addr = (FPW)0x00200020; /* erase setup */
320   - *addr = (FPW)0x00D000D0; /* erase confirm */
321   - }
322   - else {
323   - /* must be AMD style if not Intel */
324   - FPWV *base; /* first address in bank */
325   -
326   - base = (FPWV *)(info->start[0]);
327   - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
328   - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
329   - base[FLASH_CYCLE1] = (FPW)0x00800080; /* erase mode */
330   - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
331   - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
332   - *addr = (FPW)0x00300030; /* erase sector */
333   - }
334   -
335   - /* re-enable interrupts if necessary */
336   - if (flag)
337   - enable_interrupts();
338   -
339   - start = get_timer(0);
340   -
341   - /* wait at least 50us for AMD, 80us for Intel.
342   - * Let's wait 1 ms.
343   - */
344   - udelay (1000);
345   -
346   - while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
347   - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
348   - printf ("Timeout\n");
349   -
350   - if (intel) {
351   - /* suspend erase */
352   - *addr = (FPW)0x00B000B0;
353   - }
354   -
355   - flash_reset(info); /* reset to read mode */
356   - rcode = 1; /* failed */
357   - break;
358   - }
359   -
360   - /* show that we're waiting */
361   - if ((get_timer(last)) > CONFIG_SYS_HZ) {/* every second */
362   - putc ('.');
363   - last = get_timer(0);
364   - }
365   - }
366   -
367   - /* show that we're waiting */
368   - if ((get_timer(last)) > CONFIG_SYS_HZ) { /* every second */
369   - putc ('.');
370   - last = get_timer(0);
371   - }
372   -
373   - flash_reset(info); /* reset to read mode */
374   - }
375   -
376   - printf (" done\n");
377   - return rcode;
378   -}
379   -
380   -/*-----------------------------------------------------------------------
381   - * Copy memory to flash, returns:
382   - * 0 - OK
383   - * 1 - write timeout
384   - * 2 - Flash not erased
385   - */
386   -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
387   -{
388   - FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
389   - int bytes; /* number of bytes to program in current word */
390   - int left; /* number of bytes left to program */
391   - int i, res;
392   -
393   - for (left = cnt, res = 0;
394   - left > 0 && res == 0;
395   - addr += sizeof(data), left -= sizeof(data) - bytes) {
396   -
397   - bytes = addr & (sizeof(data) - 1);
398   - addr &= ~(sizeof(data) - 1);
399   -
400   - /* combine source and destination data so can program
401   - * an entire word of 16 or 32 bits
402   - */
403   - for (i = 0; i < sizeof(data); i++) {
404   - data <<= 8;
405   - if (i < bytes || i - bytes >= left )
406   - data += *((uchar *)addr + i);
407   - else
408   - data += *src++;
409   - }
410   -
411   - /* write one word to the flash */
412   - switch (info->flash_id & FLASH_VENDMASK) {
413   - case FLASH_MAN_AMD:
414   - res = write_word_amd(info, (FPWV *)addr, data);
415   - break;
416   - default:
417   - /* unknown flash type, error! */
418   - printf ("missing or unknown FLASH type\n");
419   - res = 1; /* not really a timeout, but gives error */
420   - break;
421   - }
422   - }
423   -
424   - return (res);
425   -}
426   -
427   -/*-----------------------------------------------------------------------
428   - * Write a word to Flash for AMD FLASH
429   - * A word is 16 or 32 bits, whichever the bus width of the flash bank
430   - * (not an individual chip) is.
431   - *
432   - * returns:
433   - * 0 - OK
434   - * 1 - write timeout
435   - * 2 - Flash not erased
436   - */
437   -static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
438   -{
439   - ulong start;
440   - int flag;
441   - int res = 0; /* result, assume success */
442   - FPWV *base; /* first address in flash bank */
443   -
444   - /* Check if Flash is (sufficiently) erased */
445   - if ((*dest & data) != data) {
446   - return (2);
447   - }
448   -
449   -
450   - base = (FPWV *)(info->start[0]);
451   -
452   - /* Disable interrupts which might cause a timeout here */
453   - flag = disable_interrupts();
454   -
455   - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
456   - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
457   - base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */
458   -
459   - *dest = data; /* start programming the data */
460   -
461   - /* re-enable interrupts if necessary */
462   - if (flag)
463   - enable_interrupts();
464   -
465   - start = get_timer (0);
466   -
467   - /* data polling for D7 */
468   - while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
469   - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
470   - *dest = (FPW)0x00F000F0; /* reset bank */
471   - res = 1;
472   - }
473   - }
474   -
475   - return (res);
476   -}
477   -#endif /*CONFIG_FLASH_CFI_DRIVER*/
board/icecube/icecube.c
View file @ 37b608a
1   -/*
2   - * (C) Copyright 2003
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * (C) Copyright 2004
6   - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
7   - *
8   - * SPDX-License-Identifier: GPL-2.0+
9   - */
10   -
11   -#include <common.h>
12   -#include <mpc5xxx.h>
13   -#include <pci.h>
14   -#include <asm/processor.h>
15   -#include <libfdt.h>
16   -#include <netdev.h>
17   -
18   -#if defined(CONFIG_LITE5200B)
19   -#include "mt46v32m16.h"
20   -#else
21   -# if defined(CONFIG_MPC5200_DDR)
22   -# include "mt46v16m16-75.h"
23   -# else
24   -#include "mt48lc16m16a2-75.h"
25   -# endif
26   -#endif
27   -
28   -#ifdef CONFIG_LITE5200B_PM
29   -/* u-boot part of low-power mode implementation */
30   -#define SAVED_ADDR (*(void **)0x00000000)
31   -#define PSC2_4 0x02
32   -
33   -void lite5200b_wakeup(void)
34   -{
35   - unsigned char wakeup_pin;
36   - void (*linux_wakeup)(void);
37   -
38   - /* check PSC2_4, if it's down "QT" is signaling we have a wakeup
39   - * from low power mode */
40   - *(vu_char *)MPC5XXX_WU_GPIO_ENABLE = PSC2_4;
41   - __asm__ volatile ("sync");
42   -
43   - wakeup_pin = *(vu_char *)MPC5XXX_WU_GPIO_DATA_I;
44   - if (wakeup_pin & PSC2_4)
45   - return;
46   -
47   - /* acknowledge to "QT"
48   - * by holding pin at 1 for 10 uS */
49   - *(vu_char *)MPC5XXX_WU_GPIO_DIR = PSC2_4;
50   - __asm__ volatile ("sync");
51   - *(vu_char *)MPC5XXX_WU_GPIO_DATA_O = PSC2_4;
52   - __asm__ volatile ("sync");
53   - udelay(10);
54   -
55   - /* put ram out of self-refresh */
56   - *(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x80000000; /* mode_en */
57   - __asm__ volatile ("sync");
58   - *(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x50000000; /* cke ref_en */
59   - __asm__ volatile ("sync");
60   - *(vu_long *)MPC5XXX_SDRAM_CTRL &= ~0x80000000; /* !mode_en */
61   - __asm__ volatile ("sync");
62   - udelay(10); /* wait a bit */
63   -
64   - /* jump back to linux kernel code */
65   - linux_wakeup = SAVED_ADDR;
66   - printf("\n\nLooks like we just woke, transferring control to 0x%08lx\n",
67   - (unsigned long)linux_wakeup);
68   - linux_wakeup();
69   -}
70   -#else
71   -#define lite5200b_wakeup()
72   -#endif
73   -
74   -#ifndef CONFIG_SYS_RAMBOOT
75   -static void sdram_start (int hi_addr)
76   -{
77   - long hi_addr_bit = hi_addr ? 0x01000000 : 0;
78   -
79   - /* unlock mode register */
80   - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
81   - __asm__ volatile ("sync");
82   -
83   - /* precharge all banks */
84   - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
85   - __asm__ volatile ("sync");
86   -
87   -#if SDRAM_DDR
88   - /* set mode register: extended mode */
89   - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
90   - __asm__ volatile ("sync");
91   -
92   - /* set mode register: reset DLL */
93   - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
94   - __asm__ volatile ("sync");
95   -#endif
96   -
97   - /* precharge all banks */
98   - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
99   - __asm__ volatile ("sync");
100   -
101   - /* auto refresh */
102   - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
103   - __asm__ volatile ("sync");
104   -
105   - /* set mode register */
106   - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
107   - __asm__ volatile ("sync");
108   -
109   - /* normal operation */
110   - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
111   - __asm__ volatile ("sync");
112   -}
113   -#endif
114   -
115   -/*
116   - * ATTENTION: Although partially referenced initdram does NOT make real use
117   - * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
118   - * is something else than 0x00000000.
119   - */
120   -
121   -phys_size_t initdram (int board_type)
122   -{
123   - ulong dramsize = 0;
124   - ulong dramsize2 = 0;
125   - uint svr, pvr;
126   -
127   -#ifndef CONFIG_SYS_RAMBOOT
128   - ulong test1, test2;
129   -
130   - /* setup SDRAM chip selects */
131   - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
132   - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
133   - __asm__ volatile ("sync");
134   -
135   - /* setup config registers */
136   - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
137   - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
138   - __asm__ volatile ("sync");
139   -
140   -#if SDRAM_DDR
141   - /* set tap delay */
142   - *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
143   - __asm__ volatile ("sync");
144   -#endif
145   -
146   - /* find RAM size using SDRAM CS0 only */
147   - sdram_start(0);
148   - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
149   - sdram_start(1);
150   - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
151   - if (test1 > test2) {
152   - sdram_start(0);
153   - dramsize = test1;
154   - } else {
155   - dramsize = test2;
156   - }
157   -
158   - /* memory smaller than 1MB is impossible */
159   - if (dramsize < (1 << 20)) {
160   - dramsize = 0;
161   - }
162   -
163   - /* set SDRAM CS0 size according to the amount of RAM found */
164   - if (dramsize > 0) {
165   - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
166   - } else {
167   - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
168   - }
169   -
170   - /* let SDRAM CS1 start right after CS0 */
171   - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
172   -
173   - /* find RAM size using SDRAM CS1 only */
174   - if (!dramsize)
175   - sdram_start(0);
176   - test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
177   - if (!dramsize) {
178   - sdram_start(1);
179   - test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
180   - }
181   - if (test1 > test2) {
182   - sdram_start(0);
183   - dramsize2 = test1;
184   - } else {
185   - dramsize2 = test2;
186   - }
187   -
188   - /* memory smaller than 1MB is impossible */
189   - if (dramsize2 < (1 << 20)) {
190   - dramsize2 = 0;
191   - }
192   -
193   - /* set SDRAM CS1 size according to the amount of RAM found */
194   - if (dramsize2 > 0) {
195   - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
196   - | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
197   - } else {
198   - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
199   - }
200   -
201   -#else /* CONFIG_SYS_RAMBOOT */
202   -
203   - /* retrieve size of memory connected to SDRAM CS0 */
204   - dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
205   - if (dramsize >= 0x13) {
206   - dramsize = (1 << (dramsize - 0x13)) << 20;
207   - } else {
208   - dramsize = 0;
209   - }
210   -
211   - /* retrieve size of memory connected to SDRAM CS1 */
212   - dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
213   - if (dramsize2 >= 0x13) {
214   - dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
215   - } else {
216   - dramsize2 = 0;
217   - }
218   -
219   -#endif /* CONFIG_SYS_RAMBOOT */
220   -
221   - /*
222   - * On MPC5200B we need to set the special configuration delay in the
223   - * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
224   - * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
225   - *
226   - * "The SDelay should be written to a value of 0x00000004. It is
227   - * required to account for changes caused by normal wafer processing
228   - * parameters."
229   - */
230   - svr = get_svr();
231   - pvr = get_pvr();
232   - if ((SVR_MJREV(svr) >= 2) &&
233   - (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
234   -
235   - *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
236   - __asm__ volatile ("sync");
237   - }
238   -
239   - lite5200b_wakeup();
240   -
241   - return dramsize + dramsize2;
242   -}
243   -
244   -int checkboard (void)
245   -{
246   -#if defined (CONFIG_LITE5200B)
247   - puts ("Board: Freescale Lite5200B\n");
248   -#else
249   - puts ("Board: Motorola MPC5200 (IceCube)\n");
250   -#endif
251   - return 0;
252   -}
253   -
254   -void flash_preinit(void)
255   -{
256   - /*
257   - * Now, when we are in RAM, enable flash write
258   - * access for detection process.
259   - * Note that CS_BOOT cannot be cleared when
260   - * executing in flash.
261   - */
262   - *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
263   -}
264   -
265   -void flash_afterinit(ulong size)
266   -{
267   - if (size == 0x800000) { /* adjust mapping */
268   - *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
269   - START_REG(CONFIG_SYS_BOOTCS_START | size);
270   - *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
271   - STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
272   - }
273   -}
274   -
275   -#ifdef CONFIG_PCI
276   -static struct pci_controller hose;
277   -
278   -extern void pci_mpc5xxx_init(struct pci_controller *);
279   -
280   -void pci_init_board(void)
281   -{
282   - pci_mpc5xxx_init(&hose);
283   -}
284   -#endif
285   -
286   -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
287   -
288   -void init_ide_reset (void)
289   -{
290   - debug ("init_ide_reset\n");
291   -
292   - /* Configure PSC1_4 as GPIO output for ATA reset */
293   - *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
294   - *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
295   - /* Deassert reset */
296   - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
297   -}
298   -
299   -void ide_set_reset (int idereset)
300   -{
301   - debug ("ide_reset(%d)\n", idereset);
302   -
303   - if (idereset) {
304   - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
305   - /* Make a delay. MPC5200 spec says 25 usec min */
306   - udelay(500000);
307   - } else {
308   - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
309   - }
310   -}
311   -#endif
312   -
313   -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
314   -int ft_board_setup(void *blob, bd_t *bd)
315   -{
316   - ft_cpu_setup(blob, bd);
317   -
318   - return 0;
319   -}
320   -#endif
321   -
322   -int board_eth_init(bd_t *bis)
323   -{
324   - cpu_eth_init(bis); /* Built in FEC comes first */
325   - return pci_eth_init(bis);
326   -}
board/icecube/mt46v16m16-75.h
View file @ 37b608a
1   -/*
2   - * (C) Copyright 2004
3   - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#define SDRAM_DDR 1 /* is DDR */
9   -
10   -/* Settings for XLB = 132 MHz */
11   -#define SDRAM_MODE 0x018D0000
12   -#define SDRAM_EMODE 0x40090000
13   -#define SDRAM_CONTROL 0x705f0f00
14   -#define SDRAM_CONFIG1 0x73722930
15   -#define SDRAM_CONFIG2 0x47770000
16   -#define SDRAM_TAPDELAY 0x10000000
board/icecube/mt46v32m16.h
View file @ 37b608a
1   -/*
2   - * (C) Copyright 2004
3   - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#define SDRAM_DDR 1 /* is DDR */
9   -
10   -/* Settings for XLB = 132 MHz */
11   -#define SDRAM_MODE 0x018D0000
12   -#define SDRAM_EMODE 0x40090000
13   -#define SDRAM_CONTROL 0x704f0f00
14   -#define SDRAM_CONFIG1 0x73722930
15   -#define SDRAM_CONFIG2 0x47770000
16   -#define SDRAM_TAPDELAY 0x10000000
board/icecube/mt48lc16m16a2-75.h
View file @ 37b608a
1   -/*
2   - * (C) Copyright 2004
3   - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#define SDRAM_DDR 0 /* is SDR */
9   -
10   -/* Settings for XLB = 132 MHz */
11   -#define SDRAM_MODE 0x00CD0000
12   -#define SDRAM_CONTROL 0x504F0000
13   -#define SDRAM_CONFIG1 0xD2322800
14   -#define SDRAM_CONFIG2 0x8AD70000
configs/Lite5200_LOWBOOT08_defconfig
View file @ 37b608a
1   -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFF800000"
2   -CONFIG_PPC=y
3   -CONFIG_MPC5xxx=y
4   -CONFIG_TARGET_ICECUBE=y
configs/Lite5200_LOWBOOT_defconfig
View file @ 37b608a
1   -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFF000000"
2   -CONFIG_PPC=y
3   -CONFIG_MPC5xxx=y
4   -CONFIG_TARGET_ICECUBE=y
configs/Lite5200_defconfig
View file @ 37b608a
1   -CONFIG_PPC=y
2   -CONFIG_MPC5xxx=y
3   -CONFIG_TARGET_ICECUBE=y
configs/cpci5200_defconfig
View file @ 37b608a
1   -CONFIG_PPC=y
2   -CONFIG_MPC5xxx=y
3   -CONFIG_TARGET_CPCI5200=y
configs/icecube_5200_DDR_LOWBOOT08_defconfig
View file @ 37b608a
1   -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFF800000,MPC5200_DDR"
2   -CONFIG_PPC=y
3   -CONFIG_MPC5xxx=y
4   -CONFIG_TARGET_ICECUBE=y
configs/icecube_5200_DDR_LOWBOOT_defconfig
View file @ 37b608a
1   -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFF800000,MPC5200_DDR"
2   -CONFIG_PPC=y
3   -CONFIG_MPC5xxx=y
4   -CONFIG_TARGET_ICECUBE=y
configs/icecube_5200_DDR_defconfig
View file @ 37b608a
1   -CONFIG_SYS_EXTRA_OPTIONS="MPC5200_DDR"
2   -CONFIG_PPC=y
3   -CONFIG_MPC5xxx=y
4   -CONFIG_TARGET_ICECUBE=y
configs/icecube_5200_LOWBOOT08_defconfig
View file @ 37b608a
1   -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFF800000"
2   -CONFIG_PPC=y
3   -CONFIG_MPC5xxx=y
4   -CONFIG_TARGET_ICECUBE=y
configs/icecube_5200_LOWBOOT_defconfig
View file @ 37b608a
1   -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFF000000"
2   -CONFIG_PPC=y
3   -CONFIG_MPC5xxx=y
4   -CONFIG_TARGET_ICECUBE=y
configs/icecube_5200_defconfig
View file @ 37b608a
1   -CONFIG_PPC=y
2   -CONFIG_MPC5xxx=y
3   -CONFIG_TARGET_ICECUBE=y
configs/lite5200b_LOWBOOT_defconfig
View file @ 37b608a
1   -CONFIG_SYS_EXTRA_OPTIONS="MPC5200_DDR,LITE5200B,SYS_TEXT_BASE=0xFF000000"
2   -CONFIG_PPC=y
3   -CONFIG_MPC5xxx=y
4   -CONFIG_TARGET_ICECUBE=y
configs/lite5200b_PM_defconfig
View file @ 37b608a
1   -CONFIG_SYS_EXTRA_OPTIONS="MPC5200_DDR,LITE5200B,LITE5200B_PM"
2   -CONFIG_PPC=y
3   -CONFIG_MPC5xxx=y
4   -CONFIG_TARGET_ICECUBE=y
configs/lite5200b_defconfig
View file @ 37b608a
1   -CONFIG_SYS_EXTRA_OPTIONS="MPC5200_DDR,LITE5200B"
2   -CONFIG_PPC=y
3   -CONFIG_MPC5xxx=y
4   -CONFIG_TARGET_ICECUBE=y
configs/mecp5200_defconfig
View file @ 37b608a
1   -CONFIG_PPC=y
2   -CONFIG_MPC5xxx=y
3   -CONFIG_TARGET_MECP5200=y
configs/pf5200_defconfig
View file @ 37b608a
1   -CONFIG_PPC=y
2   -CONFIG_MPC5xxx=y
3   -CONFIG_TARGET_PF5200=y
doc/README.scrapyard
Diff comments   View file @ 37b608a
... ... @@ -12,6 +12,11 @@
12 12  
13 13 Board Arch CPU Commit Removed Last known maintainer/contact
14 14 =================================================================================================
  15 +icecube_5200 powerpc mpc5xxx - - Wolfgang Denk <wd@denx.de>
  16 +Lite5200 powerpc mpc5xxx - -
  17 +cpci5200 powerpc mpc5xxx - - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
  18 +mecp5200 powerpc mpc5xxx - - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
  19 +pf5200 powerpc mpc5xxx - - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
15 20 PM520 powerpc mpc5xxx - - Josef Wagner <Wagner@Microsys.de>
16 21 Total5200 powerpc mpc5xxx - -
17 22 CATcenter powerpc ppc4xx - -
include/configs/IceCube.h
View file @ 37b608a
1   -/*
2   - * (C) Copyright 2003-2005
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#ifndef __CONFIG_H
9   -#define __CONFIG_H
10   -
11   -/*
12   - * High Level Configuration Options
13   - * (easy to change)
14   - */
15   -
16   -#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */
17   -#define CONFIG_ICECUBE 1 /* ... on IceCube board */
18   -
19   -/*
20   - * Valid values for CONFIG_SYS_TEXT_BASE are:
21   - * 0xFFF00000 boot high (standard configuration)
22   - * 0xFF000000 boot low for 16 MiB boards
23   - * 0xFF800000 boot low for 8 MiB boards
24   - * 0x00100000 boot from RAM (for testing only)
25   - */
26   -#ifndef CONFIG_SYS_TEXT_BASE
27   -#define CONFIG_SYS_TEXT_BASE 0xFFF00000
28   -#endif
29   -
30   -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
31   -
32   -#define CONFIG_HIGH_BATS 1 /* High BATs supported */
33   -
34   -/*
35   - * Serial console configuration
36   - */
37   -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
38   -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
39   -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
40   -
41   -
42   -/*
43   - * PCI Mapping:
44   - * 0x40000000 - 0x4fffffff - PCI Memory
45   - * 0x50000000 - 0x50ffffff - PCI IO Space
46   - */
47   -#define CONFIG_PCI
48   -
49   -#if defined(CONFIG_PCI)
50   -#define CONFIG_PCI_PNP 1
51   -#define CONFIG_PCI_SCAN_SHOW 1
52   -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
53   -
54   -#define CONFIG_PCI_MEM_BUS 0x40000000
55   -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
56   -#define CONFIG_PCI_MEM_SIZE 0x10000000
57   -
58   -#define CONFIG_PCI_IO_BUS 0x50000000
59   -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
60   -#define CONFIG_PCI_IO_SIZE 0x01000000
61   -#endif
62   -
63   -#define CONFIG_SYS_XLB_PIPELINING 1
64   -
65   -#define CONFIG_MII 1
66   -#define CONFIG_EEPRO100 1
67   -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
68   -#define CONFIG_NS8382X 1
69   -
70   -/* Partitions */
71   -#define CONFIG_MAC_PARTITION
72   -#define CONFIG_DOS_PARTITION
73   -#define CONFIG_ISO_PARTITION
74   -
75   -/* USB */
76   -#define CONFIG_USB_OHCI_NEW
77   -#define CONFIG_USB_STORAGE
78   -#define CONFIG_SYS_OHCI_BE_CONTROLLER
79   -#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
80   -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
81   -#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
82   -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
83   -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
84   -
85   -#define CONFIG_TIMESTAMP /* Print image info with timestamp */
86   -
87   -
88   -/*
89   - * BOOTP options
90   - */
91   -#define CONFIG_BOOTP_BOOTFILESIZE
92   -#define CONFIG_BOOTP_BOOTPATH
93   -#define CONFIG_BOOTP_GATEWAY
94   -#define CONFIG_BOOTP_HOSTNAME
95   -
96   -
97   -/*
98   - * Command line configuration.
99   - */
100   -#include <config_cmd_default.h>
101   -
102   -#define CONFIG_CMD_EEPROM
103   -#define CONFIG_CMD_FAT
104   -#define CONFIG_CMD_I2C
105   -#define CONFIG_CMD_IDE
106   -#define CONFIG_CMD_NFS
107   -#define CONFIG_CMD_SNTP
108   -#define CONFIG_CMD_USB
109   -
110   -#if defined(CONFIG_PCI)
111   -#define CONFIG_CMD_PCI
112   -#endif
113   -
114   -
115   -#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
116   -# define CONFIG_SYS_LOWBOOT 1
117   -# define CONFIG_SYS_LOWBOOT16 1
118   -#endif
119   -#if (CONFIG_SYS_TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
120   -#if defined(CONFIG_LITE5200B)
121   -# error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B
122   -#else
123   -# define CONFIG_SYS_LOWBOOT 1
124   -# define CONFIG_SYS_LOWBOOT08 1
125   -#endif
126   -#endif
127   -
128   -/*
129   - * Autobooting
130   - */
131   -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
132   -
133   -#define CONFIG_PREBOOT "echo;" \
134   - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
135   - "echo"
136   -
137   -#undef CONFIG_BOOTARGS
138   -
139   -#define CONFIG_EXTRA_ENV_SETTINGS \
140   - "netdev=eth0\0" \
141   - "nfsargs=setenv bootargs root=/dev/nfs rw " \
142   - "nfsroot=${serverip}:${rootpath}\0" \
143   - "ramargs=setenv bootargs root=/dev/ram rw\0" \
144   - "addip=setenv bootargs ${bootargs} " \
145   - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
146   - ":${hostname}:${netdev}:off panic=1\0" \
147   - "flash_nfs=run nfsargs addip;" \
148   - "bootm ${kernel_addr}\0" \
149   - "flash_self=run ramargs addip;" \
150   - "bootm ${kernel_addr} ${ramdisk_addr}\0" \
151   - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
152   - "rootpath=/opt/eldk/ppc_82xx\0" \
153   - "bootfile=/tftpboot/MPC5200/uImage\0" \
154   - ""
155   -
156   -#define CONFIG_BOOTCOMMAND "run flash_self"
157   -
158   -/*
159   - * IPB Bus clocking configuration.
160   - */
161   -#if defined(CONFIG_LITE5200B)
162   -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
163   -#else
164   -#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
165   -#endif
166   -
167   -/* pass open firmware flat tree */
168   -#define CONFIG_OF_LIBFDT 1
169   -#define CONFIG_OF_BOARD_SETUP 1
170   -
171   -#define OF_CPU "PowerPC,5200@0"
172   -#define OF_SOC "soc5200@f0000000"
173   -#define OF_TBCLK (bd->bi_busfreq / 4)
174   -#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
175   -
176   -/*
177   - * I2C configuration
178   - */
179   -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
180   -#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
181   -
182   -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
183   -#define CONFIG_SYS_I2C_SLAVE 0x7F
184   -
185   -/*
186   - * EEPROM configuration
187   - */
188   -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
189   -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
190   -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
191   -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
192   -
193   -/*
194   - * Flash configuration
195   - */
196   -#if defined(CONFIG_LITE5200B)
197   -#define CONFIG_SYS_FLASH_BASE 0xFE000000
198   -#define CONFIG_SYS_FLASH_SIZE 0x01000000
199   -#if !defined(CONFIG_SYS_LOWBOOT)
200   -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x01760000 + 0x00800000)
201   -#else /* CONFIG_SYS_LOWBOOT */
202   -#if defined(CONFIG_SYS_LOWBOOT08)
203   -# error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B
204   -#endif
205   -#if defined(CONFIG_SYS_LOWBOOT16)
206   -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x01060000)
207   -#endif
208   -#endif /* CONFIG_SYS_LOWBOOT */
209   -#else /* !CONFIG_LITE5200B (IceCube)*/
210   -#define CONFIG_SYS_FLASH_BASE 0xFF000000
211   -#define CONFIG_SYS_FLASH_SIZE 0x01000000
212   -#if !defined(CONFIG_SYS_LOWBOOT)
213   -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00740000 + 0x00800000)
214   -#else /* CONFIG_SYS_LOWBOOT */
215   -#if defined(CONFIG_SYS_LOWBOOT08)
216   -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000 + 0x00800000)
217   -#endif
218   -#if defined(CONFIG_SYS_LOWBOOT16)
219   -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
220   -#endif
221   -#endif /* CONFIG_SYS_LOWBOOT */
222   -#endif /* CONFIG_LITE5200B */
223   -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */
224   -
225   -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
226   -
227   -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
228   -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
229   -
230   -#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
231   -
232   -#if defined(CONFIG_LITE5200B)
233   -#define CONFIG_FLASH_CFI_DRIVER
234   -#define CONFIG_SYS_FLASH_CFI
235   -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_CS1_START,CONFIG_SYS_CS0_START}
236   -#endif
237   -
238   -
239   -/*
240   - * Environment settings
241   - */
242   -#define CONFIG_ENV_IS_IN_FLASH 1
243   -#define CONFIG_ENV_SIZE 0x10000
244   -#if defined(CONFIG_LITE5200B)
245   -#define CONFIG_ENV_SECT_SIZE 0x20000
246   -#else
247   -#define CONFIG_ENV_SECT_SIZE 0x10000
248   -#endif
249   -#define CONFIG_ENV_OVERWRITE 1
250   -
251   -/*
252   - * Memory map
253   - */
254   -#define CONFIG_SYS_MBAR 0xF0000000
255   -#define CONFIG_SYS_SDRAM_BASE 0x00000000
256   -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
257   -
258   -/* Use SRAM until RAM will be available */
259   -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
260   -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
261   -
262   -
263   -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
264   -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
265   -
266   -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
267   -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
268   -# define CONFIG_SYS_RAMBOOT 1
269   -#endif
270   -
271   -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
272   -#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
273   -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
274   -
275   -/*
276   - * Ethernet configuration
277   - */
278   -#define CONFIG_MPC5xxx_FEC 1
279   -#define CONFIG_MPC5xxx_FEC_MII100
280   -/*
281   - * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
282   - */
283   -/* #define CONFIG_MPC5xxx_FEC_MII10 */
284   -#define CONFIG_PHY_ADDR 0x00
285   -
286   -/*
287   - * GPIO configuration
288   - */
289   -#ifdef CONFIG_MPC5200_DDR
290   -#define CONFIG_SYS_GPS_PORT_CONFIG 0x90000004
291   -#else
292   -#define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004
293   -#endif
294   -
295   -/*
296   - * Miscellaneous configurable options
297   - */
298   -#define CONFIG_SYS_LONGHELP /* undef to save memory */
299   -#if defined(CONFIG_CMD_KGDB)
300   -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
301   -#else
302   -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
303   -#endif
304   -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
305   -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
306   -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
307   -
308   -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
309   -#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
310   -
311   -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
312   -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
313   -
314   -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
315   -
316   -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
317   -#if defined(CONFIG_CMD_KGDB)
318   -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
319   -#endif
320   -
321   -/*
322   - * Various low-level settings
323   - */
324   -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
325   -#define CONFIG_SYS_HID0_FINAL HID0_ICE
326   -
327   -#if defined(CONFIG_LITE5200B)
328   -#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE
329   -#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE
330   -#define CONFIG_SYS_CS1_CFG 0x00047800
331   -#define CONFIG_SYS_CS0_START (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE)
332   -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
333   -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_CS0_START
334   -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
335   -#define CONFIG_SYS_BOOTCS_CFG 0x00047800
336   -#else /* IceCube aka Lite5200 */
337   -#ifdef CONFIG_MPC5200_DDR
338   -
339   -#define CONFIG_SYS_BOOTCS_START (CONFIG_SYS_CS1_START + CONFIG_SYS_CS1_SIZE)
340   -#define CONFIG_SYS_BOOTCS_SIZE 0x00800000
341   -#define CONFIG_SYS_BOOTCS_CFG 0x00047801
342   -#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE
343   -#define CONFIG_SYS_CS1_SIZE 0x00800000
344   -#define CONFIG_SYS_CS1_CFG 0x00047800
345   -
346   -#else /* !CONFIG_MPC5200_DDR */
347   -
348   -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
349   -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
350   -#define CONFIG_SYS_BOOTCS_CFG 0x00047801
351   -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
352   -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
353   -
354   -#endif /* CONFIG_MPC5200_DDR */
355   -#endif /*CONFIG_LITE5200B */
356   -
357   -#define CONFIG_SYS_CS_BURST 0x00000000
358   -#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
359   -
360   -#define CONFIG_SYS_RESET_ADDRESS 0xff000000
361   -
362   -/*-----------------------------------------------------------------------
363   - * USB stuff
364   - *-----------------------------------------------------------------------
365   - */
366   -#define CONFIG_USB_CLOCK 0x0001BBBB
367   -#define CONFIG_USB_CONFIG 0x00001000
368   -
369   -/*-----------------------------------------------------------------------
370   - * IDE/ATA stuff Supports IDE harddisk
371   - *-----------------------------------------------------------------------
372   - */
373   -
374   -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
375   -
376   -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
377   -#undef CONFIG_IDE_LED /* LED for ide not supported */
378   -
379   -#define CONFIG_IDE_RESET /* reset for ide supported */
380   -#define CONFIG_IDE_PREINIT
381   -
382   -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
383   -#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
384   -
385   -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
386   -
387   -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
388   -
389   -/* Offset for data I/O */
390   -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
391   -
392   -/* Offset for normal register accesses */
393   -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
394   -
395   -/* Offset for alternate registers */
396   -#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
397   -
398   -/* Interval between registers */
399   -#define CONFIG_SYS_ATA_STRIDE 4
400   -
401   -#define CONFIG_ATAPI 1
402   -
403   -#endif /* __CONFIG_H */
include/configs/cpci5200.h
View file @ 37b608a
1   -/*
2   - * (C) Copyright 2003-2004
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   -
7   - */
8   -
9   -/*************************************************************************
10   - * (c) 2005 esd gmbh Hannover
11   - *
12   - *
13   - * from IceCube.h file
14   - * by Reinhard Arlt reinhard.arlt@esd-electronics.com
15   - *
16   - *************************************************************************/
17   -
18   -#ifndef __CONFIG_H
19   -#define __CONFIG_H
20   -
21   -/*
22   - * High Level Configuration Options
23   - * (easy to change)
24   - */
25   -
26   -#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
27   -#define CONFIG_ICECUBE 1 /* ... on IceCube board */
28   -#define CONFIG_CPCI5200 1 /* ... on CPCI5200 board */
29   -#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
30   -
31   -#ifndef CONFIG_SYS_TEXT_BASE
32   -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* Standard: boot high */
33   -#endif
34   -
35   -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
36   -
37   -#define CONFIG_HIGH_BATS 1 /* High BATs supported */
38   -
39   -/*
40   - * Serial console configuration
41   - */
42   -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
43   -#define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */
44   -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
45   -
46   -/*
47   - * PCI Mapping:
48   - * 0x40000000 - 0x4fffffff - PCI Memory
49   - * 0x50000000 - 0x50ffffff - PCI IO Space
50   - */
51   -#if 1
52   -#define CONFIG_PCI 1
53   -#if 1
54   -#define CONFIG_PCI_PNP 1
55   -#endif
56   -#define CONFIG_PCI_SCAN_SHOW 1
57   -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
58   -
59   -#define CONFIG_PCI_MEM_BUS 0x40000000
60   -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
61   -#define CONFIG_PCI_MEM_SIZE 0x10000000
62   -
63   -#define CONFIG_PCI_IO_BUS 0x50000000
64   -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
65   -#define CONFIG_PCI_IO_SIZE 0x01000000
66   -#endif
67   -
68   -#define CONFIG_MII
69   -#if 0 /* test-only !!! */
70   -#define CONFIG_EEPRO100 1
71   -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
72   -#define CONFIG_NS8382X 1
73   -#endif
74   -
75   -/* Partitions */
76   -#define CONFIG_MAC_PARTITION
77   -#define CONFIG_DOS_PARTITION
78   -
79   -/* USB */
80   -#if 0
81   -#define CONFIG_USB_OHCI
82   -#define CONFIG_USB_STORAGE
83   -#endif
84   -
85   -/*
86   - * BOOTP options
87   - */
88   -#define CONFIG_BOOTP_BOOTFILESIZE
89   -#define CONFIG_BOOTP_BOOTPATH
90   -#define CONFIG_BOOTP_GATEWAY
91   -#define CONFIG_BOOTP_HOSTNAME
92   -
93   -
94   -/*
95   - * Command line configuration.
96   - */
97   -#include <config_cmd_default.h>
98   -
99   -#if defined(CONFIG_PCI)
100   -#define CONFIG_CMD_PCI
101   -#endif
102   -
103   -#define CONFIG_CMD_EEPROM
104   -#define CONFIG_CMD_FAT
105   -#define CONFIG_CMD_IDE
106   -#define CONFIG_CMD_I2C
107   -#define CONFIG_CMD_BSP
108   -#define CONFIG_CMD_ELF
109   -#define CONFIG_CMD_EXT2
110   -#define CONFIG_CMD_DATE
111   -
112   -#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
113   -# define CONFIG_SYS_LOWBOOT 1
114   -# define CONFIG_SYS_LOWBOOT16 1
115   -#endif
116   -#if (CONFIG_SYS_TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
117   -# define CONFIG_SYS_LOWBOOT 1
118   -# define CONFIG_SYS_LOWBOOT08 1
119   -#endif
120   -
121   -/*
122   - * Autobooting
123   - */
124   -#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
125   -
126   -#define CONFIG_PREBOOT "echo;" \
127   - "echo Welcome to esd CPU CPCI/5200;" \
128   - "echo"
129   -
130   -#undef CONFIG_BOOTARGS
131   -
132   -#define CONFIG_EXTRA_ENV_SETTINGS \
133   - "netdev=eth0\0" \
134   - "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
135   - "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
136   - "net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \
137   - "vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \
138   - "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \
139   - "loadaddr=01000000\0" \
140   - "serverip=192.168.2.99\0" \
141   - "gatewayip=10.0.0.79\0" \
142   - "user=mu\0" \
143   - "target=cpci5200.esd\0" \
144   - "script=cpci5200.bat\0" \
145   - "image=/tftpboot/vxWorks_cpci5200\0" \
146   - "ipaddr=10.0.13.196\0" \
147   - "netmask=255.255.0.0\0" \
148   - ""
149   -
150   -#define CONFIG_BOOTCOMMAND "run flash_vxworks0"
151   -
152   -#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
153   -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xfd010000
154   -#define CONFIG_SYS_NVRAM_SIZE 32*1024
155   -
156   -/*
157   - * IPB Bus clocking configuration.
158   - */
159   -#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
160   -/*
161   - * I2C configuration
162   - */
163   -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
164   -#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 or #2 */
165   -
166   -#define CONFIG_SYS_I2C_SPEED 86000 /* 100 kHz */
167   -#define CONFIG_SYS_I2C_SLAVE 0x7F
168   -
169   -/*
170   - * EEPROM configuration
171   - */
172   -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
173   -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
174   -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
175   -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
176   -#define CONFIG_SYS_I2C_MULTI_EEPROMS 1
177   -/*
178   - * Flash configuration
179   - */
180   -
181   -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
182   -#define CONFIG_SYS_FLASH_BASE 0xFE000000
183   -#define CONFIG_SYS_FLASH_SIZE 0x02000000
184   -#define CONFIG_SYS_FLASH_INCREMENT 0x01000000
185   -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00000000)
186   -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */
187   -#define CONFIG_SYS_MAX_FLASH_SECT 128
188   -
189   -#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */
190   -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
191   -
192   -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
193   -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
194   -
195   -/*
196   - * Environment settings
197   - */
198   -#if 1 /* test-only */
199   -#define CONFIG_ENV_IS_IN_FLASH 1
200   -#define CONFIG_ENV_SIZE 0x20000
201   -#define CONFIG_ENV_SECT_SIZE 0x20000
202   -#define CONFIG_ENV_OVERWRITE 1
203   -#else
204   -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
205   -#define CONFIG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */
206   -#define CONFIG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars */
207   - /* total size of a CAT24WC32 is 8192 bytes */
208   -#define CONFIG_ENV_OVERWRITE 1
209   -#endif
210   -
211   -/*
212   - * Memory map
213   - */
214   -#define CONFIG_SYS_MBAR 0xF0000000
215   -#define CONFIG_SYS_SDRAM_BASE 0x00000000
216   -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
217   -
218   -/* Use SRAM until RAM will be available */
219   -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
220   -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
221   -
222   -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
223   -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
224   -
225   -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
226   -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
227   -# define CONFIG_SYS_RAMBOOT 1
228   -#endif
229   -
230   -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
231   -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
232   -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
233   -
234   -/*
235   - * Ethernet configuration
236   - */
237   -#define CONFIG_MPC5xxx_FEC 1
238   -#define CONFIG_MPC5xxx_FEC_MII100
239   -/*
240   - * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
241   - */
242   -/* #define CONFIG_FEC_10MBIT 1 */
243   -#define CONFIG_PHY_ADDR 0x00
244   -#define CONFIG_UDP_CHECKSUM 1
245   -
246   -/*
247   - * GPIO configuration
248   - */
249   -#define CONFIG_SYS_GPS_PORT_CONFIG 0x01052444
250   -
251   -/*
252   - * Miscellaneous configurable options
253   - */
254   -#define CONFIG_SYS_LONGHELP /* undef to save memory */
255   -#if defined(CONFIG_CMD_KGDB)
256   -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
257   -#else
258   -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
259   -#endif
260   -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
261   -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
262   -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
263   -
264   -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
265   -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
266   -
267   -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
268   -
269   -#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
270   -
271   -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
272   -#if defined(CONFIG_CMD_KGDB)
273   -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
274   -#endif
275   -
276   -/*
277   - * Various low-level settings
278   - */
279   -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
280   -#define CONFIG_SYS_HID0_FINAL HID0_ICE
281   -
282   -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
283   -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
284   -#define CONFIG_SYS_BOOTCS_CFG 0x0004DD00
285   -
286   -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
287   -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
288   -
289   -#define CONFIG_SYS_CS1_START 0xfd000000
290   -#define CONFIG_SYS_CS1_SIZE 0x00010000
291   -#define CONFIG_SYS_CS1_CFG 0x10101410
292   -
293   -#define CONFIG_SYS_CS3_START 0xfd010000
294   -#define CONFIG_SYS_CS3_SIZE 0x00010000
295   -#define CONFIG_SYS_CS3_CFG 0x10109410
296   -
297   -#define CONFIG_SYS_CS_BURST 0x00000000
298   -#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
299   -
300   -#define CONFIG_SYS_RESET_ADDRESS 0xff000000
301   -
302   -/*-----------------------------------------------------------------------
303   - * USB stuff
304   - *-----------------------------------------------------------------------
305   - */
306   -#define CONFIG_USB_CLOCK 0x0001BBBB
307   -#define CONFIG_USB_CONFIG 0x00001000
308   -
309   -/*-----------------------------------------------------------------------
310   - * IDE/ATA stuff Supports IDE harddisk
311   - *-----------------------------------------------------------------------
312   - */
313   -
314   -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
315   -
316   -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
317   -#undef CONFIG_IDE_LED /* LED for ide not supported */
318   -
319   -#define CONFIG_IDE_RESET /* reset for ide supported */
320   -#define CONFIG_IDE_PREINIT
321   -
322   -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
323   -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
324   -
325   -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
326   -
327   -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
328   -
329   -/* Offset for data I/O */
330   -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
331   -
332   -/* Offset for normal register accesses */
333   -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
334   -
335   -/* Offset for alternate registers */
336   -#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
337   -
338   -/* Interval between registers */
339   -#define CONFIG_SYS_ATA_STRIDE 4
340   -
341   -/*-----------------------------------------------------------------------
342   - * CPLD stuff
343   - */
344   -#define CONFIG_SYS_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */
345   -#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */
346   -
347   -/* CPLD program pin configuration */
348   -#define CONFIG_SYS_FPGA_PRG 0x20000000 /* JTAG TMS pin (ppc output) */
349   -#define CONFIG_SYS_FPGA_CLK 0x10000000 /* JTAG TCK pin (ppc output) */
350   -#define CONFIG_SYS_FPGA_DATA 0x20000000 /* JTAG TDO->TDI data pin (ppc output) */
351   -#define CONFIG_SYS_FPGA_DONE 0x10000000 /* JTAG TDI->TDO pin (ppc input) */
352   -
353   -#define JTAG_GPIO_ADDR_TMS (CONFIG_SYS_MBAR + 0xB10) /* JTAG TMS pin (GPS data out value reg.) */
354   -#define JTAG_GPIO_ADDR_TCK (CONFIG_SYS_MBAR + 0xC0C) /* JTAG TCK pin (GPW data out value reg.) */
355   -#define JTAG_GPIO_ADDR_TDI (CONFIG_SYS_MBAR + 0xC0C) /* JTAG TDO->TDI pin (GPW data out value reg.) */
356   -#define JTAG_GPIO_ADDR_TDO (CONFIG_SYS_MBAR + 0xB14) /* JTAG TDI->TDO pin (GPS data in value reg.) */
357   -
358   -#define JTAG_GPIO_ADDR_CFG (CONFIG_SYS_MBAR + 0xB00)
359   -#define JTAG_GPIO_CFG_SET 0x00000000
360   -#define JTAG_GPIO_CFG_RESET 0x00F00000
361   -
362   -#define JTAG_GPIO_ADDR_EN_TMS (CONFIG_SYS_MBAR + 0xB04)
363   -#define JTAG_GPIO_TMS_EN_SET 0x20000000 /* Enable for GPIO */
364   -#define JTAG_GPIO_TMS_EN_RESET 0x00000000
365   -#define JTAG_GPIO_ADDR_DDR_TMS (CONFIG_SYS_MBAR + 0xB0C)
366   -#define JTAG_GPIO_TMS_DDR_SET 0x20000000 /* Set as output */
367   -#define JTAG_GPIO_TMS_DDR_RESET 0x00000000
368   -
369   -#define JTAG_GPIO_ADDR_EN_TCK (CONFIG_SYS_MBAR + 0xC00)
370   -#define JTAG_GPIO_TCK_EN_SET 0x20000000 /* Enable for GPIO */
371   -#define JTAG_GPIO_TCK_EN_RESET 0x00000000
372   -#define JTAG_GPIO_ADDR_DDR_TCK (CONFIG_SYS_MBAR + 0xC08)
373   -#define JTAG_GPIO_TCK_DDR_SET 0x20000000 /* Set as output */
374   -#define JTAG_GPIO_TCK_DDR_RESET 0x00000000
375   -
376   -#define JTAG_GPIO_ADDR_EN_TDI (CONFIG_SYS_MBAR + 0xC00)
377   -#define JTAG_GPIO_TDI_EN_SET 0x10000000 /* Enable as GPIO */
378   -#define JTAG_GPIO_TDI_EN_RESET 0x00000000
379   -#define JTAG_GPIO_ADDR_DDR_TDI (CONFIG_SYS_MBAR + 0xC08)
380   -#define JTAG_GPIO_TDI_DDR_SET 0x10000000 /* Set as output */
381   -#define JTAG_GPIO_TDI_DDR_RESET 0x00000000
382   -
383   -#define JTAG_GPIO_ADDR_EN_TDO (CONFIG_SYS_MBAR + 0xB04)
384   -#define JTAG_GPIO_TDO_EN_SET 0x10000000 /* Enable as GPIO */
385   -#define JTAG_GPIO_TDO_EN_RESET 0x00000000
386   -#define JTAG_GPIO_ADDR_DDR_TDO (CONFIG_SYS_MBAR + 0xB0C)
387   -#define JTAG_GPIO_TDO_DDR_SET 0x00000000
388   -#define JTAG_GPIO_TDO_DDR_RESET 0x10000000 /* Set as input */
389   -
390   -#endif /* __CONFIG_H */
include/configs/mecp5200.h
View file @ 37b608a
1   -/*
2   - * (C) Copyright 2003-2004
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -
9   -/*************************************************************************
10   - * (c) 2005 esd gmbh Hannover
11   - *
12   - *
13   - * from IceCube.h file
14   - * by Reinhard Arlt reinhard.arlt@esd-electronics.com
15   - *
16   - *************************************************************************/
17   -
18   -#ifndef __CONFIG_H
19   -#define __CONFIG_H
20   -
21   -/*
22   - * High Level Configuration Options
23   - * (easy to change)
24   - */
25   -
26   -#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
27   -#define CONFIG_ICECUBE 1 /* ... on IceCube board */
28   -#define CONFIG_MECP5200 1 /* ... on MECP5200 board */
29   -#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
30   -
31   -#ifndef CONFIG_SYS_TEXT_BASE
32   -#define CONFIG_SYS_TEXT_BASE 0xFFF00000
33   -#endif
34   -
35   -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
36   -
37   -#define CONFIG_HIGH_BATS 1 /* High BATs supported */
38   -
39   -/*
40   - * Serial console configuration
41   - */
42   -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
43   -#if 0 /* test-only */
44   -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
45   -#else
46   -#define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */
47   -#endif
48   -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
49   -
50   -#define CONFIG_MII
51   -#if 0 /* test-only !!! */
52   -#define CONFIG_EEPRO100 1
53   -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
54   -#define CONFIG_NS8382X 1
55   -#endif
56   -
57   -/* Partitions */
58   -#define CONFIG_MAC_PARTITION
59   -#define CONFIG_DOS_PARTITION
60   -
61   -/* USB */
62   -#if 0
63   -#define CONFIG_USB_OHCI
64   -#define CONFIG_USB_STORAGE
65   -#endif
66   -
67   -
68   -/*
69   - * BOOTP options
70   - */
71   -#define CONFIG_BOOTP_BOOTFILESIZE
72   -#define CONFIG_BOOTP_BOOTPATH
73   -#define CONFIG_BOOTP_GATEWAY
74   -#define CONFIG_BOOTP_HOSTNAME
75   -
76   -
77   -/*
78   - * Command line configuration.
79   - */
80   -#include <config_cmd_default.h>
81   -
82   -#define CONFIG_CMD_EEPROM
83   -#define CONFIG_CMD_FAT
84   -#define CONFIG_CMD_EXT2
85   -#define CONFIG_CMD_I2C
86   -#define CONFIG_CMD_IDE
87   -#define CONFIG_CMD_BSP
88   -#define CONFIG_CMD_ELF
89   -
90   -
91   -#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
92   -# define CONFIG_SYS_LOWBOOT 1
93   -# define CONFIG_SYS_LOWBOOT16 1
94   -#endif
95   -#if (CONFIG_SYS_TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
96   -# define CONFIG_SYS_LOWBOOT 1
97   -# define CONFIG_SYS_LOWBOOT08 1
98   -#endif
99   -
100   -/*
101   - * Autobooting
102   - */
103   -#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
104   -
105   -#define CONFIG_PREBOOT "echo;" \
106   - "echo Welcome to CBX-CPU5200 (mecp5200);" \
107   - "echo"
108   -
109   -#undef CONFIG_BOOTARGS
110   -
111   -#define CONFIG_EXTRA_ENV_SETTINGS \
112   - "netdev=eth0\0" \
113   - "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
114   - "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
115   - "net_vxworks=tftp $(loadaddr) $(image);run vxworks_args;bootvx\0" \
116   - "vxworks_args=setenv bootargs fec(0,0)$(host):$(image) h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script)\0" \
117   - "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script) o=fec0 \0" \
118   - "loadaddr=01000000\0" \
119   - "serverip=192.168.2.99\0" \
120   - "gatewayip=10.0.0.79\0" \
121   - "user=mu\0" \
122   - "target=mecp5200.esd\0" \
123   - "script=mecp5200.bat\0" \
124   - "image=/tftpboot/vxWorks_mecp5200\0" \
125   - "ipaddr=10.0.13.196\0" \
126   - "netmask=255.255.0.0\0" \
127   - ""
128   -
129   -#define CONFIG_BOOTCOMMAND "run flash_vxworks0"
130   -
131   -/*
132   - * IPB Bus clocking configuration.
133   - */
134   -#undef CONFIG_SYS_IPBSPEED_133 /* define for 133MHz speed */
135   -/*
136   - * I2C configuration
137   - */
138   -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
139   -#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
140   -
141   -#define CONFIG_SYS_I2C_SPEED 86000 /* 100 kHz */
142   -#define CONFIG_SYS_I2C_SLAVE 0x7F
143   -
144   -/*
145   - * EEPROM configuration
146   - */
147   -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
148   -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
149   -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
150   -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
151   -#define CONFIG_SYS_I2C_MULTI_EEPROMS 1
152   -/*
153   - * Flash configuration
154   - */
155   -#define CONFIG_SYS_FLASH_BASE 0xFFC00000
156   -#define CONFIG_SYS_FLASH_SIZE 0x00400000
157   -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x003E0000)
158   -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
159   -#define CONFIG_SYS_MAX_FLASH_SECT 512
160   -
161   -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
162   -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
163   -
164   -/*
165   - * Environment settings
166   - */
167   -#if 1 /* test-only */
168   -#define CONFIG_ENV_IS_IN_FLASH 1
169   -#define CONFIG_ENV_SIZE 0x10000
170   -#define CONFIG_ENV_SECT_SIZE 0x10000
171   -#define CONFIG_ENV_OVERWRITE 1
172   -#else
173   -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
174   -#define CONFIG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */
175   -#define CONFIG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars*/
176   - /* total size of a CAT24WC32 is 8192 bytes */
177   -#define CONFIG_ENV_OVERWRITE 1
178   -#endif
179   -
180   -#define CONFIG_FLASH_CFI_DRIVER 1 /* Flash is CFI conformant */
181   -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
182   -#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */
183   -#if 0
184   -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
185   -#endif
186   -#define CONFIG_SYS_FLASH_INCREMENT 0x00400000 /* size of flash bank */
187   -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
188   -#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* show if bank is empty */
189   -
190   -
191   -/*
192   - * Memory map
193   - */
194   -#define CONFIG_SYS_MBAR 0xF0000000
195   -#define CONFIG_SYS_SDRAM_BASE 0x00000000
196   -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
197   -
198   -/* Use SRAM until RAM will be available */
199   -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
200   -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
201   -
202   -
203   -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
204   -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
205   -
206   -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
207   -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
208   -# define CONFIG_SYS_RAMBOOT 1
209   -#endif
210   -
211   -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
212   -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
213   -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
214   -
215   -/*
216   - * Ethernet configuration
217   - */
218   -#define CONFIG_MPC5xxx_FEC 1
219   -#define CONFIG_MPC5xxx_FEC_MII100
220   -/*
221   - * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
222   - */
223   -/* #define CONFIG_MPC5xxx_FEC_MII10 */
224   -#define CONFIG_PHY_ADDR 0x00
225   -#define CONFIG_UDP_CHECKSUM 1
226   -
227   -
228   -/*
229   - * GPIO configuration
230   - */
231   -#define CONFIG_SYS_GPS_PORT_CONFIG 0x01052444
232   -
233   -/*
234   - * Miscellaneous configurable options
235   - */
236   -#define CONFIG_SYS_LONGHELP /* undef to save memory */
237   -#if defined(CONFIG_CMD_KGDB)
238   -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
239   -#else
240   -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
241   -#endif
242   -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
243   -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
244   -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
245   -
246   -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
247   -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
248   -
249   -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
250   -
251   -#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
252   -
253   -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
254   -#if defined(CONFIG_CMD_KGDB)
255   -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
256   -#endif
257   -
258   -/*
259   - * Various low-level settings
260   - */
261   -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
262   -#define CONFIG_SYS_HID0_FINAL HID0_ICE
263   -
264   -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
265   -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
266   -#define CONFIG_SYS_BOOTCS_CFG 0x00085d00
267   -
268   -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
269   -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
270   -
271   -#define CONFIG_SYS_CS1_START 0xfd000000
272   -#define CONFIG_SYS_CS1_SIZE 0x00010000
273   -#define CONFIG_SYS_CS1_CFG 0x10101410
274   -
275   -#define CONFIG_SYS_CS_BURST 0x00000000
276   -#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
277   -
278   -#define CONFIG_SYS_RESET_ADDRESS 0xff000000
279   -
280   -/*-----------------------------------------------------------------------
281   - * USB stuff
282   - *-----------------------------------------------------------------------
283   - */
284   -#define CONFIG_USB_CLOCK 0x0001BBBB
285   -#define CONFIG_USB_CONFIG 0x00001000
286   -
287   -/*-----------------------------------------------------------------------
288   - * IDE/ATA stuff Supports IDE harddisk
289   - *-----------------------------------------------------------------------
290   - */
291   -
292   -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
293   -
294   -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
295   -#undef CONFIG_IDE_LED /* LED for ide not supported */
296   -
297   -#define CONFIG_IDE_RESET /* reset for ide supported */
298   -#define CONFIG_IDE_PREINIT
299   -
300   -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
301   -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
302   -
303   -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
304   -
305   -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
306   -
307   -/* Offset for data I/O */
308   -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
309   -
310   -/* Offset for normal register accesses */
311   -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
312   -
313   -/* Offset for alternate registers */
314   -#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
315   -
316   -/* Interval between registers */
317   -#define CONFIG_SYS_ATA_STRIDE 4
318   -
319   -#endif /* __CONFIG_H */
include/configs/pf5200.h
View file @ 37b608a
1   -/*
2   - * (C) Copyright 2003-2004
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -/*************************************************************************
9   - * (c) 2005 esd gmbh Hannover
10   - *
11   - *
12   - * from IceCube.h file
13   - * by Reinhard Arlt reinhard.arlt@esd-electronics.com
14   - *
15   - *************************************************************************/
16   -
17   -#ifndef __CONFIG_H
18   -#define __CONFIG_H
19   -
20   -/*
21   - * High Level Configuration Options
22   - * (easy to change)
23   - */
24   -
25   -#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
26   -#define CONFIG_ICECUBE 1 /* ... on IceCube board */
27   -#define CONFIG_PF5200 1 /* ... on PF5200 board */
28   -#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
29   -
30   -#ifndef CONFIG_SYS_TEXT_BASE
31   -#define CONFIG_SYS_TEXT_BASE 0xFFF00000
32   -#endif
33   -
34   -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
35   -
36   -#define CONFIG_HIGH_BATS 1 /* High BATs supported */
37   -/*
38   - * Serial console configuration
39   - */
40   -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
41   -#if 0 /* test-only */
42   -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
43   -#else
44   -#define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */
45   -#endif
46   -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
47   -
48   -/*
49   - * PCI Mapping:
50   - * 0x40000000 - 0x4fffffff - PCI Memory
51   - * 0x50000000 - 0x50ffffff - PCI IO Space
52   - */
53   -#define CONFIG_PCI 1
54   -#define CONFIG_PCI_PNP 1
55   -#define CONFIG_PCI_SCAN_SHOW 1
56   -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
57   -
58   -#define CONFIG_PCI_MEM_BUS 0x40000000
59   -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
60   -#define CONFIG_PCI_MEM_SIZE 0x10000000
61   -
62   -#define CONFIG_PCI_IO_BUS 0x50000000
63   -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
64   -#define CONFIG_PCI_IO_SIZE 0x01000000
65   -
66   -#define CONFIG_MII 1
67   -#if 0 /* test-only !!! */
68   -#define CONFIG_EEPRO100 1
69   -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
70   -#define CONFIG_NS8382X 1
71   -#endif
72   -
73   -/* Partitions */
74   -#define CONFIG_MAC_PARTITION
75   -#define CONFIG_DOS_PARTITION
76   -
77   -/* USB */
78   -#if 0
79   -#define CONFIG_USB_OHCI
80   -#define CONFIG_USB_STORAGE
81   -#endif
82   -
83   -
84   -/*
85   - * BOOTP options
86   - */
87   -#define CONFIG_BOOTP_BOOTFILESIZE
88   -#define CONFIG_BOOTP_BOOTPATH
89   -#define CONFIG_BOOTP_GATEWAY
90   -#define CONFIG_BOOTP_HOSTNAME
91   -
92   -
93   -/*
94   - * Command line configuration.
95   - */
96   -#include <config_cmd_default.h>
97   -
98   -#define CONFIG_CMD_BSP
99   -#define CONFIG_CMD_EEPROM
100   -#define CONFIG_CMD_ELF
101   -#define CONFIG_CMD_FAT
102   -#define CONFIG_CMD_I2C
103   -#define CONFIG_CMD_IDE
104   -
105   -#define CONFIG_CMD_PCI
106   -
107   -
108   -#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
109   -# define CONFIG_SYS_LOWBOOT 1
110   -# define CONFIG_SYS_LOWBOOT16 1
111   -#endif
112   -#if (CONFIG_SYS_TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
113   -# define CONFIG_SYS_LOWBOOT 1
114   -# define CONFIG_SYS_LOWBOOT08 1
115   -#endif
116   -
117   -/*
118   - * Autobooting
119   - */
120   -#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
121   -
122   -#define CONFIG_PREBOOT "echo;" \
123   - "echo Welcome to ParaFinder pf5200;" \
124   - "echo"
125   -
126   -#undef CONFIG_BOOTARGS
127   -
128   -#define CONFIG_EXTRA_ENV_SETTINGS \
129   - "netdev=eth0\0" \
130   - "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
131   - "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
132   - "net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \
133   - "vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \
134   - "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \
135   - "loadaddr=01000000\0" \
136   - "serverip=192.168.2.99\0" \
137   - "gatewayip=10.0.0.79\0" \
138   - "user=mu\0" \
139   - "target=pf5200.esd\0" \
140   - "script=pf5200.bat\0" \
141   - "image=/tftpboot/vxWorks_pf5200\0" \
142   - "ipaddr=10.0.13.196\0" \
143   - "netmask=255.255.0.0\0" \
144   - ""
145   -
146   -#define CONFIG_BOOTCOMMAND "run flash_vxworks0"
147   -
148   -/*
149   - * IPB Bus clocking configuration.
150   - */
151   -#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
152   -/*
153   - * I2C configuration
154   - */
155   -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
156   -#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
157   -
158   -#define CONFIG_SYS_I2C_SPEED 86000 /* 100 kHz */
159   -#define CONFIG_SYS_I2C_SLAVE 0x7F
160   -
161   -/*
162   - * EEPROM configuration
163   - */
164   -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
165   -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
166   -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
167   -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
168   -#define CONFIG_SYS_I2C_MULTI_EEPROMS 1
169   -/*
170   - * Flash configuration
171   - */
172   -#define CONFIG_SYS_FLASH_BASE 0xFE000000
173   -#define CONFIG_SYS_FLASH_SIZE 0x02000000
174   -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00000000)
175   -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
176   -#define CONFIG_SYS_MAX_FLASH_SECT 512
177   -
178   -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
179   -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
180   -
181   -/*
182   - * Environment settings
183   - */
184   -#if 1 /* test-only */
185   -#define CONFIG_ENV_IS_IN_FLASH
186   -#define CONFIG_ENV_SIZE 0x10000
187   -#define CONFIG_ENV_SECT_SIZE 0x10000
188   -#define CONFIG_ENV_OVERWRITE 1
189   -#else
190   -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
191   -#define CONFIG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */
192   -#define CONFIG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars */
193   - /* total size of a CAT24WC32 is 8192 bytes */
194   -#define CONFIG_ENV_OVERWRITE 1
195   -#endif
196   -
197   -/*
198   - * Memory map
199   - */
200   -#define CONFIG_SYS_MBAR 0xF0000000
201   -#define CONFIG_SYS_SDRAM_BASE 0x00000000
202   -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
203   -
204   -/* Use SRAM until RAM will be available */
205   -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
206   -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
207   -
208   -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
209   -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
210   -
211   -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
212   -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
213   -# define CONFIG_SYS_RAMBOOT 1
214   -#endif
215   -
216   -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
217   -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
218   -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
219   -
220   -/*
221   - * Ethernet configuration
222   - */
223   -#define CONFIG_MPC5xxx_FEC 1
224   -#define CONFIG_MPC5xxx_FEC_MII100
225   -/*
226   - * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
227   - */
228   -/* #define CONFIG_MPC5xxx_FEC_MII10 */
229   -#define CONFIG_PHY_ADDR 0x00
230   -#define CONFIG_UDP_CHECKSUM 1
231   -
232   -/*
233   - * GPIO configuration
234   - */
235   -#define CONFIG_SYS_GPS_PORT_CONFIG 0x01052444
236   -
237   -/*
238   - * Miscellaneous configurable options
239   - */
240   -#define CONFIG_SYS_LONGHELP /* undef to save memory */
241   -#if defined(CONFIG_CMD_KGDB)
242   -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
243   -#else
244   -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
245   -#endif
246   -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
247   -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
248   -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
249   -
250   -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
251   -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
252   -
253   -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
254   -
255   -#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
256   -
257   -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
258   -#if defined(CONFIG_CMD_KGDB)
259   -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
260   -#endif
261   -
262   -/*
263   - * Various low-level settings
264   - */
265   -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
266   -#define CONFIG_SYS_HID0_FINAL HID0_ICE
267   -
268   -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
269   -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
270   -#define CONFIG_SYS_BOOTCS_CFG 0x0004DD00
271   -
272   -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
273   -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
274   -
275   -#define CONFIG_SYS_CS1_START 0xfd000000
276   -#define CONFIG_SYS_CS1_SIZE 0x00010000
277   -#define CONFIG_SYS_CS1_CFG 0x10101410
278   -
279   -#define CONFIG_SYS_CS_BURST 0x00000000
280   -#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
281   -
282   -#define CONFIG_SYS_RESET_ADDRESS 0xff000000
283   -
284   -/*-----------------------------------------------------------------------
285   - * USB stuff
286   - *-----------------------------------------------------------------------
287   - */
288   -#define CONFIG_USB_CLOCK 0x0001BBBB
289   -#define CONFIG_USB_CONFIG 0x00001000
290   -
291   -/*-----------------------------------------------------------------------
292   - * IDE/ATA stuff Supports IDE harddisk
293   - *-----------------------------------------------------------------------
294   - */
295   -
296   -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
297   -
298   -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
299   -#undef CONFIG_IDE_LED /* LED for ide not supported */
300   -
301   -#define CONFIG_IDE_RESET /* reset for ide supported */
302   -#define CONFIG_IDE_PREINIT
303   -
304   -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
305   -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
306   -
307   -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
308   -
309   -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
310   -
311   -/* Offset for data I/O */
312   -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
313   -
314   -/* Offset for normal register accesses */
315   -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
316   -
317   -/* Offset for alternate registers */
318   -#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
319   -
320   -/* Interval between registers */
321   -#define CONFIG_SYS_ATA_STRIDE 4
322   -
323   -/*-----------------------------------------------------------------------
324   - * CPLD stuff
325   - */
326   -#define CONFIG_SYS_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */
327   -#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */
328   -
329   -/* CPLD program pin configuration */
330   -#define CONFIG_SYS_FPGA_PRG 0x20000000 /* JTAG TMS pin (ppc output) */
331   -#define CONFIG_SYS_FPGA_CLK 0x10000000 /* JTAG TCK pin (ppc output) */
332   -#define CONFIG_SYS_FPGA_DATA 0x20000000 /* JTAG TDO->TDI data pin (ppc output) */
333   -#define CONFIG_SYS_FPGA_DONE 0x10000000 /* JTAG TDI->TDO pin (ppc input) */
334   -
335   -#define JTAG_GPIO_ADDR_TMS (CONFIG_SYS_MBAR + 0xB10) /* JTAG TMS pin (GPS data out value reg.) */
336   -#define JTAG_GPIO_ADDR_TCK (CONFIG_SYS_MBAR + 0xC0C) /* JTAG TCK pin (GPW data out value reg.) */
337   -#define JTAG_GPIO_ADDR_TDI (CONFIG_SYS_MBAR + 0xC0C) /* JTAG TDO->TDI pin (GPW data out value reg.) */
338   -#define JTAG_GPIO_ADDR_TDO (CONFIG_SYS_MBAR + 0xB14) /* JTAG TDI->TDO pin (GPS data in value reg.) */
339   -
340   -#define JTAG_GPIO_ADDR_CFG (CONFIG_SYS_MBAR + 0xB00)
341   -#define JTAG_GPIO_CFG_SET 0x00000000
342   -#define JTAG_GPIO_CFG_RESET 0x00F00000
343   -
344   -#define JTAG_GPIO_ADDR_EN_TMS (CONFIG_SYS_MBAR + 0xB04)
345   -#define JTAG_GPIO_TMS_EN_SET 0x20000000 /* Enable for GPIO */
346   -#define JTAG_GPIO_TMS_EN_RESET 0x00000000
347   -#define JTAG_GPIO_ADDR_DDR_TMS (CONFIG_SYS_MBAR + 0xB0C)
348   -#define JTAG_GPIO_TMS_DDR_SET 0x20000000 /* Set as output */
349   -#define JTAG_GPIO_TMS_DDR_RESET 0x00000000
350   -
351   -#define JTAG_GPIO_ADDR_EN_TCK (CONFIG_SYS_MBAR + 0xC00)
352   -#define JTAG_GPIO_TCK_EN_SET 0x20000000 /* Enable for GPIO */
353   -#define JTAG_GPIO_TCK_EN_RESET 0x00000000
354   -#define JTAG_GPIO_ADDR_DDR_TCK (CONFIG_SYS_MBAR + 0xC08)
355   -#define JTAG_GPIO_TCK_DDR_SET 0x20000000 /* Set as output */
356   -#define JTAG_GPIO_TCK_DDR_RESET 0x00000000
357   -
358   -#define JTAG_GPIO_ADDR_EN_TDI (CONFIG_SYS_MBAR + 0xC00)
359   -#define JTAG_GPIO_TDI_EN_SET 0x10000000 /* Enable as GPIO */
360   -#define JTAG_GPIO_TDI_EN_RESET 0x00000000
361   -#define JTAG_GPIO_ADDR_DDR_TDI (CONFIG_SYS_MBAR + 0xC08)
362   -#define JTAG_GPIO_TDI_DDR_SET 0x10000000 /* Set as output */
363   -#define JTAG_GPIO_TDI_DDR_RESET 0x00000000
364   -
365   -#define JTAG_GPIO_ADDR_EN_TDO (CONFIG_SYS_MBAR + 0xB04)
366   -#define JTAG_GPIO_TDO_EN_SET 0x10000000 /* Enable as GPIO */
367   -#define JTAG_GPIO_TDO_EN_RESET 0x00000000
368   -#define JTAG_GPIO_ADDR_DDR_TDO (CONFIG_SYS_MBAR + 0xB0C)
369   -#define JTAG_GPIO_TDO_DDR_SET 0x00000000
370   -#define JTAG_GPIO_TDO_DDR_RESET 0x10000000 /* Set as input */
371   -
372   -#endif /* __CONFIG_H */