Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit 380e86f361e4e2aef83295972863654fde157560

Authored by Tom Rini
2 parents 8dc1b17f14 7676074ac7
Exists in smarc_8mq_lf_v2020.04 and in 20 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf-6.6.52-2.2.0, emb_lf_v2022.04, emb_lf_v2023.04, emb_lf_v2024.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

Merge git://git.denx.de/u-boot-fsl-qoriq

Showing 38 changed files Side-by-side Diff

... ... @@ -786,6 +786,20 @@
786 786 development platform that supports the QorIQ LS2080A
787 787 Layerscape Architecture processor.
788 788  
  789 +config TARGET_LS2081ARDB
  790 + bool "Support ls2081ardb"
  791 + select ARCH_LS2080A
  792 + select ARM64
  793 + select ARMV8_MULTIENTRY
  794 + select BOARD_LATE_INIT
  795 + select SUPPORT_SPL
  796 + select ARCH_MISC_INIT
  797 + help
  798 + Support for Freescale LS2081ARDB platform.
  799 + The LS2081A Reference design board (RDB) is a high-performance
  800 + development platform that supports the QorIQ LS2081A/LS2041A
  801 + Layerscape Architecture processor.
  802 +
789 803 config TARGET_HIKEY
790 804 bool "Support HiKey 96boards Consumer Edition Platform"
791 805 select ARM64
arch/arm/cpu/armv8/Kconfig
Diff comments   View file @ 380e86f
... ... @@ -91,6 +91,7 @@
91 91 !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
92 92 !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
93 93 !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
  94 + !TARGET_LS2081ARDB && \
94 95 !ARCH_UNIPHIER && !ARCH_SNAPDRAGON && !TARGET_S32V234EVB
95 96 help
96 97 Most armv8 systems have PSCI support enabled in EL3, either through
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
Diff comments   View file @ 380e86f
... ... @@ -163,11 +163,12 @@
163 163 config SYS_LS_PPA_FW_ADDR
164 164 hex "Address of PPA firmware loading from"
165 165 depends on FSL_LS_PPA
166   - default 0x40500000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
167   - default 0x580a00000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
168   - default 0x60500000 if SYS_LS_PPA_FW_IN_XIP
169   - default 0x500000 if SYS_LS_PPA_FW_IN_MMC
170   - default 0x500000 if SYS_LS_PPA_FW_IN_NAND
  166 + default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
  167 + default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
  168 + default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
  169 + default 0x60400000 if SYS_LS_PPA_FW_IN_XIP
  170 + default 0x400000 if SYS_LS_PPA_FW_IN_MMC
  171 + default 0x400000 if SYS_LS_PPA_FW_IN_NAND
171 172  
172 173 help
173 174 If the PPA firmware locate at XIP flash, such as NOR or
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
Diff comments   View file @ 380e86f
1 1 /*
  2 + * Copyright 2017 NXP
2 3 * Copyright 2014-2015 Freescale Semiconductor, Inc.
3 4 *
4 5 * SPDX-License-Identifier: GPL-2.0+
... ... @@ -98,7 +99,8 @@
98 99  
99 100 /* Fix PCIE base and size for LS2088A */
100 101 if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) ||
101   - (ver == SVR_LS2048A) || (ver == SVR_LS2044A)) {
  102 + (ver == SVR_LS2048A) || (ver == SVR_LS2044A) ||
  103 + (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) {
102 104 for (i = 0; i < ARRAY_SIZE(final_map); i++) {
103 105 switch (final_map[i].phys) {
104 106 case CONFIG_SYS_PCIE1_PHYS_ADDR:
arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
Diff comments   View file @ 380e86f
... ... @@ -5,6 +5,7 @@
5 5 3. LS1012A
6 6 4. LS1046A
7 7 5. LS2088A
  8 + 6. LS2081A
8 9  
9 10 LS1043A
10 11 ---------
... ... @@ -226,5 +227,15 @@
226 227 d) No L2 switch
227 228  
228 229 3)LS2044A, few difference w.r.t. LS2084A:
  230 + a) Four 64-bit ARM v8 Cortex-A72 CPUs
  231 +
  232 +LS2081A
  233 +--------
  234 +LS2081A is 40-pin derivative of LS2084A.
  235 +So feature-wise it is same as LS2084A.
  236 +Refer to LS2084A(LS2088A) section above for details.
  237 +
  238 +It has one more similar SoC personality
  239 +1)LS2041A, few difference w.r.t. LS2081A:
229 240 a) Four 64-bit ARM v8 Cortex-A72 CPUs
arch/arm/dts/Makefile
Diff comments   View file @ 380e86f
... ... @@ -175,7 +175,9 @@
175 175 ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \
176 176 ls1021a-iot-duart.dtb
177 177 dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
178   - fsl-ls2080a-rdb.dtb
  178 + fsl-ls2080a-rdb.dtb \
  179 + fsl-ls2081a-rdb.dtb \
  180 + fsl-ls2088a-rdb-qspi.dtb
179 181 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
180 182 fsl-ls1043a-qds-lpuart.dtb \
181 183 fsl-ls1043a-rdb.dtb \
arch/arm/dts/fsl-ls2081a-rdb.dts
Diff comments   View file @ 380e86f
  1 +/*
  2 + * NXP LS2081A RDB board device tree source for QSPI-boot
  3 + *
  4 + * Author: Priyanka Jain <priyanka.jain@nxp.com>
  5 + *
  6 + * Copyright 2017 NXP
  7 + *
  8 + * SPDX-License-Identifier: GPL-2.0+
  9 + */
  10 +
  11 +/dts-v1/;
  12 +
  13 +#include "fsl-ls2080a.dtsi"
  14 +
  15 +/ {
  16 + model = "Freescale Layerscape 2081a RDB Board";
  17 + compatible = "fsl,ls2081a-rdb", "fsl,ls2080a";
  18 +
  19 + aliases {
  20 + spi0 = &qspi;
  21 + spi1 = &dspi;
  22 + };
  23 +};
  24 +
  25 +&dspi {
  26 + bus-num = <0>;
  27 + status = "okay";
  28 +
  29 + dflash0: n25q512a {
  30 + #address-cells = <1>;
  31 + #size-cells = <1>;
  32 + compatible = "spi-flash";
  33 + spi-max-frequency = <3000000>;
  34 + spi-cpol;
  35 + spi-cpha;
  36 + reg = <0>;
  37 + };
  38 +};
  39 +
  40 +&qspi {
  41 + bus-num = <0>;
  42 + status = "okay";
  43 +
  44 + qflash0: n25q512a@0 {
  45 + #address-cells = <1>;
  46 + #size-cells = <1>;
  47 + compatible = "spi-flash";
  48 + spi-max-frequency = <50000000>;
  49 + reg = <0>;
  50 + };
  51 +
  52 + qflash1: n25q512a@1 {
  53 + #address-cells = <1>;
  54 + #size-cells = <1>;
  55 + compatible = "spi-flash";
  56 + spi-max-frequency = <50000000>;
  57 + reg = <1>;
  58 + };
  59 +};
arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
Diff comments   View file @ 380e86f
  1 +/*
  2 + * NXP ls2080a RDB board device tree source for QSPI-boot
  3 + *
  4 + * Author: Priyanka Jain <priyanka.jain@nxp.com>
  5 + *
  6 + * Copyright 2017 NXP
  7 + *
  8 + * SPDX-License-Identifier: GPL-2.0+
  9 + */
  10 +
  11 +/dts-v1/;
  12 +
  13 +#include "fsl-ls2080a.dtsi"
  14 +
  15 +/ {
  16 + model = "Freescale Layerscape 2080a RDB Board";
  17 + compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
  18 +
  19 + aliases {
  20 + spi0 = &qspi;
  21 + spi1 = &dspi;
  22 + };
  23 +};
  24 +
  25 +&dspi {
  26 + bus-num = <0>;
  27 + status = "okay";
  28 +
  29 + dflash0: n25q512a {
  30 + #address-cells = <1>;
  31 + #size-cells = <1>;
  32 + compatible = "spi-flash";
  33 + spi-max-frequency = <3000000>;
  34 + spi-cpol;
  35 + spi-cpha;
  36 + reg = <0>;
  37 + };
  38 +};
  39 +
  40 +&qspi {
  41 + bus-num = <0>;
  42 + status = "okay";
  43 +
  44 + qflash0: s25fs512s@0 {
  45 + #address-cells = <1>;
  46 + #size-cells = <1>;
  47 + compatible = "spi-flash";
  48 + spi-max-frequency = <50000000>;
  49 + reg = <0>;
  50 + };
  51 +
  52 + qflash1: s25fs512s@1 {
  53 + #address-cells = <1>;
  54 + #size-cells = <1>;
  55 + compatible = "spi-flash";
  56 + spi-max-frequency = <50000000>;
  57 + reg = <1>;
  58 + };
  59 +};
arch/arm/include/asm/arch-fsl-layerscape/cpu.h
Diff comments   View file @ 380e86f
1 1 /*
  2 + * Copyright 2017 NXP
2 3 * Copyright 2014-2015, Freescale Semiconductor
3 4 *
4 5 * SPDX-License-Identifier: GPL-2.0+
... ... @@ -15,6 +16,8 @@
15 16 CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
16 17 CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
17 18 CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
  19 + CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
  20 + CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
18 21 CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
19 22 CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
20 23 CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
Diff comments   View file @ 380e86f
1 1 /*
2 2 * LayerScape Internal Memory Map
3 3 *
  4 + * Copyright (C) 2017 NXP Semiconductors
4 5 * Copyright 2014 Freescale Semiconductor, Inc.
5 6 *
6 7 * SPDX-License-Identifier: GPL-2.0+
... ... @@ -45,6 +46,9 @@
45 46 #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000)
46 47 #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000)
47 48 #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000)
  49 +#define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01330000)
  50 +#define GPIO4_GPDIR_ADDR (GPIO4_BASE_ADDR + 0x0)
  51 +#define GPIO4_GPDAT_ADDR (GPIO4_BASE_ADDR + 0x8)
48 52  
49 53 #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
50 54 #define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
arch/arm/include/asm/arch-fsl-layerscape/soc.h
Diff comments   View file @ 380e86f
1 1 /*
  2 + * Copyright 2017 NXP
2 3 * Copyright 2015 Freescale Semiconductor
3 4 *
4 5 * SPDX-License-Identifier: GPL-2.0+
... ... @@ -54,6 +55,8 @@
54 55 #define SVR_LS2084A 0x870910
55 56 #define SVR_LS2048A 0x870920
56 57 #define SVR_LS2044A 0x870930
  58 +#define SVR_LS2081A 0x870919
  59 +#define SVR_LS2041A 0x870915
57 60  
58 61 #define SVR_DEV_LS2080A 0x8701
59 62  
board/freescale/ls1043ardb/Makefile
Diff comments   View file @ 380e86f
... ... @@ -7,7 +7,7 @@
7 7 obj-y += ddr.o
8 8 obj-y += ls1043ardb.o
9 9 ifndef CONFIG_SPL_BUILD
10   -obj-$(CONFIG_SYS_DPAA_FMAN) += eth.o
  10 +obj-$(CONFIG_NET) += eth.o
11 11 obj-y += cpld.o
12 12 endif
board/freescale/ls1046ardb/Makefile
Diff comments   View file @ 380e86f
... ... @@ -7,7 +7,7 @@
7 7 obj-y += ddr.o
8 8 obj-y += ls1046ardb.o
9 9 ifndef CONFIG_SPL_BUILD
10   -obj-$(CONFIG_SYS_DPAA_FMAN) += eth.o
  10 +obj-$(CONFIG_NET) += eth.o
11 11 obj-y += cpld.o
12 12 endif
board/freescale/ls1046ardb/README
Diff comments   View file @ 380e86f
... ... @@ -59,14 +59,14 @@
59 59 QSPI flash map:
60 60 Start Address End Address Description Size
61 61 0x00_4000_0000 - 0x00_400F_FFFF RCW + PBI 1MB
62   -0x00_4010_0000 - 0x00_401F_FFFF U-Boot 1MB
63   -0x00_4020_0000 - 0x00_402F_FFFF U-Boot Env 1MB
64   -0x00_4030_0000 - 0x00_403F_FFFF FMan ucode 1MB
65   -0x00_4040_0000 - 0x00_404F_FFFF UEFI 1MB
66   -0x00_4050_0000 - 0x00_406F_FFFF PPA 2MB
67   -0x00_4070_0000 - 0x00_408F_FFFF Secure boot header
68   - + bootscript 2MB
69   -0x00_4090_0000 - 0x00_40FF_FFFF Reserved 7MB
  62 +0x00_4010_0000 - 0x00_402F_FFFF U-Boot 2MB
  63 +0x00_4030_0000 - 0x00_403F_FFFF U-Boot Env 1MB
  64 +0x00_4040_0000 - 0x00_405F_FFFF PPA 2MB
  65 +0x00_4060_0000 - 0x00_408F_FFFF Secure boot header
  66 + + bootscript 3MB
  67 +0x00_4090_0000 - 0x00_4093_FFFF FMan ucode 256KB
  68 +0x00_4094_0000 - 0x00_4097_FFFF QE/uQE firmware 256KB
  69 +0x00_4098_0000 - 0x00_40FF_FFFF Reserved 6MB
70 70 0x00_4100_0000 - 0x00_43FF_FFFF FIT Image 48MB
71 71  
72 72 Booting Options
board/freescale/ls2080aqds/README
Diff comments   View file @ 380e86f
... ... @@ -89,6 +89,19 @@
89 89 d) SD boot
90 90 e) QSPI boot
91 91  
  92 +Memory map for NOR boot
  93 +-------------------------
  94 +Image Flash Offset
  95 +RCW+PBI 0x00000000
  96 +Boot firmware (U-Boot) 0x00100000
  97 +Boot firmware Environment 0x00300000
  98 +PPA firmware 0x00400000
  99 +Secure Headers 0x00600000
  100 +DPAA2 MC 0x00A00000
  101 +DPAA2 DPL 0x00D00000
  102 +DPAA2 DPC 0x00E00000
  103 +Kernel.itb 0x01000000
  104 +
92 105 Environment Variables
93 106 ---------------------
94 107 - mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined
board/freescale/ls2080ardb/Kconfig
Diff comments   View file @ 380e86f
... ... @@ -16,4 +16,22 @@
16 16 source "board/freescale/common/Kconfig"
17 17  
18 18 endif
  19 +
  20 +if TARGET_LS2081ARDB
  21 +
  22 +config SYS_BOARD
  23 + default "ls2080ardb"
  24 +
  25 +config SYS_VENDOR
  26 + default "freescale"
  27 +
  28 +config SYS_SOC
  29 + default "fsl-layerscape"
  30 +
  31 +config SYS_CONFIG_NAME
  32 + default "ls2080ardb"
  33 +
  34 +source "board/freescale/common/Kconfig"
  35 +
  36 +endif
board/freescale/ls2080ardb/MAINTAINERS
Diff comments   View file @ 380e86f
... ... @@ -7,6 +7,16 @@
7 7 F: configs/ls2080ardb_defconfig
8 8 F: configs/ls2080ardb_nand_defconfig
9 9  
  10 +LS2088A_QSPI-boot BOARD
  11 +M: Priyanka Jain <priyanka.jain@nxp.com>
  12 +S: Maintained
  13 +F: configs/ls2088ardb_qspi_defconfig
  14 +
  15 +LS2081ARDB BOARD
  16 +M: Priyanka Jain <priyanka.jain@nxp.com>
  17 +S: Maintained
  18 +F: configs/ls2081ardb_defconfig
  19 +
10 20 LS2080A_SECURE_BOOT BOARD
11 21 M: Saksham Jain <saksham.jain@nxp.freescale.com>
12 22 S: Maintained
board/freescale/ls2080ardb/README
Diff comments   View file @ 380e86f
... ... @@ -4,10 +4,14 @@
4 4 evaluation, and development platform that supports the QorIQ LS2080A, LS2088A
5 5 Layerscape Architecture processor.
6 6  
7   -LS2080A, LS2088A SoC Overview
8   ---------------------
  7 +The LS2081A Reference Design (RDB) is a high-performance computing,
  8 +evaluation, and development platform that supports the QorIQ LS2081A
  9 +Layerscape Architecture processor.More details in below sections
  10 +
  11 +LS2080A, LS2088A, LS2081A SoC Overview
  12 +--------------------------------------
9 13 Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A,
10   -LS2088A SoC overview.
  14 +LS2081A, LS2088A SoC overview.
11 15  
12 16 LS2080ARDB board Overview
13 17 -----------------------
14 18  
... ... @@ -38,11 +42,22 @@
38 42 - UART
39 43 - ARM JTAG support
40 44  
  45 + LS2081ARDB board Overview
  46 + -------------------------
  47 + LS2081ARDB board is similar to LS2080ARDB board
  48 + with few differences like
  49 + - Hosts LS2081A SoC
  50 + - Default boot source is QSPI-boot
  51 + - Does not have IFC interface
  52 + - RTC and QSPI flash devices are different
  53 + - Provides QIXIS access via I2C
  54 +
41 55 Memory map from core's view
42 56 ----------------------------
43 57 0x00_0000_0000 .. 0x00_000F_FFFF Boot Rom
44 58 0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR
45 59 0x00_1800_0000 .. 0x00_181F_FFFF OCRAM
  60 +0x00_2000_0000 .. 0x00_2FFF_FFFF QSPI region #1
46 61 0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1
47 62 0x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1
48 63 0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2
... ... @@ -68,6 +83,45 @@
68 83 ---------------
69 84 a) NOR boot
70 85 b) NAND boot
  86 +c) QSPI boot
  87 +
  88 +Memory map for NOR boot
  89 +-------------------------
  90 +Image Flash Offset
  91 +RCW+PBI 0x00000000
  92 +Boot firmware (U-Boot) 0x00100000
  93 +Boot firmware Environment 0x00300000
  94 +PPA firmware 0x00400000
  95 +Secure Headers 0x00600000
  96 +Cortina PHY firmware 0x00980000
  97 +DPAA2 MC 0x00A00000
  98 +DPAA2 DPL 0x00D00000
  99 +DPAA2 DPC 0x00E00000
  100 +Kernel.itb 0x01000000
  101 +
  102 +cfg_rcw_src switches needs to be changed for booting from different option.
  103 +Refer to board documentation for correct switch setting.
  104 +
  105 +QSPI boot details
  106 +===================
  107 +Supported only for
  108 + LS2088ARDB RevF board with LS2088A SoC.
  109 +
  110 +Images needs to be copied to QSPI flash
  111 +as per memory map given below.
  112 +
  113 +Memory map for QSPI flash
  114 +-------------------------
  115 +Image Flash Offset
  116 +RCW+PBI 0x00000000
  117 +Boot firmware (U-Boot) 0x00100000
  118 +Boot firmware Environment 0x00300000
  119 +PPA firmware 0x00400000
  120 +Cortina PHY firmware 0x00980000
  121 +DPAA2 MC 0x00A00000
  122 +DPAA2 DPL 0x00D00000
  123 +DPAA2 DPC 0x00E00000
  124 +Kernel.itb 0x01000000
71 125  
72 126 Booting Linux flavors which do not support 48-bit VA (< Linux 3.18)
73 127 -------------------------------------------------------------------
board/freescale/ls2080ardb/ls2080ardb.c
Diff comments   View file @ 380e86f
1 1 /*
  2 + * Copyright (C) 2017 NXP Semiconductors
2 3 * Copyright 2015 Freescale Semiconductor
3 4 *
4 5 * SPDX-License-Identifier: GPL-2.0+
5 6  
... ... @@ -22,8 +23,10 @@
22 23 #include <asm/arch/ppa.h>
23 24 #include <fsl_sec.h>
24 25  
  26 +#ifdef CONFIG_FSL_QIXIS
25 27 #include "../common/qixis.h"
26 28 #include "ls2080ardb_qixis.h"
  29 +#endif
27 30 #include "../common/vid.h"
28 31  
29 32 #define PIN_MUX_SEL_SDHC 0x00
30 33  
31 34  
32 35  
... ... @@ -57,14 +60,55 @@
57 60  
58 61 int checkboard(void)
59 62 {
  63 +#ifdef CONFIG_FSL_QIXIS
60 64 u8 sw;
  65 +#endif
61 66 char buf[15];
62 67  
63 68 cpu_name(buf);
64 69 printf("Board: %s-RDB, ", buf);
65 70  
  71 +#ifdef CONFIG_TARGET_LS2081ARDB
  72 +#ifdef CONFIG_FSL_QIXIS
66 73 sw = QIXIS_READ(arch);
67 74 printf("Board Arch: V%d, ", sw >> 4);
  75 + printf("Board version: %c, ", (sw & 0xf) + 'A');
  76 +
  77 + sw = QIXIS_READ(brdcfg[0]);
  78 + sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
  79 + switch (sw) {
  80 + case 0:
  81 + puts("boot from QSPI DEV#0\n");
  82 + puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
  83 + break;
  84 + case 1:
  85 + puts("boot from QSPI DEV#1\n");
  86 + puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
  87 + break;
  88 + case 2:
  89 + puts("boot from QSPI EMU\n");
  90 + puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
  91 + break;
  92 + case 3:
  93 + puts("boot from QSPI EMU\n");
  94 + puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
  95 + break;
  96 + case 4:
  97 + puts("boot from QSPI DEV#0\n");
  98 + puts("QSPI_CSA_1 mapped to QSPI EMU\n");
  99 + break;
  100 + default:
  101 + printf("invalid setting of SW%u\n", sw);
  102 + break;
  103 + }
  104 +#endif
  105 + puts("SERDES1 Reference : ");
  106 + printf("Clock1 = 100MHz ");
  107 + printf("Clock2 = 161.13MHz");
  108 +#else
  109 +#ifdef CONFIG_FSL_QIXIS
  110 + sw = QIXIS_READ(arch);
  111 + printf("Board Arch: V%d, ", sw >> 4);
68 112 printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
69 113  
70 114 sw = QIXIS_READ(brdcfg[0]);
71 115  
... ... @@ -78,10 +122,11 @@
78 122 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
79 123  
80 124 printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
81   -
  125 +#endif
82 126 puts("SERDES1 Reference : ");
83 127 printf("Clock1 = 156.25MHz ");
84 128 printf("Clock2 = 156.25MHz");
  129 +#endif
85 130  
86 131 puts("\nSERDES2 Reference : ");
87 132 printf("Clock1 = 100MHz ");
... ... @@ -92,6 +137,7 @@
92 137  
93 138 unsigned long get_board_sys_clk(void)
94 139 {
  140 +#ifdef CONFIG_FSL_QIXIS
95 141 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
96 142  
97 143 switch (sysclk_conf & 0x0F) {
... ... @@ -110,7 +156,8 @@
110 156 case QIXIS_SYSCLK_166:
111 157 return 166666666;
112 158 }
113   - return 66666666;
  159 +#endif
  160 + return 100000000;
114 161 }
115 162  
116 163 int select_i2c_ch_pca9547(u8 ch)
... ... @@ -133,6 +180,7 @@
133 180  
134 181 int config_board_mux(int ctrl_type)
135 182 {
  183 +#ifdef CONFIG_FSL_QIXIS
136 184 u8 reg5;
137 185  
138 186 reg5 = QIXIS_READ(brdcfg[5]);
... ... @@ -150,7 +198,7 @@
150 198 }
151 199  
152 200 QIXIS_WRITE(brdcfg[5], reg5);
153   -
  201 +#endif
154 202 return 0;
155 203 }
156 204  
157 205  
... ... @@ -180,8 +228,9 @@
180 228 #endif
181 229 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
182 230  
  231 +#ifdef CONFIG_FSL_QIXIS
183 232 QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
184   -
  233 +#endif
185 234 #ifdef CONFIG_FSL_LS_PPA
186 235 ppa_init();
187 236 #endif
188 237  
... ... @@ -199,12 +248,40 @@
199 248  
200 249 int board_early_init_f(void)
201 250 {
  251 +#ifdef CONFIG_SYS_I2C_EARLY_INIT
  252 + i2c_early_init_f();
  253 +#endif
202 254 fsl_lsch3_early_init_f();
203 255 return 0;
204 256 }
205 257  
206 258 int misc_init_r(void)
207 259 {
  260 +#ifdef CONFIG_FSL_QIXIS
  261 + /*
  262 + * LS2081ARDB has smart voltage translator which needs
  263 + * to be programmed as below
  264 + */
  265 +#ifndef CONFIG_TARGET_LS2081ARDB
  266 + u8 sw;
  267 +
  268 + sw = QIXIS_READ(arch);
  269 + /*
  270 + * LS2080ARDB/LS2088ARDB RevF board has smart voltage translator
  271 + * which needs to be programmed to enable high speed SD interface
  272 + * by setting GPIO4_10 output to zero
  273 + */
  274 + if ((sw & 0xf) == 0x5) {
  275 +#endif
  276 + out_le32(GPIO4_GPDIR_ADDR, (1 << 21 |
  277 + in_le32(GPIO4_GPDIR_ADDR)));
  278 + out_le32(GPIO4_GPDAT_ADDR, (~(1 << 21) &
  279 + in_le32(GPIO4_GPDAT_ADDR)));
  280 +#ifndef CONFIG_TARGET_LS2081ARDB
  281 + }
  282 +#endif
  283 +#endif
  284 +
208 285 if (hwconfig("sdhc"))
209 286 config_board_mux(MUX_TYPE_SDHC);
210 287  
... ... @@ -301,6 +378,7 @@
301 378  
302 379 void qixis_dump_switch(void)
303 380 {
  381 +#ifdef CONFIG_FSL_QIXIS
304 382 int i, nr_of_cfgsw;
305 383  
306 384 QIXIS_WRITE(cms[0], 0x00);
... ... @@ -311,6 +389,7 @@
311 389 QIXIS_WRITE(cms[0], i);
312 390 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
313 391 }
  392 +#endif
314 393 }
315 394  
316 395 /*
... ... @@ -321,6 +400,8 @@
321 400 unsigned int slot,
322 401 unsigned int *addr)
323 402 {
  403 +#ifndef CONFIG_TARGET_LS2081ARDB
  404 +#ifdef CONFIG_FSL_QIXIS
324 405 u8 sw;
325 406  
326 407 sw = QIXIS_READ(arch);
... ... @@ -330,5 +411,7 @@
330 411 else if (ctrl_num == 1 && slot == 1)
331 412 *addr = SPD_EEPROM_ADDRESS3;
332 413 }
  414 +#endif
  415 +#endif
333 416 }
configs/ls2081ardb_defconfig
Diff comments   View file @ 380e86f
  1 +CONFIG_ARM=y
  2 +CONFIG_TARGET_LS2081ARDB=y
  3 +CONFIG_FSL_LS_PPA=y
  4 +CONFIG_QSPI_AHB_INIT=y
  5 +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2081a-rdb"
  6 +# CONFIG_SYS_MALLOC_F is not set
  7 +CONFIG_FIT_VERBOSE=y
  8 +CONFIG_OF_BOARD_SETUP=y
  9 +CONFIG_OF_STDOUT_VIA_ALIAS=y
  10 +CONFIG_QSPI_BOOT=y
  11 +CONFIG_BOOTDELAY=10
  12 +CONFIG_CMD_GREPENV=y
  13 +# CONFIG_CMD_IMLS is not set
  14 +CONFIG_CMD_GPT=y
  15 +CONFIG_CMD_MMC=y
  16 +CONFIG_CMD_SF=y
  17 +CONFIG_CMD_I2C=y
  18 +CONFIG_CMD_DHCP=y
  19 +CONFIG_CMD_MII=y
  20 +CONFIG_CMD_PING=y
  21 +CONFIG_CMD_CACHE=y
  22 +CONFIG_CMD_EXT2=y
  23 +CONFIG_CMD_FAT=y
  24 +CONFIG_OF_CONTROL=y
  25 +CONFIG_NET_RANDOM_ETHADDR=y
  26 +CONFIG_DM=y
  27 +CONFIG_FSL_CAAM=y
  28 +CONFIG_DM_SPI_FLASH=y
  29 +CONFIG_NETDEVICES=y
  30 +CONFIG_E1000=y
  31 +CONFIG_PCI=y
  32 +CONFIG_DM_PCI=y
  33 +CONFIG_DM_PCI_COMPAT=y
  34 +CONFIG_PCIE_LAYERSCAPE=y
  35 +CONFIG_SYS_NS16550=y
  36 +CONFIG_DM_SPI=y
  37 +CONFIG_FSL_QSPI=y
  38 +CONFIG_FSL_DSPI=y
  39 +CONFIG_CMD_USB=y
  40 +# CONFIG_CMD_SETEXPR is not set
  41 +CONFIG_USB=y
  42 +CONFIG_DM_USB=y
  43 +CONFIG_USB_XHCI_HCD=y
  44 +CONFIG_USB_XHCI_DWC3=y
  45 +CONFIG_USB_STORAGE=y
  46 +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
configs/ls2088ardb_qspi_defconfig
Diff comments   View file @ 380e86f
  1 +CONFIG_ARM=y
  2 +CONFIG_TARGET_LS2080ARDB=y
  3 +CONFIG_FSL_LS_PPA=y
  4 +CONFIG_QSPI_AHB_INIT=y
  5 +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi"
  6 +# CONFIG_SYS_MALLOC_F is not set
  7 +CONFIG_FIT_VERBOSE=y
  8 +CONFIG_OF_BOARD_SETUP=y
  9 +CONFIG_OF_STDOUT_VIA_ALIAS=y
  10 +CONFIG_QSPI_BOOT=y
  11 +CONFIG_BOOTDELAY=10
  12 +CONFIG_CMD_GREPENV=y
  13 +# CONFIG_CMD_IMLS is not set
  14 +CONFIG_CMD_GPT=y
  15 +CONFIG_CMD_MMC=y
  16 +CONFIG_CMD_SF=y
  17 +CONFIG_CMD_I2C=y
  18 +CONFIG_CMD_DHCP=y
  19 +CONFIG_CMD_MII=y
  20 +CONFIG_CMD_PING=y
  21 +CONFIG_CMD_CACHE=y
  22 +CONFIG_CMD_EXT2=y
  23 +CONFIG_CMD_FAT=y
  24 +CONFIG_OF_CONTROL=y
  25 +CONFIG_NET_RANDOM_ETHADDR=y
  26 +CONFIG_DM=y
  27 +CONFIG_FSL_CAAM=y
  28 +CONFIG_DM_SPI_FLASH=y
  29 +CONFIG_NETDEVICES=y
  30 +CONFIG_E1000=y
  31 +CONFIG_PCI=y
  32 +CONFIG_DM_PCI=y
  33 +CONFIG_DM_PCI_COMPAT=y
  34 +CONFIG_PCIE_LAYERSCAPE=y
  35 +CONFIG_SYS_NS16550=y
  36 +CONFIG_DM_SPI=y
  37 +CONFIG_FSL_QSPI=y
  38 +CONFIG_FSL_DSPI=y
  39 +CONFIG_CMD_USB=y
  40 +# CONFIG_CMD_SETEXPR is not set
  41 +CONFIG_USB=y
  42 +CONFIG_DM_USB=y
  43 +CONFIG_USB_XHCI_HCD=y
  44 +CONFIG_USB_XHCI_DWC3=y
  45 +CONFIG_USB_STORAGE=y
  46 +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
drivers/net/fsl-mc/mc.c
Diff comments   View file @ 380e86f
1 1 /*
  2 + * Copyright (C) 2017 NXP Semiconductors
2 3 * Copyright (C) 2014 Freescale Semiconductor
3 4 *
4 5 * SPDX-License-Identifier: GPL-2.0+
... ... @@ -1201,6 +1202,7 @@
1201 1202 int fsl_mc_ldpaa_exit(bd_t *bd)
1202 1203 {
1203 1204 int err = 0;
  1205 + bool is_dpl_apply_status = false;
1204 1206  
1205 1207 if (bd && mc_lazy_dpl_addr && !fsl_mc_ldpaa_exit(NULL)) {
1206 1208 mc_apply_dpl(mc_lazy_dpl_addr);
1207 1209  
... ... @@ -1211,14 +1213,18 @@
1211 1213 if (bd && get_mc_boot_status() != 0)
1212 1214 return 0;
1213 1215  
1214   - if (bd && !get_mc_boot_status() && get_dpl_apply_status() == -1) {
1215   - printf("ERROR: fsl-mc: DPL is not applied\n");
1216   - err = -ENODEV;
1217   - return err;
1218   - }
  1216 + /* If DPL is deployed, set is_dpl_apply_status as TRUE. */
  1217 + if (!get_dpl_apply_status())
  1218 + is_dpl_apply_status = true;
1219 1219  
1220   - if (bd && !get_mc_boot_status() && !get_dpl_apply_status())
1221   - return err;
  1220 + /*
  1221 + * For case MC is loaded but DPL is not deployed, return success and
  1222 + * print message on console. Else FDT fix-up code execution hanged.
  1223 + */
  1224 + if (bd && !get_mc_boot_status() && !is_dpl_apply_status) {
  1225 + printf("fsl-mc: DPL not deployed, DPAA2 ethernet not work\n");
  1226 + return 0;
  1227 + }
1222 1228  
1223 1229 err = dpbp_exit();
1224 1230 if (err < 0) {
drivers/pci/pcie_layerscape.c
Diff comments   View file @ 380e86f
1 1 /*
  2 + * Copyright 2017 NXP
2 3 * Copyright 2014-2015 Freescale Semiconductor, Inc.
3 4 * Layerscape PCIe driver
4 5 *
... ... @@ -170,7 +171,8 @@
170 171 /* Fix the pcie memory map for LS2088A series SoCs */
171 172 svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
172 173 if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
173   - svr == SVR_LS2048A || svr == SVR_LS2044A) {
  174 + svr == SVR_LS2048A || svr == SVR_LS2044A ||
  175 + svr == SVR_LS2081A || svr == SVR_LS2041A) {
174 176 if (io)
175 177 io->phys_start = (io->phys_start &
176 178 (PCIE_PHYS_SIZE - 1)) +
... ... @@ -531,7 +533,8 @@
531 533 svr = get_svr();
532 534 svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
533 535 if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
534   - svr == SVR_LS2048A || svr == SVR_LS2044A) {
  536 + svr == SVR_LS2048A || svr == SVR_LS2044A ||
  537 + svr == SVR_LS2081A || svr == SVR_LS2041A) {
535 538 pcie->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR +
536 539 LS2088A_PCIE_PHYS_SIZE * pcie->idx;
537 540 pcie->ctrl = pcie->lut + 0x40000;
drivers/pci/pcie_layerscape.h
Diff comments   View file @ 380e86f
1 1 /*
  2 + * Copyright 2017 NXP
2 3 * Copyright 2014-2015 Freescale Semiconductor, Inc.
3 4 * Layerscape PCIe driver
4 5 *
... ... @@ -117,6 +118,8 @@
117 118 #define SVR_LS2084A 0x870910
118 119 #define SVR_LS2048A 0x870920
119 120 #define SVR_LS2044A 0x870930
  121 +#define SVR_LS2081A 0x870919
  122 +#define SVR_LS2041A 0x870915
120 123  
121 124 /* LS1021a PCIE space */
122 125 #define LS1021_PCIE_SPACE_OFFSET 0x4000000000ULL
drivers/pci/pcie_layerscape_fixup.c
Diff comments   View file @ 380e86f
1 1 /*
  2 + * Copyright 2017 NXP
2 3 * Copyright 2014-2015 Freescale Semiconductor, Inc.
3 4 * Layerscape PCIe driver
4 5 *
... ... @@ -82,7 +83,8 @@
82 83 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
83 84 svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
84 85 if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
85   - svr == SVR_LS2048A || svr == SVR_LS2044A)
  86 + svr == SVR_LS2048A || svr == SVR_LS2044A ||
  87 + svr == SVR_LS2081A || svr == SVR_LS2041A)
86 88 compat = "fsl,ls2088a-pcie";
87 89 else
88 90 compat = CONFIG_FSL_PCIE_COMPAT;
... ... @@ -217,7 +219,8 @@
217 219 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
218 220 svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
219 221 if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
220   - svr == SVR_LS2048A || svr == SVR_LS2044A)
  222 + svr == SVR_LS2048A || svr == SVR_LS2044A ||
  223 + svr == SVR_LS2081A || svr == SVR_LS2041A)
221 224 compat = "fsl,ls2088a-pcie";
222 225 else
223 226 compat = CONFIG_FSL_PCIE_COMPAT;
drivers/usb/host/xhci-fsl.c
Diff comments   View file @ 380e86f
... ... @@ -40,7 +40,8 @@
40 40  
41 41 static int erratum_a008751(void)
42 42 {
43   -#if defined(CONFIG_TARGET_LS2080AQDS) || defined(CONFIG_TARGET_LS2080ARDB)
  43 +#if defined(CONFIG_TARGET_LS2080AQDS) || defined(CONFIG_TARGET_LS2080ARDB) ||\
  44 + defined(CONFIG_TARGET_LS2080AQDS)
44 45 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
45 46 writel(SCFG_USB3PRM1CR_INIT, scfg + SCFG_USB3PRM1CR / 4);
46 47 return 0;
include/configs/ls1012a_common.h
Diff comments   View file @ 380e86f
... ... @@ -55,9 +55,8 @@
55 55 #define CONFIG_FSL_QSPI
56 56 #define QSPI0_AMBA_BASE 0x40000000
57 57 #define CONFIG_SPI_FLASH_SPANSION
58   -#define CONFIG_SPI_FLASH_BAR
59 58  
60   -#define FSL_QSPI_FLASH_SIZE (1 << 24)
  59 +#define FSL_QSPI_FLASH_SIZE SZ_64M
61 60 #define FSL_QSPI_FLASH_NUM 2
62 61  
63 62 /*
include/configs/ls1021aqds.h
Diff comments   View file @ 380e86f
... ... @@ -69,7 +69,7 @@
69 69 #endif
70 70  
71 71 #ifdef CONFIG_QSPI_BOOT
72   -#define CONFIG_SYS_TEXT_BASE 0x40010000
  72 +#define CONFIG_SYS_TEXT_BASE 0x40100000
73 73 #endif
74 74  
75 75 #ifdef CONFIG_NAND_BOOT
... ... @@ -497,7 +497,7 @@
497 497 #define CONFIG_FSL_DEVICE_DISABLE
498 498  
499 499  
500   -#define CONFIG_SYS_QE_FW_ADDR 0x600c0000
  500 +#define CONFIG_SYS_QE_FW_ADDR 0x60940000
501 501  
502 502 #ifdef CONFIG_LPUART
503 503 #define CONFIG_EXTRA_ENV_SETTINGS \
504 504  
... ... @@ -548,14 +548,14 @@
548 548 #define CONFIG_ENV_OVERWRITE
549 549  
550 550 #if defined(CONFIG_SD_BOOT)
551   -#define CONFIG_ENV_OFFSET 0x100000
  551 +#define CONFIG_ENV_OFFSET 0x300000
552 552 #define CONFIG_ENV_IS_IN_MMC
553 553 #define CONFIG_SYS_MMC_ENV_DEV 0
554 554 #define CONFIG_ENV_SIZE 0x2000
555 555 #elif defined(CONFIG_QSPI_BOOT)
556 556 #define CONFIG_ENV_IS_IN_SPI_FLASH
557 557 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
558   -#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
  558 +#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
559 559 #define CONFIG_ENV_SECT_SIZE 0x10000
560 560 #elif defined(CONFIG_NAND_BOOT)
561 561 #define CONFIG_ENV_IS_IN_NAND
... ... @@ -563,7 +563,7 @@
563 563 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
564 564 #else
565 565 #define CONFIG_ENV_IS_IN_FLASH
566   -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  566 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
567 567 #define CONFIG_ENV_SIZE 0x2000
568 568 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
569 569 #endif
include/configs/ls1021atwr.h
Diff comments   View file @ 380e86f
... ... @@ -132,7 +132,7 @@
132 132 #endif
133 133  
134 134 #ifdef CONFIG_QSPI_BOOT
135   -#define CONFIG_SYS_TEXT_BASE 0x40010000
  135 +#define CONFIG_SYS_TEXT_BASE 0x40100000
136 136 #endif
137 137  
138 138 #ifndef CONFIG_SYS_TEXT_BASE
... ... @@ -408,7 +408,7 @@
408 408 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
409 409 #endif
410 410  
411   -#define CONFIG_SYS_QE_FW_ADDR 0x600c0000
  411 +#define CONFIG_SYS_QE_FW_ADDR 0x60940000
412 412  
413 413 /*
414 414 * Environment
415 415  
416 416  
... ... @@ -416,18 +416,18 @@
416 416 #define CONFIG_ENV_OVERWRITE
417 417  
418 418 #if defined(CONFIG_SD_BOOT)
419   -#define CONFIG_ENV_OFFSET 0x100000
  419 +#define CONFIG_ENV_OFFSET 0x300000
420 420 #define CONFIG_ENV_IS_IN_MMC
421 421 #define CONFIG_SYS_MMC_ENV_DEV 0
422 422 #define CONFIG_ENV_SIZE 0x20000
423 423 #elif defined(CONFIG_QSPI_BOOT)
424 424 #define CONFIG_ENV_IS_IN_SPI_FLASH
425 425 #define CONFIG_ENV_SIZE 0x2000
426   -#define CONFIG_ENV_OFFSET 0x100000
  426 +#define CONFIG_ENV_OFFSET 0x300000
427 427 #define CONFIG_ENV_SECT_SIZE 0x10000
428 428 #else
429 429 #define CONFIG_ENV_IS_IN_FLASH
430   -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  430 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
431 431 #define CONFIG_ENV_SIZE 0x20000
432 432 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
433 433 #endif
include/configs/ls1043a_common.h
Diff comments   View file @ 380e86f
... ... @@ -205,20 +205,20 @@
205 205 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
206 206  
207 207 #ifdef CONFIG_NAND_BOOT
208   -/* Store Fman ucode at offeset 0x160000(11 blocks). */
  208 +/* Store Fman ucode at offeset 0x900000(72 blocks). */
209 209 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
210   -#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
  210 +#define CONFIG_SYS_FMAN_FW_ADDR (72 * CONFIG_SYS_NAND_BLOCK_SIZE)
211 211 #elif defined(CONFIG_SD_BOOT)
212 212 /*
213 213 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
214 214 * about 1MB (2040 blocks), Env is stored after the image, and the env size is
215   - * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 2080(0x820).
  215 + * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 18432(0x4800).
216 216 */
217 217 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
218   -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
  218 +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800)
219 219 #elif defined(CONFIG_QSPI_BOOT)
220 220 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
221   -#define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000
  221 +#define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
222 222 #define CONFIG_ENV_SPI_BUS 0
223 223 #define CONFIG_ENV_SPI_CS 0
224 224 #define CONFIG_ENV_SPI_MAX_HZ 1000000
... ... @@ -226,7 +226,7 @@
226 226 #else
227 227 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
228 228 /* FMan fireware Pre-load address */
229   -#define CONFIG_SYS_FMAN_FW_ADDR 0x60300000
  229 +#define CONFIG_SYS_FMAN_FW_ADDR 0x60900000
230 230 #endif
231 231 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
232 232 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
include/configs/ls1043aqds.h
Diff comments   View file @ 380e86f
... ... @@ -12,7 +12,7 @@
12 12 #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
13 13 #define CONFIG_SYS_TEXT_BASE 0x82000000
14 14 #elif defined(CONFIG_QSPI_BOOT)
15   -#define CONFIG_SYS_TEXT_BASE 0x40010000
  15 +#define CONFIG_SYS_TEXT_BASE 0x40100000
16 16 #else
17 17 #define CONFIG_SYS_TEXT_BASE 0x60100000
18 18 #endif
19 19  
20 20  
21 21  
... ... @@ -413,20 +413,20 @@
413 413 #ifdef CONFIG_NAND_BOOT
414 414 #define CONFIG_ENV_IS_IN_NAND
415 415 #define CONFIG_ENV_SIZE 0x2000
416   -#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
  416 +#define CONFIG_ENV_OFFSET (24 * CONFIG_SYS_NAND_BLOCK_SIZE)
417 417 #elif defined(CONFIG_SD_BOOT)
418   -#define CONFIG_ENV_OFFSET (1024 * 1024)
  418 +#define CONFIG_ENV_OFFSET (3 * 1024 * 1024)
419 419 #define CONFIG_ENV_IS_IN_MMC
420 420 #define CONFIG_SYS_MMC_ENV_DEV 0
421 421 #define CONFIG_ENV_SIZE 0x2000
422 422 #elif defined(CONFIG_QSPI_BOOT)
423 423 #define CONFIG_ENV_IS_IN_SPI_FLASH
424 424 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
425   -#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
  425 +#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
426 426 #define CONFIG_ENV_SECT_SIZE 0x10000
427 427 #else
428 428 #define CONFIG_ENV_IS_IN_FLASH
429   -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
  429 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
430 430 #define CONFIG_ENV_SECT_SIZE 0x20000
431 431 #define CONFIG_ENV_SIZE 0x20000
432 432 #endif
include/configs/ls1043ardb.h
Diff comments   View file @ 380e86f
... ... @@ -235,31 +235,34 @@
235 235 #if defined(CONFIG_NAND_BOOT)
236 236 #define CONFIG_ENV_IS_IN_NAND
237 237 #define CONFIG_ENV_SIZE 0x2000
238   -#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
  238 +#define CONFIG_ENV_OFFSET (24 * CONFIG_SYS_NAND_BLOCK_SIZE)
239 239 #elif defined(CONFIG_SD_BOOT)
240   -#define CONFIG_ENV_OFFSET (1024 * 1024)
  240 +#define CONFIG_ENV_OFFSET (3 * 1024 * 1024)
241 241 #define CONFIG_ENV_IS_IN_MMC
242 242 #define CONFIG_SYS_MMC_ENV_DEV 0
243 243 #define CONFIG_ENV_SIZE 0x2000
244 244 #else
245 245 #define CONFIG_ENV_IS_IN_FLASH
246   -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
  246 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
247 247 #define CONFIG_ENV_SECT_SIZE 0x20000
248 248 #define CONFIG_ENV_SIZE 0x20000
249 249 #endif
250 250  
251 251 /* FMan */
252 252 #ifndef SPL_NO_FMAN
253   -#ifdef CONFIG_SYS_DPAA_FMAN
254   -#define CONFIG_FMAN_ENET
  253 +#define AQR105_IRQ_MASK 0x40000000
  254 +
  255 +#ifdef CONFIG_NET
255 256 #define CONFIG_PHYLIB
256   -#define CONFIG_PHYLIB_10G
257 257 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
258   -
259 258 #define CONFIG_PHY_VITESSE
260 259 #define CONFIG_PHY_REALTEK
  260 +#endif
  261 +
  262 +#ifdef CONFIG_SYS_DPAA_FMAN
  263 +#define CONFIG_FMAN_ENET
  264 +#define CONFIG_PHYLIB_10G
261 265 #define CONFIG_PHY_AQUANTIA
262   -#define AQR105_IRQ_MASK 0x40000000
263 266  
264 267 #define RGMII_PHY1_ADDR 0x1
265 268 #define RGMII_PHY2_ADDR 0x2
... ... @@ -281,7 +284,7 @@
281 284 !defined(CONFIG_QSPI_BOOT)
282 285 #define CONFIG_U_QE
283 286 #endif
284   -#define CONFIG_SYS_QE_FW_ADDR 0x60600000
  287 +#define CONFIG_SYS_QE_FW_ADDR 0x60940000
285 288 #endif
286 289  
287 290 /* USB */
include/configs/ls1046a_common.h
Diff comments   View file @ 380e86f
... ... @@ -138,6 +138,16 @@
138 138 #define CONFIG_SYS_I2C_MXC_I2C3
139 139 #define CONFIG_SYS_I2C_MXC_I2C4
140 140  
  141 +/* PCIe */
  142 +#define CONFIG_PCIE1 /* PCIE controller 1 */
  143 +#define CONFIG_PCIE2 /* PCIE controller 2 */
  144 +#define CONFIG_PCIE3 /* PCIE controller 3 */
  145 +
  146 +#ifdef CONFIG_PCI
  147 +#define CONFIG_PCI_SCAN_SHOW
  148 +#define CONFIG_CMD_PCI
  149 +#endif
  150 +
141 151 /* Command line configuration */
142 152  
143 153 /* MMC */
144 154  
145 155  
146 156  
147 157  
... ... @@ -163,23 +173,23 @@
163 173 /*
164 174 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
165 175 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
166   - * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
  176 + * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 18432(0x4800).
167 177 */
168 178 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
169   -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
  179 +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800)
170 180 #elif defined(CONFIG_QSPI_BOOT)
171 181 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
172   -#define CONFIG_SYS_FMAN_FW_ADDR 0x40300000
  182 +#define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
173 183 #define CONFIG_ENV_SPI_BUS 0
174 184 #define CONFIG_ENV_SPI_CS 0
175 185 #define CONFIG_ENV_SPI_MAX_HZ 1000000
176 186 #define CONFIG_ENV_SPI_MODE 0x03
177 187 #elif defined(CONFIG_NAND_BOOT)
178 188 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
179   -#define CONFIG_SYS_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
  189 +#define CONFIG_SYS_FMAN_FW_ADDR (72 * CONFIG_SYS_NAND_BLOCK_SIZE)
180 190 #else
181 191 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
182   -#define CONFIG_SYS_FMAN_FW_ADDR 0x60300000
  192 +#define CONFIG_SYS_FMAN_FW_ADDR 0x60900000
183 193 #endif
184 194 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
185 195 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
include/configs/ls1046aqds.h
Diff comments   View file @ 380e86f
... ... @@ -12,7 +12,7 @@
12 12 #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
13 13 #define CONFIG_SYS_TEXT_BASE 0x82000000
14 14 #elif defined(CONFIG_QSPI_BOOT)
15   -#define CONFIG_SYS_TEXT_BASE 0x40010000
  15 +#define CONFIG_SYS_TEXT_BASE 0x40100000
16 16 #else
17 17 #define CONFIG_SYS_TEXT_BASE 0x60100000
18 18 #endif
19 19  
20 20  
21 21  
... ... @@ -447,20 +447,20 @@
447 447 #ifdef CONFIG_NAND_BOOT
448 448 #define CONFIG_ENV_IS_IN_NAND
449 449 #define CONFIG_ENV_SIZE 0x2000
450   -#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
  450 +#define CONFIG_ENV_OFFSET (24 * CONFIG_SYS_NAND_BLOCK_SIZE)
451 451 #elif defined(CONFIG_SD_BOOT)
452   -#define CONFIG_ENV_OFFSET (1024 * 1024)
  452 +#define CONFIG_ENV_OFFSET (3 * 1024 * 1024)
453 453 #define CONFIG_ENV_IS_IN_MMC
454 454 #define CONFIG_SYS_MMC_ENV_DEV 0
455 455 #define CONFIG_ENV_SIZE 0x2000
456 456 #elif defined(CONFIG_QSPI_BOOT)
457 457 #define CONFIG_ENV_IS_IN_SPI_FLASH
458 458 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
459   -#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
  459 +#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
460 460 #define CONFIG_ENV_SECT_SIZE 0x10000
461 461 #else
462 462 #define CONFIG_ENV_IS_IN_FLASH
463   -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
  463 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
464 464 #define CONFIG_ENV_SECT_SIZE 0x20000
465 465 #define CONFIG_ENV_SIZE 0x20000
466 466 #endif
include/configs/ls1046ardb.h
Diff comments   View file @ 380e86f
... ... @@ -169,27 +169,29 @@
169 169 #if defined(CONFIG_SD_BOOT)
170 170 #define CONFIG_ENV_IS_IN_MMC
171 171 #define CONFIG_SYS_MMC_ENV_DEV 0
172   -#define CONFIG_ENV_OFFSET (1024 * 1024)
  172 +#define CONFIG_ENV_OFFSET (3 * 1024 * 1024)
173 173 #define CONFIG_ENV_SIZE 0x2000
174 174 #else
175 175 #define CONFIG_ENV_IS_IN_SPI_FLASH
176 176 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
177   -#define CONFIG_ENV_OFFSET 0x200000 /* 2MB */
  177 +#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
178 178 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */
179 179 #endif
180 180  
  181 +#define AQR105_IRQ_MASK 0x80000000
181 182 /* FMan */
182 183 #ifndef SPL_NO_FMAN
183   -#ifdef CONFIG_SYS_DPAA_FMAN
184   -#define CONFIG_FMAN_ENET
  184 +
  185 +#ifdef CONFIG_NET
185 186 #define CONFIG_PHYLIB
186   -#define CONFIG_PHYLIB_10G
187 187 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
188   -
189 188 #define CONFIG_PHY_REALTEK
190   -#define CONFIG_PHY_AQUANTIA
191   -#define AQR105_IRQ_MASK 0x80000000
  189 +#endif
192 190  
  191 +#ifdef CONFIG_SYS_DPAA_FMAN
  192 +#define CONFIG_FMAN_ENET
  193 +#define CONFIG_PHY_AQUANTIA
  194 +#define CONFIG_PHYLIB_10G
193 195 #define RGMII_PHY1_ADDR 0x1
194 196 #define RGMII_PHY2_ADDR 0x2
195 197  
... ... @@ -200,6 +202,7 @@
200 202  
201 203 #define CONFIG_ETHPRIME "FM1@DTSEC3"
202 204 #endif
  205 +
203 206 #endif
204 207  
205 208 /* QSPI device */
... ... @@ -208,7 +211,6 @@
208 211 #define CONFIG_SPI_FLASH_SPANSION
209 212 #define FSL_QSPI_FLASH_SIZE (1 << 26)
210 213 #define FSL_QSPI_FLASH_NUM 2
211   -#define CONFIG_SPI_FLASH_BAR
212 214 #endif
213 215 #endif
214 216  
include/configs/ls2080a_common.h
Diff comments   View file @ 380e86f
1 1 /*
  2 + * Copyright 2017 NXP
2 3 * Copyright (C) 2014 Freescale Semiconductor
3 4 *
4 5 * SPDX-License-Identifier: GPL-2.0+
... ... @@ -28,6 +29,12 @@
28 29 #else
29 30 #define CONFIG_SYS_TEXT_BASE 0x30100000
30 31 #endif
  32 +#else
  33 +#define CONFIG_SYS_TEXT_BASE 0x20100000
  34 +#define CONFIG_ENV_IS_IN_SPI_FLASH
  35 +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
  36 +#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
  37 +#define CONFIG_ENV_SECT_SIZE 0x10000
31 38 #endif
32 39  
33 40 #define CONFIG_SUPPORT_RAW_INITRD
34 41  
35 42  
... ... @@ -185,18 +192,18 @@
185 192 "ramdisk_size=0x2000000\0" \
186 193 "fdt_high=0xa0000000\0" \
187 194 "initrd_high=0xffffffffffffffff\0" \
188   - "kernel_start=0x58120000000000\0" \" \
  195 + "kernel_start=0x58100000000000\0" \" \
189 196 "kernel_load=0xa0000000\0" \
190 197 "kernel_size=0x2800000\0" \
191 198 "console=ttyAMA0,38400n8\0" \
192   - "mcinitcmd=fsl_mc start mc 0x580300000" \
193   - " 0x580800000 \0"
  199 + "mcinitcmd=fsl_mc start mc 0x580a00000" \
  200 + " 0x580e00000 \0"
194 201  
195 202 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
196 203 "earlycon=uart8250,mmio,0x21c0500 " \
197 204 "ramdisk_size=0x2000000 default_hugepagesz=2m" \
198 205 " hugepagesz=2m hugepages=256"
199   -#define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580700000 &&" \
  206 +#define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580d00000 &&" \
200 207 " cp.b $kernel_start $kernel_load" \
201 208 " $kernel_size && bootm $kernel_load"
202 209  
include/configs/ls2080aqds.h
Diff comments   View file @ 380e86f
1 1 /*
  2 + * Copyright 2017 NXP
2 3 * Copyright 2015 Freescale Semiconductor
3 4 *
4 5 * SPDX-License-Identifier: GPL-2.0+
5 6  
... ... @@ -262,15 +263,9 @@
262 263 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
263 264 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
264 265  
265   -#if defined(CONFIG_QSPI_BOOT)
266   -#define CONFIG_SYS_TEXT_BASE 0x20010000
267   -#define CONFIG_ENV_IS_IN_SPI_FLASH
268   -#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
269   -#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
270   -#define CONFIG_ENV_SECT_SIZE 0x10000
271   -#else
  266 +#ifndef CONFIG_QSPI_BOOT
272 267 #define CONFIG_ENV_IS_IN_FLASH
273   -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
  268 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
274 269 #define CONFIG_ENV_SECT_SIZE 0x20000
275 270 #define CONFIG_ENV_SIZE 0x2000
276 271 #endif
277 272  
... ... @@ -363,14 +358,14 @@
363 358 "ramdisk_size=0x2000000\0" \
364 359 "fdt_high=0xa0000000\0" \
365 360 "initrd_high=0xffffffffffffffff\0" \
366   - "kernel_start=0x58110000000000\0" \" \
  361 + "kernel_start=0x58100000000000\0" \" \
367 362 "kernel_load=0xa0000000\0" \
368 363 "kernel_size=0x2800000\0" \
369 364 "mcmemsize=0x40000000\0" \
370   - "mcinitcmd=esbc_validate 0x580c80000;" \
371   - "esbc_validate 0x580cc0000;" \
372   - "fsl_mc start mc 0x580300000" \
373   - " 0x580800000 \0"
  365 + "mcinitcmd=esbc_validate 0x580700000;" \
  366 + "esbc_validate 0x580740000;" \
  367 + "fsl_mc start mc 0x580a00000" \
  368 + " 0x580e00000 \0"
374 369 #else
375 370 #define CONFIG_EXTRA_ENV_SETTINGS \
376 371 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
377 372  
... ... @@ -380,12 +375,12 @@
380 375 "ramdisk_size=0x2000000\0" \
381 376 "fdt_high=0xa0000000\0" \
382 377 "initrd_high=0xffffffffffffffff\0" \
383   - "kernel_start=0x58110000000000\0" \" \
  378 + "kernel_start=0x58100000000000\0" \" \
384 379 "kernel_load=0xa0000000\0" \
385 380 "kernel_size=0x2800000\0" \
386 381 "mcmemsize=0x40000000\0" \
387   - "mcinitcmd=fsl_mc start mc 0x580300000" \
388   - " 0x580800000 \0"
  382 + "mcinitcmd=fsl_mc start mc 0x580a00000" \
  383 + " 0x580e00000 \0"
389 384 #endif /* CONFIG_SECURE_BOOT */
390 385  
391 386  
include/configs/ls2080ardb.h
Diff comments   View file @ 380e86f
1 1 /*
  2 + * Copyright 2017 NXP
2 3 * Copyright 2015 Freescale Semiconductor
3 4 *
4 5 * SPDX-License-Identifier: GPL-2.0+
... ... @@ -12,6 +13,14 @@
12 13 #undef CONFIG_CONS_INDEX
13 14 #define CONFIG_CONS_INDEX 2
14 15  
  16 +#ifdef CONFIG_FSL_QSPI
  17 +#ifdef CONFIG_TARGET_LS2081ARDB
  18 +#define CONFIG_QIXIS_I2C_ACCESS
  19 +#endif
  20 +#define CONFIG_SYS_I2C_EARLY_INIT
  21 +#define CONFIG_DISPLAY_BOARDINFO_LATE
  22 +#endif
  23 +
15 24 #define I2C_MUX_CH_VOL_MONITOR 0xa
16 25 #define I2C_VOL_MONITOR_ADDR 0x38
17 26 #define CONFIG_VOL_MONITOR_IR36021_READ
... ... @@ -69,6 +78,7 @@
69 78 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
70 79 CONFIG_SYS_SCSI_MAX_LUN)
71 80  
  81 +#ifndef CONFIG_FSL_QSPI
72 82 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
73 83  
74 84 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
... ... @@ -157,7 +167,6 @@
157 167 #define CONFIG_CMD_NAND
158 168  
159 169 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
160   -
161 170 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
162 171 #define QIXIS_LBMAP_SWITCH 0x06
163 172 #define QIXIS_LBMAP_MASK 0x0f
... ... @@ -242,7 +251,7 @@
242 251 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
243 252  
244 253 #define CONFIG_ENV_IS_IN_FLASH
245   -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
  254 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
246 255 #define CONFIG_ENV_SECT_SIZE 0x20000
247 256 #define CONFIG_ENV_SIZE 0x2000
248 257 #endif
249 258  
250 259  
... ... @@ -250,12 +259,31 @@
250 259 /* Debug Server firmware */
251 260 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
252 261 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
253   -
  262 +#endif
254 263 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
255 264  
  265 +#ifdef CONFIG_TARGET_LS2081ARDB
  266 +#define CONFIG_FSL_QIXIS /* use common QIXIS code */
  267 +#define QIXIS_QMAP_MASK 0x07
  268 +#define QIXIS_QMAP_SHIFT 5
  269 +#define QIXIS_LBMAP_DFLTBANK 0x00
  270 +#define QIXIS_LBMAP_QSPI 0x00
  271 +#define QIXIS_RCW_SRC_QSPI 0x62
  272 +#define QIXIS_LBMAP_ALTBANK 0x20
  273 +#define QIXIS_RST_CTL_RESET 0x31
  274 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  275 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  276 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  277 +#define QIXIS_LBMAP_MASK 0x0f
  278 +#define QIXIS_RST_CTL_RESET_EN 0x30
  279 +#endif
  280 +
256 281 /*
257 282 * I2C
258 283 */
  284 +#ifdef CONFIG_TARGET_LS2081ARDB
  285 +#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
  286 +#endif
259 287 #define I2C_MUX_PCA_ADDR 0x75
260 288 #define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/
261 289  
262 290  
263 291  
264 292  
265 293  
... ... @@ -263,18 +291,33 @@
263 291 #define I2C_MUX_CH_DEFAULT 0x8
264 292  
265 293 /* SPI */
266   -#ifdef CONFIG_FSL_DSPI
  294 +#if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
267 295 #define CONFIG_SPI_FLASH
268   -#define CONFIG_SPI_FLASH_BAR
  296 +#ifdef CONFIG_FSL_QSPI
269 297 #define CONFIG_SPI_FLASH_STMICRO
270 298 #endif
  299 +#ifdef CONFIG_FSL_QSPI
  300 +#ifdef CONFIG_TARGET_LS2081ARDB
  301 +#define CONFIG_SPI_FLASH_STMICRO
  302 +#else
  303 +#define CONFIG_SPI_FLASH_SPANSION
  304 +#endif
  305 +#define FSL_QSPI_FLASH_SIZE SZ_64M /* 64MB */
  306 +#define FSL_QSPI_FLASH_NUM 2
  307 +#endif
  308 +#endif
271 309  
272 310 /*
273 311 * RTC configuration
274 312 */
275 313 #define RTC
  314 +#ifdef CONFIG_TARGET_LS2081ARDB
  315 +#define CONFIG_RTC_PCF8563 1
  316 +#define CONFIG_SYS_I2C_RTC_ADDR 0x51
  317 +#else
276 318 #define CONFIG_RTC_DS3231 1
277 319 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  320 +#endif
278 321  
279 322 /* EEPROM */
280 323 #define CONFIG_ID_EEPROM
281 324  
282 325  
... ... @@ -334,17 +377,18 @@
334 377 "ramdisk_size=0x2000000\0" \
335 378 "fdt_high=0xa0000000\0" \
336 379 "initrd_high=0xffffffffffffffff\0" \
337   - "kernel_start=0x58110000000000\0" \" \
  380 + "kernel_start=0x58100000000000\0" \" \
338 381 "kernel_load=0xa0000000\0" \
339 382 "kernel_size=0x2800000\0" \
340 383 "mcmemsize=0x40000000\0" \
341 384 "fdtfile=fsl-ls2080a-rdb.dtb\0" \
342   - "mcinitcmd=esbc_validate 0x580c80000;" \
343   - "esbc_validate 0x580cc0000;" \
344   - "fsl_mc start mc 0x580300000" \
345   - " 0x580800000 \0" \
  385 + "mcinitcmd=esbc_validate 0x580700000;" \
  386 + "esbc_validate 0x580740000;" \
  387 + "fsl_mc start mc 0x580a00000" \
  388 + " 0x580e00000 \0" \
346 389 BOOTENV
347 390 #else
  391 +#ifdef CONFIG_QSPI_BOOT
348 392 #define CONFIG_EXTRA_ENV_SETTINGS \
349 393 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
350 394 "scriptaddr=0x80800000\0" \
351 395  
352 396  
353 397  
... ... @@ -354,19 +398,38 @@
354 398 "ramdisk_addr_r=0x89000000\0" \
355 399 "loadaddr=0x80100000\0" \
356 400 "kernel_addr=0x100000\0" \
  401 + "ramdisk_size=0x2000000\0" \
  402 + "fdt_high=0xa0000000\0" \
  403 + "initrd_high=0xffffffffffffffff\0" \
  404 + "kernel_start=0x21000000\0" \
  405 + "mcmemsize=0x40000000\0" \
  406 + "mcinitcmd=fsl_mc start mc 0x20a00000" \
  407 + " 0x20e00000 \0" \
  408 + BOOTENV
  409 +#else
  410 +#define CONFIG_EXTRA_ENV_SETTINGS \
  411 + "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  412 + "scriptaddr=0x80800000\0" \
  413 + "kernel_addr_r=0x81000000\0" \
  414 + "pxefile_addr_r=0x81000000\0" \
  415 + "fdt_addr_r=0x88000000\0" \
  416 + "ramdisk_addr_r=0x89000000\0" \
  417 + "loadaddr=0x80100000\0" \
  418 + "kernel_addr=0x100000\0" \
357 419 "ramdisk_addr=0x800000\0" \
358 420 "ramdisk_size=0x2000000\0" \
359 421 "fdt_high=0xa0000000\0" \
360 422 "initrd_high=0xffffffffffffffff\0" \
361   - "kernel_start=0x58110000000000\0" \" \
  423 + "kernel_start=0x58100000000000\0" \" \
362 424 "kernel_load=0xa0000000\0" \
363 425 "kernel_size=0x2800000\0" \
364 426 "mcmemsize=0x40000000\0" \
365 427 "fdtfile=fsl-ls2080a-rdb.dtb\0" \
366   - "mcinitcmd=fsl_mc start mc 0x580300000" \
367   - " 0x580800000 \0" \
  428 + "mcinitcmd=fsl_mc start mc 0x580a00000" \
  429 + " 0x580e00000 \0" \
368 430 BOOTENV
369 431 #endif
  432 +#endif
370 433  
371 434  
372 435 #undef CONFIG_BOOTARGS
373 436  
374 437  
... ... @@ -376,11 +439,18 @@
376 439 " hugepagesz=2m hugepages=256"
377 440  
378 441 #undef CONFIG_BOOTCOMMAND
  442 +#ifdef CONFIG_QSPI_BOOT
  443 +/* Try to boot an on-QSPI kernel first, then do normal distro boot */
  444 +#define CONFIG_BOOTCOMMAND "run mcinitcmd && fsl_mc lazyapply dpl 0x20d00000" \
  445 + " && bootm $kernel_start" \
  446 + " || run distro_bootcmd"
  447 +#else
379 448 /* Try to boot an on-NOR kernel first, then do normal distro boot */
380   -#define CONFIG_BOOTCOMMAND "run mcinitcmd && fsl_mc lazyapply dpl 0x580700000" \
  449 +#define CONFIG_BOOTCOMMAND "run mcinitcmd && fsl_mc lazyapply dpl 0x580d00000" \
381 450 " && cp.b $kernel_start $kernel_load $kernel_size" \
382 451 " && bootm $kernel_load" \
383 452 " || run distro_bootcmd"
  453 +#endif
384 454  
385 455 /* MAC/PHY configuration */
386 456 #ifdef CONFIG_FSL_MC_ENET
... ... @@ -389,7 +459,11 @@
389 459 #define CONFIG_PHY_CORTINA
390 460 #define CONFIG_PHYLIB
391 461 #define CONFIG_SYS_CORTINA_FW_IN_NOR
392   -#define CONFIG_CORTINA_FW_ADDR 0x581000000
  462 +#ifdef CONFIG_QSPI_BOOT
  463 +#define CONFIG_CORTINA_FW_ADDR 0x20980000
  464 +#else
  465 +#define CONFIG_CORTINA_FW_ADDR 0x580980000
  466 +#endif
393 467 #define CONFIG_CORTINA_FW_LENGTH 0x40000
394 468  
395 469 #define CORTINA_PHY_ADDR1 0x10