dm: pch: Add get_gpio_base op

x86 GPIO registers are accessed via I/O port whose base address is configured in a PCI configuration register on the PCH device. Add an op get_gpio_base to get the GPIO base address from PCH. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>

dm: pch: Add get_gpio_base op
x86 GPIO registers are accessed via I/O port whose base address is configured in a PCI configuration register on the PCH device. Add an op get_gpio_base to get the GPIO base address from PCH. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
Bin Meng
1 parent 3e389d8ba6
Showing 2 changed files with 29 additions and 0 deletions Side-by-side Diff
drivers/pch/pch-uclass.c
include/pch.h
@@ -33,6 +33,17 @@
 	return ops->set_spi_protect(dev, protect);
 }
  
+int pch_get_gpio_base(struct udevice *dev, u32 *gbasep)
+{
+	struct pch_ops *ops = pch_get_ops(dev);
+
+	*gbasep = 0;
+	if (!ops->get_gpio_base)
+		return -ENOSYS;
+
+	return ops->get_gpio_base(dev, gbasep);
+}
+
 static int pch_uclass_post_bind(struct udevice *bus)
 {
 	/*
@@ -32,6 +32,15 @@
 	 * @return 0 on success, -ENOSYS if not implemented
 	 */
 	int (*set_spi_protect)(struct udevice *dev, bool protect);
+
+	/**
+	 * get_gpio_base() - get the address of GPIO base
+	 *
+	 * @dev:	PCH device to check
+	 * @gbasep:	Returns address of GPIO base if available, else 0
+	 * @return 0 if OK, -ve on error (e.g. there is no GPIO base)
+	 */
+	int (*get_gpio_base)(struct udevice *dev, u32 *gbasep);
 };
  
 #define pch_get_ops(dev)        ((struct pch_ops *)(dev)->driver->ops)
@@ -54,6 +63,15 @@
  * @return 0 on success, -ENOSYS if not implemented
  */
 int pch_set_spi_protect(struct udevice *dev, bool protect);
+
+/**
+ * pch_get_gpio_base() - get the address of GPIO base
+ *
+ * @dev:	PCH device to check
+ * @gbasep:	Returns address of GPIO base if available, else 0
+ * @return 0 if OK, -ve on error (e.g. there is no GPIO base)
+ */
+int pch_get_gpio_base(struct udevice *dev, u32 *gbasep);
  
 #endif
...	...	@@ -33,6 +33,17 @@
33	33	return ops->set_spi_protect(dev, protect);
34	34	}
35	35
	36	+int pch_get_gpio_base(struct udevice dev, u32 gbasep)
	37	+{
	38	+ struct pch_ops *ops = pch_get_ops(dev);
	39	+
	40	+ *gbasep = 0;
	41	+ if (!ops->get_gpio_base)
	42	+ return -ENOSYS;
	43	+
	44	+ return ops->get_gpio_base(dev, gbasep);
	45	+}
	46	+
36	47	static int pch_uclass_post_bind(struct udevice *bus)
37	48	{
38	49	/*
...	...	@@ -32,6 +32,15 @@
32	32	* @return 0 on success, -ENOSYS if not implemented
33	33	*/
34	34	int (set_spi_protect)(struct udevice dev, bool protect);
	35	+
	36	+ /**
	37	+ * get_gpio_base() - get the address of GPIO base
	38	+ *
	39	+ * @dev: PCH device to check
	40	+ * @gbasep: Returns address of GPIO base if available, else 0
	41	+ * @return 0 if OK, -ve on error (e.g. there is no GPIO base)
	42	+ */
	43	+ int (get_gpio_base)(struct udevice dev, u32 *gbasep);
35	44	};
36	45
37	46	#define pch_get_ops(dev) ((struct pch_ops *)(dev)->driver->ops)
...	...	@@ -54,6 +63,15 @@
54	63	* @return 0 on success, -ENOSYS if not implemented
55	64	*/
56	65	int pch_set_spi_protect(struct udevice *dev, bool protect);
	66	+
	67	+/**
	68	+ * pch_get_gpio_base() - get the address of GPIO base
	69	+ *
	70	+ * @dev: PCH device to check
	71	+ * @gbasep: Returns address of GPIO base if available, else 0
	72	+ * @return 0 if OK, -ve on error (e.g. there is no GPIO base)
	73	+ */
	74	+int pch_get_gpio_base(struct udevice dev, u32 gbasep);
57	75
58	76	#endif