powerpc/p2020ds: Integrated with P2020DS DDR change and enabled hwconfig

Enabled SPD Enabled DDR2 Enabled hwconfig Signed-off-by: York Sun <yorksun@freescale.com>

powerpc/p2020ds: Integrated with P2020DS DDR change and enabled hwconfig
Enabled SPD Enabled DDR2 Enabled hwconfig Signed-off-by: York Sun <yorksun@freescale.com>
york · Kumar Gala
1 parent 5fb8a8a731
Showing 4 changed files with 39 additions and 31 deletions Side-by-side Diff
Makefile
board/freescale/p2020ds/ddr.c
board/freescale/p2020ds/p2020ds.c
include/configs/P2020DS.h
@@ -1788,6 +1788,7 @@
 P2010RDB_NAND_config \
 P2010RDB_SDCARD_config \
 P2010RDB_SPIFLASH_config \
+P2020DS_DDR2_config \
 P2020RDB_config \
 P2020RDB_NAND_config \
 P2020RDB_SDCARD_config \
@@ -12,7 +12,7 @@
 #include <asm/fsl_ddr_sdram.h>
 #include <asm/fsl_ddr_dimm_params.h>
  
-static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address)
+static void get_spd(generic_spd_eeprom_t *spd, unsigned char i2c_address)
 {
 	i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t));
 }
@@ -22,7 +22,7 @@
 	return get_ddr_freq(0);
 }
  
-void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd,
+void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
 		      unsigned int ctrl_num)
 {
 	unsigned int i;
  
@@ -51,27 +51,26 @@
  *  cpo 2-0x1E (30)
  */
  
-
-/* XXX: these values need to be checked for all interleaving modes.  */
-/* XXX: No reliable dual-rank 800 MHz setting has been found.  It may
- *      seem reliable, but errors will appear when memory intensive
- *      program is run. */
-/* XXX: Single rank at 800 MHz is OK.  */
 const board_specific_parameters_t board_specific_parameters[][20] = {
 	{
 	/* 	memory controller 0 			*/
 	/*	  lo|  hi|  num|  clk| cpo|wrdata|2T	*/
 	/*	 mhz| mhz|ranks|adjst|    | delay|	*/
-		{  0, 333,    2,    6,   7,    3,  0},
-		{334, 400,    2,    6,   9,    3,  0},
-		{401, 549,    2,    6,  11,    3,  0},
-		{550, 680,    2,    1,  10,    5,  0},
-		{681, 850,    2,    1,  12,    5,  1},
-		{  0, 333,    1,    6,   7,    3,  0},
-		{334, 400,    1,    6,   9,    3,  0},
-		{401, 549,    1,    6,  11,    3,  0},
-		{550, 680,    1,    1,  10,    5,  0},
-		{681, 850,    1,    1,  12,    5,  0}
+#ifdef CONFIG_FSL_DDR2
+		{  0, 333,    2,    4,   0x1f,    2,  0},
+		{334, 400,    2,    4,   0x1f,    2,  0},
+		{401, 549,    2,    4,   0x1f,    2,  0},
+		{550, 680,    2,    4,   0x1f,    3,  0},
+		{681, 850,    2,    4,   0x1f,    4,  0},
+		{  0, 333,    1,    4,   0x1f,    2,  0},
+		{334, 400,    1,    4,   0x1f,    2,  0},
+		{401, 549,    1,    4,   0x1f,    2,  0},
+		{550, 680,    1,    4,   0x1f,    3,  0},
+		{681, 850,    1,    4,   0x1f,    4,  0}
+#else
+		{  0, 850,    2,    4,   0x1f,    4,  0},
+		{  0, 850,    1,    4,   0x1f,    4,  0}
+#endif
 	},
 };
  
  
@@ -92,18 +91,8 @@
 	 * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
 	 */
 	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-		if (i&1) {	/* odd CS */
 			popts->cs_local_opts[i].odt_rd_cfg = 0;
-			popts->cs_local_opts[i].odt_wr_cfg = 0;
-		} else {	/* even CS */
-			if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
-				popts->cs_local_opts[i].odt_rd_cfg = 0;
-				popts->cs_local_opts[i].odt_wr_cfg = 4;
-			} else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
-				popts->cs_local_opts[i].odt_rd_cfg = 3;
-				popts->cs_local_opts[i].odt_wr_cfg = 3;
-			}
-		}
+			popts->cs_local_opts[i].odt_wr_cfg = 1;
 	}
  
 	/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
@@ -127,5 +116,14 @@
 	 *	- number of DIMMs installed
 	 */
 	popts->half_strength_driver_enable = 0;
+	popts->wrlvl_en = 1;
+	/* Write leveling override */
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xa;
+	popts->wrlvl_start = 0x7;
+	/* Rtt and Rtt_WR override */
+	popts->rtt_override = 1;
+	popts->rtt_override_value = DDR3_RTT_120_OHM;
+	popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */
 }
@@ -69,13 +69,16 @@
 	return 0;
 }
  
+const char *board_hwconfig = "foo:bar=baz";
+const char *cpu_hwconfig = "foo:bar=baz";
+
 phys_size_t initdram(int board_type)
 {
 	phys_size_t dram_size = 0;
  
 	puts("Initializing....");
  
-#ifdef CONFIG_SPD_EEPROM
+#ifdef CONFIG_DDR_SPD
 	dram_size = fsl_ddr_sdram();
 #else
 	dram_size = fixed_sdram();
@@ -94,7 +97,7 @@
 	return dram_size;
 }
  
-#if !defined(CONFIG_SPD_EEPROM)
+#if !defined(CONFIG_DDR_SPD)
 /*
  * Fixed sdram init -- doesn't use serial presence detect.
  */
@@ -92,7 +92,11 @@
  
 /* DDR Setup */
 #define CONFIG_VERY_BIG_RAM
+#ifdef CONFIG_MK_DDR2
+#define CONFIG_FSL_DDR2
+#else
 #define CONFIG_FSL_DDR3		1
+#endif
 #undef CONFIG_FSL_DDR_INTERACTIVE
  
 /* ECC will be enabled based on perf_mode environment variable */
@@ -109,6 +113,7 @@
 #define CONFIG_CHIP_SELECTS_PER_CTRL	2
  
 /* I2C addresses of SPD EEPROMs */
+#define CONFIG_DDR_SPD
 #define CONFIG_SYS_SPD_BUS_NUM		0	/* SPD EEPROM located on I2C bus 0 */
 #define SPD_EEPROM_ADDRESS1	0x51	/* CTLR 0 DIMM 0 */
  
@@ -228,6 +233,7 @@
  
 #define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
  
+#define CONFIG_HWCONFIG			/* enable hwconfig */
 #define CONFIG_FSL_NGPIXIS		/* use common ngPIXIS code */
  
 #ifdef CONFIG_FSL_NGPIXIS
...	...	@@ -1788,6 +1788,7 @@
1788	1788	P2010RDB_NAND_config \
1789	1789	P2010RDB_SDCARD_config \
1790	1790	P2010RDB_SPIFLASH_config \
	1791	+P2020DS_DDR2_config \
1791	1792	P2020RDB_config \
1792	1793	P2020RDB_NAND_config \
1793	1794	P2020RDB_SDCARD_config \
...	...	@@ -12,7 +12,7 @@
12	12	#include <asm/fsl_ddr_sdram.h>
13	13	#include <asm/fsl_ddr_dimm_params.h>
14	14
15		-static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address)
	15	+static void get_spd(generic_spd_eeprom_t *spd, unsigned char i2c_address)
16	16	{
17	17	i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t));
18	18	}
...	...	@@ -22,7 +22,7 @@
22	22	return get_ddr_freq(0);
23	23	}
24	24
25		-void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd,
	25	+void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
26	26	unsigned int ctrl_num)
27	27	{
28	28	unsigned int i;
29	29
...	...	@@ -51,27 +51,26 @@
51	51	* cpo 2-0x1E (30)
52	52	*/
53	53
54		-
55		-/* XXX: these values need to be checked for all interleaving modes. */
56		-/* XXX: No reliable dual-rank 800 MHz setting has been found. It may
57		- * seem reliable, but errors will appear when memory intensive
58		- * program is run. */
59		-/* XXX: Single rank at 800 MHz is OK. */
60	54	const board_specific_parameters_t board_specific_parameters[][20] = {
61	55	{
62	56	/* memory controller 0 */
63	57	/* lo\| hi\| num\| clk\| cpo\|wrdata\|2T */
64	58	/* mhz\| mhz\|ranks\|adjst\| \| delay\| */
65		- { 0, 333, 2, 6, 7, 3, 0},
66		- {334, 400, 2, 6, 9, 3, 0},
67		- {401, 549, 2, 6, 11, 3, 0},
68		- {550, 680, 2, 1, 10, 5, 0},
69		- {681, 850, 2, 1, 12, 5, 1},
70		- { 0, 333, 1, 6, 7, 3, 0},
71		- {334, 400, 1, 6, 9, 3, 0},
72		- {401, 549, 1, 6, 11, 3, 0},
73		- {550, 680, 1, 1, 10, 5, 0},
74		- {681, 850, 1, 1, 12, 5, 0}
	59	+#ifdef CONFIG_FSL_DDR2
	60	+ { 0, 333, 2, 4, 0x1f, 2, 0},
	61	+ {334, 400, 2, 4, 0x1f, 2, 0},
	62	+ {401, 549, 2, 4, 0x1f, 2, 0},
	63	+ {550, 680, 2, 4, 0x1f, 3, 0},
	64	+ {681, 850, 2, 4, 0x1f, 4, 0},
	65	+ { 0, 333, 1, 4, 0x1f, 2, 0},
	66	+ {334, 400, 1, 4, 0x1f, 2, 0},
	67	+ {401, 549, 1, 4, 0x1f, 2, 0},
	68	+ {550, 680, 1, 4, 0x1f, 3, 0},
	69	+ {681, 850, 1, 4, 0x1f, 4, 0}
	70	+#else
	71	+ { 0, 850, 2, 4, 0x1f, 4, 0},
	72	+ { 0, 850, 1, 4, 0x1f, 4, 0}
	73	+#endif
75	74	},
76	75	};
77	76
78	77
...	...	@@ -92,18 +91,8 @@
92	91	* odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
93	92	*/
94	93	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
95		- if (i&1) { /* odd CS */
96	94	popts->cs_local_opts[i].odt_rd_cfg = 0;
97		- popts->cs_local_opts[i].odt_wr_cfg = 0;
98		- } else { /* even CS */
99		- if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
100		- popts->cs_local_opts[i].odt_rd_cfg = 0;
101		- popts->cs_local_opts[i].odt_wr_cfg = 4;
102		- } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
103		- popts->cs_local_opts[i].odt_rd_cfg = 3;
104		- popts->cs_local_opts[i].odt_wr_cfg = 3;
105		- }
106		- }
	95	+ popts->cs_local_opts[i].odt_wr_cfg = 1;
107	96	}
108	97
109	98	/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
...	...	@@ -127,5 +116,14 @@
127	116	* - number of DIMMs installed
128	117	*/
129	118	popts->half_strength_driver_enable = 0;
	119	+ popts->wrlvl_en = 1;
	120	+ /* Write leveling override */
	121	+ popts->wrlvl_override = 1;
	122	+ popts->wrlvl_sample = 0xa;
	123	+ popts->wrlvl_start = 0x7;
	124	+ /* Rtt and Rtt_WR override */
	125	+ popts->rtt_override = 1;
	126	+ popts->rtt_override_value = DDR3_RTT_120_OHM;
	127	+ popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */
130	128	}
...	...	@@ -69,13 +69,16 @@
69	69	return 0;
70	70	}
71	71
	72	+const char *board_hwconfig = "foo:bar=baz";
	73	+const char *cpu_hwconfig = "foo:bar=baz";
	74	+
72	75	phys_size_t initdram(int board_type)
73	76	{
74	77	phys_size_t dram_size = 0;
75	78
76	79	puts("Initializing....");
77	80
78		-#ifdef CONFIG_SPD_EEPROM
	81	+#ifdef CONFIG_DDR_SPD
79	82	dram_size = fsl_ddr_sdram();
80	83	#else
81	84	dram_size = fixed_sdram();
...	...	@@ -94,7 +97,7 @@
94	97	return dram_size;
95	98	}
96	99
97		-#if !defined(CONFIG_SPD_EEPROM)
	100	+#if !defined(CONFIG_DDR_SPD)
98	101	/*
99	102	* Fixed sdram init -- doesn't use serial presence detect.
100	103	*/
...	...	@@ -92,7 +92,11 @@
92	92
93	93	/* DDR Setup */
94	94	#define CONFIG_VERY_BIG_RAM
	95	+#ifdef CONFIG_MK_DDR2
	96	+#define CONFIG_FSL_DDR2
	97	+#else
95	98	#define CONFIG_FSL_DDR3 1
	99	+#endif
96	100	#undef CONFIG_FSL_DDR_INTERACTIVE
97	101
98	102	/* ECC will be enabled based on perf_mode environment variable */
...	...	@@ -109,6 +113,7 @@
109	113	#define CONFIG_CHIP_SELECTS_PER_CTRL 2
110	114
111	115	/* I2C addresses of SPD EEPROMs */
	116	+#define CONFIG_DDR_SPD
112	117	#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD EEPROM located on I2C bus 0 */
113	118	#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
114	119
...	...	@@ -228,6 +233,7 @@
228	233
229	234	#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
230	235
	236	+#define CONFIG_HWCONFIG /* enable hwconfig */
231	237	#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
232	238
233	239	#ifdef CONFIG_FSL_NGPIXIS