Eric Lee / smarc-uboot

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Commit 39ea1ae1f0d68871c070b7db3e67435069c21254

Authored by Ye Li
1 parent 0a4b78f3b3
Exists in smarc-rel_imx_4.1.15_2.0.0_ga

MLK-12737 mx6qp/mx6dp: Fix runtime CPU type checking issue 

2016 u-boot added dummy CPU types for the i.MX6QP and i.MX6DP. When
doing runtime cpu type checking, we can't use CPU type of i.MX6Q and
i.MX6D for them more, which is ok in 2015 u-boot.

This patch adds the MXC_CPU_MX6QP and MXC_CPU_MX6DP at some places missed to
do the checking.

Signed-off-by: Ye Li <ye.li@nxp.com>

Showing 6 changed files with 33 additions and 9 deletions Side-by-side Diff

arch/arm/cpu/armv7/mx6/ddr.c
Diff comments   View file @ 39ea1ae
... ... @@ -1222,7 +1222,8 @@
1222 1222 mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
1223 1223  
1224 1224 /* Limit mem_speed for MX6D/MX6Q */
1225   - if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
  1225 + if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D) ||
  1226 + is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)) {
1226 1227 if (mem_speed > 1066)
1227 1228 mem_speed = 1066; /* 1066 MT/s */
1228 1229  
... ... @@ -1241,7 +1242,8 @@
1241 1242 * Data rate of 1066 MT/s requires 533 MHz DDR3 clock, but MX6D/Q supports
1242 1243 * up to 528 MHz, so reduce the clock to fit chip specs
1243 1244 */
1244   - if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
  1245 + if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D) ||
  1246 + is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)) {
1245 1247 if (clock > 528)
1246 1248 clock = 528; /* 528 MHz */
1247 1249 }
arch/arm/cpu/armv7/mx6/soc.c
Diff comments   View file @ 39ea1ae
... ... @@ -142,14 +142,16 @@
142 142 switch (val) {
143 143 /* Valid for IMX6DQ */
144 144 case OCOTP_CFG3_SPEED_1P2GHZ:
145   - if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
  145 + if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D) ||
  146 + is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
146 147 return 1200000000;
147 148 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
148 149 case OCOTP_CFG3_SPEED_1GHZ:
149 150 return 996000000;
150 151 /* Valid for IMX6DQ */
151 152 case OCOTP_CFG3_SPEED_850MHZ:
152   - if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
  153 + if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D) ||
  154 + is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
153 155 return 852000000;
154 156 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
155 157 case OCOTP_CFG3_SPEED_800MHZ:
... ... @@ -206,6 +208,9 @@
206 208  
207 209 if (type == MXC_CPU_MX6D)
208 210 cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
  211 +
  212 + if (type == MXC_CPU_MX6QP || type == MXC_CPU_MX6DP)
  213 + cpurev = (MXC_CPU_MX6Q) << 12 | ((cpurev + 0x10) & 0xFFF);
209 214  
210 215 return cpurev;
211 216 }
arch/arm/imx-common/hab.c
Diff comments   View file @ 39ea1ae
... ... @@ -17,6 +17,9 @@
17 17  
18 18 #define hab_rvt_report_event_p \
19 19 ( \
  20 + (is_cpu_type(MXC_CPU_MX6QP) || \
  21 + is_cpu_type(MXC_CPU_MX6DP)) ? \
  22 + ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \
20 23 ((is_cpu_type(MXC_CPU_MX6Q) || \
21 24 is_cpu_type(MXC_CPU_MX6D)) && \
22 25 (soc_rev() >= CHIP_REV_1_5)) ? \
... ... @@ -30,6 +33,9 @@
30 33  
31 34 #define hab_rvt_report_status_p \
32 35 ( \
  36 + (is_cpu_type(MXC_CPU_MX6QP) || \
  37 + is_cpu_type(MXC_CPU_MX6DP)) ? \
  38 + ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
33 39 ((is_cpu_type(MXC_CPU_MX6Q) || \
34 40 is_cpu_type(MXC_CPU_MX6D)) && \
35 41 (soc_rev() >= CHIP_REV_1_5)) ? \
... ... @@ -43,6 +49,9 @@
43 49  
44 50 #define hab_rvt_authenticate_image_p \
45 51 ( \
  52 + (is_cpu_type(MXC_CPU_MX6QP) || \
  53 + is_cpu_type(MXC_CPU_MX6DP)) ? \
  54 + ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
46 55 ((is_cpu_type(MXC_CPU_MX6Q) || \
47 56 is_cpu_type(MXC_CPU_MX6D)) && \
48 57 (soc_rev() >= CHIP_REV_1_5)) ? \
... ... @@ -56,6 +65,9 @@
56 65  
57 66 #define hab_rvt_entry_p \
58 67 ( \
  68 + (is_cpu_type(MXC_CPU_MX6QP) || \
  69 + is_cpu_type(MXC_CPU_MX6DP)) ? \
  70 + ((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \
59 71 ((is_cpu_type(MXC_CPU_MX6Q) || \
60 72 is_cpu_type(MXC_CPU_MX6D)) && \
61 73 (soc_rev() >= CHIP_REV_1_5)) ? \
... ... @@ -69,6 +81,9 @@
69 81  
70 82 #define hab_rvt_exit_p \
71 83 ( \
  84 + (is_cpu_type(MXC_CPU_MX6QP) || \
  85 + is_cpu_type(MXC_CPU_MX6DP)) ? \
  86 + ((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \
72 87 ((is_cpu_type(MXC_CPU_MX6Q) || \
73 88 is_cpu_type(MXC_CPU_MX6D)) && \
74 89 (soc_rev() >= CHIP_REV_1_5)) ? \
... ... @@ -437,8 +452,7 @@
437 452 * do cache flushes. don't think any
438 453 * exist, so we ignore them.
439 454 */
440   - if (!is_mx6dqp())
441   - writel(1, MX6DQ_PU_IROM_MMU_EN_VAR);
  455 + writel(1, MX6DQ_PU_IROM_MMU_EN_VAR);
442 456 } else if (is_cpu_type(MXC_CPU_MX6DL) ||
443 457 is_cpu_type(MXC_CPU_MX6SOLO)) {
444 458 writel(1, MX6DLS_PU_IROM_MMU_EN_VAR);
arch/arm/imx-common/sata.c
Diff comments   View file @ 39ea1ae
... ... @@ -15,7 +15,8 @@
15 15 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
16 16 int ret;
17 17  
18   - if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
  18 + if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D) &&
  19 + !is_cpu_type(MXC_CPU_MX6QP) && !is_cpu_type(MXC_CPU_MX6DP))
19 20 return 1;
20 21  
21 22 ret = enable_sata_clock();
arch/arm/imx-common/timer.c
Diff comments   View file @ 39ea1ae
... ... @@ -43,7 +43,8 @@
43 43 static inline int gpt_has_clk_source_osc(void)
44 44 {
45 45 #if defined(CONFIG_MX6)
46   - if (((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) &&
  46 + if (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP) ||
  47 + ((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) &&
47 48 (soc_rev() > CHIP_REV_1_0)) || is_cpu_type(MXC_CPU_MX6DL) ||
48 49 is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX) ||
49 50 is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6ULL))
drivers/block/dwc_ahsata.c
Diff comments   View file @ 39ea1ae
... ... @@ -563,7 +563,8 @@
563 563 struct ahci_probe_ent *probe_ent = NULL;
564 564  
565 565 #if defined(CONFIG_MX6)
566   - if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
  566 + if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D) &&
  567 + !is_cpu_type(MXC_CPU_MX6QP) && !is_cpu_type(MXC_CPU_MX6DP))
567 568 return 1;
568 569 #endif
569 570 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {