Commit 3a4800a5968f689788d70f7decb000a3d3e1a2f4

Authored by Aneesh Bansal
Committed by York Sun
1 parent 9711f52806

drivers/crypto/fsl: fix endianness issue in RNG

For Setting and clearing the bits in SEC Block registers
sec_clrbits32() and sec_setbits32() are used which work as
per endianness of CAAM block.
So these must be used with SEC register address as argument.
If the value is read in a local variable, then the functions
will not behave correctly where endianness of CAAM and core is
different.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
CC: Alex Porosanu <alexandru.porosanu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

Showing 1 changed file with 2 additions and 6 deletions Side-by-side Diff

drivers/crypto/fsl/jr.c
... ... @@ -470,17 +470,13 @@
470 470 sec_out32(&rng->rtfreqmin, ent_delay >> 2);
471 471 /* disable maximum frequency count */
472 472 sec_out32(&rng->rtfreqmax, RTFRQMAX_DISABLE);
473   - /* read the control register */
474   - val = sec_in32(&rng->rtmctl);
475 473 /*
476 474 * select raw sampling in both entropy shifter
477 475 * and statistical checker
478 476 */
479   - sec_setbits32(&val, RTMCTL_SAMP_MODE_RAW_ES_SC);
  477 + sec_setbits32(&rng->rtmctl, RTMCTL_SAMP_MODE_RAW_ES_SC);
480 478 /* put RNG4 into run mode */
481   - sec_clrbits32(&val, RTMCTL_PRGM);
482   - /* write back the control register */
483   - sec_out32(&rng->rtmctl, val);
  479 + sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM);
484 480 }
485 481  
486 482 static int rng_init(void)