Revert "armv8: Enable CPUECTLR.SMPEN for coherency"

Upon further review this breaks most other platforms as we need to check what core we're running on before touching it at all. This reverts commit d73718f3236c520a92efa401084c658e6cc067f3. Signed-off-by: Tom Rini <trini@konsulko.com>

Revert "armv8: Enable CPUECTLR.SMPEN for coherency"
Upon further review this breaks most other platforms as we need to check what core we're running on before touching it at all. This reverts commit d73718f3236c520a92efa401084c658e6cc067f3. Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini
1 parent b8e599746c
Showing 1 changed file with 0 additions and 8 deletions Side-by-side Diff
arch/arm/cpu/armv8/start.S
@@ -81,14 +81,6 @@
 	msr	cpacr_el1, x0			/* Enable FP/SIMD */
 0:
  
-	/* Enalbe SMPEN bit for coherency.
-	 * This register is not architectural but at the moment
-	 * this bit should be set for A53/A57/A72.
-	 */
-	mrs     x0, S3_1_c15_c2_1               /* cpuactlr_el1 */
-	orr     x0, x0, #0x40
-	msr     S3_1_c15_c2_1, x0
-
 	/* Apply ARM core specific erratas */
 	bl	apply_core_errata
...	...	@@ -81,14 +81,6 @@
81	81	msr cpacr_el1, x0 /* Enable FP/SIMD */
82	82	0:
83	83
84		- /* Enalbe SMPEN bit for coherency.
85		- * This register is not architectural but at the moment
86		- * this bit should be set for A53/A57/A72.
87		- */
88		- mrs x0, S3_1_c15_c2_1 /* cpuactlr_el1 */
89		- orr x0, x0, #0x40
90		- msr S3_1_c15_c2_1, x0
91		-
92	84	/* Apply ARM core specific erratas */
93	85	bl apply_core_errata
94	86