Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit 3a990bfaeaf3d8388e1a62163e9361fe89ae3c79

Authored by Dirk Eibach
Committed by Tom Rini
1 parent 5568fb4402
Exists in v2017.01-smarct4x and in 40 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

board: gdsys: Make gdsys osd hardware detection more robust 

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>

Showing 5 changed files with 79 additions and 60 deletions Side-by-side Diff

board/gdsys/405ep/iocon.c
Diff comments   View file @ 3a990bf
... ... @@ -15,7 +15,6 @@
15 15 #include "405ep.h"
16 16 #include <gdsys_fpga.h>
17 17  
18   -#include "../common/dp501.h"
19 18 #include "../common/osd.h"
20 19 #include "../common/mclink.h"
21 20  
... ... @@ -99,8 +98,6 @@
99 98 unsigned int mclink_fpgacount;
100 99 struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
101 100  
102   -int dp501_i2c[] = CONFIG_SYS_DP501_I2C;
103   -
104 101 static int setup_88e1518(const char *bus, unsigned char addr);
105 102  
106 103 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
107 104  
108 105  
109 106  
... ... @@ -374,20 +371,16 @@
374 371 u16 fpga_features;
375 372 int feature_carrier_speed = fpga_features & (1<<4);
376 373 bool ch0_rgmii2_present = false;
377   - int old_bus = i2c_get_bus_num();
378 374  
379 375 FPGA_GET_REG(0, fpga_features, &fpga_features);
380 376  
381   - /* Turn on Parade DP501 */
382   - pca9698_direction_output(0x20, 9, 1);
383   - udelay(500000);
  377 + if (!legacy) {
  378 + /* Turn on Parade DP501 */
  379 + pca9698_direction_output(0x20, 9, 1);
  380 + udelay(500000);
384 381  
385   - i2c_set_bus_num(dp501_i2c[0]);
386   - dp501_powerup(0x08);
387   - i2c_set_bus_num(old_bus);
388   -
389   - if (!legacy)
390 382 ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
  383 + }
391 384  
392 385 print_fpga_info(0, ch0_rgmii2_present);
393 386 osd_probe(0);
board/gdsys/common/osd.c
Diff comments   View file @ 3a990bf
... ... @@ -9,6 +9,7 @@
9 9 #include <i2c.h>
10 10 #include <malloc.h>
11 11  
  12 +#include "dp501.h"
12 13 #include <gdsys_fpga.h>
13 14  
14 15 #define CH7301_I2C_ADDR 0x75
... ... @@ -24,6 +25,8 @@
24 25 #define SIL1178_MASTER_I2C_ADDRESS 0x38
25 26 #define SIL1178_SLAVE_I2C_ADDRESS 0x39
26 27  
  28 +#define DP501_I2C_ADDR 0x08
  29 +
27 30 #define PIXCLK_640_480_60 25180000
28 31  
29 32 enum {
30 33  
31 34  
32 35  
... ... @@ -54,18 +57,23 @@
54 57  
55 58 unsigned int max_osd_screen = CONFIG_SYS_OSD_SCREENS - 1;
56 59  
57   -#ifdef CONFIG_SYS_CH7301
58   -int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C;
  60 +#ifdef CONFIG_SYS_ICS8N3QV01_I2C
  61 +int ics8n3qv01_i2c[] = CONFIG_SYS_ICS8N3QV01_I2C;
59 62 #endif
60 63  
61   -#ifdef CONFIG_SYS_ICS8N3QV01
62   -int ics8n3qv01_i2c[] = CONFIG_SYS_ICS8N3QV01_I2C;
  64 +#ifdef CONFIG_SYS_CH7301_I2C
  65 +int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C;
63 66 #endif
64 67  
65   -#ifdef CONFIG_SYS_SIL1178
  68 +#ifdef CONFIG_SYS_SIL1178_I2C
66 69 int sil1178_i2c[] = CONFIG_SYS_SIL1178_I2C;
67 70 #endif
68 71  
  72 +#ifdef CONFIG_SYS_DP501_I2C
  73 +int dp501_i2c[] = CONFIG_SYS_DP501_I2C;
  74 +#endif
  75 +
  76 +
69 77 #ifdef CONFIG_SYS_MPC92469AC
70 78 static void mpc92469ac_calc_parameters(unsigned int fout,
71 79 unsigned int *post_div, unsigned int *feedback_div)
... ... @@ -118,7 +126,7 @@
118 126 }
119 127 #endif
120 128  
121   -#ifdef CONFIG_SYS_ICS8N3QV01
  129 +#ifdef CONFIG_SYS_ICS8N3QV01_I2C
122 130  
123 131 static unsigned int ics8n3qv01_get_fout_calc(unsigned index)
124 132 {
... ... @@ -283,6 +291,8 @@
283 291 u16 features;
284 292 u8 value;
285 293 int old_bus = i2c_get_bus_num();
  294 + bool pixclock_present = false;
  295 + bool output_driver_present = false;
286 296  
287 297 FPGA_GET_REG(0, osd.version, &version);
288 298 FPGA_GET_REG(0, osd.features, &features);
289 299  
290 300  
291 301  
292 302  
293 303  
294 304  
295 305  
... ... @@ -297,50 +307,75 @@
297 307 printf("OSD%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n",
298 308 screen, version/100, version%100, base_width, base_height);
299 309  
300   -#ifdef CONFIG_SYS_CH7301
301   - i2c_set_bus_num(ch7301_i2c[screen]);
302   - value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID);
303   - if (value != 0x17) {
304   - printf(" Probing CH7301 failed, DID %02x\n", value);
305   - i2c_set_bus_num(old_bus);
306   - return -1;
307   - }
308   - i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08);
309   - i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16);
310   - i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60);
311   - i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09);
312   - i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0);
313   -#endif
  310 + /* setup pixclock */
314 311  
315 312 #ifdef CONFIG_SYS_MPC92469AC
  313 + pixclock_present = true;
316 314 mpc92469ac_set(screen, PIXCLK_640_480_60);
317 315 #endif
318 316  
319   -#ifdef CONFIG_SYS_ICS8N3QV01
  317 +#ifdef CONFIG_SYS_ICS8N3QV01_I2C
320 318 i2c_set_bus_num(ics8n3qv01_i2c[screen]);
321   - ics8n3qv01_set(PIXCLK_640_480_60);
  319 + if (!i2c_probe(ICS8N3QV01_I2C_ADDR)) {
  320 + ics8n3qv01_set(PIXCLK_640_480_60);
  321 + pixclock_present = true;
  322 + }
322 323 #endif
323 324  
324   -#ifdef CONFIG_SYS_SIL1178
  325 + if (!pixclock_present)
  326 + printf(" no pixelclock found\n");
  327 +
  328 + /* setup output driver */
  329 +
  330 +#ifdef CONFIG_SYS_CH7301_I2C
  331 + i2c_set_bus_num(ch7301_i2c[screen]);
  332 + if (!i2c_probe(CH7301_I2C_ADDR)) {
  333 + value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID);
  334 + if (value == 0x17) {
  335 + i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08);
  336 + i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16);
  337 + i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60);
  338 + i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09);
  339 + i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0);
  340 + output_driver_present = true;
  341 + }
  342 + }
  343 +#endif
  344 +
  345 +#ifdef CONFIG_SYS_SIL1178_I2C
325 346 i2c_set_bus_num(sil1178_i2c[screen]);
326   - value = i2c_reg_read(SIL1178_SLAVE_I2C_ADDRESS, 0x02);
327   - if (value != 0x06) {
328   - printf(" Probing SIL1178, DEV_IDL %02x\n", value);
329   - i2c_set_bus_num(old_bus);
330   - return -1;
  347 + if (!i2c_probe(SIL1178_SLAVE_I2C_ADDRESS)) {
  348 + value = i2c_reg_read(SIL1178_SLAVE_I2C_ADDRESS, 0x02);
  349 + if (value == 0x06) {
  350 + /*
  351 + * magic initialization sequence,
  352 + * adapted from datasheet
  353 + */
  354 + i2c_reg_write(SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36);
  355 + i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44);
  356 + i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c);
  357 + i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10);
  358 + i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80);
  359 + i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30);
  360 + i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89);
  361 + i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60);
  362 + i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36);
  363 + i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37);
  364 + output_driver_present = true;
  365 + }
331 366 }
332   - /* magic initialization sequence adapted from datasheet */
333   - i2c_reg_write(SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36);
334   - i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44);
335   - i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c);
336   - i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10);
337   - i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80);
338   - i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30);
339   - i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89);
340   - i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60);
341   - i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36);
342   - i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37);
343 367 #endif
  368 +
  369 +#ifdef CONFIG_SYS_DP501_I2C
  370 + i2c_set_bus_num(dp501_i2c[screen]);
  371 + if (!i2c_probe(DP501_I2C_ADDR)) {
  372 + dp501_powerup(DP501_I2C_ADDR);
  373 + output_driver_present = true;
  374 + }
  375 +#endif
  376 +
  377 + if (!output_driver_present)
  378 + printf(" no output driver found\n");
344 379  
345 380 FPGA_SET_REG(screen, osd.control, 0x0049);
346 381  
drivers/i2c/ihs_i2c.c
Diff comments   View file @ 3a990bf
... ... @@ -34,7 +34,6 @@
34 34 | (read ? I2CINT_RECEIVE_EV : I2CINT_TRANSMIT_EV)))) {
35 35 udelay(10);
36 36 if (ctr++ > 5000) {
37   - printf("I2C timeout\n");
38 37 return 1;
39 38 }
40 39 FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, &val);
include/configs/dlvision-10g.h
Diff comments   View file @ 3a990bf
... ... @@ -121,9 +121,7 @@
121 121 { 54, 27 }, { 56, 31 }, { 58, 36 }, { 60, 40 } }
122 122 #define CONFIG_DTT_TACH_LIMIT 0xa10
123 123  
124   -#define CONFIG_SYS_ICS8N3QV01
125 124 #define CONFIG_SYS_ICS8N3QV01_I2C {0, 1}
126   -#define CONFIG_SYS_SIL1178
127 125 #define CONFIG_SYS_SIL1178_I2C {0, 1}
128 126  
129 127 /* EBC peripherals */
include/configs/iocon.h
Diff comments   View file @ 3a990bf
... ... @@ -167,11 +167,6 @@
167 167 #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
168 168  
169 169 /*
170   - * OSD hardware
171   - */
172   -#define CONFIG_SYS_MPC92469AC
173   -
174   -/*
175 170 * FLASH organization
176 171 */
177 172 #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
... ... @@ -298,7 +293,6 @@
298 293 /*
299 294 * OSD Setup
300 295 */
301   -#define CONFIG_SYS_ICS8N3QV01
302 296 #define CONFIG_SYS_MPC92469AC
303 297 #define CONFIG_SYS_OSD_SCREENS 1
304 298 #define CONFIG_SYS_DP501_DIFFERENTIAL