Eric Lee / smarc-uboot

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Commit 3b52847a451a81001b578353e793d7d9739b69d6

Authored by Tom Rini
2 parents c590e62d3b 4b87f2d500
Exists in smarc_8mq_lf_v2020.04 and in 11 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

Merge tag 'xilinx-for-v2018.07' of git://www.denx.de/git/u-boot-microblaze 

Xilinx changes for v2018.07

microblaze:
- Align defconfig

zynq:
- Rework fpga initialization and cpuinfo handling

zynqmp:
- Add ZynqMP R5 support
- Wire and enable watchdog on zcu100-revC
- Setup MMU map for DDR at run time
- Show board info based on DT and cleanup IDENT_STRING

zynqmp tools:
- Add read partition support
- Add initial support for Xilinx bif format for boot.bin generation

mmc:
- Fix get_timer usage on 64bit cpus
- Add support for SD3.0 UHS mode

nand-zynq:
- Add support for 16bit buswidth
- Use address cycles from onfi params

scsi:
- convert ceva sata to UCLASS_AHCI

timer:
- Add Cadence TTC for ZynqMP r5

watchdog:
- Minor cadence driver cleanup

Showing 85 changed files Side-by-side Diff

... ... @@ -274,7 +274,7 @@
274 274 M: Michal Simek <michal.simek@xilinx.com>
275 275 S: Maintained
276 276 T: git git://git.denx.de/u-boot-microblaze.git
277   -F: arch/arm/mach-zynq/
  277 +F: arch/arm/cpu/armv8/zynqmp/
278 278 F: drivers/clk/clk_zynqmp.c
279 279 F: drivers/fpga/zynqpl.c
280 280 F: drivers/gpio/zynq_gpio.c
281 281  
282 282  
... ... @@ -288,11 +288,18 @@
288 288 F: drivers/serial/serial_zynq.c
289 289 F: drivers/spi/zynq_qspi.c
290 290 F: drivers/spi/zynq_spi.c
  291 +F: drivers/timer/cadence-ttc.c
291 292 F: drivers/usb/host/ehci-zynq.c
292 293 F: drivers/watchdog/cdns_wdt.c
293 294 F: include/zynqmppl.h
294   -F: tools/zynqimage.c
  295 +F: tools/zynqmp*
295 296 N: zynqmp
  297 +
  298 +ARM ZYNQMP R5
  299 +M: Michal Simek <michal.simek@xilinx.com>
  300 +S: Maintained
  301 +T: git git://git.denx.de/u-boot-microblaze.git
  302 +F: arch/arm/mach-zynqmp-r5/
296 303  
297 304 BUILDMAN
298 305 M: Simon Glass <sjg@chromium.org>
... ... @@ -821,7 +821,16 @@
821 821 imply CMD_CLK
822 822 imply FAT_WRITE
823 823 imply CMD_SPL
  824 + imply ARCH_EARLY_INIT_R
824 825  
  826 +config ARCH_ZYNQMP_R5
  827 + bool "Xilinx ZynqMP R5 based platform"
  828 + select CPU_V7R
  829 + select OF_CONTROL
  830 + select DM
  831 + select DM_SERIAL
  832 + select CLK
  833 +
825 834 config ARCH_ZYNQMP
826 835 bool "Xilinx ZynqMP based platform"
827 836 select ARM64
... ... @@ -1343,6 +1352,8 @@
1343 1352 source "arch/arm/cpu/armv7/vf610/Kconfig"
1344 1353  
1345 1354 source "arch/arm/mach-zynq/Kconfig"
  1355 +
  1356 +source "arch/arm/mach-zynqmp-r5/Kconfig"
1346 1357  
1347 1358 source "arch/arm/cpu/armv7/Kconfig"
1348 1359  
... ... @@ -76,6 +76,7 @@
76 76 machine-$(CONFIG_TEGRA) += tegra
77 77 machine-$(CONFIG_ARCH_UNIPHIER) += uniphier
78 78 machine-$(CONFIG_ARCH_ZYNQ) += zynq
  79 +machine-$(CONFIG_ARCH_ZYNQMP_R5) += zynqmp-r5
79 80  
80 81 machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
81 82  
arch/arm/cpu/armv8/zynqmp/cpu.c
Diff comments   View file @ 3b52847
... ... @@ -15,16 +15,28 @@
15 15  
16 16 DECLARE_GLOBAL_DATA_PTR;
17 17  
18   -static struct mm_region zynqmp_mem_map[] = {
  18 +/*
  19 + * Number of filled static entries and also the first empty
  20 + * slot in zynqmp_mem_map.
  21 + */
  22 +#define ZYNQMP_MEM_MAP_USED 4
  23 +
19 24 #if !defined(CONFIG_ZYNQMP_NO_DDR)
20   - {
21   - .virt = 0x0UL,
22   - .phys = 0x0UL,
23   - .size = 0x80000000UL,
24   - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
25   - PTE_BLOCK_INNER_SHARE
26   - },
  25 +#define DRAM_BANKS CONFIG_NR_DRAM_BANKS
  26 +#else
  27 +#define DRAM_BANKS 0
27 28 #endif
  29 +
  30 +#if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
  31 +#define TCM_MAP 1
  32 +#else
  33 +#define TCM_MAP 0
  34 +#endif
  35 +
  36 +/* +1 is end of list which needs to be empty */
  37 +#define ZYNQMP_MEM_MAP_MAX (ZYNQMP_MEM_MAP_USED + DRAM_BANKS + TCM_MAP + 1)
  38 +
  39 +static struct mm_region zynqmp_mem_map[ZYNQMP_MEM_MAP_MAX] = {
28 40 {
29 41 .virt = 0x80000000UL,
30 42 .phys = 0x80000000UL,
... ... @@ -32,8 +44,7 @@
32 44 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
33 45 PTE_BLOCK_NON_SHARE |
34 46 PTE_BLOCK_PXN | PTE_BLOCK_UXN
35   - },
36   - {
  47 + }, {
37 48 .virt = 0xf8000000UL,
38 49 .phys = 0xf8000000UL,
39 50 .size = 0x07e00000UL,
40 51  
41 52  
42 53  
... ... @@ -41,42 +52,51 @@
41 52 PTE_BLOCK_NON_SHARE |
42 53 PTE_BLOCK_PXN | PTE_BLOCK_UXN
43 54 }, {
44   -#if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
45   - .virt = 0xffe00000UL,
46   - .phys = 0xffe00000UL,
47   - .size = 0x00200000UL,
48   - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
49   - PTE_BLOCK_INNER_SHARE
50   - }, {
51   -#endif
52 55 .virt = 0x400000000UL,
53 56 .phys = 0x400000000UL,
54 57 .size = 0x400000000UL,
55 58 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
56 59 PTE_BLOCK_NON_SHARE |
57 60 PTE_BLOCK_PXN | PTE_BLOCK_UXN
58   - },
59   -#if !defined(CONFIG_ZYNQMP_NO_DDR)
60   - {
61   - .virt = 0x800000000UL,
62   - .phys = 0x800000000UL,
63   - .size = 0x800000000UL,
64   - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
65   - PTE_BLOCK_INNER_SHARE
66   - },
67   -#endif
68   - {
  61 + }, {
69 62 .virt = 0x1000000000UL,
70 63 .phys = 0x1000000000UL,
71 64 .size = 0xf000000000UL,
72 65 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
73 66 PTE_BLOCK_NON_SHARE |
74 67 PTE_BLOCK_PXN | PTE_BLOCK_UXN
75   - }, {
76   - /* List terminator */
77   - 0,
78 68 }
79 69 };
  70 +
  71 +void mem_map_fill(void)
  72 +{
  73 + int banks = ZYNQMP_MEM_MAP_USED;
  74 +
  75 +#if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
  76 + zynqmp_mem_map[banks].virt = 0xffe00000UL;
  77 + zynqmp_mem_map[banks].phys = 0xffe00000UL;
  78 + zynqmp_mem_map[banks].size = 0x00200000UL;
  79 + zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  80 + PTE_BLOCK_INNER_SHARE;
  81 + banks = banks + 1;
  82 +#endif
  83 +
  84 +#if !defined(CONFIG_ZYNQMP_NO_DDR)
  85 + for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  86 + /* Zero size means no more DDR that's this is end */
  87 + if (!gd->bd->bi_dram[i].size)
  88 + break;
  89 +
  90 + zynqmp_mem_map[banks].virt = gd->bd->bi_dram[i].start;
  91 + zynqmp_mem_map[banks].phys = gd->bd->bi_dram[i].start;
  92 + zynqmp_mem_map[banks].size = gd->bd->bi_dram[i].size;
  93 + zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  94 + PTE_BLOCK_INNER_SHARE;
  95 + banks = banks + 1;
  96 + }
  97 +#endif
  98 +}
  99 +
80 100 struct mm_region *mem_map = zynqmp_mem_map;
81 101  
82 102 u64 get_page_table_size(void)
arch/arm/dts/Makefile
Diff comments   View file @ 3b52847
... ... @@ -157,11 +157,14 @@
157 157 zynqmp-zc1232-revA.dtb \
158 158 zynqmp-zc1254-revA.dtb \
159 159 zynqmp-zc1275-revA.dtb \
  160 + zynqmp-zc1275-revB.dtb \
160 161 zynqmp-zc1751-xm015-dc1.dtb \
161 162 zynqmp-zc1751-xm016-dc2.dtb \
162 163 zynqmp-zc1751-xm017-dc3.dtb \
163 164 zynqmp-zc1751-xm018-dc4.dtb \
164 165 zynqmp-zc1751-xm019-dc5.dtb
  166 +dtb-$(CONFIG_ARCH_ZYNQMP_R5) += \
  167 + zynqmp-r5.dtb
165 168 dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb \
166 169 am335x-draco.dtb \
167 170 am335x-evm.dtb \
arch/arm/dts/zynqmp-clk.dtsi
Diff comments   View file @ 3b52847
... ... @@ -219,7 +219,7 @@
219 219 };
220 220  
221 221 &watchdog0 {
222   - clocks = <&clk250>;
  222 + clocks = <&clk100>;
223 223 };
224 224  
225 225 &xilinx_drm {
arch/arm/dts/zynqmp-r5.dts
Diff comments   View file @ 3b52847
  1 +// SPDX-License-Identifier: GPL-2.0
  2 +/*
  3 + * dts file for Xilinx ZynqMP R5
  4 + *
  5 + * (C) Copyright 2018, Xilinx, Inc.
  6 + *
  7 + * Michal Simek <michal.simek@xilinx.com>
  8 + */
  9 +
  10 +/dts-v1/;
  11 +
  12 +/ {
  13 + #address-cells = <1>;
  14 + #size-cells = <1>;
  15 + compatible = "xlnx,zynqmp-r5";
  16 + model = "Xilinx ZynqMP R5";
  17 +
  18 + cpus {
  19 + #address-cells = <0x1>;
  20 + #size-cells = <0x0>;
  21 +
  22 + cpu@0 {
  23 + compatible = "arm,cortex-r5";
  24 + device_type = "cpu";
  25 + reg = <0>;
  26 + };
  27 + };
  28 +
  29 + aliases {
  30 + serial0 = &uart1;
  31 + };
  32 +
  33 + memory@0 {
  34 + device_type = "memory";
  35 + reg = <0x00000000 0x20000000>;
  36 + };
  37 +
  38 + chosen {
  39 + bootargs = "";
  40 + stdout-path = "serial0:115200n8";
  41 + };
  42 +
  43 + clk100: clk100 {
  44 + compatible = "fixed-clock";
  45 + #clock-cells = <0>;
  46 + clock-frequency = <100000000>;
  47 + u-boot,dm-pre-reloc;
  48 + };
  49 +
  50 + amba {
  51 + u-boot,dm-pre-reloc;
  52 + compatible = "simple-bus";
  53 + #address-cells = <1>;
  54 + #size-cells = <1>;
  55 + ranges;
  56 +
  57 + ttc0: timer@ff110000 {
  58 + compatible = "cdns,ttc";
  59 + status = "okay";
  60 + reg = <0xff110000 0x1000>;
  61 + timer-width = <32>;
  62 + clocks = <&clk100>;
  63 + };
  64 +
  65 + uart1: serial@ff010000 {
  66 + u-boot,dm-pre-reloc;
  67 + compatible = "cdns,uart-r1p12", "xlnx,xuartps";
  68 + reg = <0xff010000 0x1000>;
  69 + clock-names = "uart_clk", "pclk";
  70 + clocks = <&clk100 &clk100>;
  71 + };
  72 + };
  73 +};
arch/arm/dts/zynqmp-zc1275-revB.dts
Diff comments   View file @ 3b52847
  1 +// SPDX-License-Identifier: GPL-2.0
  2 +/*
  3 + * dts file for Xilinx ZynqMP ZC1275 RevB
  4 + *
  5 + * (C) Copyright 2018, Xilinx, Inc.
  6 + *
  7 + * Michal Simek <michal.simek@xilinx.com>
  8 + * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
  9 + */
  10 +
  11 +/dts-v1/;
  12 +
  13 +#include "zynqmp.dtsi"
  14 +#include "zynqmp-clk-ccf.dtsi"
  15 +
  16 +/ {
  17 + model = "ZynqMP ZC1275 RevB";
  18 + compatible = "xlnx,zynqmp-zc1275-revB", "xlnx,zynqmp-zc1275", "xlnx,zynqmp";
  19 +
  20 + aliases {
  21 + serial0 = &uart0;
  22 + serial1 = &dcc;
  23 + spi0 = &qspi;
  24 + mmc0 = &sdhci1;
  25 + };
  26 +
  27 + chosen {
  28 + bootargs = "earlycon";
  29 + stdout-path = "serial0:115200n8";
  30 + };
  31 +
  32 + memory@0 {
  33 + device_type = "memory";
  34 + reg = <0x0 0x0 0x0 0x80000000>;
  35 + };
  36 +};
  37 +
  38 +&dcc {
  39 + status = "okay";
  40 +};
  41 +
  42 +&qspi {
  43 + status = "okay";
  44 + flash@0 {
  45 + compatible = "m25p80"; /* 32MB */
  46 + #address-cells = <1>;
  47 + #size-cells = <1>;
  48 + reg = <0x0>;
  49 + spi-tx-bus-width = <1>;
  50 + spi-rx-bus-width = <4>;
  51 + spi-max-frequency = <108000000>; /* Based on DC1 spec */
  52 + partition@qspi-fsbl-uboot { /* for testing purpose */
  53 + label = "qspi-fsbl-uboot";
  54 + reg = <0x0 0x100000>;
  55 + };
  56 + partition@qspi-linux { /* for testing purpose */
  57 + label = "qspi-linux";
  58 + reg = <0x100000 0x500000>;
  59 + };
  60 + partition@qspi-device-tree { /* for testing purpose */
  61 + label = "qspi-device-tree";
  62 + reg = <0x600000 0x20000>;
  63 + };
  64 + partition@qspi-rootfs { /* for testing purpose */
  65 + label = "qspi-rootfs";
  66 + reg = <0x620000 0x5E0000>;
  67 + };
  68 + };
  69 +};
  70 +
  71 +&uart0 {
  72 + status = "okay";
  73 +};
  74 +
  75 +&sdhci1 {
  76 + status = "okay";
  77 + no-1-8-v;
  78 + xlnx,mio_bank = <1>;
  79 +};
arch/arm/dts/zynqmp-zcu100-revC.dts
Diff comments   View file @ 3b52847
... ... @@ -332,6 +332,7 @@
332 332  
333 333 &watchdog0 {
334 334 status = "okay";
  335 + reset-on-timeout;
335 336 };
336 337  
337 338 &xilinx_ams {
arch/arm/include/asm/arch-zynqmp/sys_proto.h
Diff comments   View file @ 3b52847
... ... @@ -45,7 +45,7 @@
45 45 u32 *ret_payload);
46 46  
47 47 void initialize_tcm(bool mode);
48   -
  48 +void mem_map_fill(void);
49 49 int chip_id(unsigned char id);
50 50  
51 51 #endif /* _ASM_ARCH_SYS_PROTO_H */
arch/arm/mach-zynq/cpu.c
Diff comments   View file @ 3b52847
... ... @@ -4,14 +4,45 @@
4 4 * Copyright (C) 2012 Xilinx, Inc. All rights reserved.
5 5 */
6 6 #include <common.h>
  7 +#include <zynqpl.h>
7 8 #include <asm/io.h>
8 9 #include <asm/arch/clk.h>
9   -#include <asm/arch/sys_proto.h>
10 10 #include <asm/arch/hardware.h>
  11 +#include <asm/arch/ps7_init_gpl.h>
  12 +#include <asm/arch/sys_proto.h>
11 13  
12 14 #define ZYNQ_SILICON_VER_MASK 0xF0000000
13 15 #define ZYNQ_SILICON_VER_SHIFT 28
14 16  
  17 +#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
  18 + (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
  19 +xilinx_desc fpga = {
  20 + .family = xilinx_zynq,
  21 + .iface = devcfg,
  22 + .operations = &zynq_op,
  23 +};
  24 +#endif
  25 +
  26 +static const struct {
  27 + u8 idcode;
  28 +#if defined(CONFIG_FPGA)
  29 + u32 fpga_size;
  30 +#endif
  31 + char *devicename;
  32 +} zynq_fpga_descs[] = {
  33 + ZYNQ_DESC(7Z007S),
  34 + ZYNQ_DESC(7Z010),
  35 + ZYNQ_DESC(7Z012S),
  36 + ZYNQ_DESC(7Z014S),
  37 + ZYNQ_DESC(7Z015),
  38 + ZYNQ_DESC(7Z020),
  39 + ZYNQ_DESC(7Z030),
  40 + ZYNQ_DESC(7Z035),
  41 + ZYNQ_DESC(7Z045),
  42 + ZYNQ_DESC(7Z100),
  43 + { /* Sentinel */ },
  44 +};
  45 +
15 46 int arch_cpu_init(void)
16 47 {
17 48 zynq_slcr_unlock();
... ... @@ -57,6 +88,58 @@
57 88 {
58 89 /* Enable D-cache. I-cache is already enabled in start.S */
59 90 dcache_enable();
  91 +}
  92 +#endif
  93 +
  94 +static int __maybe_unused cpu_desc_id(void)
  95 +{
  96 + u32 idcode;
  97 + u8 i;
  98 +
  99 + idcode = zynq_slcr_get_idcode();
  100 + for (i = 0; zynq_fpga_descs[i].idcode; i++) {
  101 + if (zynq_fpga_descs[i].idcode == idcode)
  102 + return i;
  103 + }
  104 +
  105 + return -ENODEV;
  106 +}
  107 +
  108 +#if defined(CONFIG_ARCH_EARLY_INIT_R)
  109 +int arch_early_init_r(void)
  110 +{
  111 +#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
  112 + (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
  113 + int cpu_id = cpu_desc_id();
  114 +
  115 + if (cpu_id < 0)
  116 + return 0;
  117 +
  118 + fpga.size = zynq_fpga_descs[cpu_id].fpga_size;
  119 + fpga.name = zynq_fpga_descs[cpu_id].devicename;
  120 + fpga_init();
  121 + fpga_add(fpga_xilinx, &fpga);
  122 +#endif
  123 + return 0;
  124 +}
  125 +#endif
  126 +
  127 +#ifdef CONFIG_DISPLAY_CPUINFO
  128 +int print_cpuinfo(void)
  129 +{
  130 + u32 version;
  131 + int cpu_id = cpu_desc_id();
  132 +
  133 + if (cpu_id < 0)
  134 + return 0;
  135 +
  136 + version = zynq_get_silicon_version() << 1;
  137 + if (version > (PCW_SILICON_VERSION_3 << 1))
  138 + version += 1;
  139 +
  140 + printf("CPU: Zynq %s\n", zynq_fpga_descs[cpu_id].devicename);
  141 + printf("Silicon: v%d.%d\n", version >> 1, version & 1);
  142 + return 0;
60 143 }
61 144 #endif
arch/arm/mach-zynq/spl.c
Diff comments   View file @ 3b52847
... ... @@ -17,11 +17,12 @@
17 17 ps7_init();
18 18  
19 19 arch_cpu_init();
20   - /*
21   - * The debug UART can be used from this point:
22   - * debug_uart_init();
23   - * printch('x');
24   - */
  20 +
  21 +#ifdef CONFIG_DEBUG_UART
  22 + /* Uart debug for sure */
  23 + debug_uart_init();
  24 + puts("Debug uart enabled\n"); /* or printch() */
  25 +#endif
25 26 }
26 27  
27 28 #ifdef CONFIG_SPL_BOARD_INIT
arch/arm/mach-zynqmp-r5/Kconfig
Diff comments   View file @ 3b52847
  1 +# SPDX-License-Identifier: GPL-2.0
  2 +
  3 +if ARCH_ZYNQMP_R5
  4 +
  5 +config SYS_BOARD
  6 + string "Board name"
  7 + default "zynqmp_r5"
  8 +
  9 +config SYS_VENDOR
  10 + string "Vendor name"
  11 + default "xilinx"
  12 +
  13 +config SYS_SOC
  14 + default "zynqmp-r5"
  15 +
  16 +config SYS_CONFIG_NAME
  17 + string "Board configuration name"
  18 + default "xilinx_zynqmp_r5"
  19 + help
  20 + This option contains information about board configuration name.
  21 + Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
  22 + will be used for board configuration.
  23 +
  24 +config SYS_MALLOC_F_LEN
  25 + default 0x600
  26 +
  27 +endif
arch/arm/mach-zynqmp-r5/Makefile
Diff comments   View file @ 3b52847
  1 +# SPDX-License-Identifier: GPL-2.0
  2 +
  3 +obj-y += cpu.o
arch/arm/mach-zynqmp-r5/cpu.c
Diff comments   View file @ 3b52847
  1 +// SPDX-License-Identifier: GPL-2.0
  2 +/*
  3 + * Copyright (C) 2018 Xilinx, Inc. (Michal Simek)
  4 + */
  5 +
  6 +#include <common.h>
  7 +#include <asm/armv7_mpu.h>
  8 +
  9 +DECLARE_GLOBAL_DATA_PTR;
  10 +
  11 +struct mpu_region_config region_config[] = {
  12 + { 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
  13 + O_I_WB_RD_WR_ALLOC, REGION_1GB },
  14 + { 0x20000000, REGION_1, XN_EN, PRIV_RO_USR_RO,
  15 + O_I_WB_RD_WR_ALLOC, REGION_512MB },
  16 + { 0x40000000, REGION_2, XN_EN, PRIV_RO_USR_RO,
  17 + O_I_WB_RD_WR_ALLOC, REGION_1GB },
  18 +};
  19 +
  20 +int arch_cpu_init(void)
  21 +{
  22 + gd->cpu_clk = CONFIG_CPU_FREQ_HZ;
  23 +
  24 + setup_mpu_regions(region_config, sizeof(region_config) /
  25 + sizeof(struct mpu_region_config));
  26 +
  27 + return 0;
  28 +}
  29 +
  30 +/*
  31 + * Perform the low-level reset.
  32 + */
  33 +void reset_cpu(ulong addr)
  34 +{
  35 + while (1)
  36 + ;
  37 +}
board/xilinx/zynq/board.c
Diff comments   View file @ 3b52847
... ... @@ -13,27 +13,9 @@
13 13 #include <zynqpl.h>
14 14 #include <asm/arch/hardware.h>
15 15 #include <asm/arch/sys_proto.h>
16   -#include <asm/arch/ps7_init_gpl.h>
17 16  
18 17 DECLARE_GLOBAL_DATA_PTR;
19 18  
20   -#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
21   - (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
22   -static xilinx_desc fpga;
23   -
24   -/* It can be done differently */
25   -static xilinx_desc fpga007s = XILINX_XC7Z007S_DESC(0x7);
26   -static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
27   -static xilinx_desc fpga012s = XILINX_XC7Z012S_DESC(0x12);
28   -static xilinx_desc fpga014s = XILINX_XC7Z014S_DESC(0x14);
29   -static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
30   -static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
31   -static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
32   -static xilinx_desc fpga035 = XILINX_XC7Z035_DESC(0x35);
33   -static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
34   -static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
35   -#endif
36   -
37 19 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
38 20 static struct udevice *watchdog_dev;
39 21 #endif
... ... @@ -52,46 +34,6 @@
52 34  
53 35 int board_init(void)
54 36 {
55   -#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
56   - (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
57   - u32 idcode;
58   -
59   - idcode = zynq_slcr_get_idcode();
60   -
61   - switch (idcode) {
62   - case XILINX_ZYNQ_7007S:
63   - fpga = fpga007s;
64   - break;
65   - case XILINX_ZYNQ_7010:
66   - fpga = fpga010;
67   - break;
68   - case XILINX_ZYNQ_7012S:
69   - fpga = fpga012s;
70   - break;
71   - case XILINX_ZYNQ_7014S:
72   - fpga = fpga014s;
73   - break;
74   - case XILINX_ZYNQ_7015:
75   - fpga = fpga015;
76   - break;
77   - case XILINX_ZYNQ_7020:
78   - fpga = fpga020;
79   - break;
80   - case XILINX_ZYNQ_7030:
81   - fpga = fpga030;
82   - break;
83   - case XILINX_ZYNQ_7035:
84   - fpga = fpga035;
85   - break;
86   - case XILINX_ZYNQ_7045:
87   - fpga = fpga045;
88   - break;
89   - case XILINX_ZYNQ_7100:
90   - fpga = fpga100;
91   - break;
92   - }
93   -#endif
94   -
95 37 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
96 38 if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
97 39 puts("Watchdog: Not found!\n");
... ... @@ -101,12 +43,6 @@
101 43 }
102 44 # endif
103 45  
104   -#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
105   - (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
106   - fpga_init();
107   - fpga_add(fpga_xilinx, &fpga);
108   -#endif
109   -
110 46 return 0;
111 47 }
112 48  
... ... @@ -135,22 +71,6 @@
135 71  
136 72 return 0;
137 73 }
138   -
139   -#ifdef CONFIG_DISPLAY_BOARDINFO
140   -int checkboard(void)
141   -{
142   - u32 version = zynq_get_silicon_version();
143   -
144   - version <<= 1;
145   - if (version > (PCW_SILICON_VERSION_3 << 1))
146   - version += 1;
147   -
148   - puts("Board: Xilinx Zynq\n");
149   - printf("Silicon: v%d.%d\n", version >> 1, version & 1);
150   -
151   - return 0;
152   -}
153   -#endif
154 74  
155 75 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
156 76 {
board/xilinx/zynqmp/Makefile
Diff comments   View file @ 3b52847
... ... @@ -24,6 +24,8 @@
24 24 obj-y += $(init-objs)
25 25 endif
26 26  
  27 +obj-$(CONFIG_MMC_SDHCI_ZYNQ) += tap_delays.o
  28 +
27 29 ifndef CONFIG_SPL_BUILD
28 30 obj-$(CONFIG_CMD_ZYNQMP) += cmds.o
29 31 endif
board/xilinx/zynqmp/tap_delays.c
Diff comments   View file @ 3b52847
  1 +// SPDX-License-Identifier: GPL-2.0
  2 +/*
  3 + * Xilinx ZynqMP SoC Tap Delay Programming
  4 + *
  5 + * Copyright (C) 2018 Xilinx, Inc.
  6 + */
  7 +
  8 +#include <common.h>
  9 +#include <asm/arch/sys_proto.h>
  10 +
  11 +#define SD_DLL_CTRL 0xFF180358
  12 +#define SD_ITAP_DLY 0xFF180314
  13 +#define SD_OTAP_DLY 0xFF180318
  14 +#define SD0_DLL_RST_MASK 0x00000004
  15 +#define SD0_DLL_RST 0x00000004
  16 +#define SD1_DLL_RST_MASK 0x00040000
  17 +#define SD1_DLL_RST 0x00040000
  18 +#define SD0_ITAPCHGWIN_MASK 0x00000200
  19 +#define SD0_ITAPCHGWIN 0x00000200
  20 +#define SD1_ITAPCHGWIN_MASK 0x02000000
  21 +#define SD1_ITAPCHGWIN 0x02000000
  22 +#define SD0_ITAPDLYENA_MASK 0x00000100
  23 +#define SD0_ITAPDLYENA 0x00000100
  24 +#define SD1_ITAPDLYENA_MASK 0x01000000
  25 +#define SD1_ITAPDLYENA 0x01000000
  26 +#define SD0_ITAPDLYSEL_MASK 0x000000FF
  27 +#define SD0_ITAPDLYSEL_HSD 0x00000015
  28 +#define SD0_ITAPDLYSEL_SD_DDR50 0x0000003D
  29 +#define SD0_ITAPDLYSEL_MMC_DDR50 0x00000012
  30 +
  31 +#define SD1_ITAPDLYSEL_MASK 0x00FF0000
  32 +#define SD1_ITAPDLYSEL_HSD 0x00150000
  33 +#define SD1_ITAPDLYSEL_SD_DDR50 0x003D0000
  34 +#define SD1_ITAPDLYSEL_MMC_DDR50 0x00120000
  35 +
  36 +#define SD0_OTAPDLYSEL_MASK 0x0000003F
  37 +#define SD0_OTAPDLYSEL_MMC_HSD 0x00000006
  38 +#define SD0_OTAPDLYSEL_SD_HSD 0x00000005
  39 +#define SD0_OTAPDLYSEL_SDR50 0x00000003
  40 +#define SD0_OTAPDLYSEL_SDR104_B0 0x00000003
  41 +#define SD0_OTAPDLYSEL_SDR104_B2 0x00000002
  42 +#define SD0_OTAPDLYSEL_SD_DDR50 0x00000004
  43 +#define SD0_OTAPDLYSEL_MMC_DDR50 0x00000006
  44 +
  45 +#define SD1_OTAPDLYSEL_MASK 0x003F0000
  46 +#define SD1_OTAPDLYSEL_MMC_HSD 0x00060000
  47 +#define SD1_OTAPDLYSEL_SD_HSD 0x00050000
  48 +#define SD1_OTAPDLYSEL_SDR50 0x00030000
  49 +#define SD1_OTAPDLYSEL_SDR104_B0 0x00030000
  50 +#define SD1_OTAPDLYSEL_SDR104_B2 0x00020000
  51 +#define SD1_OTAPDLYSEL_SD_DDR50 0x00040000
  52 +#define SD1_OTAPDLYSEL_MMC_DDR50 0x00060000
  53 +
  54 +#define MMC_BANK2 0x2
  55 +
  56 +#define MMC_TIMING_UHS_SDR25 1
  57 +#define MMC_TIMING_UHS_SDR50 2
  58 +#define MMC_TIMING_UHS_SDR104 3
  59 +#define MMC_TIMING_UHS_DDR50 4
  60 +#define MMC_TIMING_MMC_HS200 5
  61 +#define MMC_TIMING_SD_HS 6
  62 +#define MMC_TIMING_MMC_DDR52 7
  63 +#define MMC_TIMING_MMC_HS 8
  64 +
  65 +void zynqmp_dll_reset(u8 deviceid)
  66 +{
  67 + /* Issue DLL Reset */
  68 + if (deviceid == 0)
  69 + zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK,
  70 + SD0_DLL_RST);
  71 + else
  72 + zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK,
  73 + SD1_DLL_RST);
  74 +
  75 + mdelay(1);
  76 +
  77 + /* Release DLL Reset */
  78 + if (deviceid == 0)
  79 + zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, 0x0);
  80 + else
  81 + zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, 0x0);
  82 +}
  83 +
  84 +static void arasan_zynqmp_tap_sdr104(u8 deviceid, u8 timing, u8 bank)
  85 +{
  86 + if (deviceid == 0) {
  87 + /* Program OTAP */
  88 + if (bank == MMC_BANK2)
  89 + zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
  90 + SD0_OTAPDLYSEL_SDR104_B2);
  91 + else
  92 + zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
  93 + SD0_OTAPDLYSEL_SDR104_B0);
  94 + } else {
  95 + /* Program OTAP */
  96 + if (bank == MMC_BANK2)
  97 + zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
  98 + SD1_OTAPDLYSEL_SDR104_B2);
  99 + else
  100 + zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
  101 + SD1_OTAPDLYSEL_SDR104_B0);
  102 + }
  103 +}
  104 +
  105 +static void arasan_zynqmp_tap_hs(u8 deviceid, u8 timing, u8 bank)
  106 +{
  107 + if (deviceid == 0) {
  108 + /* Program ITAP */
  109 + zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK,
  110 + SD0_ITAPCHGWIN);
  111 + zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA_MASK,
  112 + SD0_ITAPDLYENA);
  113 + zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK,
  114 + SD0_ITAPDLYSEL_HSD);
  115 + zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK, 0x0);
  116 + /* Program OTAP */
  117 + if (timing == MMC_TIMING_MMC_HS)
  118 + zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
  119 + SD0_OTAPDLYSEL_MMC_HSD);
  120 + else
  121 + zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
  122 + SD0_OTAPDLYSEL_SD_HSD);
  123 + } else {
  124 + /* Program ITAP */
  125 + zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK,
  126 + SD1_ITAPCHGWIN);
  127 + zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA_MASK,
  128 + SD1_ITAPDLYENA);
  129 + zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK,
  130 + SD1_ITAPDLYSEL_HSD);
  131 + zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK, 0x0);
  132 + /* Program OTAP */
  133 + if (timing == MMC_TIMING_MMC_HS)
  134 + zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
  135 + SD1_OTAPDLYSEL_MMC_HSD);
  136 + else
  137 + zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
  138 + SD1_OTAPDLYSEL_SD_HSD);
  139 + }
  140 +}
  141 +
  142 +static void arasan_zynqmp_tap_ddr50(u8 deviceid, u8 timing, u8 bank)
  143 +{
  144 + if (deviceid == 0) {
  145 + /* Program ITAP */
  146 + zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK,
  147 + SD0_ITAPCHGWIN);
  148 + zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA_MASK,
  149 + SD0_ITAPDLYENA);
  150 + if (timing == MMC_TIMING_UHS_DDR50)
  151 + zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK,
  152 + SD0_ITAPDLYSEL_SD_DDR50);
  153 + else
  154 + zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK,
  155 + SD0_ITAPDLYSEL_MMC_DDR50);
  156 + zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK, 0x0);
  157 + /* Program OTAP */
  158 + if (timing == MMC_TIMING_UHS_DDR50)
  159 + zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
  160 + SD0_OTAPDLYSEL_SD_DDR50);
  161 + else
  162 + zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
  163 + SD0_OTAPDLYSEL_MMC_DDR50);
  164 + } else {
  165 + /* Program ITAP */
  166 + zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK,
  167 + SD1_ITAPCHGWIN);
  168 + zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA_MASK,
  169 + SD1_ITAPDLYENA);
  170 + if (timing == MMC_TIMING_UHS_DDR50)
  171 + zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK,
  172 + SD1_ITAPDLYSEL_SD_DDR50);
  173 + else
  174 + zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK,
  175 + SD1_ITAPDLYSEL_MMC_DDR50);
  176 + zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK, 0x0);
  177 + /* Program OTAP */
  178 + if (timing == MMC_TIMING_UHS_DDR50)
  179 + zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
  180 + SD1_OTAPDLYSEL_SD_DDR50);
  181 + else
  182 + zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
  183 + SD1_OTAPDLYSEL_MMC_DDR50);
  184 + }
  185 +}
  186 +
  187 +static void arasan_zynqmp_tap_sdr50(u8 deviceid, u8 timing, u8 bank)
  188 +{
  189 + if (deviceid == 0) {
  190 + /* Program OTAP */
  191 + zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
  192 + SD0_OTAPDLYSEL_SDR50);
  193 + } else {
  194 + /* Program OTAP */
  195 + zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
  196 + SD1_OTAPDLYSEL_SDR50);
  197 + }
  198 +}
  199 +
  200 +void arasan_zynqmp_set_tapdelay(u8 deviceid, u8 timing, u8 bank)
  201 +{
  202 + if (deviceid == 0)
  203 + zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK,
  204 + SD0_DLL_RST);
  205 + else
  206 + zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK,
  207 + SD1_DLL_RST);
  208 +
  209 + switch (timing) {
  210 + case MMC_TIMING_UHS_SDR25:
  211 + arasan_zynqmp_tap_hs(deviceid, timing, bank);
  212 + break;
  213 + case MMC_TIMING_UHS_SDR50:
  214 + arasan_zynqmp_tap_sdr50(deviceid, timing, bank);
  215 + break;
  216 + case MMC_TIMING_UHS_SDR104:
  217 + case MMC_TIMING_MMC_HS200:
  218 + arasan_zynqmp_tap_sdr104(deviceid, timing, bank);
  219 + break;
  220 + case MMC_TIMING_UHS_DDR50:
  221 + arasan_zynqmp_tap_ddr50(deviceid, timing, bank);
  222 + break;
  223 + }
  224 +
  225 + if (deviceid == 0)
  226 + zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, 0x0);
  227 + else
  228 + zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, 0x0);
  229 +}
board/xilinx/zynqmp/zynqmp-zc1275-revB/psu_init_gpl.c
Diff comments   View file @ 3b52847
  1 +/*
  2 + * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <asm/arch/psu_init_gpl.h>
  8 +#include <xil_io.h>
  9 +
  10 +static unsigned long psu_pll_init_data(void)
  11 +{
  12 + psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4E2C62U);
  13 + psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00013C00U);
  14 + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
  15 + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
  16 + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
  17 + mask_poll(0xFF5E0040, 0x00000002U);
  18 + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
  19 + psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000200U);
  20 + psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U);
  21 + psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U);
  22 + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
  23 + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
  24 + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
  25 + mask_poll(0xFF5E0040, 0x00000001U);
  26 + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
  27 + psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
  28 + psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
  29 + psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014200U);
  30 + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
  31 + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
  32 + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
  33 + mask_poll(0xFD1A0044, 0x00000001U);
  34 + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
  35 + psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
  36 + psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
  37 + psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014800U);
  38 + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
  39 + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
  40 + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
  41 + mask_poll(0xFD1A0044, 0x00000002U);
  42 + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
  43 + psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
  44 + psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U);
  45 + psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014000U);
  46 + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
  47 + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
  48 + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
  49 + mask_poll(0xFD1A0044, 0x00000004U);
  50 + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
  51 + psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000200U);
  52 +
  53 + return 1;
  54 +}
  55 +
  56 +static unsigned long psu_clock_init_data(void)
  57 +{
  58 + psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U);
  59 + psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010502U);
  60 + psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U);
  61 + psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
  62 + psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
  63 + psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
  64 + psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000400U);
  65 + psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000900U);
  66 + psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
  67 + psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
  68 + psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
  69 + psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
  70 + psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010A02U);
  71 + psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01010402U);
  72 + psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010802U);
  73 + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
  74 + psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
  75 + psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000104U);
  76 + psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
  77 + psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
  78 + psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000600U);
  79 + psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000203U);
  80 + psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000203U);
  81 + psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000203U);
  82 + psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000202U);
  83 + psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
  84 + psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
  85 + psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
  86 + psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
  87 + psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
  88 + psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
  89 +
  90 + return 1;
  91 +}
  92 +
  93 +static unsigned long psu_ddr_init_data(void)
  94 +{
  95 + psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
  96 + psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040001U);
  97 + psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
  98 + psu_mask_write(0xFD070020, 0x000003F3U, 0x00000100U);
  99 + psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
  100 + psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
  101 + psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00403210U);
  102 + psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
  103 + psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
  104 + psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
  105 + psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x00308034U);
  106 + psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
  107 + psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
  108 + psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
  109 + psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0030051FU);
  110 + psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020063U);
  111 + psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00290000U);
  112 + psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00000E05U);
  113 + psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x05200004U);
  114 + psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00000000U);
  115 + psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00110004U);
  116 + psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x00000000U);
  117 + psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x00000000U);
  118 + psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
  119 + psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
  120 + psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x07080D07U);
  121 + psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0005020BU);
  122 + psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x03030607U);
  123 + psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x00502006U);
  124 + psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x13020206U);
  125 + psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x03030202U);
  126 + psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010003U);
  127 + psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000303U);
  128 + psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x02020909U);
  129 + psu_mask_write(0xFD070124, 0x40070F3FU, 0x0004040DU);
  130 + psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x440C011CU);
  131 + psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
  132 + psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x80800020U);
  133 + psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x02009896U);
  134 + psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x04828202U);
  135 + psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00020304U);
  136 + psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
  137 + psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
  138 + psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
  139 + psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU);
  140 + psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
  141 + psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000000U);
  142 + psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000000U);
  143 + psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
  144 + psu_mask_write(0xFD070204, 0x001F1F1FU, 0x00080808U);
  145 + psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
  146 + psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
  147 + psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
  148 + psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U);
  149 + psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F070707U);
  150 + psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
  151 + psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000000U);
  152 + psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U);
  153 + psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U);
  154 + psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U);
  155 + psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000604U);
  156 + psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
  157 + psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
  158 + psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
  159 + psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
  160 + psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
  161 + psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
  162 + psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
  163 + psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
  164 + psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
  165 + psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
  166 + psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
  167 + psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
  168 + psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
  169 + psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
  170 + psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
  171 + psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
  172 + psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
  173 + psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
  174 + psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
  175 + psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
  176 + psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
  177 + psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
  178 + psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
  179 + psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
  180 + psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
  181 + psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
  182 + psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
  183 + psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
  184 + psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
  185 + psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
  186 + psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
  187 + psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
  188 + psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
  189 + psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
  190 + psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
  191 + psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
  192 + psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
  193 + psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
  194 + psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
  195 + psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
  196 + psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
  197 + psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
  198 + psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
  199 + psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
  200 + psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
  201 + psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
  202 + psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
  203 + psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
  204 + psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
  205 + psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
  206 + psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
  207 + psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
  208 + psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
  209 + psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
  210 + psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
  211 + psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
  212 + psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
  213 + psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F05D90U);
  214 + psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
  215 + psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
  216 + psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x1900C810U);
  217 + psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x4E200708U);
  218 + psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x06124000U);
  219 + psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04061U);
  220 + psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U);
  221 + psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000DAU);
  222 + psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040BU);
  223 + psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x040E0A04U);
  224 + psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28100004U);
  225 + psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0200U);
  226 + psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x82000800U);
  227 + psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x00682B0AU);
  228 + psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00152504U);
  229 + psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000506U);
  230 + psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
  231 + psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
  232 + psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
  233 + psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000000U);
  234 + psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000520U);
  235 + psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000004U);
  236 + psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000000U);
  237 + psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000000U);
  238 + psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
  239 + psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x00000000U);
  240 + psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000000U);
  241 + psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
  242 + psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
  243 + psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
  244 + psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
  245 + psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
  246 + psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800081C7U);
  247 + psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
  248 + psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
  249 + psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
  250 + psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12340800U);
  251 + psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
  252 + psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
  253 + psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
  254 + psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
  255 + psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
  256 + psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0B0U);
  257 + psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF1032019U);
  258 + psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
  259 + psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
  260 + psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
  261 + psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
  262 + psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
  263 + psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
  264 + psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
  265 + psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x0088E858U);
  266 + psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000077BBU);
  267 + psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
  268 + psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
  269 + psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x000076BBU);
  270 + psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
  271 + psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU);
  272 + psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U);
  273 + psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B00CU);
  274 + psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09093030U);
  275 + psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
  276 + psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
  277 + psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU);
  278 + psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U);
  279 + psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B00CU);
  280 + psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09093030U);
  281 + psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
  282 + psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
  283 + psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
  284 + psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U);
  285 + psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B00CU);
  286 + psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09093030U);
  287 + psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
  288 + psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
  289 + psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
  290 + psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U);
  291 + psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B00CU);
  292 + psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09093030U);
  293 + psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
  294 + psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
  295 + psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
  296 + psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U);
  297 + psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U);
  298 + psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U);
  299 + psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09093030U);
  300 + psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
  301 + psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
  302 + psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
  303 + psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U);
  304 + psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U);
  305 + psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B00CU);
  306 + psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09093030U);
  307 + psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
  308 + psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
  309 + psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
  310 + psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U);
  311 + psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U);
  312 + psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U);
  313 + psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09093030U);
  314 + psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
  315 + psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
  316 + psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
  317 + psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U);
  318 + psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U);
  319 + psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B00CU);
  320 + psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09093030U);
  321 + psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
  322 + psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40803660U);
  323 + psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U);
  324 + psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU);
  325 + psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U);
  326 + psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U);
  327 + psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09093030U);
  328 + psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
  329 + psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
  330 + psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x06124000U);
  331 + psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
  332 + psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
  333 + psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70000000U);
  334 + psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
  335 + psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x06124000U);
  336 + psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
  337 + psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
  338 + psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70000000U);
  339 + psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
  340 + psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x06124000U);
  341 + psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
  342 + psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
  343 + psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70000000U);
  344 + psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
  345 + psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x06124000U);
  346 + psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
  347 + psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
  348 + psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70000000U);
  349 + psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU);
  350 + psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x06124000U);
  351 + psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U);
  352 + psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
  353 + psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70000000U);
  354 + psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x06124000U);
  355 + psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
  356 +
  357 + return 1;
  358 +}
  359 +
  360 +static unsigned long psu_mio_init_data(void)
  361 +{
  362 + psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
  363 + psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
  364 + psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
  365 + psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
  366 + psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
  367 + psu_mask_write(0xFF180088, 0x000000FEU, 0x000000C0U);
  368 + psu_mask_write(0xFF18008C, 0x000000FEU, 0x000000C0U);
  369 + psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U);
  370 + psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U);
  371 + psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U);
  372 + psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U);
  373 + psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000010U);
  374 + psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000010U);
  375 + psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
  376 + psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
  377 + psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
  378 + psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
  379 + psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
  380 + psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
  381 + psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
  382 + psu_mask_write(0xFF180204, 0x0000007FU, 0x00000002U);
  383 + psu_mask_write(0xFF180208, 0x000FFF8CU, 0x00003004U);
  384 + psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
  385 + psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
  386 + psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
  387 + psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
  388 + psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
  389 + psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
  390 + psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
  391 + psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
  392 + psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
  393 + psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
  394 + psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
  395 + psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
  396 + psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
  397 + psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
  398 + psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
  399 + psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
  400 + psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
  401 + psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
  402 + psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
  403 +
  404 + return 1;
  405 +}
  406 +
  407 +static unsigned long psu_peripherals_pre_init_data(void)
  408 +{
  409 + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x00012302U);
  410 +
  411 + return 1;
  412 +}
  413 +
  414 +static unsigned long psu_peripherals_init_data(void)
  415 +{
  416 + psu_mask_write(0xFD1A0100, 0x0000807CU, 0x00000000U);
  417 + psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
  418 + psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
  419 + psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
  420 + psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U);
  421 + psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U);
  422 + psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U);
  423 + psu_mask_write(0xFF180320, 0x33800000U, 0x02800000U);
  424 + psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
  425 + psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
  426 + psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
  427 + psu_mask_write(0xFF5E0238, 0x00000200U, 0x00000000U);
  428 + psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
  429 + psu_mask_write(0xFF5E0238, 0x00000800U, 0x00000000U);
  430 + psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
  431 + psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
  432 + psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
  433 + psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
  434 + psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
  435 + psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
  436 + psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
  437 + psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
  438 + psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
  439 + psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
  440 + psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x01FC9F08U);
  441 + psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
  442 +
  443 + return 1;
  444 +}
  445 +
  446 +static unsigned long psu_afi_config(void)
  447 +{
  448 + psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
  449 + psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
  450 + psu_mask_write(0xFD615000, 0x00000300U, 0x00000200U);
  451 +
  452 + return 1;
  453 +}
  454 +
  455 +static unsigned long psu_ddr_phybringup_data(void)
  456 +{
  457 + unsigned int regval = 0;
  458 + unsigned int pll_retry = 10;
  459 + unsigned int pll_locked = 0;
  460 +
  461 + while ((pll_retry > 0) && (!pll_locked)) {
  462 + Xil_Out32(0xFD080004, 0x00040010);
  463 + Xil_Out32(0xFD080004, 0x00040011);
  464 +
  465 + while ((Xil_In32(0xFD080030) & 0x1) != 1)
  466 + ;
  467 +
  468 + pll_locked = (Xil_In32(0xFD080030) & 0x80000000) >> 31;
  469 + pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) >> 16;
  470 + pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16;
  471 + pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) >> 16;
  472 + pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) >> 16;
  473 + pll_retry--;
  474 + }
  475 + Xil_Out32(0xFD0800C0, Xil_In32(0xFD0800C0) | (pll_retry << 16));
  476 + Xil_Out32(0xFD080004U, 0x00040063U);
  477 +
  478 + while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
  479 + ;
  480 + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
  481 +
  482 + while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
  483 + ;
  484 + Xil_Out32(0xFD0701B0U, 0x00000001U);
  485 + Xil_Out32(0xFD070320U, 0x00000001U);
  486 + while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
  487 + ;
  488 + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
  489 + Xil_Out32(0xFD080004, 0x0004FE01);
  490 + regval = Xil_In32(0xFD080030);
  491 + while (regval != 0x80000FFF)
  492 + regval = Xil_In32(0xFD080030);
  493 + Xil_Out32(0xFD070180U, 0x00800020U);
  494 + Xil_Out32(0xFD070060U, 0x00000000U);
  495 + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
  496 +
  497 + return 1;
  498 +}
  499 +
  500 +static void init_peripheral(void)
  501 +{
  502 + psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
  503 +}
  504 +
  505 +int psu_init(void)
  506 +{
  507 + int status = 1;
  508 +
  509 + status &= psu_mio_init_data();
  510 + status &= psu_peripherals_pre_init_data();
  511 + status &= psu_pll_init_data();
  512 + status &= psu_clock_init_data();
  513 + status &= psu_ddr_init_data();
  514 + status &= psu_ddr_phybringup_data();
  515 + status &= psu_peripherals_init_data();
  516 + init_peripheral();
  517 +
  518 + status &= psu_afi_config();
  519 +
  520 + if (status == 0)
  521 + return 1;
  522 + return 0;
  523 +}
board/xilinx/zynqmp/zynqmp-zcu100-revC/psu_init_gpl.c
Diff comments   View file @ 3b52847
... ... @@ -481,7 +481,7 @@
481 481  
482 482 static unsigned long psu_peripherals_init_data(void)
483 483 {
484   - psu_mask_write(0xFD1A0100, 0x0001007CU, 0x00000000U);
  484 + psu_mask_write(0xFD1A0100, 0x0001807CU, 0x00000000U);
485 485 psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
486 486 psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
487 487 psu_mask_write(0xFF5E023C, 0x00000FC0U, 0x00000000U);
board/xilinx/zynqmp/zynqmp.c
Diff comments   View file @ 3b52847
... ... @@ -9,11 +9,13 @@
9 9 #include <ahci.h>
10 10 #include <scsi.h>
11 11 #include <malloc.h>
  12 +#include <wdt.h>
12 13 #include <asm/arch/clk.h>
13 14 #include <asm/arch/hardware.h>
14 15 #include <asm/arch/sys_proto.h>
15 16 #include <asm/arch/psu_init_gpl.h>
16 17 #include <asm/io.h>
  18 +#include <dm/uclass.h>
17 19 #include <usb.h>
18 20 #include <dwc3-uboot.h>
19 21 #include <zynqmppl.h>
... ... @@ -22,6 +24,10 @@
22 24  
23 25 DECLARE_GLOBAL_DATA_PTR;
24 26  
  27 +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
  28 +static struct udevice *watchdog_dev;
  29 +#endif
  30 +
25 31 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
26 32 !defined(CONFIG_SPL_BUILD)
27 33 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
... ... @@ -281,6 +287,11 @@
281 287 ret = psu_init();
282 288 #endif
283 289  
  290 +#if defined(CONFIG_WDT) && !defined(CONFIG_SPL_BUILD)
  291 + /* bss is not cleared at time when watchdog_reset() is called */
  292 + watchdog_dev = NULL;
  293 +#endif
  294 +
284 295 return ret;
285 296 }
286 297  
287 298  
... ... @@ -299,9 +310,40 @@
299 310 }
300 311 #endif
301 312  
  313 +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
  314 + if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
  315 + puts("Watchdog: Not found!\n");
  316 + } else {
  317 + wdt_start(watchdog_dev, 0, 0);
  318 + puts("Watchdog: Started\n");
  319 + }
  320 +#endif
  321 +
302 322 return 0;
303 323 }
304 324  
  325 +#ifdef CONFIG_WATCHDOG
  326 +/* Called by macro WATCHDOG_RESET */
  327 +void watchdog_reset(void)
  328 +{
  329 +# if !defined(CONFIG_SPL_BUILD)
  330 + static ulong next_reset;
  331 + ulong now;
  332 +
  333 + if (!watchdog_dev)
  334 + return;
  335 +
  336 + now = timer_get_us();
  337 +
  338 + /* Do not reset the watchdog too often */
  339 + if (now > next_reset) {
  340 + wdt_reset(watchdog_dev);
  341 + next_reset = now + 1000;
  342 + }
  343 +# endif
  344 +}
  345 +#endif
  346 +
305 347 int board_early_init_r(void)
306 348 {
307 349 u32 val;
... ... @@ -363,7 +405,15 @@
363 405 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
364 406 int dram_init_banksize(void)
365 407 {
366   - return fdtdec_setup_memory_banksize();
  408 + int ret;
  409 +
  410 + ret = fdtdec_setup_memory_banksize();
  411 + if (ret)
  412 + return ret;
  413 +
  414 + mem_map_fill();
  415 +
  416 + return 0;
367 417 }
368 418  
369 419 int dram_init(void)
... ... @@ -374,6 +424,18 @@
374 424 return 0;
375 425 }
376 426 #else
  427 +int dram_init_banksize(void)
  428 +{
  429 +#if defined(CONFIG_NR_DRAM_BANKS)
  430 + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  431 + gd->bd->bi_dram[0].size = get_effective_memsize();
  432 +#endif
  433 +
  434 + mem_map_fill();
  435 +
  436 + return 0;
  437 +}
  438 +
377 439 int dram_init(void)
378 440 {
379 441 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
... ... @@ -391,6 +453,7 @@
391 453 {
392 454 u32 reg = 0;
393 455 u8 bootmode;
  456 + int env_targets_len = 0;
394 457 const char *mode;
395 458 char *new_targets;
396 459 char *env_targets;
... ... @@ -467,14 +530,13 @@
467 530 * and default boot_targets
468 531 */
469 532 env_targets = env_get("boot_targets");
470   - if (env_targets) {
471   - new_targets = calloc(1, strlen(mode) +
472   - strlen(env_targets) + 2);
473   - sprintf(new_targets, "%s %s", mode, env_targets);
474   - } else {
475   - new_targets = calloc(1, strlen(mode) + 2);
476   - sprintf(new_targets, "%s", mode);
477   - }
  533 + if (env_targets)
  534 + env_targets_len = strlen(env_targets);
  535 +
  536 + new_targets = calloc(1, strlen(mode) + env_targets_len + 2);
  537 +
  538 + sprintf(new_targets, "%s %s", mode,
  539 + env_targets ? env_targets : "");
478 540  
479 541 env_set("boot_targets", new_targets);
480 542  
board/xilinx/zynqmp_r5/MAINTAINERS
Diff comments   View file @ 3b52847
  1 +XILINX_ZYNQMP_R5 BOARDS
  2 +M: Michal Simek <michal.simek@xilinx.com>
  3 +S: Maintained
  4 +F: arch/arm/dts/zynqmp-r5*
  5 +F: board/xilinx/zynqmp_r5/
  6 +F: include/configs/xilinx_zynqmp_r5_*
  7 +F: configs/xilinx_zynqmp_r5_*
board/xilinx/zynqmp_r5/Makefile
Diff comments   View file @ 3b52847
  1 +# SPDX-License-Identifier: GPL-2.0
  2 +#
  3 +# (C) Copyright 2018 Xilinx, Inc. (Michal Simek)
  4 +#
  5 +
  6 +obj-y := board.o
board/xilinx/zynqmp_r5/board.c
Diff comments   View file @ 3b52847
  1 +// SPDX-License-Identifier: GPL-2.0
  2 +/*
  3 + * (C) Copyright 2018 Xilinx, Inc. (Michal Simek)
  4 + */
  5 +
  6 +#include <common.h>
  7 +#include <fdtdec.h>
  8 +
  9 +int board_init(void)
  10 +{
  11 + return 0;
  12 +}
  13 +
  14 +int dram_init_banksize(void)
  15 +{
  16 + return fdtdec_setup_memory_banksize();
  17 +}
  18 +
  19 +int dram_init(void)
  20 +{
  21 + if (fdtdec_setup_memory_size() != 0)
  22 + return -EINVAL;
  23 +
  24 + return 0;
  25 +}
... ... @@ -159,6 +159,7 @@
159 159 { IH_TYPE_VYBRIDIMAGE, "vybridimage", "Vybrid Boot Image", },
160 160 { IH_TYPE_ZYNQIMAGE, "zynqimage", "Xilinx Zynq Boot Image" },
161 161 { IH_TYPE_ZYNQMPIMAGE, "zynqmpimage", "Xilinx ZynqMP Boot Image" },
  162 + { IH_TYPE_ZYNQMPBIF, "zynqmpbif", "Xilinx ZynqMP Boot Image (bif)" },
162 163 { IH_TYPE_FPGA, "fpga", "FPGA Image" },
163 164 { IH_TYPE_TEE, "tee", "Trusted Execution Environment Image",},
164 165 { IH_TYPE_FIRMWARE_IVT, "firmware_ivt", "Firmware with HABv4 IVT" },
configs/microblaze-generic_defconfig
Diff comments   View file @ 3b52847
... ... @@ -35,10 +35,6 @@
35 35 CONFIG_CMD_MII=y
36 36 CONFIG_CMD_PING=y
37 37 CONFIG_CMD_JFFS2=y
38   -CONFIG_MTDIDS_DEFAULT="nor0=flash-0"
39   -CONFIG_MTDPARTS_DEFAULT="mtdparts=flash-0:256k(u-boot),256k(env),3m(kernel),1m(romfs),1m(cramfs),-(jffs2)"
40   -CONFIG_CMD_UBI=y
41   -# CONFIG_CMD_UBIFS is not set
42 38 CONFIG_SPL_OF_CONTROL=y
43 39 CONFIG_OF_EMBED=y
44 40 CONFIG_NETCONSOLE=y
configs/syzygy_hub_defconfig
Diff comments   View file @ 3b52847
... ... @@ -13,7 +13,6 @@
13 13 CONFIG_FIT_VERBOSE=y
14 14 CONFIG_IMAGE_FORMAT_LEGACY=y
15 15 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
16   -# CONFIG_DISPLAY_CPUINFO is not set
17 16 CONFIG_SPL_STACK_R=y
18 17 CONFIG_SPL_OS_BOOT=y
19 18 CONFIG_SYS_PROMPT="Zynq> "
configs/topic_miami_defconfig
Diff comments   View file @ 3b52847
... ... @@ -11,7 +11,6 @@
11 11 CONFIG_DISTRO_DEFAULTS=y
12 12 CONFIG_BOOTDELAY=0
13 13 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
14   -# CONFIG_DISPLAY_CPUINFO is not set
15 14 CONFIG_SPL_STACK_R=y
16 15 CONFIG_SPL_SPI_LOAD=y
17 16 CONFIG_SYS_PROMPT="zynq-uboot> "
configs/topic_miamilite_defconfig
Diff comments   View file @ 3b52847
... ... @@ -11,7 +11,6 @@
11 11 CONFIG_DISTRO_DEFAULTS=y
12 12 CONFIG_BOOTDELAY=0
13 13 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
14   -# CONFIG_DISPLAY_CPUINFO is not set
15 14 CONFIG_SPL_STACK_R=y
16 15 CONFIG_SPL_SPI_LOAD=y
17 16 CONFIG_SYS_PROMPT="zynq-uboot> "
configs/topic_miamiplus_defconfig
Diff comments   View file @ 3b52847
... ... @@ -11,7 +11,6 @@
11 11 CONFIG_DISTRO_DEFAULTS=y
12 12 CONFIG_BOOTDELAY=0
13 13 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
14   -# CONFIG_DISPLAY_CPUINFO is not set
15 14 CONFIG_SPL_STACK_R=y
16 15 CONFIG_SPL_SPI_LOAD=y
17 16 CONFIG_SYS_PROMPT="zynq-uboot> "
configs/xilinx_zynqmp_r5_defconfig
Diff comments   View file @ 3b52847
  1 +CONFIG_ARM=y
  2 +CONFIG_ARCH_ZYNQMP_R5=y
  3 +CONFIG_SYS_TEXT_BASE=0x10000000
  4 +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-r5"
  5 +CONFIG_DEBUG_UART=y
  6 +# CONFIG_DISPLAY_CPUINFO is not set
  7 +CONFIG_SYS_PROMPT="ZynqMP r5> "
  8 +# CONFIG_CMD_FLASH is not set
  9 +# CONFIG_CMD_SETEXPR is not set
  10 +CONFIG_OF_EMBED=y
  11 +CONFIG_DEBUG_UART_ZYNQ=y
  12 +CONFIG_DEBUG_UART_BASE=0xff010000
  13 +CONFIG_DEBUG_UART_CLOCK=100000000
  14 +CONFIG_ZYNQ_SERIAL=y
  15 +CONFIG_TIMER=y
  16 +CONFIG_CADENCE_TTC_TIMER=y
configs/xilinx_zynqmp_zc1232_revA_defconfig
Diff comments   View file @ 3b52847
... ... @@ -4,7 +4,6 @@
4 4 CONFIG_SYS_MALLOC_F_LEN=0x8000
5 5 # CONFIG_SPL_LIBDISK_SUPPORT is not set
6 6 CONFIG_SPL=y
7   -CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1232 revA"
8 7 # CONFIG_SPL_FAT_SUPPORT is not set
9 8 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1232-revA"
10 9 CONFIG_DEBUG_UART=y
... ... @@ -13,7 +12,6 @@
13 12 CONFIG_FIT_VERBOSE=y
14 13 CONFIG_SPL_LOAD_FIT=y
15 14 # CONFIG_DISPLAY_CPUINFO is not set
16   -# CONFIG_DISPLAY_BOARDINFO is not set
17 15 CONFIG_SPL_OS_BOOT=y
18 16 CONFIG_SPL_RAM_SUPPORT=y
19 17 CONFIG_SPL_RAM_DEVICE=y
configs/xilinx_zynqmp_zc1254_revA_defconfig
Diff comments   View file @ 3b52847
... ... @@ -4,7 +4,6 @@
4 4 CONFIG_SYS_MALLOC_F_LEN=0x8000
5 5 # CONFIG_SPL_LIBDISK_SUPPORT is not set
6 6 CONFIG_SPL=y
7   -CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1254 revA"
8 7 # CONFIG_SPL_FAT_SUPPORT is not set
9 8 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1254-revA"
10 9 CONFIG_DEBUG_UART=y
... ... @@ -13,7 +12,6 @@
13 12 CONFIG_FIT_VERBOSE=y
14 13 CONFIG_SPL_LOAD_FIT=y
15 14 # CONFIG_DISPLAY_CPUINFO is not set
16   -# CONFIG_DISPLAY_BOARDINFO is not set
17 15 CONFIG_SPL_OS_BOOT=y
18 16 CONFIG_SPL_RAM_SUPPORT=y
19 17 CONFIG_SPL_RAM_DEVICE=y
configs/xilinx_zynqmp_zc1275_revA_defconfig
Diff comments   View file @ 3b52847
... ... @@ -4,7 +4,6 @@
4 4 CONFIG_SYS_MALLOC_F_LEN=0x8000
5 5 # CONFIG_SPL_LIBDISK_SUPPORT is not set
6 6 CONFIG_SPL=y
7   -CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1275 revA"
8 7 # CONFIG_SPL_FAT_SUPPORT is not set
9 8 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1275-revA"
10 9 CONFIG_DEBUG_UART=y
... ... @@ -13,7 +12,6 @@
13 12 CONFIG_FIT_VERBOSE=y
14 13 CONFIG_SPL_LOAD_FIT=y
15 14 # CONFIG_DISPLAY_CPUINFO is not set
16   -# CONFIG_DISPLAY_BOARDINFO is not set
17 15 CONFIG_SPL_OS_BOOT=y
18 16 CONFIG_SPL_RAM_SUPPORT=y
19 17 CONFIG_SPL_RAM_DEVICE=y
configs/xilinx_zynqmp_zc1275_revB_defconfig
Diff comments   View file @ 3b52847
  1 +CONFIG_ARM=y
  2 +CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1275_revB"
  3 +CONFIG_ARCH_ZYNQMP=y
  4 +CONFIG_SYS_TEXT_BASE=0x8000000
  5 +CONFIG_SYS_MALLOC_F_LEN=0x8000
  6 +# CONFIG_SPL_LIBDISK_SUPPORT is not set
  7 +CONFIG_SPL=y
  8 +# CONFIG_SPL_FAT_SUPPORT is not set
  9 +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1275-revB"
  10 +CONFIG_DEBUG_UART=y
  11 +CONFIG_DISTRO_DEFAULTS=y
  12 +CONFIG_FIT=y
  13 +CONFIG_FIT_VERBOSE=y
  14 +CONFIG_SPL_LOAD_FIT=y
  15 +# CONFIG_DISPLAY_CPUINFO is not set
  16 +CONFIG_SPL_OS_BOOT=y
  17 +CONFIG_SPL_RAM_SUPPORT=y
  18 +CONFIG_SPL_RAM_DEVICE=y
  19 +CONFIG_SPL_ATF=y
  20 +CONFIG_SYS_PROMPT="ZynqMP> "
  21 +CONFIG_CMD_MEMTEST=y
  22 +CONFIG_CMD_CLK=y
  23 +# CONFIG_CMD_FLASH is not set
  24 +CONFIG_CMD_FPGA_LOADBP=y
  25 +CONFIG_CMD_FPGA_LOADP=y
  26 +CONFIG_CMD_MMC=y
  27 +# CONFIG_CMD_NET is not set
  28 +CONFIG_CMD_TIME=y
  29 +CONFIG_CMD_TIMER=y
  30 +CONFIG_SPL_OF_CONTROL=y
  31 +CONFIG_OF_EMBED=y
  32 +CONFIG_SPL_DM=y
  33 +CONFIG_CLK_ZYNQMP=y
  34 +CONFIG_FPGA_XILINX=y
  35 +CONFIG_FPGA_ZYNQMPPL=y
  36 +CONFIG_MISC=y
  37 +CONFIG_DM_MMC=y
  38 +CONFIG_MMC_SDHCI=y
  39 +CONFIG_MMC_SDHCI_ZYNQ=y
  40 +CONFIG_SPI_FLASH=y
  41 +CONFIG_SPI_FLASH_BAR=y
  42 +CONFIG_SF_DUAL_FLASH=y
  43 +CONFIG_SPI_FLASH_MACRONIX=y
  44 +CONFIG_SPI_FLASH_SPANSION=y
  45 +CONFIG_SPI_FLASH_STMICRO=y
  46 +CONFIG_SPI_FLASH_WINBOND=y
  47 +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
  48 +CONFIG_DEBUG_UART_ZYNQ=y
  49 +CONFIG_DEBUG_UART_BASE=0xff000000
  50 +CONFIG_DEBUG_UART_CLOCK=100000000
  51 +CONFIG_DEBUG_UART_ANNOUNCE=y
  52 +CONFIG_ZYNQ_SERIAL=y
  53 +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
Diff comments   View file @ 3b52847
... ... @@ -4,7 +4,6 @@
4 4 CONFIG_SYS_TEXT_BASE=0x8000000
5 5 CONFIG_SYS_MALLOC_F_LEN=0x8000
6 6 CONFIG_SPL=y
7   -CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm015 dc1"
8 7 CONFIG_ZYNQMP_USB=y
9 8 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1"
10 9 CONFIG_DEBUG_UART=y
... ... @@ -14,7 +13,6 @@
14 13 CONFIG_FIT_VERBOSE=y
15 14 CONFIG_SPL_LOAD_FIT=y
16 15 # CONFIG_DISPLAY_CPUINFO is not set
17   -# CONFIG_DISPLAY_BOARDINFO is not set
18 16 CONFIG_BOARD_EARLY_INIT_R=y
19 17 CONFIG_SPL_OS_BOOT=y
20 18 CONFIG_SPL_RAM_SUPPORT=y
configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
Diff comments   View file @ 3b52847
... ... @@ -5,7 +5,6 @@
5 5 CONFIG_SYS_MALLOC_F_LEN=0x8000
6 6 # CONFIG_SPL_LIBDISK_SUPPORT is not set
7 7 CONFIG_SPL=y
8   -CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm016 dc2"
9 8 # CONFIG_SPL_FAT_SUPPORT is not set
10 9 CONFIG_ZYNQMP_USB=y
11 10 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm016-dc2"
... ... @@ -15,7 +14,6 @@
15 14 CONFIG_FIT_VERBOSE=y
16 15 CONFIG_SPL_LOAD_FIT=y
17 16 # CONFIG_DISPLAY_CPUINFO is not set
18   -# CONFIG_DISPLAY_BOARDINFO is not set
19 17 CONFIG_BOARD_EARLY_INIT_R=y
20 18 CONFIG_SPL_OS_BOOT=y
21 19 CONFIG_SPL_RAM_SUPPORT=y
configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig
Diff comments   View file @ 3b52847
... ... @@ -4,7 +4,6 @@
4 4 CONFIG_SYS_TEXT_BASE=0x8000000
5 5 CONFIG_SYS_MALLOC_F_LEN=0x8000
6 6 CONFIG_SPL=y
7   -CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm017 dc3"
8 7 CONFIG_ZYNQMP_USB=y
9 8 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm017-dc3"
10 9 CONFIG_DEBUG_UART=y
... ... @@ -14,7 +13,6 @@
14 13 CONFIG_FIT_VERBOSE=y
15 14 CONFIG_SPL_LOAD_FIT=y
16 15 # CONFIG_DISPLAY_CPUINFO is not set
17   -# CONFIG_DISPLAY_BOARDINFO is not set
18 16 CONFIG_SPL_OS_BOOT=y
19 17 CONFIG_SPL_RAM_SUPPORT=y
20 18 CONFIG_SPL_RAM_DEVICE=y
configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
Diff comments   View file @ 3b52847
... ... @@ -3,7 +3,6 @@
3 3 CONFIG_SYS_TEXT_BASE=0x8000000
4 4 CONFIG_SYS_MALLOC_F_LEN=0x8000
5 5 CONFIG_SPL=y
6   -CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm018 dc4"
7 6 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm018-dc4"
8 7 CONFIG_DEBUG_UART=y
9 8 CONFIG_DISTRO_DEFAULTS=y
... ... @@ -11,7 +10,6 @@
11 10 CONFIG_FIT_VERBOSE=y
12 11 CONFIG_SPL_LOAD_FIT=y
13 12 # CONFIG_DISPLAY_CPUINFO is not set
14   -# CONFIG_DISPLAY_BOARDINFO is not set
15 13 CONFIG_BOARD_EARLY_INIT_R=y
16 14 CONFIG_SPL_OS_BOOT=y
17 15 CONFIG_SPL_RAM_SUPPORT=y
configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
Diff comments   View file @ 3b52847
... ... @@ -4,7 +4,6 @@
4 4 CONFIG_SYS_TEXT_BASE=0x8000000
5 5 CONFIG_SYS_MALLOC_F_LEN=0x8000
6 6 CONFIG_SPL=y
7   -CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm019 dc5"
8 7 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm019-dc5"
9 8 CONFIG_DEBUG_UART=y
10 9 CONFIG_DISTRO_DEFAULTS=y
... ... @@ -12,7 +11,6 @@
12 11 CONFIG_FIT_VERBOSE=y
13 12 CONFIG_SPL_LOAD_FIT=y
14 13 # CONFIG_DISPLAY_CPUINFO is not set
15   -# CONFIG_DISPLAY_BOARDINFO is not set
16 14 CONFIG_BOARD_EARLY_INIT_R=y
17 15 CONFIG_SPL_OS_BOOT=y
18 16 CONFIG_SPL_RAM_SUPPORT=y
configs/xilinx_zynqmp_zcu100_revC_defconfig
Diff comments   View file @ 3b52847
... ... @@ -4,7 +4,6 @@
4 4 CONFIG_SYS_TEXT_BASE=0x8000000
5 5 CONFIG_SYS_MALLOC_F_LEN=0x8000
6 6 CONFIG_SPL=y
7   -CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU100 RevC"
8 7 CONFIG_ZYNQ_SDHCI_MAX_FREQ=15000000
9 8 CONFIG_ZYNQMP_USB=y
10 9 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu100-revC"
... ... @@ -14,7 +13,6 @@
14 13 CONFIG_FIT_VERBOSE=y
15 14 CONFIG_SPL_LOAD_FIT=y
16 15 # CONFIG_DISPLAY_CPUINFO is not set
17   -# CONFIG_DISPLAY_BOARDINFO is not set
18 16 CONFIG_SPL_OS_BOOT=y
19 17 CONFIG_SPL_RAM_SUPPORT=y
20 18 CONFIG_SPL_RAM_DEVICE=y
... ... @@ -80,6 +78,8 @@
80 78 CONFIG_USB_STORAGE=y
81 79 CONFIG_USB_GADGET=y
82 80 CONFIG_USB_GADGET_DOWNLOAD=y
  81 +CONFIG_WDT=y
  82 +CONFIG_WDT_CDNS=y
83 83 CONFIG_OF_LIBFDT_OVERLAY=y
84 84 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
Diff comments   View file @ 3b52847
... ... @@ -4,7 +4,6 @@
4 4 CONFIG_SYS_TEXT_BASE=0x8000000
5 5 CONFIG_SYS_MALLOC_F_LEN=0x8000
6 6 CONFIG_SPL=y
7   -CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102 rev1.0"
8 7 CONFIG_ZYNQMP_USB=y
9 8 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-rev1.0"
10 9 CONFIG_DEBUG_UART=y
... ... @@ -14,7 +13,6 @@
14 13 CONFIG_FIT_VERBOSE=y
15 14 CONFIG_SPL_LOAD_FIT=y
16 15 # CONFIG_DISPLAY_CPUINFO is not set
17   -# CONFIG_DISPLAY_BOARDINFO is not set
18 16 CONFIG_BOARD_EARLY_INIT_R=y
19 17 CONFIG_SPL_OS_BOOT=y
20 18 CONFIG_SPL_RAM_SUPPORT=y
... ... @@ -62,6 +60,8 @@
62 60 CONFIG_MISC=y
63 61 CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20
64 62 CONFIG_DM_MMC=y
  63 +CONFIG_MMC_IO_VOLTAGE=y
  64 +CONFIG_MMC_UHS_SUPPORT=y
65 65 CONFIG_MMC_SDHCI=y
66 66 CONFIG_MMC_SDHCI_ZYNQ=y
67 67 CONFIG_SPI_FLASH=y
configs/xilinx_zynqmp_zcu102_revA_defconfig
Diff comments   View file @ 3b52847
... ... @@ -4,7 +4,6 @@
4 4 CONFIG_SYS_TEXT_BASE=0x8000000
5 5 CONFIG_SYS_MALLOC_F_LEN=0x8000
6 6 CONFIG_SPL=y
7   -CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102 revA"
8 7 CONFIG_ZYNQMP_USB=y
9 8 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revA"
10 9 CONFIG_DEBUG_UART=y
... ... @@ -14,7 +13,6 @@
14 13 CONFIG_FIT_VERBOSE=y
15 14 CONFIG_SPL_LOAD_FIT=y
16 15 # CONFIG_DISPLAY_CPUINFO is not set
17   -# CONFIG_DISPLAY_BOARDINFO is not set
18 16 CONFIG_BOARD_EARLY_INIT_R=y
19 17 CONFIG_SPL_OS_BOOT=y
20 18 CONFIG_SPL_RAM_SUPPORT=y
configs/xilinx_zynqmp_zcu102_revB_defconfig
Diff comments   View file @ 3b52847
... ... @@ -4,7 +4,6 @@
4 4 CONFIG_SYS_TEXT_BASE=0x8000000
5 5 CONFIG_SYS_MALLOC_F_LEN=0x8000
6 6 CONFIG_SPL=y
7   -CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102 revB"
8 7 CONFIG_ZYNQMP_USB=y
9 8 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revB"
10 9 CONFIG_DEBUG_UART=y
... ... @@ -14,7 +13,6 @@
14 13 CONFIG_FIT_VERBOSE=y
15 14 CONFIG_SPL_LOAD_FIT=y
16 15 # CONFIG_DISPLAY_CPUINFO is not set
17   -# CONFIG_DISPLAY_BOARDINFO is not set
18 16 CONFIG_BOARD_EARLY_INIT_R=y
19 17 CONFIG_SPL_OS_BOOT=y
20 18 CONFIG_SPL_RAM_SUPPORT=y
configs/xilinx_zynqmp_zcu104_revA_defconfig
Diff comments   View file @ 3b52847
... ... @@ -4,7 +4,6 @@
4 4 CONFIG_SYS_TEXT_BASE=0x8000000
5 5 CONFIG_SYS_MALLOC_F_LEN=0x8000
6 6 CONFIG_SPL=y
7   -CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU104 revA"
8 7 CONFIG_ZYNQMP_USB=y
9 8 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu104-revA"
10 9 CONFIG_DEBUG_UART=y
... ... @@ -14,7 +13,6 @@
14 13 CONFIG_FIT_VERBOSE=y
15 14 CONFIG_SPL_LOAD_FIT=y
16 15 # CONFIG_DISPLAY_CPUINFO is not set
17   -# CONFIG_DISPLAY_BOARDINFO is not set
18 16 CONFIG_SPL_OS_BOOT=y
19 17 CONFIG_SPL_RAM_SUPPORT=y
20 18 CONFIG_SPL_RAM_DEVICE=y
configs/xilinx_zynqmp_zcu104_revC_defconfig
Diff comments   View file @ 3b52847
... ... @@ -4,7 +4,6 @@
4 4 CONFIG_SYS_TEXT_BASE=0x8000000
5 5 CONFIG_SYS_MALLOC_F_LEN=0x8000
6 6 CONFIG_SPL=y
7   -CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU104 revC"
8 7 CONFIG_ZYNQMP_USB=y
9 8 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu104-revC"
10 9 CONFIG_DEBUG_UART=y
... ... @@ -14,7 +13,6 @@
14 13 CONFIG_FIT_VERBOSE=y
15 14 CONFIG_SPL_LOAD_FIT=y
16 15 # CONFIG_DISPLAY_CPUINFO is not set
17   -# CONFIG_DISPLAY_BOARDINFO is not set
18 16 CONFIG_SPL_OS_BOOT=y
19 17 CONFIG_SPL_RAM_SUPPORT=y
20 18 CONFIG_SPL_RAM_DEVICE=y
configs/xilinx_zynqmp_zcu106_revA_defconfig
Diff comments   View file @ 3b52847
... ... @@ -4,7 +4,6 @@
4 4 CONFIG_SYS_TEXT_BASE=0x8000000
5 5 CONFIG_SYS_MALLOC_F_LEN=0x8000
6 6 CONFIG_SPL=y
7   -CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU106 revA"
8 7 CONFIG_ZYNQMP_USB=y
9 8 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu106-revA"
10 9 CONFIG_DEBUG_UART=y
... ... @@ -14,7 +13,6 @@
14 13 CONFIG_FIT_VERBOSE=y
15 14 CONFIG_SPL_LOAD_FIT=y
16 15 # CONFIG_DISPLAY_CPUINFO is not set
17   -# CONFIG_DISPLAY_BOARDINFO is not set
18 16 CONFIG_SPL_OS_BOOT=y
19 17 CONFIG_SPL_RAM_SUPPORT=y
20 18 CONFIG_SPL_RAM_DEVICE=y
configs/xilinx_zynqmp_zcu111_revA_defconfig
Diff comments   View file @ 3b52847
... ... @@ -4,7 +4,6 @@
4 4 CONFIG_SYS_TEXT_BASE=0x8000000
5 5 CONFIG_SYS_MALLOC_F_LEN=0x8000
6 6 CONFIG_SPL=y
7   -CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU111"
8 7 CONFIG_ZYNQMP_USB=y
9 8 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu111-revA"
10 9 CONFIG_DEBUG_UART=y
... ... @@ -14,7 +13,6 @@
14 13 CONFIG_FIT_VERBOSE=y
15 14 CONFIG_SPL_LOAD_FIT=y
16 15 # CONFIG_DISPLAY_CPUINFO is not set
17   -# CONFIG_DISPLAY_BOARDINFO is not set
18 16 CONFIG_SPL_OS_BOOT=y
19 17 CONFIG_SPL_RAM_SUPPORT=y
20 18 CONFIG_SPL_RAM_DEVICE=y
configs/zynq_cc108_defconfig
Diff comments   View file @ 3b52847
... ... @@ -11,7 +11,6 @@
11 11 CONFIG_FIT_VERBOSE=y
12 12 CONFIG_IMAGE_FORMAT_LEGACY=y
13 13 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
14   -# CONFIG_DISPLAY_CPUINFO is not set
15 14 CONFIG_SPL_STACK_R=y
16 15 CONFIG_SPL_SPI_LOAD=y
17 16 CONFIG_SYS_PROMPT="Zynq> "
configs/zynq_cse_qspi_defconfig
Diff comments   View file @ 3b52847
... ... @@ -12,6 +12,7 @@
12 12 CONFIG_BOOTDELAY=-1
13 13 # CONFIG_USE_BOOTCOMMAND is not set
14 14 # CONFIG_DISPLAY_CPUINFO is not set
  15 +# CONFIG_ARCH_EARLY_INIT_R is not set
15 16 CONFIG_SPL_STACK_R=y
16 17 CONFIG_SPL_SPI_LOAD=y
17 18 CONFIG_SYS_PROMPT="Zynq> "
configs/zynq_microzed_defconfig
Diff comments   View file @ 3b52847
... ... @@ -10,7 +10,6 @@
10 10 CONFIG_FIT_VERBOSE=y
11 11 CONFIG_IMAGE_FORMAT_LEGACY=y
12 12 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
13   -# CONFIG_DISPLAY_CPUINFO is not set
14 13 CONFIG_SPL_STACK_R=y
15 14 CONFIG_SPL_OS_BOOT=y
16 15 CONFIG_SPL_SPI_LOAD=y
configs/zynq_picozed_defconfig
Diff comments   View file @ 3b52847
... ... @@ -6,7 +6,6 @@
6 6 CONFIG_DEFAULT_DEVICE_TREE="zynq-picozed"
7 7 CONFIG_DISTRO_DEFAULTS=y
8 8 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
9   -# CONFIG_DISPLAY_CPUINFO is not set
10 9 CONFIG_SPL_STACK_R=y
11 10 CONFIG_SPL_OS_BOOT=y
12 11 CONFIG_SYS_PROMPT="Zynq> "
configs/zynq_z_turn_defconfig
Diff comments   View file @ 3b52847
... ... @@ -11,7 +11,6 @@
11 11 CONFIG_FIT_VERBOSE=y
12 12 CONFIG_IMAGE_FORMAT_LEGACY=y
13 13 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
14   -# CONFIG_DISPLAY_CPUINFO is not set
15 14 CONFIG_SPL_STACK_R=y
16 15 CONFIG_SPL_OS_BOOT=y
17 16 CONFIG_SPL_SPI_LOAD=y
configs/zynq_zc702_defconfig
Diff comments   View file @ 3b52847
... ... @@ -13,7 +13,6 @@
13 13 CONFIG_FIT_VERBOSE=y
14 14 CONFIG_IMAGE_FORMAT_LEGACY=y
15 15 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
16   -# CONFIG_DISPLAY_CPUINFO is not set
17 16 CONFIG_SPL_STACK_R=y
18 17 CONFIG_SPL_OS_BOOT=y
19 18 CONFIG_SPL_SPI_LOAD=y
configs/zynq_zc706_defconfig
Diff comments   View file @ 3b52847
... ... @@ -13,7 +13,6 @@
13 13 CONFIG_FIT_VERBOSE=y
14 14 CONFIG_IMAGE_FORMAT_LEGACY=y
15 15 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
16   -# CONFIG_DISPLAY_CPUINFO is not set
17 16 CONFIG_SPL_STACK_R=y
18 17 CONFIG_SPL_OS_BOOT=y
19 18 CONFIG_SPL_SPI_LOAD=y
configs/zynq_zc770_xm010_defconfig
Diff comments   View file @ 3b52847
... ... @@ -12,7 +12,6 @@
12 12 CONFIG_FIT_VERBOSE=y
13 13 CONFIG_IMAGE_FORMAT_LEGACY=y
14 14 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
15   -# CONFIG_DISPLAY_CPUINFO is not set
16 15 CONFIG_SPL_STACK_R=y
17 16 CONFIG_SPL_OS_BOOT=y
18 17 CONFIG_SPL_SPI_LOAD=y
configs/zynq_zc770_xm011_defconfig
Diff comments   View file @ 3b52847
... ... @@ -13,7 +13,6 @@
13 13 CONFIG_FIT_VERBOSE=y
14 14 CONFIG_IMAGE_FORMAT_LEGACY=y
15 15 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
16   -# CONFIG_DISPLAY_CPUINFO is not set
17 16 CONFIG_SPL_STACK_R=y
18 17 CONFIG_SPL_OS_BOOT=y
19 18 CONFIG_SYS_PROMPT="Zynq> "
configs/zynq_zc770_xm011_x16_defconfig
Diff comments   View file @ 3b52847
... ... @@ -13,7 +13,6 @@
13 13 CONFIG_FIT_VERBOSE=y
14 14 CONFIG_IMAGE_FORMAT_LEGACY=y
15 15 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
16   -# CONFIG_DISPLAY_CPUINFO is not set
17 16 CONFIG_SPL_STACK_R=y
18 17 CONFIG_SPL_OS_BOOT=y
19 18 CONFIG_SYS_PROMPT="Zynq> "
configs/zynq_zc770_xm012_defconfig
Diff comments   View file @ 3b52847
... ... @@ -12,7 +12,6 @@
12 12 CONFIG_FIT_VERBOSE=y
13 13 CONFIG_IMAGE_FORMAT_LEGACY=y
14 14 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
15   -# CONFIG_DISPLAY_CPUINFO is not set
16 15 CONFIG_SPL_STACK_R=y
17 16 CONFIG_SPL_OS_BOOT=y
18 17 CONFIG_SYS_PROMPT="Zynq> "
configs/zynq_zc770_xm013_defconfig
Diff comments   View file @ 3b52847
... ... @@ -12,7 +12,6 @@
12 12 CONFIG_FIT_VERBOSE=y
13 13 CONFIG_IMAGE_FORMAT_LEGACY=y
14 14 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
15   -# CONFIG_DISPLAY_CPUINFO is not set
16 15 CONFIG_SPL_STACK_R=y
17 16 CONFIG_SPL_OS_BOOT=y
18 17 CONFIG_SPL_SPI_LOAD=y
configs/zynq_zed_defconfig
Diff comments   View file @ 3b52847
... ... @@ -11,7 +11,6 @@
11 11 CONFIG_FIT_VERBOSE=y
12 12 CONFIG_IMAGE_FORMAT_LEGACY=y
13 13 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
14   -# CONFIG_DISPLAY_CPUINFO is not set
15 14 CONFIG_SPL_STACK_R=y
16 15 CONFIG_SPL_OS_BOOT=y
17 16 CONFIG_SPL_SPI_LOAD=y
configs/zynq_zybo_defconfig
Diff comments   View file @ 3b52847
... ... @@ -12,7 +12,6 @@
12 12 CONFIG_FIT_VERBOSE=y
13 13 CONFIG_IMAGE_FORMAT_LEGACY=y
14 14 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
15   -# CONFIG_DISPLAY_CPUINFO is not set
16 15 CONFIG_SPL_STACK_R=y
17 16 CONFIG_SPL_OS_BOOT=y
18 17 CONFIG_SPL_SPI_LOAD=y
drivers/ata/sata_ceva.c
Diff comments   View file @ 3b52847
... ... @@ -72,6 +72,10 @@
72 72 #define DRV_NAME "ahci-ceva"
73 73 #define CEVA_FLAG_BROKEN_GEN2 1
74 74  
  75 +struct ceva_sata_priv {
  76 + ulong base;
  77 +};
  78 +
75 79 static int ceva_init_sata(ulong mmio)
76 80 {
77 81 ulong tmp;
78 82  
79 83  
80 84  
81 85  
... ... @@ -110,18 +114,20 @@
110 114 return 0;
111 115 }
112 116  
113   -static int sata_ceva_probe(struct udevice *dev)
  117 +static int sata_ceva_bind(struct udevice *dev)
114 118 {
115   - int ret;
116   - struct scsi_platdata *plat = dev_get_uclass_platdata(dev);
  119 + struct udevice *scsi_dev;
117 120  
118   - ceva_init_sata(plat->base);
  121 + return ahci_bind_scsi(dev, &scsi_dev);
  122 +}
119 123  
120   - ret = ahci_init_one_dm(dev);
121   - if (ret)
122   - return ret;
  124 +static int sata_ceva_probe(struct udevice *dev)
  125 +{
  126 + struct ceva_sata_priv *priv = dev_get_priv(dev);
123 127  
124   - return ahci_start_ports_dm(dev);
  128 + ceva_init_sata(priv->base);
  129 +
  130 + return ahci_probe_scsi(dev, priv->base);
125 131 }
126 132  
127 133 static const struct udevice_id sata_ceva_ids[] = {
128 134  
129 135  
130 136  
131 137  
132 138  
... ... @@ -131,24 +137,22 @@
131 137  
132 138 static int sata_ceva_ofdata_to_platdata(struct udevice *dev)
133 139 {
134   - struct scsi_platdata *plat = dev_get_uclass_platdata(dev);
  140 + struct ceva_sata_priv *priv = dev_get_priv(dev);
135 141  
136   - plat->base = devfdt_get_addr(dev);
137   - if (plat->base == FDT_ADDR_T_NONE)
  142 + priv->base = devfdt_get_addr(dev);
  143 + if (priv->base == FDT_ADDR_T_NONE)
138 144 return -EINVAL;
139 145  
140   - /* Hardcode number for ceva sata controller */
141   - plat->max_lun = 1; /* Actually two but untested */
142   - plat->max_id = 2;
143   -
144 146 return 0;
145 147 }
146 148  
147 149 U_BOOT_DRIVER(ceva_host_blk) = {
148 150 .name = "ceva_sata",
149   - .id = UCLASS_SCSI,
  151 + .id = UCLASS_AHCI,
150 152 .of_match = sata_ceva_ids,
  153 + .bind = sata_ceva_bind,
151 154 .ops = &scsi_ops,
  155 + .priv_auto_alloc_size = sizeof(struct ceva_sata_priv),
152 156 .probe = sata_ceva_probe,
153 157 .ofdata_to_platdata = sata_ceva_ofdata_to_platdata,
154 158 };
... ... @@ -679,7 +679,7 @@
679 679 {
680 680 struct mmc_cmd cmd;
681 681 int timeout = 1000;
682   - uint start;
  682 + ulong start;
683 683 int err;
684 684  
685 685 mmc->op_cond_pending = 0;
... ... @@ -2611,7 +2611,7 @@
2611 2611 int mmc_init(struct mmc *mmc)
2612 2612 {
2613 2613 int err = 0;
2614   - __maybe_unused unsigned start;
  2614 + __maybe_unused ulong start;
2615 2615 #if CONFIG_IS_ENABLED(DM_MMC)
2616 2616 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
2617 2617  
... ... @@ -151,7 +151,7 @@
151 151 u32 mask, flags, mode;
152 152 unsigned int time = 0, start_addr = 0;
153 153 int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
154   - unsigned start = get_timer(0);
  154 + ulong start = get_timer(0);
155 155  
156 156 /* Timeout unit - ms */
157 157 static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
... ... @@ -160,7 +160,8 @@
160 160  
161 161 /* We shouldn't wait for data inihibit for stop commands, even
162 162 though they might use busy signaling */
163   - if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
  163 + if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ||
  164 + cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
164 165 mask &= ~SDHCI_DATA_INHIBIT;
165 166  
166 167 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
... ... @@ -182,6 +183,9 @@
182 183 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
183 184  
184 185 mask = SDHCI_INT_RESPONSE;
  186 + if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
  187 + mask = SDHCI_INT_DATA_AVAIL;
  188 +
185 189 if (!(cmd->resp_type & MMC_RSP_PRESENT))
186 190 flags = SDHCI_CMD_RESP_NONE;
187 191 else if (cmd->resp_type & MMC_RSP_136)
... ... @@ -197,7 +201,7 @@
197 201 flags |= SDHCI_CMD_CRC;
198 202 if (cmd->resp_type & MMC_RSP_OPCODE)
199 203 flags |= SDHCI_CMD_INDEX;
200   - if (data)
  204 + if (data || cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
201 205 flags |= SDHCI_CMD_DATA;
202 206  
203 207 /* Set Transfer mode regarding to data flag */
... ... @@ -301,6 +305,24 @@
301 305 return -ECOMM;
302 306 }
303 307  
  308 +#if defined(CONFIG_DM_MMC) && defined(MMC_SUPPORTS_TUNING)
  309 +static int sdhci_execute_tuning(struct udevice *dev, uint opcode)
  310 +{
  311 + int err;
  312 + struct mmc *mmc = mmc_get_mmc_dev(dev);
  313 + struct sdhci_host *host = mmc->priv;
  314 +
  315 + debug("%s\n", __func__);
  316 +
  317 + if (host->ops->platform_execute_tuning) {
  318 + err = host->ops->platform_execute_tuning(mmc, opcode);
  319 + if (err)
  320 + return err;
  321 + return 0;
  322 + }
  323 + return 0;
  324 +}
  325 +#endif
304 326 static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
305 327 {
306 328 struct sdhci_host *host = mmc->priv;
... ... @@ -325,6 +347,9 @@
325 347 if (clock == 0)
326 348 return 0;
327 349  
  350 + if (host->ops->set_delay)
  351 + host->ops->set_delay(host);
  352 +
328 353 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
329 354 /*
330 355 * Check if the Host Controller supports Programmable Clock
... ... @@ -439,6 +464,9 @@
439 464 if (mmc->clock != host->clock)
440 465 sdhci_set_clock(mmc, mmc->clock);
441 466  
  467 + if (mmc->clk_disable)
  468 + sdhci_set_clock(mmc, 0);
  469 +
442 470 /* Set bus width */
443 471 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
444 472 if (mmc->bus_width == 8) {
... ... @@ -514,6 +542,9 @@
514 542 const struct dm_mmc_ops sdhci_ops = {
515 543 .send_cmd = sdhci_send_command,
516 544 .set_ios = sdhci_set_ios,
  545 +#ifdef MMC_SUPPORTS_TUNING
  546 + .execute_tuning = sdhci_execute_tuning,
  547 +#endif
517 548 };
518 549 #else
519 550 static const struct mmc_ops sdhci_ops = {
... ... @@ -526,7 +557,7 @@
526 557 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
527 558 u32 f_max, u32 f_min)
528 559 {
529   - u32 caps, caps_1;
  560 + u32 caps, caps_1 = 0;
530 561  
531 562 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
532 563  
... ... @@ -606,6 +637,32 @@
606 637 cfg->host_caps &= ~MMC_MODE_HS;
607 638 cfg->host_caps &= ~MMC_MODE_HS_52MHz;
608 639 }
  640 +
  641 + if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
  642 + caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
  643 +
  644 + if (!(cfg->voltages & MMC_VDD_165_195) ||
  645 + (host->quirks & SDHCI_QUIRK_NO_1_8_V))
  646 + caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
  647 + SDHCI_SUPPORT_DDR50);
  648 +
  649 + if (caps_1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
  650 + SDHCI_SUPPORT_DDR50))
  651 + cfg->host_caps |= MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25);
  652 +
  653 + if (caps_1 & SDHCI_SUPPORT_SDR104) {
  654 + cfg->host_caps |= MMC_CAP(UHS_SDR104) | MMC_CAP(UHS_SDR50);
  655 + /*
  656 + * SD3.0: SDR104 is supported so (for eMMC) the caps2
  657 + * field can be promoted to support HS200.
  658 + */
  659 + cfg->host_caps |= MMC_CAP(MMC_HS_200);
  660 + } else if (caps_1 & SDHCI_SUPPORT_SDR50) {
  661 + cfg->host_caps |= MMC_CAP(UHS_SDR50);
  662 + }
  663 +
  664 + if (caps_1 & SDHCI_SUPPORT_DDR50)
  665 + cfg->host_caps |= MMC_CAP(UHS_DDR50);
609 666  
610 667 if (host->host_caps)
611 668 cfg->host_caps |= host->host_caps;
drivers/mmc/zynq_sdhci.c
Diff comments   View file @ 3b52847
... ... @@ -9,9 +9,11 @@
9 9 #include <common.h>
10 10 #include <dm.h>
11 11 #include <fdtdec.h>
  12 +#include "mmc_private.h"
12 13 #include <linux/libfdt.h>
13 14 #include <malloc.h>
14 15 #include <sdhci.h>
  16 +#include <zynqmp_tap_delay.h>
15 17  
16 18 DECLARE_GLOBAL_DATA_PTR;
17 19  
18 20  
19 21  
... ... @@ -21,15 +23,212 @@
21 23 unsigned int f_max;
22 24 };
23 25  
  26 +struct arasan_sdhci_priv {
  27 + struct sdhci_host *host;
  28 + u8 deviceid;
  29 + u8 bank;
  30 + u8 no_1p8;
  31 + bool pwrseq;
  32 +};
  33 +
  34 +#if defined(CONFIG_ARCH_ZYNQMP)
  35 +static const u8 mode2timing[] = {
  36 + [UHS_SDR12] = UHS_SDR12_BUS_SPEED,
  37 + [UHS_SDR25] = UHS_SDR25_BUS_SPEED,
  38 + [UHS_SDR50] = UHS_SDR50_BUS_SPEED,
  39 + [UHS_SDR104] = UHS_SDR104_BUS_SPEED,
  40 + [UHS_DDR50] = UHS_DDR50_BUS_SPEED,
  41 +};
  42 +
  43 +#define SDHCI_HOST_CTRL2 0x3E
  44 +#define SDHCI_CTRL2_MODE_MASK 0x7
  45 +#define SDHCI_18V_SIGNAL 0x8
  46 +#define SDHCI_CTRL_EXEC_TUNING 0x0040
  47 +#define SDHCI_CTRL_TUNED_CLK 0x80
  48 +#define SDHCI_TUNING_LOOP_COUNT 40
  49 +
  50 +static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u8 deviceid)
  51 +{
  52 + u16 clk;
  53 + unsigned long timeout;
  54 +
  55 + clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
  56 + clk &= ~(SDHCI_CLOCK_CARD_EN);
  57 + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  58 +
  59 + /* Issue DLL Reset */
  60 + zynqmp_dll_reset(deviceid);
  61 +
  62 + /* Wait max 20 ms */
  63 + timeout = 100;
  64 + while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
  65 + & SDHCI_CLOCK_INT_STABLE)) {
  66 + if (timeout == 0) {
  67 + dev_err(mmc_dev(host->mmc),
  68 + ": Internal clock never stabilised.\n");
  69 + return;
  70 + }
  71 + timeout--;
  72 + udelay(1000);
  73 + }
  74 +
  75 + clk |= SDHCI_CLOCK_CARD_EN;
  76 + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  77 +}
  78 +
  79 +static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
  80 +{
  81 + struct mmc_cmd cmd;
  82 + struct mmc_data data;
  83 + u32 ctrl;
  84 + struct sdhci_host *host;
  85 + struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
  86 + u8 tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
  87 + u8 deviceid;
  88 +
  89 + debug("%s\n", __func__);
  90 +
  91 + host = priv->host;
  92 + deviceid = priv->deviceid;
  93 +
  94 + ctrl = sdhci_readw(host, SDHCI_HOST_CTRL2);
  95 + ctrl |= SDHCI_CTRL_EXEC_TUNING;
  96 + sdhci_writew(host, ctrl, SDHCI_HOST_CTRL2);
  97 +
  98 + mdelay(1);
  99 +
  100 + arasan_zynqmp_dll_reset(host, deviceid);
  101 +
  102 + sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
  103 + sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
  104 +
  105 + do {
  106 + cmd.cmdidx = opcode;
  107 + cmd.resp_type = MMC_RSP_R1;
  108 + cmd.cmdarg = 0;
  109 +
  110 + data.blocksize = 64;
  111 + data.blocks = 1;
  112 + data.flags = MMC_DATA_READ;
  113 +
  114 + if (tuning_loop_counter-- == 0)
  115 + break;
  116 +
  117 + if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200 &&
  118 + mmc->bus_width == 8)
  119 + data.blocksize = 128;
  120 +
  121 + sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
  122 + data.blocksize),
  123 + SDHCI_BLOCK_SIZE);
  124 + sdhci_writew(host, data.blocks, SDHCI_BLOCK_COUNT);
  125 + sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
  126 +
  127 + mmc_send_cmd(mmc, &cmd, NULL);
  128 + ctrl = sdhci_readw(host, SDHCI_HOST_CTRL2);
  129 +
  130 + if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
  131 + udelay(1);
  132 +
  133 + } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
  134 +
  135 + if (tuning_loop_counter < 0) {
  136 + ctrl &= ~SDHCI_CTRL_TUNED_CLK;
  137 + sdhci_writel(host, ctrl, SDHCI_HOST_CTRL2);
  138 + }
  139 +
  140 + if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
  141 + printf("%s:Tuning failed\n", __func__);
  142 + return -1;
  143 + }
  144 +
  145 + udelay(1);
  146 + arasan_zynqmp_dll_reset(host, deviceid);
  147 +
  148 + /* Enable only interrupts served by the SD controller */
  149 + sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
  150 + SDHCI_INT_ENABLE);
  151 + /* Mask all sdhci interrupt sources */
  152 + sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
  153 +
  154 + return 0;
  155 +}
  156 +
  157 +static void arasan_sdhci_set_tapdelay(struct sdhci_host *host)
  158 +{
  159 + struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
  160 + struct mmc *mmc = (struct mmc *)host->mmc;
  161 + u8 uhsmode;
  162 +
  163 + if (!IS_SD(mmc))
  164 + return;
  165 +
  166 + uhsmode = mode2timing[mmc->selected_mode];
  167 +
  168 + if (uhsmode >= UHS_SDR25_BUS_SPEED)
  169 + arasan_zynqmp_set_tapdelay(priv->deviceid, uhsmode,
  170 + priv->bank);
  171 +}
  172 +
  173 +static void arasan_sdhci_set_control_reg(struct sdhci_host *host)
  174 +{
  175 + struct mmc *mmc = (struct mmc *)host->mmc;
  176 + u32 reg;
  177 +
  178 + if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
  179 + reg = sdhci_readw(host, SDHCI_HOST_CTRL2);
  180 + reg |= SDHCI_18V_SIGNAL;
  181 + sdhci_writew(host, reg, SDHCI_HOST_CTRL2);
  182 + }
  183 +
  184 + if (mmc->selected_mode > SD_HS &&
  185 + mmc->selected_mode <= UHS_DDR50) {
  186 + reg = sdhci_readw(host, SDHCI_HOST_CTRL2);
  187 + reg &= ~SDHCI_CTRL2_MODE_MASK;
  188 + switch (mmc->selected_mode) {
  189 + case UHS_SDR12:
  190 + reg |= UHS_SDR12_BUS_SPEED;
  191 + break;
  192 + case UHS_SDR25:
  193 + reg |= UHS_SDR25_BUS_SPEED;
  194 + break;
  195 + case UHS_SDR50:
  196 + reg |= UHS_SDR50_BUS_SPEED;
  197 + break;
  198 + case UHS_SDR104:
  199 + reg |= UHS_SDR104_BUS_SPEED;
  200 + break;
  201 + case UHS_DDR50:
  202 + reg |= UHS_DDR50_BUS_SPEED;
  203 + break;
  204 + default:
  205 + break;
  206 + }
  207 + sdhci_writew(host, reg, SDHCI_HOST_CTRL2);
  208 + }
  209 +}
  210 +#endif
  211 +
  212 +#if defined(CONFIG_DM_MMC) && defined(CONFIG_ARCH_ZYNQMP)
  213 +const struct sdhci_ops arasan_ops = {
  214 + .platform_execute_tuning = &arasan_sdhci_execute_tuning,
  215 + .set_delay = &arasan_sdhci_set_tapdelay,
  216 + .set_control_reg = &arasan_sdhci_set_control_reg,
  217 +};
  218 +#endif
  219 +
24 220 static int arasan_sdhci_probe(struct udevice *dev)
25 221 {
26 222 struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
27 223 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
28   - struct sdhci_host *host = dev_get_priv(dev);
  224 + struct arasan_sdhci_priv *priv = dev_get_priv(dev);
  225 + struct sdhci_host *host;
29 226 struct clk clk;
30 227 unsigned long clock;
31 228 int ret;
32 229  
  230 + host = priv->host;
  231 +
33 232 ret = clk_get_by_index(dev, 0, &clk);
34 233 if (ret < 0) {
35 234 dev_err(dev, "failed to get clock\n");
... ... @@ -41,6 +240,7 @@
41 240 dev_err(dev, "failed to get rate\n");
42 241 return clock;
43 242 }
  243 +
44 244 debug("%s: CLK %ld\n", __func__, clock);
45 245  
46 246 ret = clk_enable(&clk);
... ... @@ -56,6 +256,9 @@
56 256 host->quirks |= SDHCI_QUIRK_BROKEN_HISPD_MODE;
57 257 #endif
58 258  
  259 + if (priv->no_1p8)
  260 + host->quirks |= SDHCI_QUIRK_NO_1_8_V;
  261 +
59 262 host->max_clk = clock;
60 263  
61 264 ret = sdhci_setup_cfg(&plat->cfg, host, plat->f_max,
62 265  
63 266  
... ... @@ -73,11 +276,29 @@
73 276 static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
74 277 {
75 278 struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
76   - struct sdhci_host *host = dev_get_priv(dev);
  279 + struct arasan_sdhci_priv *priv = dev_get_priv(dev);
77 280  
78   - host->name = dev->name;
79   - host->ioaddr = (void *)devfdt_get_addr(dev);
  281 + priv->host = calloc(1, sizeof(struct sdhci_host));
  282 + if (!priv->host)
  283 + return -1;
80 284  
  285 + priv->host->name = dev->name;
  286 + priv->host->ioaddr = (void *)devfdt_get_addr(dev);
  287 +
  288 + priv->deviceid = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  289 + "xlnx,device_id", -1);
  290 + priv->bank = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  291 + "xlnx,mio_bank", -1);
  292 + if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev),
  293 + "no-1-8-v", NULL))
  294 + priv->no_1p8 = 1;
  295 + else
  296 + priv->no_1p8 = 0;
  297 +
  298 +#if defined(CONFIG_DM_MMC) && defined(CONFIG_ARCH_ZYNQMP)
  299 + priv->host->ops = &arasan_ops;
  300 +#endif
  301 +
81 302 plat->f_max = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
82 303 "max-frequency", CONFIG_ZYNQ_SDHCI_MAX_FREQ);
83 304  
... ... @@ -104,7 +325,7 @@
104 325 .ops = &sdhci_ops,
105 326 .bind = arasan_sdhci_bind,
106 327 .probe = arasan_sdhci_probe,
107   - .priv_auto_alloc_size = sizeof(struct sdhci_host),
  328 + .priv_auto_alloc_size = sizeof(struct arasan_sdhci_priv),
108 329 .platdata_auto_alloc_size = sizeof(struct arasan_sdhci_plat),
109 330 };
drivers/mtd/nand/zynq_nand.c
Diff comments   View file @ 3b52847
... ... @@ -16,6 +16,7 @@
16 16 #include <linux/mtd/partitions.h>
17 17 #include <linux/mtd/nand_ecc.h>
18 18 #include <asm/arch/hardware.h>
  19 +#include <asm/arch/sys_proto.h>
19 20  
20 21 /* The NAND flash driver defines */
21 22 #define ZYNQ_NAND_CMD_PHASE 1
... ... @@ -83,6 +84,18 @@
83 84 #define ZYNQ_NAND_ECC_BUSY (1 << 6) /* ECC block is busy */
84 85 #define ZYNQ_NAND_ECC_MASK 0x00FFFFFF /* ECC value mask */
85 86  
  87 +#define ZYNQ_NAND_ROW_ADDR_CYCL_MASK 0x0F
  88 +#define ZYNQ_NAND_COL_ADDR_CYCL_MASK 0xF0
  89 +
  90 +#define ZYNQ_NAND_MIO_NUM_NAND_8BIT 13
  91 +#define ZYNQ_NAND_MIO_NUM_NAND_16BIT 8
  92 +
  93 +enum zynq_nand_bus_width {
  94 + NAND_BW_UNKNOWN = -1,
  95 + NAND_BW_8BIT,
  96 + NAND_BW_16BIT,
  97 +};
  98 +
86 99 #ifndef NAND_CMD_LOCK_TIGHT
87 100 #define NAND_CMD_LOCK_TIGHT 0x2c
88 101 #endif
... ... @@ -768,6 +781,7 @@
768 781 {
769 782 struct nand_chip *chip = mtd->priv;
770 783 const struct zynq_nand_command_format *curr_cmd = NULL;
  784 + u8 addr_cycles = 0;
771 785 struct zynq_nand_info *xnand = (struct zynq_nand_info *)chip->priv;
772 786 void *cmd_addr;
773 787 unsigned long cmd_data = 0;
774 788  
... ... @@ -818,8 +832,18 @@
818 832 else
819 833 end_cmd = curr_cmd->end_cmd;
820 834  
  835 + if (command == NAND_CMD_READ0 ||
  836 + command == NAND_CMD_SEQIN) {
  837 + addr_cycles = chip->onfi_params.addr_cycles &
  838 + ZYNQ_NAND_ROW_ADDR_CYCL_MASK;
  839 + addr_cycles += ((chip->onfi_params.addr_cycles &
  840 + ZYNQ_NAND_COL_ADDR_CYCL_MASK) >> 4);
  841 + } else {
  842 + addr_cycles = curr_cmd->addr_cycles;
  843 + }
  844 +
821 845 cmd_phase_addr = (unsigned long)xnand->nand_base |
822   - (curr_cmd->addr_cycles << ADDR_CYCLES_SHIFT) |
  846 + (addr_cycles << ADDR_CYCLES_SHIFT) |
823 847 (end_cmd_valid << END_CMD_VALID_SHIFT) |
824 848 (COMMAND_PHASE) |
825 849 (end_cmd << END_CMD_SHIFT) |
... ... @@ -1005,6 +1029,23 @@
1005 1029 return 0;
1006 1030 }
1007 1031  
  1032 +static int zynq_nand_check_is_16bit_bw_flash(void)
  1033 +{
  1034 + int is_16bit_bw = NAND_BW_UNKNOWN;
  1035 + int mio_num_8bit = 0, mio_num_16bit = 0;
  1036 +
  1037 + mio_num_8bit = zynq_slcr_get_mio_pin_status("nand8");
  1038 + if (mio_num_8bit == ZYNQ_NAND_MIO_NUM_NAND_8BIT)
  1039 + is_16bit_bw = NAND_BW_8BIT;
  1040 +
  1041 + mio_num_16bit = zynq_slcr_get_mio_pin_status("nand16");
  1042 + if (mio_num_8bit == ZYNQ_NAND_MIO_NUM_NAND_8BIT &&
  1043 + mio_num_16bit == ZYNQ_NAND_MIO_NUM_NAND_16BIT)
  1044 + is_16bit_bw = NAND_BW_16BIT;
  1045 +
  1046 + return is_16bit_bw;
  1047 +}
  1048 +
1008 1049 static int zynq_nand_init(struct nand_chip *nand_chip, int devnum)
1009 1050 {
1010 1051 struct zynq_nand_info *xnand;
... ... @@ -1016,6 +1057,7 @@
1016 1057 unsigned long ecc_cfg;
1017 1058 int ondie_ecc_enabled = 0;
1018 1059 int err = -1;
  1060 + int is_16bit_bw;
1019 1061  
1020 1062 xnand = calloc(1, sizeof(struct zynq_nand_info));
1021 1063 if (!xnand) {
... ... @@ -1044,6 +1086,16 @@
1044 1086 /* Buffer read/write routines */
1045 1087 nand_chip->read_buf = zynq_nand_read_buf;
1046 1088 nand_chip->write_buf = zynq_nand_write_buf;
  1089 +
  1090 + is_16bit_bw = zynq_nand_check_is_16bit_bw_flash();
  1091 + if (is_16bit_bw == NAND_BW_UNKNOWN) {
  1092 + printf("%s: Unable detect NAND based on MIO settings\n",
  1093 + __func__);
  1094 + goto fail;
  1095 + }
  1096 +
  1097 + if (is_16bit_bw == NAND_BW_16BIT)
  1098 + nand_chip->options = NAND_BUSWIDTH_16;
1047 1099  
1048 1100 nand_chip->bbt_options = NAND_BBT_USE_FLASH;
1049 1101  
drivers/serial/Kconfig
Diff comments   View file @ 3b52847
... ... @@ -624,7 +624,7 @@
624 624  
625 625 config ZYNQ_SERIAL
626 626 bool "Cadence (Xilinx Zynq) UART support"
627   - depends on DM_SERIAL && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP)
  627 + depends on DM_SERIAL && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_ZYNQMP_R5)
628 628 help
629 629 This driver supports the Cadence UART. It is found e.g. in Xilinx
630 630 Zynq/ZynqMP.
drivers/serial/serial_zynq.c
Diff comments   View file @ 3b52847
... ... @@ -14,7 +14,6 @@
14 14 #include <asm/io.h>
15 15 #include <linux/compiler.h>
16 16 #include <serial.h>
17   -#include <asm/arch/hardware.h>
18 17  
19 18 #define ZYNQ_UART_SR_TXEMPTY (1 << 3) /* TX FIFO empty */
20 19 #define ZYNQ_UART_SR_TXACTIVE (1 << 11) /* TX active */
drivers/timer/Kconfig
Diff comments   View file @ 3b52847
... ... @@ -52,6 +52,13 @@
52 52 it is designed to offer maximum accuracy and efficient management,
53 53 even for systems with long response time.
54 54  
  55 +config CADENCE_TTC_TIMER
  56 + bool "Cadence TTC (Triple Timer Counter)"
  57 + depends on TIMER
  58 + help
  59 + Enables support for the cadence ttc driver. This driver is present
  60 + on Xilinx Zynq and ZynqMP SoCs.
  61 +
55 62 config SANDBOX_TIMER
56 63 bool "Sandbox timer support"
57 64 depends on SANDBOX && TIMER
drivers/timer/Makefile
Diff comments   View file @ 3b52847
... ... @@ -4,6 +4,7 @@
4 4  
5 5 obj-y += timer-uclass.o
6 6 obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o
  7 +obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence-ttc.o
7 8 obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o
8 9 obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o
9 10 obj-$(CONFIG_OMAP_TIMER) += omap-timer.o
drivers/timer/cadence-ttc.c
Diff comments   View file @ 3b52847
  1 +// SPDX-License-Identifier: GPL-2.0
  2 +/*
  3 + * Copyright (C) 2018 Xilinx, Inc. (Michal Simek)
  4 + */
  5 +
  6 +#include <common.h>
  7 +#include <dm.h>
  8 +#include <errno.h>
  9 +#include <timer.h>
  10 +#include <asm/io.h>
  11 +
  12 +#define CNT_CNTRL_RESET BIT(4)
  13 +
  14 +struct cadence_ttc_regs {
  15 + u32 clk_cntrl1; /* 0x0 - Clock Control 1 */
  16 + u32 clk_cntrl2; /* 0x4 - Clock Control 2 */
  17 + u32 clk_cntrl3; /* 0x8 - Clock Control 3 */
  18 + u32 counter_cntrl1; /* 0xC - Counter Control 1 */
  19 + u32 counter_cntrl2; /* 0x10 - Counter Control 2 */
  20 + u32 counter_cntrl3; /* 0x14 - Counter Control 3 */
  21 + u32 counter_val1; /* 0x18 - Counter Control 1 */
  22 + u32 counter_val2; /* 0x1C - Counter Control 2 */
  23 + u32 counter_val3; /* 0x20 - Counter Control 3 */
  24 + u32 reserved[15];
  25 + u32 interrupt_enable1; /* 0x60 - Interrupt Enable 1 */
  26 + u32 interrupt_enable2; /* 0x64 - Interrupt Enable 2 */
  27 + u32 interrupt_enable3; /* 0x68 - Interrupt Enable 3 */
  28 +};
  29 +
  30 +struct cadence_ttc_priv {
  31 + struct cadence_ttc_regs *regs;
  32 +};
  33 +
  34 +static int cadence_ttc_get_count(struct udevice *dev, u64 *count)
  35 +{
  36 + struct cadence_ttc_priv *priv = dev_get_priv(dev);
  37 +
  38 + *count = readl(&priv->regs->counter_val1);
  39 +
  40 + return 0;
  41 +}
  42 +
  43 +static int cadence_ttc_probe(struct udevice *dev)
  44 +{
  45 + struct cadence_ttc_priv *priv = dev_get_priv(dev);
  46 +
  47 + /* Disable interrupts for sure */
  48 + writel(0, &priv->regs->interrupt_enable1);
  49 + writel(0, &priv->regs->interrupt_enable2);
  50 + writel(0, &priv->regs->interrupt_enable3);
  51 +
  52 + /* Make sure that clocks are configured properly without prescaller */
  53 + writel(0, &priv->regs->clk_cntrl1);
  54 + writel(0, &priv->regs->clk_cntrl2);
  55 + writel(0, &priv->regs->clk_cntrl3);
  56 +
  57 + /* Reset and enable this counter */
  58 + writel(CNT_CNTRL_RESET, &priv->regs->counter_cntrl1);
  59 +
  60 + return 0;
  61 +}
  62 +
  63 +static int cadence_ttc_ofdata_to_platdata(struct udevice *dev)
  64 +{
  65 + struct cadence_ttc_priv *priv = dev_get_priv(dev);
  66 +
  67 + priv->regs = map_physmem(devfdt_get_addr(dev),
  68 + sizeof(struct cadence_ttc_regs), MAP_NOCACHE);
  69 +
  70 + return 0;
  71 +}
  72 +
  73 +static const struct timer_ops cadence_ttc_ops = {
  74 + .get_count = cadence_ttc_get_count,
  75 +};
  76 +
  77 +static const struct udevice_id cadence_ttc_ids[] = {
  78 + { .compatible = "cdns,ttc" },
  79 + {}
  80 +};
  81 +
  82 +U_BOOT_DRIVER(cadence_ttc) = {
  83 + .name = "cadence_ttc",
  84 + .id = UCLASS_TIMER,
  85 + .of_match = cadence_ttc_ids,
  86 + .ofdata_to_platdata = cadence_ttc_ofdata_to_platdata,
  87 + .priv_auto_alloc_size = sizeof(struct cadence_ttc_priv),
  88 + .probe = cadence_ttc_probe,
  89 + .ops = &cadence_ttc_ops,
  90 + .flags = DM_FLAG_PRE_RELOC,
  91 +};
drivers/watchdog/cdns_wdt.c
Diff comments   View file @ 3b52847
... ... @@ -142,12 +142,12 @@
142 142 return -1;
143 143 }
144 144  
145   - debug("%s: CLK_FREQ %ld, timeout %lld\n", __func__, clk_f, timeout);
146   -
147 145 if ((timeout < CDNS_WDT_MIN_TIMEOUT) ||
148 146 (timeout > CDNS_WDT_MAX_TIMEOUT)) {
149 147 timeout = priv->timeout;
150 148 }
  149 +
  150 + debug("%s: CLK_FREQ %ld, timeout %lld\n", __func__, clk_f, timeout);
151 151  
152 152 if (clk_f <= CDNS_WDT_CLK_75MHZ) {
153 153 prescaler = CDNS_WDT_PRESCALE_512;
include/configs/xilinx_zynqmp_r5.h
Diff comments   View file @ 3b52847
  1 +/* SPDX-License-Identifier: GPL-2.0 */
  2 +/*
  3 + * (C) Copyright 2018 Xilinx, Inc. (Michal Simek)
  4 + */
  5 +
  6 +#ifndef __CONFIG_ZYNQMP_R5_H
  7 +#define __CONFIG_ZYNQMP_R5_H
  8 +
  9 +#define CONFIG_EXTRA_ENV_SETTINGS
  10 +
  11 +/* CPU clock */
  12 +#define CONFIG_CPU_FREQ_HZ 500000000
  13 +
  14 +/* Serial drivers */
  15 +/* The following table includes the supported baudrates */
  16 +#define CONFIG_SYS_BAUDRATE_TABLE \
  17 + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
  18 +
  19 +# define CONFIG_ENV_SIZE (128 << 10)
  20 +
  21 +/* Allow to overwrite serial and ethaddr */
  22 +#define CONFIG_ENV_OVERWRITE
  23 +
  24 +/* Boot configuration */
  25 +#define CONFIG_SYS_LOAD_ADDR 0 /* default? */
  26 +
  27 +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
  28 +
  29 +#define CONFIG_NR_DRAM_BANKS 1
  30 +
  31 +#define CONFIG_SYS_MALLOC_LEN 0x1400000
  32 +
  33 +#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
  34 +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
  35 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
  36 + CONFIG_SYS_INIT_RAM_SIZE - \
  37 + GENERATED_GBL_DATA_SIZE)
  38 +
  39 +/* Extend size of kernel image for uncompression */
  40 +#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024)
  41 +
  42 +#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
  43 +
  44 +#define CONFIG_SKIP_LOWLEVEL_INIT
  45 +
  46 +/* 0x0 - 0x40 is used for placing exception vectors */
  47 +#define CONFIG_SYS_MEMTEST_START 0x40
  48 +#define CONFIG_SYS_MEMTEST_END 0x100
  49 +#define CONFIG_SYS_MEMTEST_SCRATCH 0
  50 +
  51 +#endif /* __CONFIG_ZYNQ_ZYNQMP_R5_H */
include/configs/xilinx_zynqmp_zc1275_revB.h
Diff comments   View file @ 3b52847
  1 +/*
  2 + * Configuration for Xilinx ZynqMP zc1275 RevB
  3 + *
  4 + * (C) Copyright 2018 Xilinx, Inc.
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#ifndef __CONFIG_ZYNQMP_ZC1275_REVB_H
  10 +#define __CONFIG_ZYNQMP_ZC1275_REVB_H
  11 +
  12 +#define CONFIG_ZYNQ_SDHCI1
  13 +
  14 +#include <configs/xilinx_zynqmp.h>
  15 +
  16 +#endif /* __CONFIG_ZYNQMP_ZC1275_REVB_H */
... ... @@ -268,6 +268,7 @@
268 268 IH_TYPE_RKSPI, /* Rockchip SPI image */
269 269 IH_TYPE_ZYNQIMAGE, /* Xilinx Zynq Boot Image */
270 270 IH_TYPE_ZYNQMPIMAGE, /* Xilinx ZynqMP Boot Image */
  271 + IH_TYPE_ZYNQMPBIF, /* Xilinx ZynqMP Boot Image (bif) */
271 272 IH_TYPE_FPGA, /* FPGA Image */
272 273 IH_TYPE_VYBRIDIMAGE, /* VYBRID .vyb Image */
273 274 IH_TYPE_TEE, /* Trusted Execution Environment OS Image */
... ... @@ -166,6 +166,11 @@
166 166 #define SDHCI_CAN_64BIT BIT(28)
167 167  
168 168 #define SDHCI_CAPABILITIES_1 0x44
  169 +#define SDHCI_SUPPORT_SDR50 0x00000001
  170 +#define SDHCI_SUPPORT_SDR104 0x00000002
  171 +#define SDHCI_SUPPORT_DDR50 0x00000004
  172 +#define SDHCI_USE_SDR50_TUNING 0x00002000
  173 +
169 174 #define SDHCI_CLOCK_MUL_MASK 0x00FF0000
170 175 #define SDHCI_CLOCK_MUL_SHIFT 16
171 176  
... ... @@ -220,6 +225,7 @@
220 225 #define SDHCI_QUIRK_BROKEN_HISPD_MODE BIT(5)
221 226 #define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6)
222 227 #define SDHCI_QUIRK_USE_WIDE8 (1 << 8)
  228 +#define SDHCI_QUIRK_NO_1_8_V (1 << 9)
223 229  
224 230 /* to make gcc happy */
225 231 struct sdhci_host;
... ... @@ -242,6 +248,8 @@
242 248 void (*set_control_reg)(struct sdhci_host *host);
243 249 void (*set_ios_post)(struct sdhci_host *host);
244 250 void (*set_clock)(struct sdhci_host *host, u32 div);
  251 + int (*platform_execute_tuning)(struct mmc *host, u8 opcode);
  252 + void (*set_delay)(struct sdhci_host *host);
245 253 };
246 254  
247 255 struct sdhci_host {
include/zynqmp_tap_delay.h
Diff comments   View file @ 3b52847
  1 +/* SPDX-License-Identifier: GPL-2.0 */
  2 +/*
  3 + * Xilinx ZynqMP SoC Tap Delay Programming
  4 + *
  5 + * Copyright (C) 2018 Xilinx, Inc.
  6 + */
  7 +
  8 +#ifndef __ZYNQMP_TAP_DELAY_H__
  9 +#define __ZYNQMP_TAP_DELAY_H__
  10 +
  11 +#ifdef CONFIG_ARCH_ZYNQMP
  12 +void zynqmp_dll_reset(u8 deviceid);
  13 +void arasan_zynqmp_set_tapdelay(u8 device_id, u8 uhsmode, u8 bank);
  14 +#else
  15 +inline void zynqmp_dll_reset(u8 deviceid) {}
  16 +inline void arasan_zynqmp_set_tapdelay(u8 device_id, u8 uhsmode, u8 bank) {}
  17 +#endif
  18 +
  19 +#endif
... ... @@ -11,23 +11,18 @@
11 11  
12 12 #include <xilinx.h>
13 13  
14   -#if defined(CONFIG_FPGA_ZYNQPL)
15 14 extern struct xilinx_fpga_op zynq_op;
16   -# define FPGA_ZYNQPL_OPS &zynq_op
17   -#else
18   -# define FPGA_ZYNQPL_OPS NULL
19   -#endif
20 15  
21   -#define XILINX_ZYNQ_7007S 0x3
22   -#define XILINX_ZYNQ_7010 0x2
23   -#define XILINX_ZYNQ_7012S 0x1c
24   -#define XILINX_ZYNQ_7014S 0x8
25   -#define XILINX_ZYNQ_7015 0x1b
26   -#define XILINX_ZYNQ_7020 0x7
27   -#define XILINX_ZYNQ_7030 0xc
28   -#define XILINX_ZYNQ_7035 0x12
29   -#define XILINX_ZYNQ_7045 0x11
30   -#define XILINX_ZYNQ_7100 0x16
  16 +#define XILINX_ZYNQ_XC7Z007S 0x3
  17 +#define XILINX_ZYNQ_XC7Z010 0x2
  18 +#define XILINX_ZYNQ_XC7Z012S 0x1c
  19 +#define XILINX_ZYNQ_XC7Z014S 0x8
  20 +#define XILINX_ZYNQ_XC7Z015 0x1b
  21 +#define XILINX_ZYNQ_XC7Z020 0x7
  22 +#define XILINX_ZYNQ_XC7Z030 0xc
  23 +#define XILINX_ZYNQ_XC7Z035 0x12
  24 +#define XILINX_ZYNQ_XC7Z045 0x11
  25 +#define XILINX_ZYNQ_XC7Z100 0x16
31 26  
32 27 /* Device Image Sizes */
33 28 #define XILINX_XC7Z007S_SIZE 16669920/8
34 29  
... ... @@ -41,46 +36,30 @@
41 36 #define XILINX_XC7Z045_SIZE 106571232/8
42 37 #define XILINX_XC7Z100_SIZE 139330784/8
43 38  
44   -/* Descriptor Macros */
45   -#define XILINX_XC7Z007S_DESC(cookie) \
46   -{ xilinx_zynq, devcfg, XILINX_XC7Z007S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
47   - "7z007s" }
  39 +/* Device Names */
  40 +#define XILINX_XC7Z007S_NAME "7z007s"
  41 +#define XILINX_XC7Z010_NAME "7z010"
  42 +#define XILINX_XC7Z012S_NAME "7z012s"
  43 +#define XILINX_XC7Z014S_NAME "7z014s"
  44 +#define XILINX_XC7Z015_NAME "7z015"
  45 +#define XILINX_XC7Z020_NAME "7z020"
  46 +#define XILINX_XC7Z030_NAME "7z030"
  47 +#define XILINX_XC7Z035_NAME "7z035"
  48 +#define XILINX_XC7Z045_NAME "7z045"
  49 +#define XILINX_XC7Z100_NAME "7z100"
48 50  
49   -#define XILINX_XC7Z010_DESC(cookie) \
50   -{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
51   - "7z010" }
52   -
53   -#define XILINX_XC7Z012S_DESC(cookie) \
54   -{ xilinx_zynq, devcfg, XILINX_XC7Z012S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
55   - "7z012s" }
56   -
57   -#define XILINX_XC7Z014S_DESC(cookie) \
58   -{ xilinx_zynq, devcfg, XILINX_XC7Z014S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
59   - "7z014s" }
60   -
61   -#define XILINX_XC7Z015_DESC(cookie) \
62   -{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
63   - "7z015" }
64   -
65   -#define XILINX_XC7Z020_DESC(cookie) \
66   -{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
67   - "7z020" }
68   -
69   -#define XILINX_XC7Z030_DESC(cookie) \
70   -{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
71   - "7z030" }
72   -
73   -#define XILINX_XC7Z035_DESC(cookie) \
74   -{ xilinx_zynq, devcfg, XILINX_XC7Z035_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
75   - "7z035" }
76   -
77   -#define XILINX_XC7Z045_DESC(cookie) \
78   -{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
79   - "7z045" }
80   -
81   -#define XILINX_XC7Z100_DESC(cookie) \
82   -{ xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
83   - "7z100" }
  51 +#if defined(CONFIG_FPGA)
  52 +#define ZYNQ_DESC(name) { \
  53 + .idcode = XILINX_ZYNQ_XC##name, \
  54 + .fpga_size = XILINX_XC##name##_SIZE, \
  55 + .devicename = XILINX_XC##name##_NAME \
  56 + }
  57 +#else
  58 +#define ZYNQ_DESC(name) { \
  59 + .idcode = XILINX_ZYNQ_XC##name, \
  60 + .devicename = XILINX_XC##name##_NAME \
  61 + }
  62 +#endif
84 63  
85 64 #endif /* _ZYNQPL_H_ */
... ... @@ -111,6 +111,7 @@
111 111 ublimage.o \
112 112 zynqimage.o \
113 113 zynqmpimage.o \
  114 + zynqmpbif.o \
114 115 $(LIBFDT_OBJS) \
115 116 gpimage.o \
116 117 gpimage-common.o \
... ... @@ -231,6 +231,7 @@
231 231  
232 232  
233 233 void pbl_load_uboot(int fd, struct image_tool_params *mparams);
  234 +int zynqmpbif_copy_image(int fd, struct image_tool_params *mparams);
234 235  
235 236 #define ___cat(a, b) a ## b
236 237 #define __cat(a, b) ___cat(a, b)
... ... @@ -515,6 +515,13 @@
515 515 } else if (params.type == IH_TYPE_PBLIMAGE) {
516 516 /* PBL has special Image format, implements its' own */
517 517 pbl_load_uboot(ifd, &params);
  518 + } else if (params.type == IH_TYPE_ZYNQMPBIF) {
  519 + /* Image file is meta, walk through actual targets */
  520 + int ret;
  521 +
  522 + ret = zynqmpbif_copy_image(ifd, &params);
  523 + if (ret)
  524 + return ret;
518 525 } else {
519 526 copy_file(ifd, params.datafile, pad_len);
520 527 }
Changes suppressed. Click to show
  1 +/*
  2 + * Copyright (C) 2018 Alexander Graf <agraf@suse.de>
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include "imagetool.h"
  8 +#include "mkimage.h"
  9 +#include "zynqmpimage.h"
  10 +#include <elf.h>
  11 +#include <image.h>
  12 +
  13 +struct bif_entry {
  14 + const char *filename;
  15 + uint64_t flags;
  16 + uint64_t dest_cpu;
  17 + uint64_t exp_lvl;
  18 + uint64_t dest_dev;
  19 + uint64_t load;
  20 + uint64_t entry;
  21 + size_t offset;
  22 +};
  23 +
  24 +enum bif_flag {
  25 + BIF_FLAG_AESKEYFILE,
  26 + BIF_FLAG_INIT,
  27 + BIF_FLAG_UDF_BH,
  28 + BIF_FLAG_HEADERSIGNATURE,
  29 + BIF_FLAG_PPKFILE,
  30 + BIF_FLAG_PSKFILE,
  31 + BIF_FLAG_SPKFILE,
  32 + BIF_FLAG_SSKFILE,
  33 + BIF_FLAG_SPKSIGNATURE,
  34 + BIF_FLAG_FSBL_CONFIG,
  35 + BIF_FLAG_AUTH_PARAMS,
  36 + BIF_FLAG_KEYSRC_ENCRYPTION,
  37 + BIF_FLAG_PMUFW_IMAGE,
  38 + BIF_FLAG_BOOTLOADER,
  39 + BIF_FLAG_TZ,
  40 + BIF_FLAG_BH_KEY_IV,
  41 + BIF_FLAG_BH_KEYFILE,
  42 + BIF_FLAG_PUF_FILE,
  43 + BIF_FLAG_AARCH32,
  44 + BIF_FLAG_PART_OWNER_UBOOT,
  45 +
  46 + /* Internal flags */
  47 + BIF_FLAG_BIT_FILE,
  48 + BIF_FLAG_ELF_FILE,
  49 + BIF_FLAG_BIN_FILE,
  50 +};
  51 +
  52 +struct bif_flags {
  53 + const char name[32];
  54 + uint64_t flag;
  55 + char *(*parse)(char *line, struct bif_entry *bf);
  56 +};
  57 +
  58 +struct bif_file_type {
  59 + const char name[32];
  60 + uint32_t header;
  61 + int (*add)(struct bif_entry *bf);
  62 +};
  63 +
  64 +struct bif_output {
  65 + size_t data_len;
  66 + char *data;
  67 + struct image_header_table *imgheader;
  68 + struct zynqmp_header *header;
  69 + struct partition_header *last_part;
  70 +};
  71 +
  72 +struct bif_output bif_output;
  73 +
  74 +static uint32_t zynqmp_csum(void *start, void *end)
  75 +{
  76 + uint32_t checksum = 0;
  77 + uint32_t *ptr32 = start;
  78 +
  79 + while (ptr32 != end) {
  80 + checksum += le32_to_cpu(*ptr32);
  81 + ptr32++;
  82 + }
  83 +
  84 + return ~checksum;
  85 +}
  86 +
  87 +static int zynqmpbif_check_params(struct image_tool_params *params)
  88 +{
  89 + if (!params)
  90 + return 0;
  91 +
  92 + if (params->addr != 0x0) {
  93 + fprintf(stderr, "Error: Load Address can not be specified.\n");
  94 + return -1;
  95 + }
  96 +
  97 + if (params->eflag) {
  98 + fprintf(stderr, "Error: Entry Point can not be specified.\n");
  99 + return -1;
  100 + }
  101 +
  102 + return !(params->lflag || params->dflag);
  103 +}
  104 +
  105 +static int zynqmpbif_check_image_types(uint8_t type)
  106 +{
  107 + return (type == IH_TYPE_ZYNQMPBIF) ? EXIT_SUCCESS : EXIT_FAILURE;
  108 +}
  109 +
  110 +static char *parse_dest_cpu(char *line, struct bif_entry *bf)
  111 +{
  112 + uint64_t i;
  113 +
  114 + for (i = 0; i < ARRAY_SIZE(dest_cpus); i++) {
  115 + if (!strncmp(line, dest_cpus[i], strlen(dest_cpus[i]))) {
  116 + bf->dest_cpu = i << PART_ATTR_DEST_CPU_SHIFT;
  117 + return line + strlen(dest_cpus[i]);
  118 + }
  119 +
  120 + /* a5x can also be written as a53 */
  121 + if (!strncmp(dest_cpus[i], "a5x", 3)) {
  122 + char a53[] = "a53-X";
  123 +
  124 + a53[4] = dest_cpus[i][4];
  125 + if (!strncmp(line, a53, strlen(a53))) {
  126 + bf->dest_cpu = i << PART_ATTR_DEST_CPU_SHIFT;
  127 + return line + strlen(a53);
  128 + }
  129 + }
  130 + }
  131 +
  132 + return line;
  133 +}
  134 +
  135 +static char *parse_el(char *line, struct bif_entry *bf)
  136 +{
  137 + const char *dest_els[] = { "none", "el-0", "el-1", "el-2", "el-3" };
  138 + int i;
  139 +
  140 + for (i = 0; i < ARRAY_SIZE(dest_els); i++) {
  141 + if (!strncmp(line, dest_els[i], strlen(dest_els[i]))) {
  142 + bf->exp_lvl = i;
  143 + return line + strlen(dest_els[i]);
  144 + }
  145 + }
  146 +
  147 + return line;
  148 +}
  149 +
  150 +static char *parse_load(char *line, struct bif_entry *bf)
  151 +{
  152 + char *endptr;
  153 +
  154 + bf->load = strtoll(line, &endptr, 0);
  155 +
  156 + return endptr;
  157 +}
  158 +
  159 +static char *parse_entry(char *line, struct bif_entry *bf)
  160 +{
  161 + char *endptr;
  162 +
  163 + bf->entry = strtoll(line, &endptr, 0);
  164 +
  165 + return endptr;
  166 +}
  167 +
  168 +static char *parse_offset(char *line, struct bif_entry *bf)
  169 +{
  170 + char *endptr;
  171 +
  172 + bf->offset = strtoll(line, &endptr, 0);
  173 +
  174 + return endptr;
  175 +}
  176 +
  177 +static char *parse_partition_owner(char *line, struct bif_entry *bf)
  178 +{
  179 + char *endptr = NULL;
  180 +
  181 + if (!strncmp(line, "fsbl", 4)) {
  182 + endptr = line + 4;
  183 + } else if (!strncmp(line, "uboot", 5)) {
  184 + bf->flags |= 1ULL << BIF_FLAG_PART_OWNER_UBOOT;
  185 + endptr = line + 5;
  186 + } else {
  187 + printf("ERROR: Unknown partition type '%s'\n", line);
  188 + }
  189 +
  190 + return endptr;
  191 +}
  192 +
  193 +static const struct bif_flags bif_flags[] = {
  194 + { "fsbl_config", BIF_FLAG_FSBL_CONFIG },
  195 + { "trustzone", BIF_FLAG_TZ },
  196 + { "pmufw_image", BIF_FLAG_PMUFW_IMAGE },
  197 + { "bootloader", BIF_FLAG_BOOTLOADER },
  198 + { "destination_cpu=", 0, parse_dest_cpu },
  199 + { "exception_level=", 0, parse_el },
  200 + { "load=", 0, parse_load },
  201 + { "startup=", 0, parse_entry },
  202 + { "offset=", 0, parse_offset },
  203 + { "partition_owner=", 0, parse_partition_owner },
  204 +};
  205 +
  206 +static char *read_full_file(const char *filename, size_t *size)
  207 +{
  208 + char *buf, *bufp;
  209 + struct stat sbuf;
  210 + int len = 0, r, fd;
  211 +
  212 + fd = open(filename, O_RDONLY);
  213 + if (fd < 0)
  214 + return NULL;
  215 +
  216 + if (fstat(fd, &sbuf) < 0)
  217 + return NULL;
  218 +
  219 + if (size)
  220 + *size = sbuf.st_size;
  221 +
  222 + buf = malloc(sbuf.st_size);
  223 + if (!buf)
  224 + return NULL;
  225 +
  226 + bufp = buf;
  227 + while (len < sbuf.st_size) {
  228 + r = read(fd, bufp, sbuf.st_size - len);
  229 + if (r < 0)
  230 + return NULL;
  231 + len += r;
  232 + bufp += r;
  233 + }
  234 +
  235 + close(fd);
  236 +
  237 + return buf;
  238 +}
  239 +
  240 +static int bif_add_blob(const void *data, size_t len, size_t *offset)
  241 +{
  242 + size_t new_size;
  243 + uintptr_t header_off;
  244 + uintptr_t last_part_off;
  245 + uintptr_t imgheader_off;
  246 + uintptr_t old_data = (uintptr_t)bif_output.data;
  247 + void *new_data;
  248 +
  249 + header_off = (uintptr_t)bif_output.header - old_data;
  250 + last_part_off = (uintptr_t)bif_output.last_part - old_data;
  251 + imgheader_off = (uintptr_t)bif_output.imgheader - old_data;
  252 +
  253 + if (offset && *offset) {
  254 + /* Pad to a given offset */
  255 + if (bif_output.data_len > *offset) {
  256 + printf("Can not pad to offset %zx\n", *offset);
  257 + return -1;
  258 + }
  259 +
  260 + bif_output.data_len = *offset;
  261 + }
  262 +
  263 + new_size = ROUND(bif_output.data_len + len, 64);
  264 + new_data = realloc(bif_output.data, new_size);
  265 + memcpy(new_data + bif_output.data_len, data, len);
  266 + if (offset)
  267 + *offset = bif_output.data_len;
  268 + bif_output.data = new_data;
  269 + bif_output.data_len = new_size;
  270 +
  271 + /* Readjust internal pointers */
  272 + if (bif_output.header)
  273 + bif_output.header = new_data + header_off;
  274 + if (bif_output.last_part)
  275 + bif_output.last_part = new_data + last_part_off;
  276 + if (bif_output.imgheader)
  277 + bif_output.imgheader = new_data + imgheader_off;
  278 +
  279 + return 0;
  280 +}
  281 +
  282 +static int bif_init(void)
  283 +{
  284 + struct zynqmp_header header = { { 0 } };
  285 + int r;
  286 +
  287 + zynqmpimage_default_header(&header);
  288 +
  289 + r = bif_add_blob(&header, sizeof(header), NULL);
  290 + if (r)
  291 + return r;
  292 +
  293 + bif_output.header = (void *)bif_output.data;
  294 +
  295 + return 0;
  296 +}
  297 +
  298 +static int bif_add_pmufw(struct bif_entry *bf, const char *data, size_t len)
  299 +{
  300 + int r;
  301 +
  302 + if (bif_output.header->image_offset) {
  303 + printf("PMUFW expected before bootloader in your .bif file!\n");
  304 + return -1;
  305 + }
  306 +
  307 + r = bif_add_blob(data, len, &bf->offset);
  308 + if (r)
  309 + return r;
  310 +
  311 + len = ROUND(len, 64);
  312 + bif_output.header->pfw_image_length = cpu_to_le32(len);
  313 + bif_output.header->total_pfw_image_length = cpu_to_le32(len);
  314 + bif_output.header->image_offset = cpu_to_le32(bf->offset);
  315 +
  316 + return 0;
  317 +}
  318 +
  319 +static int bif_add_part(struct bif_entry *bf, const char *data, size_t len)
  320 +{
  321 + size_t parthdr_offset = 0;
  322 + struct partition_header parthdr = {
  323 + .len_enc = cpu_to_le32(len / 4),
  324 + .len_unenc = cpu_to_le32(len / 4),
  325 + .len = cpu_to_le32(len / 4),
  326 + .entry_point = cpu_to_le64(bf->entry),
  327 + .load_address = cpu_to_le64(bf->load),
  328 + };
  329 + int r;
  330 + uint32_t csum;
  331 +
  332 + if (bf->flags & (1ULL << BIF_FLAG_PMUFW_IMAGE))
  333 + return bif_add_pmufw(bf, data, len);
  334 +
  335 + r = bif_add_blob(data, len, &bf->offset);
  336 + if (r)
  337 + return r;
  338 +
  339 + parthdr.offset = cpu_to_le32(bf->offset / 4);
  340 +
  341 + if (bf->flags & (1ULL << BIF_FLAG_BOOTLOADER)) {
  342 + if (bif_output.last_part) {
  343 + printf("ERROR: Bootloader expected before others\n");
  344 + return -1;
  345 + }
  346 +
  347 + parthdr.offset = cpu_to_le32(bif_output.header->image_offset);
  348 + parthdr.len = cpu_to_le32((bf->offset + len -
  349 + bif_output.header->image_offset) / 4);
  350 + parthdr.len_enc = parthdr.len;
  351 + parthdr.len_unenc = parthdr.len;
  352 + }
  353 +
  354 + /* Normalize EL */
  355 + bf->exp_lvl = bf->exp_lvl ? bf->exp_lvl - 1 : 3;
  356 + parthdr.attributes |= bf->exp_lvl << PART_ATTR_TARGET_EL_SHIFT;
  357 + parthdr.attributes |= bf->dest_dev;
  358 + parthdr.attributes |= bf->dest_cpu;
  359 + if (bf->flags & (1ULL << BIF_FLAG_TZ))
  360 + parthdr.attributes |= PART_ATTR_TZ_SECURE;
  361 + if (bf->flags & (1ULL << BIF_FLAG_PART_OWNER_UBOOT))
  362 + parthdr.attributes |= PART_ATTR_PART_OWNER_UBOOT;
  363 + switch (bf->dest_cpu) {
  364 + case PART_ATTR_DEST_CPU_NONE:
  365 + case PART_ATTR_DEST_CPU_A53_0:
  366 + case PART_ATTR_DEST_CPU_A53_1:
  367 + case PART_ATTR_DEST_CPU_A53_2:
  368 + case PART_ATTR_DEST_CPU_A53_3:
  369 + if (bf->flags & (1ULL << BIF_FLAG_AARCH32))
  370 + parthdr.attributes |= PART_ATTR_A53_EXEC_AARCH32;
  371 + }
  372 +
  373 + csum = zynqmp_csum(&parthdr, &parthdr.checksum);
  374 + parthdr.checksum = cpu_to_le32(csum);
  375 +
  376 + r = bif_add_blob(&parthdr, sizeof(parthdr), &parthdr_offset);
  377 + if (r)
  378 + return r;
  379 +
  380 + /* Add image header table if not there yet */
  381 + if (!bif_output.imgheader) {
  382 + size_t imghdr_off = 0;
  383 + struct image_header_table imghdr = {
  384 + .version = cpu_to_le32(0x01020000),
  385 + .nr_parts = 0,
  386 + };
  387 +
  388 + r = bif_add_blob(&imghdr, sizeof(imghdr), &imghdr_off);
  389 + if (r)
  390 + return r;
  391 +
  392 + bif_output.header->image_header_table_offset = imghdr_off;
  393 + bif_output.imgheader = (void *)(bif_output.data + imghdr_off);
  394 + }
  395 +
  396 + bif_output.imgheader->nr_parts = cpu_to_le32(le32_to_cpu(
  397 + bif_output.imgheader->nr_parts) + 1);
  398 +
  399 + /* Link to this partition header */
  400 + if (bif_output.last_part) {
  401 + bif_output.last_part->next_partition_offset =
  402 + cpu_to_le32(parthdr_offset / 4);
  403 +
  404 + /* Recalc checksum of last_part */
  405 + csum = zynqmp_csum(bif_output.last_part,
  406 + &bif_output.last_part->checksum);
  407 + bif_output.last_part->checksum = cpu_to_le32(csum);
  408 + } else {
  409 + bif_output.imgheader->partition_header_offset =
  410 + cpu_to_le32(parthdr_offset / 4);
  411 + }
  412 + bif_output.last_part = (void *)(bif_output.data + parthdr_offset);
  413 +
  414 + if (bf->flags & (1ULL << BIF_FLAG_BOOTLOADER)) {
  415 + bif_output.header->image_load = cpu_to_le32(bf->load);
  416 + if (!bif_output.header->image_offset)
  417 + bif_output.header->image_offset =
  418 + cpu_to_le32(bf->offset);
  419 + bif_output.header->image_size = cpu_to_le32(len);
  420 + bif_output.header->image_stored_size = cpu_to_le32(len);
  421 +
  422 + bif_output.header->image_attributes &= ~HEADER_CPU_SELECT_MASK;
  423 + switch (bf->dest_cpu) {
  424 + default:
  425 + case PART_ATTR_DEST_CPU_A53_0:
  426 + if (bf->flags & BIF_FLAG_AARCH32)
  427 + bif_output.header->image_attributes |=
  428 + HEADER_CPU_SELECT_A53_32BIT;
  429 + else
  430 + bif_output.header->image_attributes |=
  431 + HEADER_CPU_SELECT_A53_64BIT;
  432 + break;
  433 + case PART_ATTR_DEST_CPU_R5_0:
  434 + bif_output.header->image_attributes |=
  435 + HEADER_CPU_SELECT_R5_SINGLE;
  436 + break;
  437 + case PART_ATTR_DEST_CPU_R5_L:
  438 + bif_output.header->image_attributes |=
  439 + HEADER_CPU_SELECT_R5_DUAL;
  440 + break;
  441 + }
  442 + }
  443 +
  444 + return 0;
  445 +}
  446 +
  447 +/* Add .bit bitstream */
  448 +static int bif_add_bit(struct bif_entry *bf)
  449 +{
  450 + char *bit = read_full_file(bf->filename, NULL);
  451 + char *bitbin;
  452 + uint8_t initial_header[] = { 0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f,
  453 + 0xf0, 0x0f, 0xf0, 0x00, 0x00, 0x01, 0x61 };
  454 + uint16_t len;
  455 + uint32_t bitlen;
  456 + int i;
  457 +
  458 + if (!bit)
  459 + return -1;
  460 +
  461 + /* Skip initial header */
  462 + if (memcmp(bit, initial_header, sizeof(initial_header)))
  463 + return -1;
  464 +
  465 + bit += sizeof(initial_header);
  466 +
  467 + /* Design name */
  468 + len = be16_to_cpu(*(uint16_t *)bit);
  469 + bit += sizeof(uint16_t);
  470 + debug("Design: %s\n", bit);
  471 + bit += len;
  472 +
  473 + /* Device identifier */
  474 + if (*bit != 'b')
  475 + return -1;
  476 + bit++;
  477 + len = be16_to_cpu(*(uint16_t *)bit);
  478 + bit += sizeof(uint16_t);
  479 + debug("Device: %s\n", bit);
  480 + bit += len;
  481 +
  482 + /* Date */
  483 + if (*bit != 'c')
  484 + return -1;
  485 + bit++;
  486 + len = be16_to_cpu(*(uint16_t *)bit);
  487 + bit += sizeof(uint16_t);
  488 + debug("Date: %s\n", bit);
  489 + bit += len;
  490 +
  491 + /* Time */
  492 + if (*bit != 'd')
  493 + return -1;
  494 + bit++;
  495 + len = be16_to_cpu(*(uint16_t *)bit);
  496 + bit += sizeof(uint16_t);
  497 + debug("Time: %s\n", bit);
  498 + bit += len;
  499 +
  500 + /* Bitstream length */
  501 + if (*bit != 'e')
  502 + return -1;
  503 + bit++;
  504 + bitlen = be32_to_cpu(*(uint32_t *)bit);
  505 + bit += sizeof(uint32_t);
  506 + bitbin = bit;
  507 +
  508 + debug("Bitstream Length: 0x%x\n", bitlen);
  509 + for (i = 0; i < bitlen; i += sizeof(uint32_t)) {
  510 + uint32_t *bitbin32 = (uint32_t *)&bitbin[i];
  511 + *bitbin32 = __swab32(*bitbin32);
  512 + }
  513 +
  514 + if (!bf->dest_dev)
  515 + bf->dest_dev = PART_ATTR_DEST_DEVICE_PL;
  516 +
  517 + bf->load = 0xffffffff;
  518 + bf->entry = 0;
  519 +
  520 + bf->flags |= 1ULL << BIF_FLAG_BIT_FILE;
  521 + return bif_add_part(bf, bit, bitlen);
  522 +}
  523 +
  524 +/* Add .bin bitstream */
  525 +static int bif_add_bin(struct bif_entry *bf)
  526 +{
  527 + size_t size;
  528 + char *bin = read_full_file(bf->filename, &size);
  529 +
  530 + if (!bf->dest_dev)
  531 + bf->dest_dev = PART_ATTR_DEST_DEVICE_PS;
  532 +
  533 + bf->flags |= 1ULL << BIF_FLAG_BIN_FILE;
  534 + return bif_add_part(bf, bin, size);
  535 +}
  536 +
  537 +/* Add elf file */
  538 +static char *elf2flat64(char *elf, size_t *flat_size, size_t *load_addr)
  539 +{
  540 + Elf64_Ehdr *ehdr;
  541 + Elf64_Shdr *shdr;
  542 + size_t min_addr = -1, max_addr = 0;
  543 + char *flat;
  544 + int i;
  545 +
  546 + ehdr = (void *)elf;
  547 + shdr = (void *)(elf + le64_to_cpu(ehdr->e_shoff));
  548 +
  549 + /* Look for smallest / biggest address */
  550 + for (i = 0; i < le64_to_cpu(ehdr->e_shnum); i++, shdr++) {
  551 + if (!shdr->sh_size || !shdr->sh_addr ||
  552 + !(shdr->sh_flags & SHF_ALLOC) ||
  553 + (shdr->sh_type == SHT_NOBITS))
  554 + continue;
  555 +
  556 + if (le64_to_cpu(shdr->sh_addr) < min_addr)
  557 + min_addr = le64_to_cpu(shdr->sh_addr);
  558 + if ((le64_to_cpu(shdr->sh_addr) + le64_to_cpu(shdr->sh_size)) >
  559 + max_addr)
  560 + max_addr = le64_to_cpu(shdr->sh_addr) +
  561 + le64_to_cpu(shdr->sh_size);
  562 + }
  563 +
  564 + *load_addr = min_addr;
  565 + *flat_size = max_addr - min_addr;
  566 + flat = calloc(1, *flat_size);
  567 + if (!flat)
  568 + return NULL;
  569 +
  570 + shdr = (void *)(elf + le64_to_cpu(ehdr->e_shoff));
  571 + for (i = 0; i < le64_to_cpu(ehdr->e_shnum); i++, shdr++) {
  572 + char *dst = flat + le64_to_cpu(shdr->sh_addr) - min_addr;
  573 + char *src = elf + le64_to_cpu(shdr->sh_offset);
  574 +
  575 + if (!shdr->sh_size || !shdr->sh_addr ||
  576 + !(shdr->sh_flags & SHF_ALLOC))
  577 + continue;
  578 +
  579 + if (shdr->sh_type != SHT_NOBITS)
  580 + memcpy(dst, src, le64_to_cpu(shdr->sh_size));
  581 + }
  582 +
  583 + return flat;
  584 +}
  585 +
  586 +static char *elf2flat32(char *elf, size_t *flat_size, size_t *load_addr)
  587 +{
  588 + Elf32_Ehdr *ehdr;
  589 + Elf32_Shdr *shdr;
  590 + size_t min_addr = -1, max_addr = 0;
  591 + char *flat;
  592 + int i;
  593 +
  594 + ehdr = (void *)elf;
  595 + shdr = (void *)(elf + le32_to_cpu(ehdr->e_shoff));
  596 +
  597 + /* Look for smallest / biggest address */
  598 + for (i = 0; i < le32_to_cpu(ehdr->e_shnum); i++, shdr++) {
  599 + if (!shdr->sh_size || !shdr->sh_addr ||
  600 + !(shdr->sh_flags & SHF_ALLOC) ||
  601 + (shdr->sh_type == SHT_NOBITS))
  602 + continue;
  603 +
  604 + if (le32_to_cpu(shdr->sh_addr) < min_addr)
  605 + min_addr = le32_to_cpu(shdr->sh_addr);
  606 + if ((le32_to_cpu(shdr->sh_addr) + le32_to_cpu(shdr->sh_size)) >
  607 + max_addr)
  608 + max_addr = le32_to_cpu(shdr->sh_addr) +
  609 + le32_to_cpu(shdr->sh_size);
  610 + }
  611 +
  612 + *load_addr = min_addr;
  613 + *flat_size = max_addr - min_addr;
  614 + flat = calloc(1, *flat_size);
  615 + if (!flat)
  616 + return NULL;
  617 +
  618 + shdr = (void *)(elf + le32_to_cpu(ehdr->e_shoff));
  619 + for (i = 0; i < le32_to_cpu(ehdr->e_shnum); i++, shdr++) {
  620 + char *dst = flat + le32_to_cpu(shdr->sh_addr) - min_addr;
  621 + char *src = elf + le32_to_cpu(shdr->sh_offset);
  622 +
  623 + if (!shdr->sh_size || !shdr->sh_addr ||
  624 + !(shdr->sh_flags & SHF_ALLOC))
  625 + continue;
  626 +
  627 + if (shdr->sh_type != SHT_NOBITS)
  628 + memcpy(dst, src, le32_to_cpu(shdr->sh_size));
  629 + }
  630 +
  631 + return flat;
  632 +}
  633 +
  634 +static int bif_add_elf(struct bif_entry *bf)
  635 +{
  636 + size_t size;
  637 + size_t elf_size;
  638 + char *elf;
  639 + char *flat;
  640 + size_t load_addr;
  641 + Elf32_Ehdr *ehdr32;
  642 + Elf64_Ehdr *ehdr64;
  643 +
  644 + elf = read_full_file(bf->filename, &elf_size);
  645 + if (!elf)
  646 + return -1;
  647 +
  648 + ehdr32 = (void *)elf;
  649 + ehdr64 = (void *)elf;
  650 +
  651 + switch (ehdr32->e_ident[EI_CLASS]) {
  652 + case ELFCLASS32:
  653 + flat = elf2flat32(elf, &size, &load_addr);
  654 + bf->entry = le32_to_cpu(ehdr32->e_entry);
  655 + bf->flags |= 1ULL << BIF_FLAG_AARCH32;
  656 + break;
  657 + case ELFCLASS64:
  658 + flat = elf2flat64(elf, &size, &load_addr);
  659 + bf->entry = le64_to_cpu(ehdr64->e_entry);
  660 + break;
  661 + default:
  662 + printf("Unknown ELF class: %d\n", ehdr32->e_ident[EI_CLASS]);
  663 + return -1;
  664 + }
  665 +
  666 + if (!flat)
  667 + return -1;
  668 +
  669 + bf->load = load_addr;
  670 + if (!bf->dest_dev)
  671 + bf->dest_dev = PART_ATTR_DEST_DEVICE_PS;
  672 +
  673 + bf->flags |= 1ULL << BIF_FLAG_ELF_FILE;
  674 + return bif_add_part(bf, flat, size);
  675 +}
  676 +
  677 +static const struct bif_file_type bif_file_types[] = {
  678 + {
  679 + .name = "bitstream (.bit)",
  680 + .header = 0x00090ff0,
  681 + .add = bif_add_bit,
  682 + },
  683 +
  684 + {
  685 + .name = "ELF",
  686 + .header = 0x7f454c46,
  687 + .add = bif_add_elf,
  688 + },
  689 +
  690 + /* Anything else is a .bin file */
  691 + {
  692 + .name = ".bin",
  693 + .add = bif_add_bin,
  694 + },
  695 +};
  696 +
  697 +static int bif_fsbl_config(struct bif_entry *fsbl_config,
  698 + struct bif_entry *entries, int nr_entries)
  699 +{
  700 + int i;
  701 + int config_set = 0;
  702 + struct {
  703 + const char *name;
  704 + uint64_t flags;
  705 + uint64_t dest_cpu;
  706 + } configs[] = {
  707 + { .name = "a5x_x64", .dest_cpu = PART_ATTR_DEST_CPU_A53_0 },
  708 + { .name = "a53_x64", .dest_cpu = PART_ATTR_DEST_CPU_A53_0 },
  709 + { .name = "a5x_x32", .dest_cpu = PART_ATTR_DEST_CPU_A53_0,
  710 + .flags = 1ULL << BIF_FLAG_AARCH32 },
  711 + { .name = "a53_x32", .dest_cpu = PART_ATTR_DEST_CPU_A53_0,
  712 + .flags = 1ULL << BIF_FLAG_AARCH32 },
  713 + { .name = "r5_single", .dest_cpu = PART_ATTR_DEST_CPU_R5_0 },
  714 + { .name = "r5_dual", .dest_cpu = PART_ATTR_DEST_CPU_R5_L },
  715 + };
  716 +
  717 + /* Set target CPU of bootloader entry */
  718 + for (i = 0; i < nr_entries; i++) {
  719 + struct bif_entry *b = &entries[i];
  720 + const char *config_attr = fsbl_config->filename;
  721 + int j;
  722 +
  723 + if (!(b->flags & (1ULL << BIF_FLAG_BOOTLOADER)))
  724 + continue;
  725 +
  726 + for (j = 0; j < ARRAY_SIZE(configs); j++) {
  727 + if (!strncmp(config_attr, configs[j].name,
  728 + strlen(configs[j].name))) {
  729 + b->dest_cpu = configs[j].dest_cpu;
  730 + b->flags |= configs[j].flags;
  731 + config_set = 1;
  732 + }
  733 + }
  734 +
  735 + if (!config_set) {
  736 + printf("ERROR: Unsupported fsbl_config: %s\n",
  737 + config_attr);
  738 + return -1;
  739 + }
  740 + }
  741 +
  742 + if (!config_set) {
  743 + printf("ERROR: fsbl_config w/o bootloader\n");
  744 + return -1;
  745 + }
  746 +
  747 + return 0;
  748 +}
  749 +
  750 +static const struct bif_flags *find_flag(char *str)
  751 +{
  752 + const struct bif_flags *bf;
  753 + int i;
  754 +
  755 + for (i = 0; i < ARRAY_SIZE(bif_flags); i++) {
  756 + bf = &bif_flags[i];
  757 + if (!strncmp(bf->name, str, strlen(bf->name)))
  758 + return bf;
  759 + }
  760 +
  761 + printf("ERROR: Flag '%s' not found\n", str);
  762 +
  763 + return NULL;
  764 +}
  765 +
  766 +static int bif_open_file(struct bif_entry *entry)
  767 +{
  768 + int fd = open(entry->filename, O_RDONLY);
  769 +
  770 + if (fd < 0)
  771 + printf("Error opening file %s\n", entry->filename);
  772 +
  773 + return fd;
  774 +}
  775 +
  776 +static const struct bif_file_type *get_file_type(struct bif_entry *entry)
  777 +{
  778 + int fd = bif_open_file(entry);
  779 + uint32_t header;
  780 + int i;
  781 +
  782 + if (fd < 0)
  783 + return NULL;
  784 +
  785 + if (read(fd, &header, sizeof(header)) != sizeof(header)) {
  786 + printf("Error reading file %s", entry->filename);
  787 + return NULL;
  788 + }
  789 +
  790 + close(fd);
  791 +
  792 + for (i = 0; i < ARRAY_SIZE(bif_file_types); i++) {
  793 + const struct bif_file_type *type = &bif_file_types[i];
  794 +
  795 + if (!type->header)
  796 + return type;
  797 + if (type->header == be32_to_cpu(header))
  798 + return type;
  799 + }
  800 +
  801 + return NULL;
  802 +}
  803 +
  804 +#define NEXT_CHAR(str, chr) ({ \
  805 + char *_n = strchr(str, chr); \
  806 + if (!_n) \
  807 + goto err; \
  808 + _n; \
  809 +})
  810 +
  811 +static char *skip_whitespace(char *str)
  812 +{
  813 + while (*str == ' ' || *str == '\t')
  814 + str++;
  815 +
  816 + return str;
  817 +}
  818 +
  819 +int zynqmpbif_copy_image(int outfd, struct image_tool_params *mparams)
  820 +{
  821 + char *bif, *bifp, *bifpn;
  822 + char *line;
  823 + struct bif_entry entries[32] = { { 0 } };
  824 + int nr_entries = 0;
  825 + struct bif_entry *entry = entries;
  826 + size_t len;
  827 + int i;
  828 + uint32_t csum;
  829 + int bldr = -1;
  830 +
  831 + bif_init();
  832 +
  833 + /* Read .bif input file */
  834 + bif = read_full_file(mparams->datafile, NULL);
  835 + if (!bif)
  836 + goto err;
  837 +
  838 + /* Interpret .bif file */
  839 + bifp = bif;
  840 +
  841 + /* A bif description starts with a { section */
  842 + bifp = NEXT_CHAR(bifp, '{') + 1;
  843 +
  844 + /* Read every line */
  845 + while (1) {
  846 + bifpn = NEXT_CHAR(bifp, '\n');
  847 +
  848 + if (bifpn[-1] == '\r')
  849 + bifpn[-1] = '\0';
  850 +
  851 + *bifpn = '\0';
  852 + bifpn++;
  853 + line = bifp;
  854 +
  855 + line = skip_whitespace(line);
  856 +
  857 + /* Attributes? */
  858 + if (*line == '[') {
  859 + line++;
  860 + while (1) {
  861 + const struct bif_flags *bf;
  862 +
  863 + line = skip_whitespace(line);
  864 + bf = find_flag(line);
  865 + if (!bf)
  866 + goto err;
  867 +
  868 + line += strlen(bf->name);
  869 + if (bf->parse)
  870 + line = bf->parse(line, entry);
  871 + else
  872 + entry->flags |= 1ULL << bf->flag;
  873 +
  874 + if (!line)
  875 + goto err;
  876 +
  877 + /* Go to next attribute or quit */
  878 + if (*line == ']') {
  879 + line++;
  880 + break;
  881 + }
  882 + if (*line == ',')
  883 + line++;
  884 + }
  885 + }
  886 +
  887 + /* End of image description */
  888 + if (*line == '}')
  889 + break;
  890 +
  891 + if (*line) {
  892 + line = skip_whitespace(line);
  893 + entry->filename = line;
  894 + nr_entries++;
  895 + entry++;
  896 + }
  897 +
  898 + /* Use next line */
  899 + bifp = bifpn;
  900 + }
  901 +
  902 + for (i = 0; i < nr_entries; i++) {
  903 + debug("Entry flags=%#lx name=%s\n", entries[i].flags,
  904 + entries[i].filename);
  905 + }
  906 +
  907 + /*
  908 + * Some entries are actually configuration option for other ones,
  909 + * let's apply them in an intermediate step.
  910 + */
  911 + for (i = 0; i < nr_entries; i++) {
  912 + struct bif_entry *entry = &entries[i];
  913 +
  914 + if (entry->flags & (1ULL << BIF_FLAG_FSBL_CONFIG))
  915 + if (bif_fsbl_config(entry, entries, nr_entries))
  916 + goto err;
  917 + }
  918 +
  919 + /* Make sure PMUFW comes before bootloader */
  920 + for (i = 0; i < nr_entries; i++) {
  921 + struct bif_entry *entry = &entries[i];
  922 +
  923 + if (entry->flags & (1ULL << BIF_FLAG_BOOTLOADER))
  924 + bldr = i;
  925 + if (entry->flags & (1ULL << BIF_FLAG_PMUFW_IMAGE)) {
  926 + if (bldr >= 0) {
  927 + struct bif_entry tmp = *entry;
  928 +
  929 + *entry = entries[bldr];
  930 + entries[bldr] = tmp;
  931 + }
  932 + }
  933 + }
  934 +
  935 + for (i = 0; i < nr_entries; i++) {
  936 + struct bif_entry *entry = &entries[i];
  937 + const struct bif_file_type *type;
  938 + int r;
  939 +
  940 + if (entry->flags & (1ULL << BIF_FLAG_FSBL_CONFIG))
  941 + continue;
  942 +
  943 + type = get_file_type(entry);
  944 + if (!type)
  945 + goto err;
  946 +
  947 + debug("type=%s file=%s\n", type->name, entry->filename);
  948 + r = type->add(entry);
  949 + if (r)
  950 + goto err;
  951 + }
  952 +
  953 + /* Calculate checksums */
  954 + csum = zynqmp_csum(&bif_output.header->width_detection,
  955 + &bif_output.header->checksum);
  956 + bif_output.header->checksum = cpu_to_le32(csum);
  957 +
  958 + if (bif_output.imgheader) {
  959 + csum = zynqmp_csum(bif_output.imgheader,
  960 + &bif_output.imgheader->checksum);
  961 + bif_output.imgheader->checksum = cpu_to_le32(csum);
  962 + }
  963 +
  964 + /* Write headers and components */
  965 + if (lseek(outfd, 0, SEEK_SET) != 0)
  966 + goto err;
  967 +
  968 + len = bif_output.data_len;
  969 + bifp = bif_output.data;
  970 + while (len) {
  971 + int r;
  972 +
  973 + r = write(outfd, bifp, len);
  974 + if (r < 0)
  975 + goto err;
  976 + len -= r;
  977 + bifp += r;
  978 + }
  979 +
  980 + return 0;
  981 +
  982 +err:
  983 + fprintf(stderr, "Error: Failed to create image.\n");
  984 + return -1;
  985 +}
  986 +
  987 +/* Needs to be stubbed out so we can print after creation */
  988 +static void zynqmpbif_set_header(void *ptr, struct stat *sbuf, int ifd,
  989 + struct image_tool_params *params)
  990 +{
  991 +}
  992 +
  993 +static struct zynqmp_header zynqmpimage_header;
  994 +
  995 +U_BOOT_IMAGE_TYPE(
  996 + zynqmpbif,
  997 + "Xilinx ZynqMP Boot Image support (bif)",
  998 + sizeof(struct zynqmp_header),
  999 + (void *)&zynqmpimage_header,
  1000 + zynqmpbif_check_params,
  1001 + NULL,
  1002 + zynqmpimage_print_header,
  1003 + zynqmpbif_set_header,
  1004 + NULL,
  1005 + zynqmpbif_check_image_types,
  1006 + NULL,
  1007 + NULL
  1008 +);
... ... @@ -6,6 +6,7 @@
6 6 * The following Boot Header format/structures and values are defined in the
7 7 * following documents:
8 8 * * ug1085 ZynqMP TRM doc v1.4 (Chapter 11, Table 11-4)
  9 + * * ug1137 ZynqMP Software Developer Guide v6.0 (Chapter 16)
9 10 *
10 11 * Expected Header Size = 0x9C0
11 12 * Forced as 'little' endian, 32-bit words
12 13  
... ... @@ -56,47 +57,9 @@
56 57  
57 58 #include "imagetool.h"
58 59 #include "mkimage.h"
  60 +#include "zynqmpimage.h"
59 61 #include <image.h>
60 62  
61   -#define HEADER_INTERRUPT_DEFAULT (cpu_to_le32(0xeafffffe))
62   -#define HEADER_REGINIT_NULL (cpu_to_le32(0xffffffff))
63   -#define HEADER_WIDTHDETECTION (cpu_to_le32(0xaa995566))
64   -#define HEADER_IMAGEIDENTIFIER (cpu_to_le32(0x584c4e58))
65   -
66   -enum {
67   - ENCRYPTION_EFUSE = 0xa5c3c5a3,
68   - ENCRYPTION_OEFUSE = 0xa5c3c5a7,
69   - ENCRYPTION_BBRAM = 0x3a5c3c5a,
70   - ENCRYPTION_OBBRAM = 0xa35c7ca5,
71   - ENCRYPTION_NONE = 0x0,
72   -};
73   -
74   -struct zynqmp_reginit {
75   - uint32_t address;
76   - uint32_t data;
77   -};
78   -
79   -#define HEADER_INTERRUPT_VECTORS 8
80   -#define HEADER_REGINITS 256
81   -
82   -struct zynqmp_header {
83   - uint32_t interrupt_vectors[HEADER_INTERRUPT_VECTORS]; /* 0x0 */
84   - uint32_t width_detection; /* 0x20 */
85   - uint32_t image_identifier; /* 0x24 */
86   - uint32_t encryption; /* 0x28 */
87   - uint32_t image_load; /* 0x2c */
88   - uint32_t image_offset; /* 0x30 */
89   - uint32_t pfw_image_length; /* 0x34 */
90   - uint32_t total_pfw_image_length; /* 0x38 */
91   - uint32_t image_size; /* 0x3c */
92   - uint32_t image_stored_size; /* 0x40 */
93   - uint32_t image_attributes; /* 0x44 */
94   - uint32_t checksum; /* 0x48 */
95   - uint32_t __reserved1[27]; /* 0x4c */
96   - struct zynqmp_reginit register_init[HEADER_REGINITS]; /* 0xb8 */
97   - uint32_t __reserved4[66]; /* 0x9c0 */
98   -};
99   -
100 63 static struct zynqmp_header zynqmpimage_header;
101 64 static void *dynamic_header;
102 65 static FILE *fpmu;
... ... @@ -123,7 +86,7 @@
123 86 return cpu_to_le32(checksum);
124 87 }
125 88  
126   -static void zynqmpimage_default_header(struct zynqmp_header *ptr)
  89 +void zynqmpimage_default_header(struct zynqmp_header *ptr)
127 90 {
128 91 int i;
129 92  
... ... @@ -131,7 +94,7 @@
131 94 return;
132 95  
133 96 ptr->width_detection = HEADER_WIDTHDETECTION;
134   - ptr->image_attributes = 0x800;
  97 + ptr->image_attributes = HEADER_CPU_SELECT_A53_64BIT;
135 98 ptr->image_identifier = HEADER_IMAGEIDENTIFIER;
136 99 ptr->encryption = cpu_to_le32(ENCRYPTION_NONE);
137 100  
138 101  
... ... @@ -172,8 +135,82 @@
172 135 return 0;
173 136 }
174 137  
175   -static void zynqmpimage_print_header(const void *ptr)
  138 +static void print_partition(const void *ptr, const struct partition_header *ph)
176 139 {
  140 + uint32_t attr = le32_to_cpu(ph->attributes);
  141 + unsigned long len = le32_to_cpu(ph->len) * 4;
  142 + const char *part_owner;
  143 + const char *dest_devs[0x8] = {
  144 + "none", "PS", "PL", "PMU", "unknown", "unknown", "unknown",
  145 + "unknown"
  146 + };
  147 +
  148 + switch (attr & PART_ATTR_PART_OWNER_MASK) {
  149 + case PART_ATTR_PART_OWNER_FSBL:
  150 + part_owner = "FSBL";
  151 + break;
  152 + case PART_ATTR_PART_OWNER_UBOOT:
  153 + part_owner = "U-Boot";
  154 + break;
  155 + default:
  156 + part_owner = "Unknown";
  157 + break;
  158 + }
  159 +
  160 + printf("%s payload on CPU %s (%s):\n", part_owner,
  161 + dest_cpus[(attr & PART_ATTR_DEST_CPU_MASK) >> 8],
  162 + dest_devs[(attr & PART_ATTR_DEST_DEVICE_MASK) >> 4]);
  163 +
  164 + printf(" Offset : 0x%08x\n", le32_to_cpu(ph->offset) * 4);
  165 + printf(" Size : %lu (0x%lx) bytes\n", len, len);
  166 + printf(" Load : 0x%08llx",
  167 + (unsigned long long)le64_to_cpu(ph->load_address));
  168 + if (ph->load_address != ph->entry_point)
  169 + printf(" (entry=0x%08llx)\n",
  170 + (unsigned long long)le64_to_cpu(ph->entry_point));
  171 + else
  172 + printf("\n");
  173 + printf(" Attributes : ");
  174 +
  175 + if (attr & PART_ATTR_VEC_LOCATION)
  176 + printf("vec ");
  177 +
  178 + if (attr & PART_ATTR_ENCRYPTED)
  179 + printf("encrypted ");
  180 +
  181 + switch (attr & PART_ATTR_CHECKSUM_MASK) {
  182 + case PART_ATTR_CHECKSUM_MD5:
  183 + printf("md5 ");
  184 + break;
  185 + case PART_ATTR_CHECKSUM_SHA2:
  186 + printf("sha2 ");
  187 + break;
  188 + case PART_ATTR_CHECKSUM_SHA3:
  189 + printf("sha3 ");
  190 + break;
  191 + }
  192 +
  193 + if (attr & PART_ATTR_BIG_ENDIAN)
  194 + printf("BigEndian ");
  195 +
  196 + if (attr & PART_ATTR_RSA_SIG)
  197 + printf("RSA ");
  198 +
  199 + if (attr & PART_ATTR_A53_EXEC_AARCH32)
  200 + printf("AArch32 ");
  201 +
  202 + if (attr & PART_ATTR_TARGET_EL_MASK)
  203 + printf("EL%d ", (attr & PART_ATTR_TARGET_EL_MASK) >> 1);
  204 +
  205 + if (attr & PART_ATTR_TZ_SECURE)
  206 + printf("secure ");
  207 + printf("\n");
  208 +
  209 + printf(" Checksum : 0x%08x\n", le32_to_cpu(ph->checksum));
  210 +}
  211 +
  212 +void zynqmpimage_print_header(const void *ptr)
  213 +{
177 214 struct zynqmp_header *zynqhdr = (struct zynqmp_header *)ptr;
178 215 int i;
179 216  
... ... @@ -210,6 +247,27 @@
210 247 printf(" @ 0x%08x -> 0x%08x\n",
211 248 le32_to_cpu(zynqhdr->register_init[i].address),
212 249 le32_to_cpu(zynqhdr->register_init[i].data));
  250 + }
  251 +
  252 + if (zynqhdr->image_header_table_offset) {
  253 + struct image_header_table *iht = (void *)ptr +
  254 + zynqhdr->image_header_table_offset;
  255 + struct partition_header *ph;
  256 + uint32_t ph_offset;
  257 + uint32_t next;
  258 + int i;
  259 +
  260 + ph_offset = le32_to_cpu(iht->partition_header_offset) * 4;
  261 + ph = (void *)ptr + ph_offset;
  262 + for (i = 0; i < le32_to_cpu(iht->nr_parts); i++) {
  263 + next = le32_to_cpu(ph->next_partition_offset) * 4;
  264 +
  265 + /* Partition 0 is the base image itself */
  266 + if (i)
  267 + print_partition(ptr, ph);
  268 +
  269 + ph = (void *)ptr + next;
  270 + }
213 271 }
214 272  
215 273 free(dynamic_header);
  1 +/*
  2 + * Copyright (C) 2016 Michal Simek <michals@xilinx.com>
  3 + * Copyright (C) 2015 Nathan Rossi <nathan@nathanrossi.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + *
  7 + * The following Boot Header format/structures and values are defined in the
  8 + * following documents:
  9 + * * ug1085 ZynqMP TRM doc v1.4 (Chapter 11, Table 11-4)
  10 + * * ug1137 ZynqMP Software Developer Guide v6.0 (Chapter 16)
  11 + */
  12 +
  13 +#ifndef _ZYNQMPIMAGE_H_
  14 +#define _ZYNQMPIMAGE_H_
  15 +
  16 +#include <stdint.h>
  17 +
  18 +#define HEADER_INTERRUPT_DEFAULT (cpu_to_le32(0xeafffffe))
  19 +#define HEADER_REGINIT_NULL (cpu_to_le32(0xffffffff))
  20 +#define HEADER_WIDTHDETECTION (cpu_to_le32(0xaa995566))
  21 +#define HEADER_IMAGEIDENTIFIER (cpu_to_le32(0x584c4e58))
  22 +#define HEADER_CPU_SELECT_MASK (0x3 << 10)
  23 +#define HEADER_CPU_SELECT_R5_SINGLE (0x0 << 10)
  24 +#define HEADER_CPU_SELECT_A53_32BIT (0x1 << 10)
  25 +#define HEADER_CPU_SELECT_A53_64BIT (0x2 << 10)
  26 +#define HEADER_CPU_SELECT_R5_DUAL (0x3 << 10)
  27 +
  28 +enum {
  29 + ENCRYPTION_EFUSE = 0xa5c3c5a3,
  30 + ENCRYPTION_OEFUSE = 0xa5c3c5a7,
  31 + ENCRYPTION_BBRAM = 0x3a5c3c5a,
  32 + ENCRYPTION_OBBRAM = 0xa35c7ca5,
  33 + ENCRYPTION_NONE = 0x0,
  34 +};
  35 +
  36 +struct zynqmp_reginit {
  37 + uint32_t address;
  38 + uint32_t data;
  39 +};
  40 +
  41 +#define HEADER_INTERRUPT_VECTORS 8
  42 +#define HEADER_REGINITS 256
  43 +
  44 +struct image_header_table {
  45 + uint32_t version; /* 0x00 */
  46 + uint32_t nr_parts; /* 0x04 */
  47 + uint32_t partition_header_offset; /* 0x08, divided by 4 */
  48 + uint32_t image_header_offset; /* 0x0c, divided by 4 */
  49 + uint32_t auth_certificate_offset; /* 0x10 */
  50 + uint32_t boot_device; /* 0x14 */
  51 + uint32_t __reserved1[9]; /* 0x18 - 0x38 */
  52 + uint32_t checksum; /* 0x3c */
  53 +};
  54 +
  55 +#define PART_ATTR_VEC_LOCATION 0x800000
  56 +#define PART_ATTR_BS_BLOCK_SIZE_MASK 0x700000
  57 +#define PART_ATTR_BS_BLOCK_SIZE_DEFAULT 0x000000
  58 +#define PART_ATTR_BS_BLOCK_SIZE_8MB 0x400000
  59 +#define PART_ATTR_BIG_ENDIAN 0x040000
  60 +#define PART_ATTR_PART_OWNER_MASK 0x030000
  61 +#define PART_ATTR_PART_OWNER_FSBL 0x000000
  62 +#define PART_ATTR_PART_OWNER_UBOOT 0x010000
  63 +#define PART_ATTR_RSA_SIG 0x008000
  64 +#define PART_ATTR_CHECKSUM_MASK 0x007000
  65 +#define PART_ATTR_CHECKSUM_NONE 0x000000
  66 +#define PART_ATTR_CHECKSUM_MD5 0x001000
  67 +#define PART_ATTR_CHECKSUM_SHA2 0x002000
  68 +#define PART_ATTR_CHECKSUM_SHA3 0x003000
  69 +#define PART_ATTR_DEST_CPU_SHIFT 8
  70 +#define PART_ATTR_DEST_CPU_MASK 0x000f00
  71 +#define PART_ATTR_DEST_CPU_NONE 0x000000
  72 +#define PART_ATTR_DEST_CPU_A53_0 0x000100
  73 +#define PART_ATTR_DEST_CPU_A53_1 0x000200
  74 +#define PART_ATTR_DEST_CPU_A53_2 0x000300
  75 +#define PART_ATTR_DEST_CPU_A53_3 0x000400
  76 +#define PART_ATTR_DEST_CPU_R5_0 0x000500
  77 +#define PART_ATTR_DEST_CPU_R5_1 0x000600
  78 +#define PART_ATTR_DEST_CPU_R5_L 0x000700
  79 +#define PART_ATTR_DEST_CPU_PMU 0x000800
  80 +#define PART_ATTR_ENCRYPTED 0x000080
  81 +#define PART_ATTR_DEST_DEVICE_SHIFT 4
  82 +#define PART_ATTR_DEST_DEVICE_MASK 0x000070
  83 +#define PART_ATTR_DEST_DEVICE_NONE 0x000000
  84 +#define PART_ATTR_DEST_DEVICE_PS 0x000010
  85 +#define PART_ATTR_DEST_DEVICE_PL 0x000020
  86 +#define PART_ATTR_DEST_DEVICE_PMU 0x000030
  87 +#define PART_ATTR_DEST_DEVICE_XIP 0x000040
  88 +#define PART_ATTR_A53_EXEC_AARCH32 0x000008
  89 +#define PART_ATTR_TARGET_EL_SHIFT 1
  90 +#define PART_ATTR_TARGET_EL_MASK 0x000006
  91 +#define PART_ATTR_TZ_SECURE 0x000001
  92 +
  93 +static const char *dest_cpus[0x10] = {
  94 + "none", "a5x-0", "a5x-1", "a5x-2", "a5x-3", "r5-0", "r5-1",
  95 + "r5-lockstep", "pmu", "unknown", "unknown", "unknown", "unknown",
  96 + "unknown", "unknown", "unknown"
  97 +};
  98 +
  99 +struct partition_header {
  100 + uint32_t len_enc; /* 0x00, divided by 4 */
  101 + uint32_t len_unenc; /* 0x04, divided by 4 */
  102 + uint32_t len; /* 0x08, divided by 4 */
  103 + uint32_t next_partition_offset; /* 0x0c */
  104 + uint64_t entry_point; /* 0x10 */
  105 + uint64_t load_address; /* 0x18 */
  106 + uint32_t offset; /* 0x20, divided by 4 */
  107 + uint32_t attributes; /* 0x24 */
  108 + uint32_t __reserved1; /* 0x28 */
  109 + uint32_t checksum_offset; /* 0x2c, divided by 4 */
  110 + uint32_t __reserved2; /* 0x30 */
  111 + uint32_t auth_certificate_offset; /* 0x34 */
  112 + uint32_t __reserved3; /* 0x38 */
  113 + uint32_t checksum; /* 0x3c */
  114 +};
  115 +
  116 +struct zynqmp_header {
  117 + uint32_t interrupt_vectors[HEADER_INTERRUPT_VECTORS]; /* 0x0 */
  118 + uint32_t width_detection; /* 0x20 */
  119 + uint32_t image_identifier; /* 0x24 */
  120 + uint32_t encryption; /* 0x28 */
  121 + uint32_t image_load; /* 0x2c */
  122 + uint32_t image_offset; /* 0x30 */
  123 + uint32_t pfw_image_length; /* 0x34 */
  124 + uint32_t total_pfw_image_length; /* 0x38 */
  125 + uint32_t image_size; /* 0x3c */
  126 + uint32_t image_stored_size; /* 0x40 */
  127 + uint32_t image_attributes; /* 0x44 */
  128 + uint32_t checksum; /* 0x48 */
  129 + uint32_t __reserved1[19]; /* 0x4c */
  130 + uint32_t image_header_table_offset; /* 0x98 */
  131 + uint32_t __reserved2[7]; /* 0x9c */
  132 + struct zynqmp_reginit register_init[HEADER_REGINITS]; /* 0xb8 */
  133 + uint32_t __reserved4[66]; /* 0x9c0 */
  134 +};
  135 +
  136 +void zynqmpimage_default_header(struct zynqmp_header *ptr);
  137 +void zynqmpimage_print_header(const void *ptr);
  138 +
  139 +#endif /* _ZYNQMPIMAGE_H_ */