Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit 3b5df50ec02efbef84cff05d279bd734c020996f

Authored by Heiko Schocher
Committed by Tom Rini
1 parent c10ac540ea
Exists in v2017.01-smarct4x and in 30 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

arm, at91: support for sam9260 based smartweb board 

add support for the at91sam9260 based board smartweb from
siemens. SPL is used without serial support, as this
SoC has only 4k sram for running SPL. Here a U-Boot
bootlog:

RomBOOT
>

U-Boot 2015.07-rc2-00109-g4ae828c (Jun 15 2015 - 09:31:16 +0200)

CPU: AT91SAM9260
Crystal frequency:   18.432 MHz
CPU clock        :  198.656 MHz
Master clock     :   99.328 MHz
       Watchdog enabled
DRAM:  64 MiB
WARNING: Caches not enabled
NAND:  256 MiB
In:    serial
Out:   serial
Err:   serial
Net:   macb0
Hit any key to stop autoboot:  0
U-Boot>

Signed-off-by: Heiko Schocher <hs@denx.de>

Showing 9 changed files with 561 additions and 0 deletions Side-by-side Diff

arch/arm/include/asm/mach-types.h
Diff comments   View file @ 3b5df50
... ... @@ -276,6 +276,7 @@
276 276 #define MACH_TYPE_TRIZEPS4WL 1649
277 277 #define MACH_TYPE_TS78XX 1652
278 278 #define MACH_TYPE_SFFSDR 1657
  279 +#define MACH_TYPE_SMARTWEB 1668
279 280 #define MACH_TYPE_PCM037 1673
280 281 #define MACH_TYPE_DB88F6281_BP 1680
281 282 #define MACH_TYPE_RD88F6192_NAS 1681
arch/arm/mach-at91/Kconfig
Diff comments   View file @ 3b5df50
... ... @@ -124,6 +124,11 @@
124 124 select CPU_ARM926EJS
125 125 select SUPPORT_SPL
126 126  
  127 +config TARGET_SMARTWEB
  128 + bool "Support smartweb"
  129 + select CPU_ARM926EJS
  130 + select SUPPORT_SPL
  131 +
127 132 endchoice
128 133  
129 134 config SYS_SOC
... ... @@ -155,6 +160,7 @@
155 160 source "board/ronetix/pm9g45/Kconfig"
156 161 source "board/siemens/corvus/Kconfig"
157 162 source "board/siemens/taurus/Kconfig"
  163 +source "board/siemens/smartweb/Kconfig"
158 164 source "board/taskit/stamp9g20/Kconfig"
159 165  
160 166 endif
arch/arm/mach-at91/Makefile
Diff comments   View file @ 3b5df50
1 1 obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o
2 2 ifneq ($(CONFIG_SPL_BUILD),)
  3 +obj-$(CONFIG_AT91SAM9260) += sdram.o spl_at91.o
3 4 obj-$(CONFIG_AT91SAM9G20) += sdram.o spl_at91.o
4 5 obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o
5 6 obj-$(CONFIG_AT91SAM9N12) += mpddrc.o spl_at91.o
board/siemens/smartweb/Kconfig
Diff comments   View file @ 3b5df50
  1 +if TARGET_SMARTWEB
  2 +
  3 +config SYS_BOARD
  4 + default "smartweb"
  5 +
  6 +config SYS_VENDOR
  7 + default "siemens"
  8 +
  9 +config SYS_CONFIG_NAME
  10 + default "smartweb"
  11 +
  12 +endif
board/siemens/smartweb/MAINTAINERS
Diff comments   View file @ 3b5df50
  1 +SMARTWEB_HW BOARD
  2 +M: Heiko Schocher <hs@denx.de>
  3 +S: Maintained
  4 +F: board/siemens/smartweb
  5 +F: include/configs/smartweb.h
  6 +F: configs/smartweb_defconfig
board/siemens/smartweb/Makefile
Diff comments   View file @ 3b5df50
  1 +#
  2 +# (C) Copyright 2003-2008
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +#
  5 +# (C) Copyright 2008
  6 +# Stelian Pop <stelian@popies.net>
  7 +# Lead Tech Design <www.leadtechdesign.com>
  8 +#
  9 +# (C) Copyright 2012
  10 +# Markus Hubig <mhubig@imko.de>
  11 +# IMKO GmbH <www.imko.de>
  12 +#
  13 +# (C) Copyright 2014
  14 +# Heiko Schocher <hs@denx.de>
  15 +# DENX Software Engineering GmbH
  16 +#
  17 +# SPDX-License-Identifier: GPL-2.0+
  18 +#
  19 +
  20 +obj-y += smartweb.o
board/siemens/smartweb/smartweb.c
Diff comments   View file @ 3b5df50
  1 +/*
  2 + * (C) Copyright 2007-2008
  3 + * Stelian Pop <stelian@popies.net>
  4 + * Lead Tech Design <www.leadtechdesign.com>
  5 + *
  6 + * Achim Ehrlich <aehrlich@taskit.de>
  7 + * taskit GmbH <www.taskit.de>
  8 + *
  9 + * (C) Copyright 2012-
  10 + * Markus Hubig <mhubig@imko.de>
  11 + * IMKO GmbH <www.imko.de>
  12 + * (C) Copyright 2014
  13 + * Heiko Schocher <hs@denx.de>
  14 + * DENX Software Engineering GmbH
  15 + *
  16 + * SPDX-License-Identifier: GPL-2.0+
  17 + */
  18 +
  19 +#include <common.h>
  20 +#include <asm/io.h>
  21 +#include <asm/arch/at91sam9_sdramc.h>
  22 +#include <asm/arch/at91sam9260_matrix.h>
  23 +#include <asm/arch/at91sam9_smc.h>
  24 +#include <asm/arch/at91_common.h>
  25 +#include <asm/arch/at91_pmc.h>
  26 +#include <asm/arch/at91_spi.h>
  27 +#include <spi.h>
  28 +#include <asm/arch/gpio.h>
  29 +#include <watchdog.h>
  30 +#ifdef CONFIG_MACB
  31 +# include <net.h>
  32 +# include <netdev.h>
  33 +#endif
  34 +
  35 +DECLARE_GLOBAL_DATA_PTR;
  36 +
  37 +static void smartweb_nand_hw_init(void)
  38 +{
  39 + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  40 + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  41 + unsigned long csa;
  42 +
  43 + /* Assign CS3 to NAND/SmartMedia Interface */
  44 + csa = readl(&matrix->ebicsa);
  45 + csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
  46 + writel(csa, &matrix->ebicsa);
  47 +
  48 + /* Configure SMC CS3 for NAND/SmartMedia */
  49 + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  50 + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  51 + &smc->cs[3].setup);
  52 + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  53 + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  54 + &smc->cs[3].pulse);
  55 + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  56 + &smc->cs[3].cycle);
  57 + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  58 + AT91_SMC_MODE_TDF_CYCLE(2),
  59 + &smc->cs[3].mode);
  60 +
  61 + /* Configure RDY/BSY */
  62 + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  63 +
  64 + /* Enable NandFlash */
  65 + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  66 +}
  67 +
  68 +#ifdef CONFIG_MACB
  69 +static void smartweb_macb_hw_init(void)
  70 +{
  71 + struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
  72 +
  73 + /* Enable the PHY Chip via PA26 on the Stamp 2 Adaptor */
  74 + at91_set_gpio_output(AT91_PIN_PA26, 0);
  75 +
  76 + /*
  77 + * Disable pull-up on:
  78 + * RXDV (PA17) => PHY normal mode (not Test mode)
  79 + * ERX0 (PA14) => PHY ADDR0
  80 + * ERX1 (PA15) => PHY ADDR1
  81 + * ERX2 (PA25) => PHY ADDR2
  82 + * ERX3 (PA26) => PHY ADDR3
  83 + * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0
  84 + *
  85 + * PHY has internal pull-down
  86 + */
  87 + writel(pin_to_mask(AT91_PIN_PA14) |
  88 + pin_to_mask(AT91_PIN_PA15) |
  89 + pin_to_mask(AT91_PIN_PA17) |
  90 + pin_to_mask(AT91_PIN_PA25) |
  91 + pin_to_mask(AT91_PIN_PA26) |
  92 + pin_to_mask(AT91_PIN_PA28),
  93 + &pioa->pudr);
  94 +
  95 + at91_phy_reset();
  96 +
  97 + /* Re-enable pull-up */
  98 + writel(pin_to_mask(AT91_PIN_PA14) |
  99 + pin_to_mask(AT91_PIN_PA15) |
  100 + pin_to_mask(AT91_PIN_PA17) |
  101 + pin_to_mask(AT91_PIN_PA25) |
  102 + pin_to_mask(AT91_PIN_PA26) |
  103 + pin_to_mask(AT91_PIN_PA28),
  104 + &pioa->puer);
  105 +
  106 + /* Initialize EMAC=MACB hardware */
  107 + at91_macb_hw_init();
  108 +}
  109 +#endif /* CONFIG_MACB */
  110 +
  111 +int board_early_init_f(void)
  112 +{
  113 + /* enable this here, as we have SPL without serial support */
  114 + at91_seriald_hw_init();
  115 + return 0;
  116 +}
  117 +
  118 +int board_init(void)
  119 +{
  120 + /* Adress of boot parameters */
  121 + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  122 +
  123 + smartweb_nand_hw_init();
  124 +#ifdef CONFIG_MACB
  125 + smartweb_macb_hw_init();
  126 +#endif
  127 + /* power LED red */
  128 + at91_set_gpio_output(AT91_PIN_PC6, 0);
  129 + at91_set_gpio_output(AT91_PIN_PC7, 1);
  130 + /* alarm LED off */
  131 + at91_set_gpio_output(AT91_PIN_PC8, 0);
  132 + at91_set_gpio_output(AT91_PIN_PC9, 0);
  133 + /* prog LED red */
  134 + at91_set_gpio_output(AT91_PIN_PC10, 0);
  135 + at91_set_gpio_output(AT91_PIN_PC11, 1);
  136 +
  137 + return 0;
  138 +}
  139 +
  140 +int dram_init(void)
  141 +{
  142 + gd->ram_size = get_ram_size(
  143 + (void *)CONFIG_SYS_SDRAM_BASE,
  144 + CONFIG_SYS_SDRAM_SIZE);
  145 + return 0;
  146 +}
  147 +
  148 +#ifdef CONFIG_MACB
  149 +int board_eth_init(bd_t *bis)
  150 +{
  151 + return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
  152 +}
  153 +#endif /* CONFIG_MACB */
  154 +
  155 +#if defined(CONFIG_SPL_BUILD)
  156 +#include <spl.h>
  157 +#include <nand.h>
  158 +#include <spi_flash.h>
  159 +
  160 +void matrix_init(void)
  161 +{
  162 + struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  163 +
  164 + writel((readl(&mat->scfg[3]) & (~AT91_MATRIX_SLOT_CYCLE))
  165 + | AT91_MATRIX_SLOT_CYCLE_(0x40),
  166 + &mat->scfg[3]);
  167 +}
  168 +
  169 +void spl_board_init(void)
  170 +{
  171 + at91_set_gpio_output(AT91_PIN_PC6, 1);
  172 + at91_set_gpio_output(AT91_PIN_PC7, 1);
  173 + /* alarm LED orange */
  174 + at91_set_gpio_output(AT91_PIN_PC8, 1);
  175 + at91_set_gpio_output(AT91_PIN_PC9, 1);
  176 + /* prog LED red */
  177 + at91_set_gpio_output(AT91_PIN_PC10, 0);
  178 + at91_set_gpio_output(AT91_PIN_PC11, 1);
  179 +
  180 + smartweb_nand_hw_init();
  181 + at91_set_gpio_input(AT91_PIN_PA28, 1);
  182 + at91_set_gpio_input(AT91_PIN_PA29, 1);
  183 +
  184 + /* check if both button are pressed */
  185 + if (at91_get_gpio_value(AT91_PIN_PA28) == 0 &&
  186 + at91_get_gpio_value(AT91_PIN_PA29) == 0) {
  187 + debug("Recovery button pressed\n");
  188 + nand_init();
  189 + spl_nand_erase_one(0, 0);
  190 + }
  191 +}
  192 +
  193 +#define SDRAM_BASE_CONF (AT91_SDRAMC_NC_9 | AT91_SDRAMC_NR_13 \
  194 + | AT91_SDRAMC_CAS_2 \
  195 + | AT91_SDRAMC_NB_4 | AT91_SDRAMC_DBW_32 \
  196 + | AT91_SDRAMC_TWR_VAL(2) | AT91_SDRAMC_TRC_VAL(7) \
  197 + | AT91_SDRAMC_TRP_VAL(2) | AT91_SDRAMC_TRCD_VAL(2) \
  198 + | AT91_SDRAMC_TRAS_VAL(5) | AT91_SDRAMC_TXSR_VAL(8))
  199 +
  200 +void mem_init(void)
  201 +{
  202 + struct at91_matrix *ma = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  203 + struct at91_port *port = (struct at91_port *)ATMEL_BASE_PIOC;
  204 + struct sdramc_reg setting;
  205 +
  206 + setting.cr = SDRAM_BASE_CONF;
  207 + setting.mdr = AT91_SDRAMC_MD_SDRAM;
  208 + setting.tr = (CONFIG_SYS_MASTER_CLOCK * 7) / 1000000;
  209 +
  210 + /*
  211 + * I write here directly in this register, because this
  212 + * approach is smaller than calling at91_set_a_periph() in a
  213 + * for loop. This saved me 96 bytes.
  214 + */
  215 + writel(0xffff0000, &port->pdr);
  216 +
  217 + writel(readl(&ma->ebicsa) | AT91_MATRIX_CS1A_SDRAMC, &ma->ebicsa);
  218 + sdramc_initialize(ATMEL_BASE_CS1, &setting);
  219 +}
  220 +#endif
configs/smartweb_defconfig
Diff comments   View file @ 3b5df50
  1 +CONFIG_ARM=y
  2 +CONFIG_ARCH_AT91=y
  3 +CONFIG_TARGET_SMARTWEB=y
  4 +CONFIG_SPL=y
  5 +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260"
  6 +CONFIG_CMD_NET=y
include/configs/smartweb.h
Diff comments   View file @ 3b5df50
  1 +/*
  2 + * (C) Copyright 2007-2008
  3 + * Stelian Pop <stelian@popies.net>
  4 + * Lead Tech Design <www.leadtechdesign.com>
  5 + *
  6 + * (C) Copyright 2010
  7 + * Achim Ehrlich <aehrlich@taskit.de>
  8 + * taskit GmbH <www.taskit.de>
  9 + *
  10 + * (C) Copyright 2012
  11 + * Markus Hubig <mhubig@imko.de>
  12 + * IMKO GmbH <www.imko.de>
  13 + *
  14 + * (C) Copyright 2014
  15 + * Heiko Schocher <hs@denx.de>
  16 + * DENX Software Engineering GmbH
  17 + *
  18 + * Configuation settings for the smartweb.
  19 + *
  20 + * SPDX-License-Identifier: GPL-2.0+
  21 + */
  22 +
  23 +#ifndef __CONFIG_H
  24 +#define __CONFIG_H
  25 +
  26 +/*
  27 + * SoC must be defined first, before hardware.h is included.
  28 + * In this case SoC is defined in boards.cfg.
  29 + */
  30 +#include <asm/hardware.h>
  31 +
  32 +/*
  33 + * Warning: changing CONFIG_SYS_TEXT_BASE requires adapting the initial boot
  34 + * program. Since the linker has to swallow that define, we must use a pure
  35 + * hex number here!
  36 + */
  37 +#define CONFIG_SYS_TEXT_BASE 0x23000000
  38 +
  39 +/* ARM asynchronous clock */
  40 +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
  41 +#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432MHz crystal */
  42 +
  43 +/* misc settings */
  44 +#define CONFIG_CMDLINE_TAG /* pass commandline to Kernel */
  45 +#define CONFIG_SETUP_MEMORY_TAGS /* pass memory defs to kernel */
  46 +#define CONFIG_INITRD_TAG /* pass initrd param to kernel */
  47 +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
  48 +#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
  49 +#define CONFIG_DISPLAY_CPUINFO /* display CPU Info at startup */
  50 +
  51 +/* setting board specific options */
  52 +# define CONFIG_MACH_TYPE MACH_TYPE_SMARTWEB
  53 +#define CONFIG_SYS_GENERIC_BOARD
  54 +#define CONFIG_CMDLINE_EDITING
  55 +#define CONFIG_AUTO_COMPLETE
  56 +
  57 +/* The LED PINs */
  58 +#define CONFIG_RED_LED AT91_PIN_PA9
  59 +#define CONFIG_GREEN_LED AT91_PIN_PA6
  60 +
  61 +/*
  62 + * SDRAM: 1 bank, 64 MB, base address 0x20000000
  63 + * Already initialized before u-boot gets started.
  64 + */
  65 +#define CONFIG_NR_DRAM_BANKS 1
  66 +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
  67 +#define CONFIG_SYS_SDRAM_SIZE (64 << 20)
  68 +
  69 +/*
  70 + * Perform a SDRAM Memtest from the start of SDRAM
  71 + * till the beginning of the U-Boot position in RAM.
  72 + */
  73 +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
  74 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
  75 +
  76 +/* Size of malloc() pool */
  77 +#define CONFIG_SYS_MALLOC_LEN \
  78 + ROUND(3 * CONFIG_ENV_SIZE + (128 << 10), 0x1000)
  79 +
  80 +/* NAND flash settings */
  81 +#define CONFIG_NAND_ATMEL
  82 +#define CONFIG_SYS_NO_FLASH
  83 +#define CONFIG_SYS_MAX_NAND_DEVICE 1
  84 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
  85 +#define CONFIG_SYS_NAND_DBW_8
  86 +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
  87 +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
  88 +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
  89 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
  90 +
  91 +#define CONFIG_CMD_MTDPARTS
  92 +#define CONFIG_MTD_DEVICE
  93 +#define MTDIDS_NAME_STR "atmel_nand"
  94 +#define MTDIDS_DEFAULT "nand0=" MTDIDS_NAME_STR
  95 +#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
  96 + "128k(Bootstrap)," \
  97 + "896k(U-Boot)," \
  98 + "512k(ENV0)," \
  99 + "512k(ENV1)," \
  100 + "4M(Linux)," \
  101 + "-(Root-FS)"
  102 +
  103 +/* general purpose I/O */
  104 +#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
  105 +#define CONFIG_AT91_GPIO /* enable the GPIO features */
  106 +#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */
  107 +
  108 +/* serial console */
  109 +#define CONFIG_ATMEL_USART
  110 +#define CONFIG_USART_BASE ATMEL_BASE_DBGU
  111 +#define CONFIG_USART_ID ATMEL_ID_SYS
  112 +#define CONFIG_BAUDRATE 115200
  113 +
  114 +/*
  115 + * Ethernet configuration
  116 + *
  117 + */
  118 +#define CONFIG_MACB
  119 +#define CONFIG_RMII /* use reduced MII inteface */
  120 +#define CONFIG_NET_RETRY_COUNT 20 /* # of DHCP/BOOTP retries */
  121 +#define CONFIG_AT91_WANTS_COMMON_PHY
  122 +
  123 +/* BOOTP and DHCP options */
  124 +#define CONFIG_BOOTP_BOOTFILESIZE
  125 +#define CONFIG_BOOTP_BOOTPATH
  126 +#define CONFIG_BOOTP_GATEWAY
  127 +#define CONFIG_BOOTP_HOSTNAME
  128 +#define CONFIG_NFSBOOTCOMMAND \
  129 + "setenv autoload yes; setenv autoboot yes; " \
  130 + "setenv bootargs ${basicargs} ${mtdparts} " \
  131 + "root=/dev/nfs ip=dhcp nfsroot=${serverip}:/srv/nfs/rootfs; " \
  132 + "dhcp"
  133 +
  134 +/* Enable the watchdog */
  135 +#define CONFIG_AT91SAM9_WATCHDOG
  136 +#if !defined(CONFIG_SPL_BUILD)
  137 +#define CONFIG_HW_WATCHDOG
  138 +#endif
  139 +#define CONFIG_AT91_HW_WDT_TIMEOUT 15
  140 +
  141 +#if !defined(CONFIG_SPL_BUILD)
  142 +/* USB configuration */
  143 +#define CONFIG_USB_ATMEL
  144 +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
  145 +#define CONFIG_USB_OHCI_NEW
  146 +#define CONFIG_USB_STORAGE
  147 +#define CONFIG_DOS_PARTITION
  148 +#define CONFIG_SYS_USB_OHCI_CPU_INIT
  149 +#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE
  150 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
  151 +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
  152 +#endif
  153 +
  154 +/* General Boot Parameter */
  155 +#define CONFIG_BOOTDELAY 3
  156 +#define CONFIG_BOOTCOMMAND "run flashboot"
  157 +#define CONFIG_SYS_PROMPT "U-Boot> "
  158 +#define CONFIG_SYS_CBSIZE 512
  159 +#define CONFIG_SYS_MAXARGS 16
  160 +#define CONFIG_SYS_PBSIZE \
  161 + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  162 +#define CONFIG_SYS_LONGHELP
  163 +#define CONFIG_CMDLINE_EDITING
  164 +
  165 +/*
  166 + * RAM Memory address where to put the
  167 + * Linux Kernel befor starting.
  168 + */
  169 +#define CONFIG_SYS_LOAD_ADDR 0x22000000
  170 +
  171 +/*
  172 + * The NAND Flash partitions:
  173 + */
  174 +#define CONFIG_ENV_IS_IN_NAND
  175 +#define CONFIG_ENV_OFFSET (0x100000)
  176 +#define CONFIG_ENV_OFFSET_REDUND (0x180000)
  177 +#define CONFIG_ENV_RANGE (0x80000)
  178 +#define CONFIG_ENV_SIZE (0x20000)
  179 +
  180 +/*
  181 + * Predefined environment variables.
  182 + * Usefull to define some easy to use boot commands.
  183 + */
  184 +#define CONFIG_EXTRA_ENV_SETTINGS \
  185 + \
  186 + "basicargs=console=ttyS0,115200\0" \
  187 + \
  188 + "mtdparts="MTDPARTS_DEFAULT"\0"
  189 +
  190 +/* Command line & features configuration */
  191 +#undef CONFIG_CMD_FPGA
  192 +#undef CONFIG_CMD_IMI
  193 +#undef CONFIG_CMD_IMLS
  194 +#undef CONFIG_CMD_LOADS
  195 +
  196 +#define CONFIG_CMD_NAND
  197 +#define CONFIG_CMD_USB
  198 +#define CONFIG_CMD_FAT
  199 +
  200 +#ifdef CONFIG_MACB
  201 +# define CONFIG_CMD_PING
  202 +# define CONFIG_CMD_DHCP
  203 +#else
  204 +# undef CONFIG_CMD_BOOTD
  205 +# undef CONFIG_CMD_NET
  206 +# undef CONFIG_CMD_NFS
  207 +#endif /* CONFIG_MACB */
  208 +
  209 +#if !defined(CONFIG_SPL_BUILD)
  210 +/* Enable Device-Tree (FDT) support */
  211 +#define CONFIG_OF_LIBFDT
  212 +#define CONFIG_CMD_FDT
  213 +#define CONFIG_FIT
  214 +#endif
  215 +
  216 +#ifdef CONFIG_SPL_BUILD
  217 +#define CONFIG_SYS_INIT_SP_ADDR 0x301000
  218 +#define CONFIG_SPL_STACK_R
  219 +#define CONFIG_SPL_STACK_R_ADDR CONFIG_SYS_TEXT_BASE
  220 +#else
  221 +/*
  222 + * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
  223 + * leaving the correct space for initial global data structure above that
  224 + * address while providing maximum stack area below.
  225 + */
  226 +#define CONFIG_SYS_INIT_SP_ADDR \
  227 + (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
  228 +#endif
  229 +
  230 +
  231 +/* Defines for SPL */
  232 +#define CONFIG_SPL_FRAMEWORK
  233 +#define CONFIG_SPL_TEXT_BASE 0x0
  234 +#define CONFIG_SPL_MAX_SIZE (4 * 1024)
  235 +
  236 +#define CONFIG_SPL_BSS_START_ADDR CONFIG_SYS_SDRAM_BASE
  237 +#define CONFIG_SPL_BSS_MAX_SIZE (16 * 1024)
  238 +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
  239 + CONFIG_SPL_BSS_MAX_SIZE)
  240 +#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
  241 +#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
  242 +
  243 +#define CONFIG_SPL_LIBCOMMON_SUPPORT
  244 +#define CONFIG_SPL_LIBGENERIC_SUPPORT
  245 +
  246 +#define CONFIG_SPL_BOARD_INIT
  247 +#define CONFIG_SPL_GPIO_SUPPORT
  248 +#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14)
  249 +#define CONFIG_SPL_NAND_SUPPORT
  250 +#define CONFIG_SYS_USE_NANDFLASH 1
  251 +#define CONFIG_SPL_NAND_DRIVERS
  252 +#define CONFIG_SPL_NAND_BASE
  253 +#define CONFIG_SPL_NAND_ECC
  254 +#define CONFIG_SPL_NAND_RAW_ONLY
  255 +#define CONFIG_SPL_NAND_SOFTECC
  256 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
  257 +#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
  258 +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
  259 +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
  260 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE
  261 +
  262 +#define CONFIG_SYS_NAND_SIZE (256*1024*1024)
  263 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048
  264 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
  265 +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
  266 + CONFIG_SYS_NAND_PAGE_SIZE)
  267 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
  268 +#define CONFIG_SYS_NAND_ECCSIZE 256
  269 +#define CONFIG_SYS_NAND_ECCBYTES 3
  270 +#define CONFIG_SYS_NAND_OOBSIZE 64
  271 +#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
  272 + 48, 49, 50, 51, 52, 53, 54, 55, \
  273 + 56, 57, 58, 59, 60, 61, 62, 63, }
  274 +
  275 +#define CONFIG_SPL_ATMEL_SIZE
  276 +#define CONFIG_SYS_MASTER_CLOCK (198656000/2)
  277 +#define AT91_PLL_LOCK_TIMEOUT 1000000
  278 +#define CONFIG_SYS_AT91_PLLA 0x2060bf09
  279 +#define CONFIG_SYS_MCKR 0x100
  280 +#define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR)
  281 +#define CONFIG_SYS_AT91_PLLB 0x10483f0e
  282 +
  283 +#if defined(CONFIG_SPL_BUILD)
  284 +#define CONFIG_SYS_THUMB_BUILD
  285 +#define CONFIG_SYS_ICACHE_OFF
  286 +#define CONFIG_SYS_DCACHE_OFF
  287 +#undef CONFIG_SPL_OS_BOOT /* Not supported by existing map */
  288 +#endif
  289 +#endif /* __CONFIG_H */