Commit 3c1af17c5eebc3718095907c254ae3eb8a3412f8
Exists in
smarc_8mq_lf_v2020.04
and in
17 other branches
Merge branch 'master' of git://www.denx.de/git/u-boot-imx
Showing 34 changed files Side-by-side Diff
- arch/arm/include/asm/arch-mx6/imx-regs.h
- board/dhelectronics/dh_imx6/dh_imx6.c
- board/freescale/mx6slevk/mx6slevk.c
- board/udoo/udoo.c
- board/wandboard/spl.c
- board/wandboard/wandboard.c
- configs/dh_imx6_defconfig
- configs/imx6q_logic_defconfig
- configs/imx6qdl_icore_nand_defconfig
- configs/imx6ul_geam_mmc_defconfig
- configs/imx6ul_geam_nand_defconfig
- configs/imx6ul_isiot_emmc_defconfig
- configs/imx6ul_isiot_mmc_defconfig
- configs/imx6ul_isiot_nand_defconfig
- configs/mx6slevk_defconfig
- configs/mx6slevk_spinor_defconfig
- configs/mx6slevk_spl_defconfig
- configs/mx6sllevk_defconfig
- configs/mx6sllevk_plugin_defconfig
- configs/mx6sxsabreauto_defconfig
- configs/mx6ull_14x14_evk_defconfig
- configs/mx6ull_14x14_evk_plugin_defconfig
- configs/mx7dsabresd_defconfig
- configs/mx7dsabresd_secure_defconfig
- configs/mx7ulp_evk_defconfig
- configs/mx7ulp_evk_plugin_defconfig
- configs/opos6uldev_defconfig
- drivers/net/fec_mxc.c
- include/configs/colibri_vf.h
- include/configs/dh_imx6.h
- include/configs/opos6uldev.h
- include/configs/pcm052.h
- include/configs/vf610twr.h
- include/configs/wandboard.h
arch/arm/include/asm/arch-mx6/imx-regs.h
... | ... | @@ -346,6 +346,9 @@ |
346 | 346 | #define IOMUXC_SNVS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000) |
347 | 347 | #define SNVS_GPR_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000) |
348 | 348 | #endif |
349 | + | |
350 | +#define NOC_DDR_BASE_ADDR (GPV0_BASE_ADDR + 0xB0000) | |
351 | + | |
349 | 352 | /* Only for i.MX6SX */ |
350 | 353 | #define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000) |
351 | 354 | #define MX6SX_LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000) |
board/dhelectronics/dh_imx6/dh_imx6.c
... | ... | @@ -253,16 +253,10 @@ |
253 | 253 | |
254 | 254 | int board_usb_phy_mode(int port) |
255 | 255 | { |
256 | - return USB_INIT_HOST; | |
257 | -} | |
258 | - | |
259 | -/* Use only Port 1 == DHCOM USB Host 1 */ | |
260 | -int board_ehci_hcd_init(int port) | |
261 | -{ | |
262 | 256 | if (port == 1) |
263 | - return 0; | |
257 | + return USB_INIT_HOST; | |
264 | 258 | else |
265 | - return -ENODEV; | |
259 | + return USB_INIT_DEVICE; | |
266 | 260 | } |
267 | 261 | |
268 | 262 | int board_ehci_power(int port, int on) |
board/freescale/mx6slevk/mx6slevk.c
... | ... | @@ -27,8 +27,6 @@ |
27 | 27 | #include <power/pmic.h> |
28 | 28 | #include <power/pfuze100_pmic.h> |
29 | 29 | #include "../common/pfuze.h" |
30 | -#include <usb.h> | |
31 | -#include <usb/ehci-ci.h> | |
32 | 30 | |
33 | 31 | DECLARE_GLOBAL_DATA_PTR; |
34 | 32 | |
... | ... | @@ -223,49 +221,6 @@ |
223 | 221 | } |
224 | 222 | #endif |
225 | 223 | |
226 | -#ifdef CONFIG_USB_EHCI_MX6 | |
227 | -#define USB_OTHERREGS_OFFSET 0x800 | |
228 | -#define UCTRL_PWR_POL (1 << 9) | |
229 | - | |
230 | -static iomux_v3_cfg_t const usb_otg_pads[] = { | |
231 | - /* OTG1 */ | |
232 | - MX6_PAD_KEY_COL4__USB_USBOTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), | |
233 | - MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL), | |
234 | - /* OTG2 */ | |
235 | - MX6_PAD_KEY_COL5__USB_USBOTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL) | |
236 | -}; | |
237 | - | |
238 | -static void setup_usb(void) | |
239 | -{ | |
240 | - imx_iomux_v3_setup_multiple_pads(usb_otg_pads, | |
241 | - ARRAY_SIZE(usb_otg_pads)); | |
242 | -} | |
243 | - | |
244 | -int board_usb_phy_mode(int port) | |
245 | -{ | |
246 | - if (port == 1) | |
247 | - return USB_INIT_HOST; | |
248 | - else | |
249 | - return usb_phy_mode(port); | |
250 | -} | |
251 | - | |
252 | -int board_ehci_hcd_init(int port) | |
253 | -{ | |
254 | - u32 *usbnc_usb_ctrl; | |
255 | - | |
256 | - if (port > 1) | |
257 | - return -EINVAL; | |
258 | - | |
259 | - usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + | |
260 | - port * 4); | |
261 | - | |
262 | - /* Set Power polarity */ | |
263 | - setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); | |
264 | - | |
265 | - return 0; | |
266 | -} | |
267 | -#endif | |
268 | - | |
269 | 224 | int board_early_init_f(void) |
270 | 225 | { |
271 | 226 | setup_iomux_uart(); |
... | ... | @@ -287,10 +242,6 @@ |
287 | 242 | setup_fec(); |
288 | 243 | #endif |
289 | 244 | |
290 | -#ifdef CONFIG_USB_EHCI_MX6 | |
291 | - setup_usb(); | |
292 | -#endif | |
293 | - | |
294 | 245 | return 0; |
295 | 246 | } |
296 | 247 | |
297 | 248 | |
298 | 249 | |
... | ... | @@ -322,12 +273,15 @@ |
322 | 273 | |
323 | 274 | switch (cfg->esdhc_base) { |
324 | 275 | case USDHC1_BASE_ADDR: |
276 | + gpio_request(USDHC1_CD_GPIO, "cd1_gpio"); | |
325 | 277 | ret = !gpio_get_value(USDHC1_CD_GPIO); |
326 | 278 | break; |
327 | 279 | case USDHC2_BASE_ADDR: |
280 | + gpio_request(USDHC2_CD_GPIO, "cd2_gpio"); | |
328 | 281 | ret = !gpio_get_value(USDHC2_CD_GPIO); |
329 | 282 | break; |
330 | 283 | case USDHC3_BASE_ADDR: |
284 | + gpio_request(USDHC3_CD_GPIO, "cd3_gpio"); | |
331 | 285 | ret = !gpio_get_value(USDHC3_CD_GPIO); |
332 | 286 | break; |
333 | 287 | } |
board/udoo/udoo.c
board/wandboard/spl.c
... | ... | @@ -32,6 +32,7 @@ |
32 | 32 | |
33 | 33 | #define IMX6DQ_DRIVE_STRENGTH 0x30 |
34 | 34 | #define IMX6SDL_DRIVE_STRENGTH 0x28 |
35 | +#define IMX6QP_DRIVE_STRENGTH 0x28 | |
35 | 36 | |
36 | 37 | /* configure MX6Q/DUAL mmdc DDR io registers */ |
37 | 38 | static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { |
... | ... | @@ -63,6 +64,36 @@ |
63 | 64 | .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH, |
64 | 65 | }; |
65 | 66 | |
67 | +/* configure MX6QP mmdc DDR io registers */ | |
68 | +static struct mx6dq_iomux_ddr_regs mx6qp_ddr_ioregs = { | |
69 | + .dram_sdclk_0 = IMX6QP_DRIVE_STRENGTH, | |
70 | + .dram_sdclk_1 = IMX6QP_DRIVE_STRENGTH, | |
71 | + .dram_cas = IMX6QP_DRIVE_STRENGTH, | |
72 | + .dram_ras = IMX6QP_DRIVE_STRENGTH, | |
73 | + .dram_reset = IMX6QP_DRIVE_STRENGTH, | |
74 | + .dram_sdcke0 = IMX6QP_DRIVE_STRENGTH, | |
75 | + .dram_sdcke1 = IMX6QP_DRIVE_STRENGTH, | |
76 | + .dram_sdba2 = 0x00000000, | |
77 | + .dram_sdodt0 = IMX6QP_DRIVE_STRENGTH, | |
78 | + .dram_sdodt1 = IMX6QP_DRIVE_STRENGTH, | |
79 | + .dram_sdqs0 = IMX6QP_DRIVE_STRENGTH, | |
80 | + .dram_sdqs1 = IMX6QP_DRIVE_STRENGTH, | |
81 | + .dram_sdqs2 = IMX6QP_DRIVE_STRENGTH, | |
82 | + .dram_sdqs3 = IMX6QP_DRIVE_STRENGTH, | |
83 | + .dram_sdqs4 = IMX6QP_DRIVE_STRENGTH, | |
84 | + .dram_sdqs5 = IMX6QP_DRIVE_STRENGTH, | |
85 | + .dram_sdqs6 = IMX6QP_DRIVE_STRENGTH, | |
86 | + .dram_sdqs7 = IMX6QP_DRIVE_STRENGTH, | |
87 | + .dram_dqm0 = IMX6QP_DRIVE_STRENGTH, | |
88 | + .dram_dqm1 = IMX6QP_DRIVE_STRENGTH, | |
89 | + .dram_dqm2 = IMX6QP_DRIVE_STRENGTH, | |
90 | + .dram_dqm3 = IMX6QP_DRIVE_STRENGTH, | |
91 | + .dram_dqm4 = IMX6QP_DRIVE_STRENGTH, | |
92 | + .dram_dqm5 = IMX6QP_DRIVE_STRENGTH, | |
93 | + .dram_dqm6 = IMX6QP_DRIVE_STRENGTH, | |
94 | + .dram_dqm7 = IMX6QP_DRIVE_STRENGTH, | |
95 | +}; | |
96 | + | |
66 | 97 | /* configure MX6Q/DUAL mmdc GRP io registers */ |
67 | 98 | static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { |
68 | 99 | .grp_ddr_type = 0x000c0000, |
... | ... | @@ -81,6 +112,24 @@ |
81 | 112 | .grp_b7ds = IMX6DQ_DRIVE_STRENGTH, |
82 | 113 | }; |
83 | 114 | |
115 | +/* configure MX6QP mmdc GRP io registers */ | |
116 | +static struct mx6dq_iomux_grp_regs mx6qp_grp_ioregs = { | |
117 | + .grp_ddr_type = 0x000c0000, | |
118 | + .grp_ddrmode_ctl = 0x00020000, | |
119 | + .grp_ddrpke = 0x00000000, | |
120 | + .grp_addds = IMX6QP_DRIVE_STRENGTH, | |
121 | + .grp_ctlds = IMX6QP_DRIVE_STRENGTH, | |
122 | + .grp_ddrmode = 0x00020000, | |
123 | + .grp_b0ds = IMX6QP_DRIVE_STRENGTH, | |
124 | + .grp_b1ds = IMX6QP_DRIVE_STRENGTH, | |
125 | + .grp_b2ds = IMX6QP_DRIVE_STRENGTH, | |
126 | + .grp_b3ds = IMX6QP_DRIVE_STRENGTH, | |
127 | + .grp_b4ds = IMX6QP_DRIVE_STRENGTH, | |
128 | + .grp_b5ds = IMX6QP_DRIVE_STRENGTH, | |
129 | + .grp_b6ds = IMX6QP_DRIVE_STRENGTH, | |
130 | + .grp_b7ds = IMX6QP_DRIVE_STRENGTH, | |
131 | +}; | |
132 | + | |
84 | 133 | /* configure MX6SOLO/DUALLITE mmdc DDR io registers */ |
85 | 134 | struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { |
86 | 135 | .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH, |
87 | 136 | |
88 | 137 | |
... | ... | @@ -260,15 +309,87 @@ |
260 | 309 | writel(0x00C03F3F, &ccm->CCGR0); |
261 | 310 | writel(0x0030FC03, &ccm->CCGR1); |
262 | 311 | writel(0x0FFFC000, &ccm->CCGR2); |
263 | - writel(0x3FF00000, &ccm->CCGR3); | |
312 | + writel(0x3FF03000, &ccm->CCGR3); | |
264 | 313 | writel(0x00FFF300, &ccm->CCGR4); |
265 | 314 | writel(0x0F0000C3, &ccm->CCGR5); |
266 | 315 | writel(0x000003FF, &ccm->CCGR6); |
267 | 316 | } |
268 | 317 | |
318 | +static void spl_dram_init_imx6qp_lpddr3(void) | |
319 | +{ | |
320 | + /* MMDC0_MDSCR set the Configuration request bit during MMDC set up */ | |
321 | + writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c); | |
322 | + /* Calibrations - ZQ */ | |
323 | + writel(0xa1390003, MMDC_P0_BASE_ADDR + 0x800); | |
324 | + /* write leveling */ | |
325 | + writel(0x00060004, MMDC_P0_BASE_ADDR + 0x80c); | |
326 | + writel(0x000B0004, MMDC_P0_BASE_ADDR + 0x810); | |
327 | + writel(0x00000004, MMDC_P1_BASE_ADDR + 0x80c); | |
328 | + writel(0x00000000, MMDC_P1_BASE_ADDR + 0x810); | |
329 | + /* | |
330 | + * DQS gating, read delay, write delay calibration values | |
331 | + * based on calibration compare of 0x00ffff00 | |
332 | + */ | |
333 | + writel(0x03040314, MMDC_P0_BASE_ADDR + 0x83c); | |
334 | + writel(0x03080300, MMDC_P0_BASE_ADDR + 0x840); | |
335 | + writel(0x03000310, MMDC_P1_BASE_ADDR + 0x83c); | |
336 | + writel(0x0268023C, MMDC_P1_BASE_ADDR + 0x840); | |
337 | + writel(0x4034363A, MMDC_P0_BASE_ADDR + 0x848); | |
338 | + writel(0x36302C3C, MMDC_P1_BASE_ADDR + 0x848); | |
339 | + writel(0x3E3E4046, MMDC_P0_BASE_ADDR + 0x850); | |
340 | + writel(0x483A4844, MMDC_P1_BASE_ADDR + 0x850); | |
341 | + writel(0x33333333, MMDC_P0_BASE_ADDR + 0x81c); | |
342 | + writel(0x33333333, MMDC_P0_BASE_ADDR + 0x820); | |
343 | + writel(0x33333333, MMDC_P0_BASE_ADDR + 0x824); | |
344 | + writel(0x33333333, MMDC_P0_BASE_ADDR + 0x828); | |
345 | + writel(0x33333333, MMDC_P1_BASE_ADDR + 0x81c); | |
346 | + writel(0x33333333, MMDC_P1_BASE_ADDR + 0x820); | |
347 | + writel(0x33333333, MMDC_P1_BASE_ADDR + 0x824); | |
348 | + writel(0x33333333, MMDC_P1_BASE_ADDR + 0x828); | |
349 | + writel(0x24912489, MMDC_P0_BASE_ADDR + 0x8c0); | |
350 | + writel(0x24914452, MMDC_P1_BASE_ADDR + 0x8c0); | |
351 | + writel(0x00000800, MMDC_P0_BASE_ADDR + 0x8b8); | |
352 | + writel(0x00000800, MMDC_P1_BASE_ADDR + 0x8b8); | |
353 | + /* MMDC init: in DDR3, 64-bit mode, only MMDC0 is initiated */ | |
354 | + writel(0x00020036, MMDC_P0_BASE_ADDR + 0x004); | |
355 | + writel(0x09444040, MMDC_P0_BASE_ADDR + 0x008); | |
356 | + writel(0x898E79A4, MMDC_P0_BASE_ADDR + 0x00c); | |
357 | + writel(0xDB538F64, MMDC_P0_BASE_ADDR + 0x010); | |
358 | + writel(0x01FF00DD, MMDC_P0_BASE_ADDR + 0x014); | |
359 | + writel(0x00011740, MMDC_P0_BASE_ADDR + 0x018); | |
360 | + writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c); | |
361 | + writel(0x000026D2, MMDC_P0_BASE_ADDR + 0x02c); | |
362 | + writel(0x008E1023, MMDC_P0_BASE_ADDR + 0x030); | |
363 | + writel(0x00000047, MMDC_P0_BASE_ADDR + 0x040); | |
364 | + writel(0x14420000, MMDC_P0_BASE_ADDR + 0x400); | |
365 | + writel(0x841A0000, MMDC_P0_BASE_ADDR + 0x000); | |
366 | + writel(0x00400c58, MMDC_P0_BASE_ADDR + 0x890); | |
367 | + /* add NOC DDR configuration */ | |
368 | + writel(0x00000000, NOC_DDR_BASE_ADDR + 0x008); | |
369 | + writel(0x2871C39B, NOC_DDR_BASE_ADDR + 0x00c); | |
370 | + writel(0x000005B4, NOC_DDR_BASE_ADDR + 0x038); | |
371 | + writel(0x00000040, NOC_DDR_BASE_ADDR + 0x014); | |
372 | + writel(0x00000020, NOC_DDR_BASE_ADDR + 0x028); | |
373 | + writel(0x00000020, NOC_DDR_BASE_ADDR + 0x02c); | |
374 | + writel(0x02088032, MMDC_P0_BASE_ADDR + 0x01c); | |
375 | + writel(0x00008033, MMDC_P0_BASE_ADDR + 0x01c); | |
376 | + writel(0x00048031, MMDC_P0_BASE_ADDR + 0x01c); | |
377 | + writel(0x19308030, MMDC_P0_BASE_ADDR + 0x01c); | |
378 | + writel(0x04008040, MMDC_P0_BASE_ADDR + 0x01c); | |
379 | + writel(0x00007800, MMDC_P0_BASE_ADDR + 0x020); | |
380 | + writel(0x00022227, MMDC_P0_BASE_ADDR + 0x818); | |
381 | + writel(0x00022227, MMDC_P1_BASE_ADDR + 0x818); | |
382 | + writel(0x00025576, MMDC_P0_BASE_ADDR + 0x004); | |
383 | + writel(0x00011006, MMDC_P0_BASE_ADDR + 0x404); | |
384 | + writel(0x00000000, MMDC_P0_BASE_ADDR + 0x01c); | |
385 | +} | |
386 | + | |
269 | 387 | static void spl_dram_init(void) |
270 | 388 | { |
271 | - if (is_cpu_type(MXC_CPU_MX6SOLO)) { | |
389 | + if (is_mx6dqp()) { | |
390 | + mx6dq_dram_iocfg(64, &mx6qp_ddr_ioregs, &mx6qp_grp_ioregs); | |
391 | + spl_dram_init_imx6qp_lpddr3(); | |
392 | + } else if (is_cpu_type(MXC_CPU_MX6SOLO)) { | |
272 | 393 | mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); |
273 | 394 | mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63dfr); |
274 | 395 | } else if (is_cpu_type(MXC_CPU_MX6DL)) { |
board/wandboard/wandboard.c
... | ... | @@ -435,9 +435,7 @@ |
435 | 435 | { |
436 | 436 | setup_iomux_uart(); |
437 | 437 | #ifdef CONFIG_SATA |
438 | - /* Only mx6q wandboard has SATA */ | |
439 | - if (is_cpu_type(MXC_CPU_MX6Q)) | |
440 | - setup_sata(); | |
438 | + setup_sata(); | |
441 | 439 | #endif |
442 | 440 | |
443 | 441 | return 0; |
... | ... | @@ -512,7 +510,9 @@ |
512 | 510 | #endif |
513 | 511 | |
514 | 512 | #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
515 | - if (is_mx6dq()) | |
513 | + if (is_mx6dqp()) | |
514 | + env_set("board_rev", "MX6QP"); | |
515 | + else if (is_mx6dq()) | |
516 | 516 | env_set("board_rev", "MX6Q"); |
517 | 517 | else |
518 | 518 | env_set("board_rev", "MX6DL"); |
... | ... | @@ -534,7 +534,7 @@ |
534 | 534 | |
535 | 535 | #if defined(CONFIG_VIDEO_IPUV3) |
536 | 536 | setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info); |
537 | - if (is_mx6dq()) { | |
537 | + if (is_mx6dq() || is_mx6dqp()) { | |
538 | 538 | setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info); |
539 | 539 | setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c3_pad_info); |
540 | 540 | } else { |
configs/dh_imx6_defconfig
... | ... | @@ -19,6 +19,7 @@ |
19 | 19 | CONFIG_CMD_BOOTZ=y |
20 | 20 | CONFIG_CMD_MEMTEST=y |
21 | 21 | CONFIG_CMD_UNZIP=y |
22 | +CONFIG_CMD_DFU=y | |
22 | 23 | # CONFIG_CMD_FLASH is not set |
23 | 24 | CONFIG_CMD_GPIO=y |
24 | 25 | CONFIG_CMD_I2C=y |
... | ... | @@ -27,6 +28,7 @@ |
27 | 28 | CONFIG_CMD_SATA=y |
28 | 29 | CONFIG_CMD_SF=y |
29 | 30 | CONFIG_CMD_USB=y |
31 | +CONFIG_CMD_USB_MASS_STORAGE=y | |
30 | 32 | CONFIG_CMD_DHCP=y |
31 | 33 | CONFIG_CMD_MII=y |
32 | 34 | CONFIG_CMD_PING=y |
... | ... | @@ -47,5 +49,11 @@ |
47 | 49 | CONFIG_FEC_MXC=y |
48 | 50 | CONFIG_USB=y |
49 | 51 | CONFIG_USB_STORAGE=y |
52 | +CONFIG_USB_GADGET=y | |
53 | +CONFIG_USB_GADGET_MANUFACTURER="dh" | |
54 | +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 | |
55 | +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 | |
56 | +CONFIG_CI_UDC=y | |
57 | +CONFIG_USB_GADGET_DOWNLOAD=y | |
50 | 58 | CONFIG_OF_LIBFDT=y |
configs/imx6q_logic_defconfig
configs/imx6qdl_icore_nand_defconfig
configs/imx6ul_geam_mmc_defconfig
configs/imx6ul_geam_nand_defconfig
configs/imx6ul_isiot_emmc_defconfig
configs/imx6ul_isiot_mmc_defconfig
configs/imx6ul_isiot_nand_defconfig
configs/mx6slevk_defconfig
... | ... | @@ -28,7 +28,6 @@ |
28 | 28 | CONFIG_OF_CONTROL=y |
29 | 29 | CONFIG_ENV_IS_IN_MMC=y |
30 | 30 | CONFIG_DM=y |
31 | -# CONFIG_BLK is not set | |
32 | 31 | CONFIG_DM_GPIO=y |
33 | 32 | CONFIG_DM_I2C=y |
34 | 33 | CONFIG_DM_MMC=y |
... | ... | @@ -45,6 +44,7 @@ |
45 | 44 | CONFIG_DM_REGULATOR_GPIO=y |
46 | 45 | CONFIG_DM_THERMAL=y |
47 | 46 | CONFIG_USB=y |
47 | +CONFIG_DM_USB=y | |
48 | 48 | CONFIG_USB_STORAGE=y |
49 | 49 | CONFIG_USB_HOST_ETHER=y |
50 | 50 | CONFIG_USB_ETHER_ASIX=y |
configs/mx6slevk_spinor_defconfig
... | ... | @@ -28,7 +28,6 @@ |
28 | 28 | CONFIG_OF_CONTROL=y |
29 | 29 | CONFIG_ENV_IS_IN_SPI_FLASH=y |
30 | 30 | CONFIG_DM=y |
31 | -# CONFIG_BLK is not set | |
32 | 31 | CONFIG_DM_GPIO=y |
33 | 32 | CONFIG_DM_I2C=y |
34 | 33 | CONFIG_DM_MMC=y |
... | ... | @@ -45,6 +44,7 @@ |
45 | 44 | CONFIG_DM_REGULATOR_GPIO=y |
46 | 45 | CONFIG_DM_THERMAL=y |
47 | 46 | CONFIG_USB=y |
47 | +CONFIG_DM_USB=y | |
48 | 48 | CONFIG_USB_STORAGE=y |
49 | 49 | CONFIG_USB_HOST_ETHER=y |
50 | 50 | CONFIG_USB_ETHER_ASIX=y |
configs/mx6slevk_spl_defconfig
... | ... | @@ -9,7 +9,8 @@ |
9 | 9 | CONFIG_SPL_LIBDISK_SUPPORT=y |
10 | 10 | CONFIG_SPL_WATCHDOG_SUPPORT=y |
11 | 11 | # CONFIG_CMD_BMODE is not set |
12 | -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6SL,SYS_I2C" | |
12 | +CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk" | |
13 | +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6SL" | |
13 | 14 | CONFIG_BOOTDELAY=3 |
14 | 15 | CONFIG_BOARD_EARLY_INIT_F=y |
15 | 16 | CONFIG_SPL=y |
16 | 17 | |
17 | 18 | |
18 | 19 | |
... | ... | @@ -32,13 +33,26 @@ |
32 | 33 | CONFIG_CMD_EXT4_WRITE=y |
33 | 34 | CONFIG_CMD_FAT=y |
34 | 35 | CONFIG_CMD_FS_GENERIC=y |
36 | +CONFIG_OF_CONTROL=y | |
35 | 37 | CONFIG_ENV_IS_IN_MMC=y |
36 | 38 | CONFIG_DM=y |
39 | +CONFIG_DM_GPIO=y | |
40 | +CONFIG_DM_I2C=y | |
41 | +CONFIG_DM_MMC=y | |
37 | 42 | CONFIG_SPI_FLASH=y |
38 | 43 | CONFIG_SPI_FLASH_STMICRO=y |
39 | 44 | CONFIG_PHYLIB=y |
45 | +CONFIG_PINCTRL=y | |
46 | +CONFIG_PINCTRL_IMX6=y | |
47 | +CONFIG_DM_PMIC=y | |
48 | +CONFIG_DM_PMIC_PFUZE100=y | |
49 | +CONFIG_DM_REGULATOR=y | |
50 | +CONFIG_DM_REGULATOR_PFUZE100=y | |
51 | +CONFIG_DM_REGULATOR_FIXED=y | |
52 | +CONFIG_DM_REGULATOR_GPIO=y | |
40 | 53 | CONFIG_DM_THERMAL=y |
41 | 54 | CONFIG_USB=y |
55 | +CONFIG_DM_USB=y | |
42 | 56 | CONFIG_USB_STORAGE=y |
43 | 57 | CONFIG_USB_HOST_ETHER=y |
44 | 58 | CONFIG_USB_ETHER_ASIX=y |
configs/mx6sllevk_defconfig
configs/mx6sllevk_plugin_defconfig
configs/mx6sxsabreauto_defconfig
... | ... | @@ -28,7 +28,6 @@ |
28 | 28 | CONFIG_CMD_FAT=y |
29 | 29 | CONFIG_CMD_FS_GENERIC=y |
30 | 30 | CONFIG_OF_CONTROL=y |
31 | -# CONFIG_BLK is not set | |
32 | 31 | CONFIG_DM_GPIO=y |
33 | 32 | CONFIG_DM_PCA953X=y |
34 | 33 | CONFIG_DM_I2C=y |
... | ... | @@ -47,6 +46,7 @@ |
47 | 46 | CONFIG_DM_REGULATOR_GPIO=y |
48 | 47 | CONFIG_FSL_QSPI=y |
49 | 48 | CONFIG_USB=y |
49 | +CONFIG_DM_USB=y | |
50 | 50 | CONFIG_USB_STORAGE=y |
51 | 51 | CONFIG_USB_HOST_ETHER=y |
52 | 52 | CONFIG_USB_ETHER_ASIX=y |
configs/mx6ull_14x14_evk_defconfig
configs/mx6ull_14x14_evk_plugin_defconfig
configs/mx7dsabresd_defconfig
configs/mx7dsabresd_secure_defconfig
configs/mx7ulp_evk_defconfig
configs/mx7ulp_evk_plugin_defconfig
configs/opos6uldev_defconfig
drivers/net/fec_mxc.c
include/configs/colibri_vf.h
... | ... | @@ -75,8 +75,8 @@ |
75 | 75 | #define CONFIG_FDTADDR 0x84000000 |
76 | 76 | |
77 | 77 | /* We boot from the gfxRAM area of the OCRAM. */ |
78 | -#define CONFIG_SYS_TEXT_BASE 0x3f408000 | |
79 | -#define CONFIG_BOARD_SIZE_LIMIT 524288 | |
78 | +#define CONFIG_SYS_TEXT_BASE 0x3f401000 | |
79 | +#define CONFIG_BOARD_SIZE_LIMIT 520192 | |
80 | 80 | |
81 | 81 | #define SD_BOOTCMD \ |
82 | 82 | "sdargs=root=/dev/mmcblk0p2 rw rootwait\0" \ |
include/configs/dh_imx6.h
... | ... | @@ -115,6 +115,18 @@ |
115 | 115 | #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) |
116 | 116 | #define CONFIG_MXC_USB_FLAGS 0 |
117 | 117 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */ |
118 | + | |
119 | +/* USB Gadget (DFU, UMS) */ | |
120 | +#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) | |
121 | +#define CONFIG_USB_FUNCTION_MASS_STORAGE | |
122 | + | |
123 | +#define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024) | |
124 | +#define DFU_DEFAULT_POLL_TIMEOUT 300 | |
125 | + | |
126 | +/* USB IDs */ | |
127 | +#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 | |
128 | +#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 | |
129 | +#endif | |
118 | 130 | #endif |
119 | 131 | |
120 | 132 | /* Watchdog */ |
include/configs/opos6uldev.h
include/configs/pcm052.h
... | ... | @@ -89,8 +89,8 @@ |
89 | 89 | #define CONFIG_LOADADDR 0x82000000 |
90 | 90 | |
91 | 91 | /* We boot from the gfxRAM area of the OCRAM. */ |
92 | -#define CONFIG_SYS_TEXT_BASE 0x3f408000 | |
93 | -#define CONFIG_BOARD_SIZE_LIMIT 524288 | |
92 | +#define CONFIG_SYS_TEXT_BASE 0x3f401000 | |
93 | +#define CONFIG_BOARD_SIZE_LIMIT 520192 | |
94 | 94 | |
95 | 95 | /* if no target-specific extra environment settings were defined by the |
96 | 96 | target, define an empty one */ |
include/configs/vf610twr.h
... | ... | @@ -79,8 +79,8 @@ |
79 | 79 | #define CONFIG_SYS_LOAD_ADDR 0x82000000 |
80 | 80 | |
81 | 81 | /* We boot from the gfxRAM area of the OCRAM. */ |
82 | -#define CONFIG_SYS_TEXT_BASE 0x3f408000 | |
83 | -#define CONFIG_BOARD_SIZE_LIMIT 524288 | |
82 | +#define CONFIG_SYS_TEXT_BASE 0x3f401000 | |
83 | +#define CONFIG_BOARD_SIZE_LIMIT 520192 | |
84 | 84 | |
85 | 85 | /* |
86 | 86 | * We do have 128MB of memory on the Vybrid Tower board. Leave the last |
include/configs/wandboard.h
... | ... | @@ -109,6 +109,8 @@ |
109 | 109 | "fi; " \ |
110 | 110 | "fi\0" \ |
111 | 111 | "findfdt="\ |
112 | + "if test $board_name = D1 && test $board_rev = MX6QP ; then " \ | |
113 | + "setenv fdtfile imx6qp-wandboard-revd1.dtb; fi; " \ | |
112 | 114 | "if test $board_name = D1 && test $board_rev = MX6Q ; then " \ |
113 | 115 | "setenv fdtfile imx6q-wandboard-revd1.dtb; fi; " \ |
114 | 116 | "if test $board_name = D1 && test $board_rev = MX6DL ; then " \ |