gpio: mpc8xxx: Rename Kconfig option, structures, and functions

Rename the Kconfig option, structures (and their members), as well as functions of the mpc85xx driver to include mpc8xxx to reflect the more generic usage. Signed-off-by: Mario Six <mario.six@gdsys.cc>

gpio: mpc8xxx: Rename Kconfig option, structures, and functions
Rename the Kconfig option, structures (and their members), as well as functions of the mpc85xx driver to include mpc8xxx to reflect the more generic usage. Signed-off-by: Mario Six <mario.six@gdsys.cc>
Mario Six · Tom Rini
1 parent 76d00cc9cb
Showing 4 changed files with 64 additions and 65 deletions Side-by-side Diff
arch/powerpc/include/asm/arch-mpc85xx/gpio.h
drivers/gpio/Kconfig
drivers/gpio/Makefile
drivers/gpio/mpc8xxx_gpio.c
@@ -18,7 +18,7 @@
 #include <asm/mpc85xx_gpio.h>
 #endif
  
-struct mpc85xx_gpio_plat {
+struct mpc8xxx_gpio_plat {
 	ulong addr;
 	unsigned long size;
 	uint ngpios;
@@ -276,11 +276,11 @@
 	  Now, max 24 bits chips and PCA953X compatible chips are
 	  supported
  
-config MPC85XX_GPIO
-	bool "Freescale MPC85XX GPIO driver"
+config MPC8XXX_GPIO
+	bool "Freescale MPC8XXX GPIO driver"
 	depends on DM_GPIO
 	help
-	  This driver supports the built-in GPIO controller of MPC85XX CPUs.
+	  This driver supports the built-in GPIO controller of MPC8XXX CPUs.
 	  Each GPIO bank is identified by its own entry in the device tree,
 	  i.e.
  
@@ -298,8 +298,5 @@
 	  Aside from the standard functions of input/output mode, and output
 	  value setting, the open-drain feature, which can configure individual
 	  GPIOs to work as open-drain outputs, is supported.
-
-	  The driver has been tested on MPC85XX, but it is likely that other
-	  PowerQUICC III devices will work as well.
 endmenu
@@ -38,7 +38,7 @@
 obj-$(CONFIG_DM644X_GPIO)	+= da8xx_gpio.o
 obj-$(CONFIG_ALTERA_PIO)	+= altera_pio.o
 obj-$(CONFIG_MPC83XX_GPIO)	+= mpc83xx_gpio.o
-obj-$(CONFIG_MPC85XX_GPIO)	+= mpc8xxx_gpio.o
+obj-$(CONFIG_MPC8XXX_GPIO)	+= mpc8xxx_gpio.o
 obj-$(CONFIG_SH_GPIO_PFC)	+= sh_pfc.o
 obj-$(CONFIG_OMAP_GPIO)	+= omap_gpio.o
 obj-$(CONFIG_DB8500_GPIO)	+= db8500_gpio.o
@@ -25,7 +25,7 @@
 	u32	gpicr;
 };
  
-struct mpc85xx_gpio_data {
+struct mpc8xxx_gpio_data {
 	/* The bank's register base in memory */
 	struct ccsr_gpio __iomem *base;
 	/* The address of the registers; used to identify the bank */
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
@@ -44,130 +44,130 @@
 	return (1U << (31 - (gpio)));
 }
  
-static inline u32 mpc85xx_gpio_get_val(struct ccsr_gpio *base, u32 mask)
+static inline u32 mpc8xxx_gpio_get_val(struct ccsr_gpio *base, u32 mask)
 {
 	return in_be32(&base->gpdat) & mask;
 }
  
-static inline u32 mpc85xx_gpio_get_dir(struct ccsr_gpio *base, u32 mask)
+static inline u32 mpc8xxx_gpio_get_dir(struct ccsr_gpio *base, u32 mask)
 {
 	return in_be32(&base->gpdir) & mask;
 }
  
-static inline void mpc85xx_gpio_set_in(struct ccsr_gpio *base, u32 gpios)
+static inline void mpc8xxx_gpio_set_in(struct ccsr_gpio *base, u32 gpios)
 {
 	clrbits_be32(&base->gpdat, gpios);
 	/* GPDIR register 0 -> input */
 	clrbits_be32(&base->gpdir, gpios);
 }
  
-static inline void mpc85xx_gpio_set_low(struct ccsr_gpio *base, u32 gpios)
+static inline void mpc8xxx_gpio_set_low(struct ccsr_gpio *base, u32 gpios)
 {
 	clrbits_be32(&base->gpdat, gpios);
 	/* GPDIR register 1 -> output */
 	setbits_be32(&base->gpdir, gpios);
 }
  
-static inline void mpc85xx_gpio_set_high(struct ccsr_gpio *base, u32 gpios)
+static inline void mpc8xxx_gpio_set_high(struct ccsr_gpio *base, u32 gpios)
 {
 	setbits_be32(&base->gpdat, gpios);
 	/* GPDIR register 1 -> output */
 	setbits_be32(&base->gpdir, gpios);
 }
  
-static inline int mpc85xx_gpio_open_drain_val(struct ccsr_gpio *base, u32 mask)
+static inline int mpc8xxx_gpio_open_drain_val(struct ccsr_gpio *base, u32 mask)
 {
 	return in_be32(&base->gpodr) & mask;
 }
  
-static inline void mpc85xx_gpio_open_drain_on(struct ccsr_gpio *base, u32
+static inline void mpc8xxx_gpio_open_drain_on(struct ccsr_gpio *base, u32
 					      gpios)
 {
 	/* GPODR register 1 -> open drain on */
 	setbits_be32(&base->gpodr, gpios);
 }
  
-static inline void mpc85xx_gpio_open_drain_off(struct ccsr_gpio *base,
+static inline void mpc8xxx_gpio_open_drain_off(struct ccsr_gpio *base,
 					       u32 gpios)
 {
 	/* GPODR register 0 -> open drain off (actively driven) */
 	clrbits_be32(&base->gpodr, gpios);
 }
  
-static int mpc85xx_gpio_direction_input(struct udevice *dev, uint gpio)
+static int mpc8xxx_gpio_direction_input(struct udevice *dev, uint gpio)
 {
-	struct mpc85xx_gpio_data *data = dev_get_priv(dev);
+	struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
  
-	mpc85xx_gpio_set_in(data->base, gpio_mask(gpio));
+	mpc8xxx_gpio_set_in(data->base, gpio_mask(gpio));
 	return 0;
 }
  
-static int mpc85xx_gpio_set_value(struct udevice *dev, uint gpio, int value)
+static int mpc8xxx_gpio_set_value(struct udevice *dev, uint gpio, int value)
 {
-	struct mpc85xx_gpio_data *data = dev_get_priv(dev);
+	struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
  
 	if (value) {
 		data->dat_shadow |= gpio_mask(gpio);
-		mpc85xx_gpio_set_high(data->base, gpio_mask(gpio));
+		mpc8xxx_gpio_set_high(data->base, gpio_mask(gpio));
 	} else {
 		data->dat_shadow &= ~gpio_mask(gpio);
-		mpc85xx_gpio_set_low(data->base, gpio_mask(gpio));
+		mpc8xxx_gpio_set_low(data->base, gpio_mask(gpio));
 	}
 	return 0;
 }
  
-static int mpc85xx_gpio_direction_output(struct udevice *dev, uint gpio,
+static int mpc8xxx_gpio_direction_output(struct udevice *dev, uint gpio,
 					 int value)
 {
-	return mpc85xx_gpio_set_value(dev, gpio, value);
+	return mpc8xxx_gpio_set_value(dev, gpio, value);
 }
  
-static int mpc85xx_gpio_get_value(struct udevice *dev, uint gpio)
+static int mpc8xxx_gpio_get_value(struct udevice *dev, uint gpio)
 {
-	struct mpc85xx_gpio_data *data = dev_get_priv(dev);
+	struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
  
-	if (!!mpc85xx_gpio_get_dir(data->base, gpio_mask(gpio))) {
+	if (!!mpc8xxx_gpio_get_dir(data->base, gpio_mask(gpio))) {
 		/* Output -> use shadowed value */
 		return !!(data->dat_shadow & gpio_mask(gpio));
 	}
  
 	/* Input -> read value from GPDAT register */
-	return !!mpc85xx_gpio_get_val(data->base, gpio_mask(gpio));
+	return !!mpc8xxx_gpio_get_val(data->base, gpio_mask(gpio));
 }
  
-static int mpc85xx_gpio_get_open_drain(struct udevice *dev, uint gpio)
+static int mpc8xxx_gpio_get_open_drain(struct udevice *dev, uint gpio)
 {
-	struct mpc85xx_gpio_data *data = dev_get_priv(dev);
+	struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
  
-	return !!mpc85xx_gpio_open_drain_val(data->base, gpio_mask(gpio));
+	return !!mpc8xxx_gpio_open_drain_val(data->base, gpio_mask(gpio));
 }
  
-static int mpc85xx_gpio_set_open_drain(struct udevice *dev, uint gpio,
+static int mpc8xxx_gpio_set_open_drain(struct udevice *dev, uint gpio,
 				       int value)
 {
-	struct mpc85xx_gpio_data *data = dev_get_priv(dev);
+	struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
  
 	if (value)
-		mpc85xx_gpio_open_drain_on(data->base, gpio_mask(gpio));
+		mpc8xxx_gpio_open_drain_on(data->base, gpio_mask(gpio));
 	else
-		mpc85xx_gpio_open_drain_off(data->base, gpio_mask(gpio));
+		mpc8xxx_gpio_open_drain_off(data->base, gpio_mask(gpio));
  
 	return 0;
 }
  
-static int mpc85xx_gpio_get_function(struct udevice *dev, uint gpio)
+static int mpc8xxx_gpio_get_function(struct udevice *dev, uint gpio)
 {
-	struct mpc85xx_gpio_data *data = dev_get_priv(dev);
+	struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
 	int dir;
  
-	dir = !!mpc85xx_gpio_get_dir(data->base, gpio_mask(gpio));
+	dir = !!mpc8xxx_gpio_get_dir(data->base, gpio_mask(gpio));
 	return dir ? GPIOF_OUTPUT : GPIOF_INPUT;
 }
  
 #if CONFIG_IS_ENABLED(OF_CONTROL)
-static int mpc85xx_gpio_ofdata_to_platdata(struct udevice *dev)
+static int mpc8xxx_gpio_ofdata_to_platdata(struct udevice *dev)
 {
-	struct mpc85xx_gpio_plat *plat = dev_get_platdata(dev);
+	struct mpc8xxx_gpio_plat *plat = dev_get_platdata(dev);
 	fdt_addr_t addr;
 	fdt_size_t size;
  
  
@@ -183,10 +183,10 @@
 }
 #endif
  
-static int mpc85xx_gpio_platdata_to_priv(struct udevice *dev)
+static int mpc8xxx_gpio_platdata_to_priv(struct udevice *dev)
 {
-	struct mpc85xx_gpio_data *priv = dev_get_priv(dev);
-	struct mpc85xx_gpio_plat *plat = dev_get_platdata(dev);
+	struct mpc8xxx_gpio_data *priv = dev_get_priv(dev);
+	struct mpc8xxx_gpio_plat *plat = dev_get_platdata(dev);
 	unsigned long size = plat->size;
  
 	if (size == 0)
  
  
  
@@ -201,16 +201,18 @@
 	priv->gpio_count = plat->ngpios;
 	priv->dat_shadow = 0;
  
+	priv->type = driver_data;
+
 	return 0;
 }
  
-static int mpc85xx_gpio_probe(struct udevice *dev)
+static int mpc8xxx_gpio_probe(struct udevice *dev)
 {
 	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
-	struct mpc85xx_gpio_data *data = dev_get_priv(dev);
+	struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
 	char name[32], *str;
  
-	mpc85xx_gpio_platdata_to_priv(dev);
+	mpc8xxx_gpio_platdata_to_priv(dev);
  
 	snprintf(name, sizeof(name), "MPC@%lx_", data->addr);
 	str = strdup(name);
  
  
  
  
  
@@ -224,31 +226,31 @@
 	return 0;
 }
  
-static const struct dm_gpio_ops gpio_mpc85xx_ops = {
-	.direction_input	= mpc85xx_gpio_direction_input,
-	.direction_output	= mpc85xx_gpio_direction_output,
-	.get_value		= mpc85xx_gpio_get_value,
-	.set_value		= mpc85xx_gpio_set_value,
-	.get_open_drain		= mpc85xx_gpio_get_open_drain,
-	.set_open_drain		= mpc85xx_gpio_set_open_drain,
-	.get_function		= mpc85xx_gpio_get_function,
+static const struct dm_gpio_ops gpio_mpc8xxx_ops = {
+	.direction_input	= mpc8xxx_gpio_direction_input,
+	.direction_output	= mpc8xxx_gpio_direction_output,
+	.get_value		= mpc8xxx_gpio_get_value,
+	.set_value		= mpc8xxx_gpio_set_value,
+	.get_open_drain		= mpc8xxx_gpio_get_open_drain,
+	.set_open_drain		= mpc8xxx_gpio_set_open_drain,
+	.get_function		= mpc8xxx_gpio_get_function,
 };
  
-static const struct udevice_id mpc85xx_gpio_ids[] = {
+static const struct udevice_id mpc8xxx_gpio_ids[] = {
 	{ .compatible = "fsl,pq3-gpio" },
 	{ /* sentinel */ }
 };
  
-U_BOOT_DRIVER(gpio_mpc85xx) = {
-	.name	= "gpio_mpc85xx",
+U_BOOT_DRIVER(gpio_mpc8xxx) = {
+	.name	= "gpio_mpc8xxx",
 	.id	= UCLASS_GPIO,
-	.ops	= &gpio_mpc85xx_ops,
+	.ops	= &gpio_mpc8xxx_ops,
 #if CONFIG_IS_ENABLED(OF_CONTROL)
-	.ofdata_to_platdata = mpc85xx_gpio_ofdata_to_platdata,
-	.platdata_auto_alloc_size = sizeof(struct mpc85xx_gpio_plat),
-	.of_match = mpc85xx_gpio_ids,
+	.ofdata_to_platdata = mpc8xxx_gpio_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct mpc8xxx_gpio_plat),
+	.of_match = mpc8xxx_gpio_ids,
 #endif
-	.probe	= mpc85xx_gpio_probe,
-	.priv_auto_alloc_size = sizeof(struct mpc85xx_gpio_data),
+	.probe	= mpc8xxx_gpio_probe,
+	.priv_auto_alloc_size = sizeof(struct mpc8xxx_gpio_data),
 };
...	...	@@ -18,7 +18,7 @@
18	18	#include <asm/mpc85xx_gpio.h>
19	19	#endif
20	20
21		-struct mpc85xx_gpio_plat {
	21	+struct mpc8xxx_gpio_plat {
22	22	ulong addr;
23	23	unsigned long size;
24	24	uint ngpios;
...	...	@@ -276,11 +276,11 @@
276	276	Now, max 24 bits chips and PCA953X compatible chips are
277	277	supported
278	278
279		-config MPC85XX_GPIO
280		- bool "Freescale MPC85XX GPIO driver"
	279	+config MPC8XXX_GPIO
	280	+ bool "Freescale MPC8XXX GPIO driver"
281	281	depends on DM_GPIO
282	282	help
283		- This driver supports the built-in GPIO controller of MPC85XX CPUs.
	283	+ This driver supports the built-in GPIO controller of MPC8XXX CPUs.
284	284	Each GPIO bank is identified by its own entry in the device tree,
285	285	i.e.
286	286
...	...	@@ -298,8 +298,5 @@
298	298	Aside from the standard functions of input/output mode, and output
299	299	value setting, the open-drain feature, which can configure individual
300	300	GPIOs to work as open-drain outputs, is supported.
301		-
302		- The driver has been tested on MPC85XX, but it is likely that other
303		- PowerQUICC III devices will work as well.
304	301	endmenu
...	...	@@ -38,7 +38,7 @@
38	38	obj-$(CONFIG_DM644X_GPIO) += da8xx_gpio.o
39	39	obj-$(CONFIG_ALTERA_PIO) += altera_pio.o
40	40	obj-$(CONFIG_MPC83XX_GPIO) += mpc83xx_gpio.o
41		-obj-$(CONFIG_MPC85XX_GPIO) += mpc8xxx_gpio.o
	41	+obj-$(CONFIG_MPC8XXX_GPIO) += mpc8xxx_gpio.o
42	42	obj-$(CONFIG_SH_GPIO_PFC) += sh_pfc.o
43	43	obj-$(CONFIG_OMAP_GPIO) += omap_gpio.o
44	44	obj-$(CONFIG_DB8500_GPIO) += db8500_gpio.o
...	...	@@ -25,7 +25,7 @@
25	25	u32 gpicr;
26	26	};
27	27
28		-struct mpc85xx_gpio_data {
	28	+struct mpc8xxx_gpio_data {
29	29	/* The bank's register base in memory */
30	30	struct ccsr_gpio __iomem *base;
31	31	/* The address of the registers; used to identify the bank */
32	32
33	33
34	34
35	35
36	36
37	37
38	38
39	39
40	40
41	41
42	42
43	43
44	44
45	45
46	46
47	47
48	48
49	49
50	50
51	51
52	52
53	53
54	54
55	55
56	56
57	57
58	58
59	59
60	60
61	61
62	62
63	63
...	...	@@ -44,130 +44,130 @@
44	44	return (1U << (31 - (gpio)));
45	45	}
46	46
47		-static inline u32 mpc85xx_gpio_get_val(struct ccsr_gpio *base, u32 mask)
	47	+static inline u32 mpc8xxx_gpio_get_val(struct ccsr_gpio *base, u32 mask)
48	48	{
49	49	return in_be32(&base->gpdat) & mask;
50	50	}
51	51
52		-static inline u32 mpc85xx_gpio_get_dir(struct ccsr_gpio *base, u32 mask)
	52	+static inline u32 mpc8xxx_gpio_get_dir(struct ccsr_gpio *base, u32 mask)
53	53	{
54	54	return in_be32(&base->gpdir) & mask;
55	55	}
56	56
57		-static inline void mpc85xx_gpio_set_in(struct ccsr_gpio *base, u32 gpios)
	57	+static inline void mpc8xxx_gpio_set_in(struct ccsr_gpio *base, u32 gpios)
58	58	{
59	59	clrbits_be32(&base->gpdat, gpios);
60	60	/* GPDIR register 0 -> input */
61	61	clrbits_be32(&base->gpdir, gpios);
62	62	}
63	63
64		-static inline void mpc85xx_gpio_set_low(struct ccsr_gpio *base, u32 gpios)
	64	+static inline void mpc8xxx_gpio_set_low(struct ccsr_gpio *base, u32 gpios)
65	65	{
66	66	clrbits_be32(&base->gpdat, gpios);
67	67	/* GPDIR register 1 -> output */
68	68	setbits_be32(&base->gpdir, gpios);
69	69	}
70	70
71		-static inline void mpc85xx_gpio_set_high(struct ccsr_gpio *base, u32 gpios)
	71	+static inline void mpc8xxx_gpio_set_high(struct ccsr_gpio *base, u32 gpios)
72	72	{
73	73	setbits_be32(&base->gpdat, gpios);
74	74	/* GPDIR register 1 -> output */
75	75	setbits_be32(&base->gpdir, gpios);
76	76	}
77	77
78		-static inline int mpc85xx_gpio_open_drain_val(struct ccsr_gpio *base, u32 mask)
	78	+static inline int mpc8xxx_gpio_open_drain_val(struct ccsr_gpio *base, u32 mask)
79	79	{
80	80	return in_be32(&base->gpodr) & mask;
81	81	}
82	82
83		-static inline void mpc85xx_gpio_open_drain_on(struct ccsr_gpio *base, u32
	83	+static inline void mpc8xxx_gpio_open_drain_on(struct ccsr_gpio *base, u32
84	84	gpios)
85	85	{
86	86	/* GPODR register 1 -> open drain on */
87	87	setbits_be32(&base->gpodr, gpios);
88	88	}
89	89
90		-static inline void mpc85xx_gpio_open_drain_off(struct ccsr_gpio *base,
	90	+static inline void mpc8xxx_gpio_open_drain_off(struct ccsr_gpio *base,
91	91	u32 gpios)
92	92	{
93	93	/* GPODR register 0 -> open drain off (actively driven) */
94	94	clrbits_be32(&base->gpodr, gpios);
95	95	}
96	96
97		-static int mpc85xx_gpio_direction_input(struct udevice *dev, uint gpio)
	97	+static int mpc8xxx_gpio_direction_input(struct udevice *dev, uint gpio)
98	98	{
99		- struct mpc85xx_gpio_data *data = dev_get_priv(dev);
	99	+ struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
100	100
101		- mpc85xx_gpio_set_in(data->base, gpio_mask(gpio));
	101	+ mpc8xxx_gpio_set_in(data->base, gpio_mask(gpio));
102	102	return 0;
103	103	}
104	104
105		-static int mpc85xx_gpio_set_value(struct udevice *dev, uint gpio, int value)
	105	+static int mpc8xxx_gpio_set_value(struct udevice *dev, uint gpio, int value)
106	106	{
107		- struct mpc85xx_gpio_data *data = dev_get_priv(dev);
	107	+ struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
108	108
109	109	if (value) {
110	110	data->dat_shadow \|= gpio_mask(gpio);
111		- mpc85xx_gpio_set_high(data->base, gpio_mask(gpio));
	111	+ mpc8xxx_gpio_set_high(data->base, gpio_mask(gpio));
112	112	} else {
113	113	data->dat_shadow &= ~gpio_mask(gpio);
114		- mpc85xx_gpio_set_low(data->base, gpio_mask(gpio));
	114	+ mpc8xxx_gpio_set_low(data->base, gpio_mask(gpio));
115	115	}
116	116	return 0;
117	117	}
118	118
119		-static int mpc85xx_gpio_direction_output(struct udevice *dev, uint gpio,
	119	+static int mpc8xxx_gpio_direction_output(struct udevice *dev, uint gpio,
120	120	int value)
121	121	{
122		- return mpc85xx_gpio_set_value(dev, gpio, value);
	122	+ return mpc8xxx_gpio_set_value(dev, gpio, value);
123	123	}
124	124
125		-static int mpc85xx_gpio_get_value(struct udevice *dev, uint gpio)
	125	+static int mpc8xxx_gpio_get_value(struct udevice *dev, uint gpio)
126	126	{
127		- struct mpc85xx_gpio_data *data = dev_get_priv(dev);
	127	+ struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
128	128
129		- if (!!mpc85xx_gpio_get_dir(data->base, gpio_mask(gpio))) {
	129	+ if (!!mpc8xxx_gpio_get_dir(data->base, gpio_mask(gpio))) {
130	130	/* Output -> use shadowed value */
131	131	return !!(data->dat_shadow & gpio_mask(gpio));
132	132	}
133	133
134	134	/* Input -> read value from GPDAT register */
135		- return !!mpc85xx_gpio_get_val(data->base, gpio_mask(gpio));
	135	+ return !!mpc8xxx_gpio_get_val(data->base, gpio_mask(gpio));
136	136	}
137	137
138		-static int mpc85xx_gpio_get_open_drain(struct udevice *dev, uint gpio)
	138	+static int mpc8xxx_gpio_get_open_drain(struct udevice *dev, uint gpio)
139	139	{
140		- struct mpc85xx_gpio_data *data = dev_get_priv(dev);
	140	+ struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
141	141
142		- return !!mpc85xx_gpio_open_drain_val(data->base, gpio_mask(gpio));
	142	+ return !!mpc8xxx_gpio_open_drain_val(data->base, gpio_mask(gpio));
143	143	}
144	144
145		-static int mpc85xx_gpio_set_open_drain(struct udevice *dev, uint gpio,
	145	+static int mpc8xxx_gpio_set_open_drain(struct udevice *dev, uint gpio,
146	146	int value)
147	147	{
148		- struct mpc85xx_gpio_data *data = dev_get_priv(dev);
	148	+ struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
149	149
150	150	if (value)
151		- mpc85xx_gpio_open_drain_on(data->base, gpio_mask(gpio));
	151	+ mpc8xxx_gpio_open_drain_on(data->base, gpio_mask(gpio));
152	152	else
153		- mpc85xx_gpio_open_drain_off(data->base, gpio_mask(gpio));
	153	+ mpc8xxx_gpio_open_drain_off(data->base, gpio_mask(gpio));
154	154
155	155	return 0;
156	156	}
157	157
158		-static int mpc85xx_gpio_get_function(struct udevice *dev, uint gpio)
	158	+static int mpc8xxx_gpio_get_function(struct udevice *dev, uint gpio)
159	159	{
160		- struct mpc85xx_gpio_data *data = dev_get_priv(dev);
	160	+ struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
161	161	int dir;
162	162
163		- dir = !!mpc85xx_gpio_get_dir(data->base, gpio_mask(gpio));
	163	+ dir = !!mpc8xxx_gpio_get_dir(data->base, gpio_mask(gpio));
164	164	return dir ? GPIOF_OUTPUT : GPIOF_INPUT;
165	165	}
166	166
167	167	#if CONFIG_IS_ENABLED(OF_CONTROL)
168		-static int mpc85xx_gpio_ofdata_to_platdata(struct udevice *dev)
	168	+static int mpc8xxx_gpio_ofdata_to_platdata(struct udevice *dev)
169	169	{
170		- struct mpc85xx_gpio_plat *plat = dev_get_platdata(dev);
	170	+ struct mpc8xxx_gpio_plat *plat = dev_get_platdata(dev);
171	171	fdt_addr_t addr;
172	172	fdt_size_t size;
173	173
174	174
...	...	@@ -183,10 +183,10 @@
183	183	}
184	184	#endif
185	185
186		-static int mpc85xx_gpio_platdata_to_priv(struct udevice *dev)
	186	+static int mpc8xxx_gpio_platdata_to_priv(struct udevice *dev)
187	187	{
188		- struct mpc85xx_gpio_data *priv = dev_get_priv(dev);
189		- struct mpc85xx_gpio_plat *plat = dev_get_platdata(dev);
	188	+ struct mpc8xxx_gpio_data *priv = dev_get_priv(dev);
	189	+ struct mpc8xxx_gpio_plat *plat = dev_get_platdata(dev);
190	190	unsigned long size = plat->size;
191	191
192	192	if (size == 0)
193	193
194	194
195	195
...	...	@@ -201,16 +201,18 @@
201	201	priv->gpio_count = plat->ngpios;
202	202	priv->dat_shadow = 0;
203	203
	204	+ priv->type = driver_data;
	205	+
204	206	return 0;
205	207	}
206	208
207		-static int mpc85xx_gpio_probe(struct udevice *dev)
	209	+static int mpc8xxx_gpio_probe(struct udevice *dev)
208	210	{
209	211	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
210		- struct mpc85xx_gpio_data *data = dev_get_priv(dev);
	212	+ struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
211	213	char name[32], *str;
212	214
213		- mpc85xx_gpio_platdata_to_priv(dev);
	215	+ mpc8xxx_gpio_platdata_to_priv(dev);
214	216
215	217	snprintf(name, sizeof(name), "MPC@%lx_", data->addr);
216	218	str = strdup(name);
217	219
218	220
219	221
220	222
221	223
...	...	@@ -224,31 +226,31 @@
224	226	return 0;
225	227	}
226	228
227		-static const struct dm_gpio_ops gpio_mpc85xx_ops = {
228		- .direction_input = mpc85xx_gpio_direction_input,
229		- .direction_output = mpc85xx_gpio_direction_output,
230		- .get_value = mpc85xx_gpio_get_value,
231		- .set_value = mpc85xx_gpio_set_value,
232		- .get_open_drain = mpc85xx_gpio_get_open_drain,
233		- .set_open_drain = mpc85xx_gpio_set_open_drain,
234		- .get_function = mpc85xx_gpio_get_function,
	229	+static const struct dm_gpio_ops gpio_mpc8xxx_ops = {
	230	+ .direction_input = mpc8xxx_gpio_direction_input,
	231	+ .direction_output = mpc8xxx_gpio_direction_output,
	232	+ .get_value = mpc8xxx_gpio_get_value,
	233	+ .set_value = mpc8xxx_gpio_set_value,
	234	+ .get_open_drain = mpc8xxx_gpio_get_open_drain,
	235	+ .set_open_drain = mpc8xxx_gpio_set_open_drain,
	236	+ .get_function = mpc8xxx_gpio_get_function,
235	237	};
236	238
237		-static const struct udevice_id mpc85xx_gpio_ids[] = {
	239	+static const struct udevice_id mpc8xxx_gpio_ids[] = {
238	240	{ .compatible = "fsl,pq3-gpio" },
239	241	{ /* sentinel */ }
240	242	};
241	243
242		-U_BOOT_DRIVER(gpio_mpc85xx) = {
243		- .name = "gpio_mpc85xx",
	244	+U_BOOT_DRIVER(gpio_mpc8xxx) = {
	245	+ .name = "gpio_mpc8xxx",
244	246	.id = UCLASS_GPIO,
245		- .ops = &gpio_mpc85xx_ops,
	247	+ .ops = &gpio_mpc8xxx_ops,
246	248	#if CONFIG_IS_ENABLED(OF_CONTROL)
247		- .ofdata_to_platdata = mpc85xx_gpio_ofdata_to_platdata,
248		- .platdata_auto_alloc_size = sizeof(struct mpc85xx_gpio_plat),
249		- .of_match = mpc85xx_gpio_ids,
	249	+ .ofdata_to_platdata = mpc8xxx_gpio_ofdata_to_platdata,
	250	+ .platdata_auto_alloc_size = sizeof(struct mpc8xxx_gpio_plat),
	251	+ .of_match = mpc8xxx_gpio_ids,
250	252	#endif
251		- .probe = mpc85xx_gpio_probe,
252		- .priv_auto_alloc_size = sizeof(struct mpc85xx_gpio_data),
	253	+ .probe = mpc8xxx_gpio_probe,
	254	+ .priv_auto_alloc_size = sizeof(struct mpc8xxx_gpio_data),
253	255	};