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Commit 3c5628ccf4459bef29471889b9af255a388244fa

Authored by Anson Huang
1 parent 9ebc498844
Exists in smarc-rel_imx_4.1.15_2.0.0_ga

MLK-12748-3 imx: adjust imx7d lpddr3 lpsr exit flow 

On i.MX7D lpddr3, retention mode exit flow should restore
more registers to make sure the ddr controller and ddr phy
settings restored properly, otherwise, some of the boards
can NOT pass memtester after retention mode exited.

For LPSR mode, ddr resume flow is same as retention mode,
just adjust it accordingly.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

Showing 1 changed file with 13 additions and 1 deletions Inline Diff

board/freescale/mx7d_12x12_lpddr3_arm2/plugin.S
Diff comments   View file @ 3c5628c
1 /* 1 /*
2 * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. 2 * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #include <config.h> 7 #include <config.h>
8 8
9 /* DDR script */ 9 /* DDR script */
10 .macro imx7d_ddrphy_latency_setting 10 .macro imx7d_ddrphy_latency_setting
11 ldr r2, =ANATOP_BASE_ADDR 11 ldr r2, =ANATOP_BASE_ADDR
12 ldr r3, [r2, #0x800] 12 ldr r3, [r2, #0x800]
13 and r3, r3, #0xFF 13 and r3, r3, #0xFF
14 cmp r3, #0x11 14 cmp r3, #0x11
15 bne TUNE_END 15 bne TUNE_END
16 16
17 /*TO 1.1*/ 17 /*TO 1.1*/
18 ldr r1, =0x1c1c1c1c 18 ldr r1, =0x1c1c1c1c
19 str r1, [r0, #0x7c] 19 str r1, [r0, #0x7c]
20 ldr r1, =0x1c1c1c1c 20 ldr r1, =0x1c1c1c1c
21 str r1, [r0, #0x80] 21 str r1, [r0, #0x80]
22 ldr r1, =0x30301c1c 22 ldr r1, =0x30301c1c
23 str r1, [r0, #0x84] 23 str r1, [r0, #0x84]
24 ldr r1, =0x00000030 24 ldr r1, =0x00000030
25 str r1, [r0, #0x88] 25 str r1, [r0, #0x88]
26 ldr r1, =0x30303030 26 ldr r1, =0x30303030
27 str r1, [r0, #0x6c] 27 str r1, [r0, #0x6c]
28 28
29 TUNE_END: 29 TUNE_END:
30 .endm 30 .endm
31 31
32 .macro imx7d_12x12_lpddr3_arm2_setting 32 .macro imx7d_12x12_lpddr3_arm2_setting
33 33
34 /* check whether it is a LPSR resume */ 34 /* check whether it is a LPSR resume */
35 ldr r1, =0x30270000 35 ldr r1, =0x30270000
36 ldr r7, [r1] 36 ldr r7, [r1]
37 cmp r7, #0 37 cmp r7, #0
38 beq 16f 38 beq 16f
39 39
40 /* disable wdog powerdown counter */ 40 /* disable wdog powerdown counter */
41 ldr r0, =0x30280000 41 ldr r0, =0x30280000
42 ldrh r1, =0x0 42 ldrh r1, =0x0
43 strh r1, [r0, #0x8] 43 strh r1, [r0, #0x8]
44 44
45 /* initialize AIPs 1-3 port */ 45 /* initialize AIPs 1-3 port */
46 ldr r0, =0x301f0000 46 ldr r0, =0x301f0000
47 ldr r1, =0x77777777 47 ldr r1, =0x77777777
48 str r1, [r0] 48 str r1, [r0]
49 str r1, [r0, #0x4] 49 str r1, [r0, #0x4]
50 ldr r1, =0x0 50 ldr r1, =0x0
51 str r1, [r0, #0x40] 51 str r1, [r0, #0x40]
52 str r1, [r0, #0x44] 52 str r1, [r0, #0x44]
53 str r1, [r0, #0x48] 53 str r1, [r0, #0x48]
54 str r1, [r0, #0x4c] 54 str r1, [r0, #0x4c]
55 str r1, [r0, #0x50] 55 str r1, [r0, #0x50]
56 56
57 ldr r0, =0x305f0000 57 ldr r0, =0x305f0000
58 ldr r1, =0x77777777 58 ldr r1, =0x77777777
59 str r1, [r0] 59 str r1, [r0]
60 str r1, [r0, #0x4] 60 str r1, [r0, #0x4]
61 ldr r1, =0x0 61 ldr r1, =0x0
62 str r1, [r0, #0x40] 62 str r1, [r0, #0x40]
63 str r1, [r0, #0x44] 63 str r1, [r0, #0x44]
64 str r1, [r0, #0x48] 64 str r1, [r0, #0x48]
65 str r1, [r0, #0x4c] 65 str r1, [r0, #0x4c]
66 str r1, [r0, #0x50] 66 str r1, [r0, #0x50]
67 67
68 ldr r0, =0x309f0000 68 ldr r0, =0x309f0000
69 ldr r1, =0x77777777 69 ldr r1, =0x77777777
70 str r1, [r0] 70 str r1, [r0]
71 str r1, [r0, #0x4] 71 str r1, [r0, #0x4]
72 ldr r1, =0x0 72 ldr r1, =0x0
73 str r1, [r0, #0x40] 73 str r1, [r0, #0x40]
74 str r1, [r0, #0x44] 74 str r1, [r0, #0x44]
75 str r1, [r0, #0x48] 75 str r1, [r0, #0x48]
76 str r1, [r0, #0x4c] 76 str r1, [r0, #0x4c]
77 str r1, [r0, #0x50] 77 str r1, [r0, #0x50]
78 78
79 ldr r1, =0x30360000 79 ldr r1, =0x30360000
80 ldr r2, =0x30390000 80 ldr r2, =0x30390000
81 ldr r3, =0x307a0000 81 ldr r3, =0x307a0000
82 ldr r4, =0x30790000 82 ldr r4, =0x30790000
83 ldr r10, =0x30380000 83 ldr r10, =0x30380000
84 ldr r11, =0x30340000 84 ldr r11, =0x30340000
85 85
86 /* turn on ddr power */ 86 /* turn on ddr power */
87 ldr r7, =(0x1 << 29) 87 ldr r7, =(0x1 << 29)
88 str r7, [r1, #0x388] 88 str r7, [r1, #0x388]
89 89
90 ldr r6, =50 90 ldr r6, =50
91 1: 91 1:
92 subs r6, r6, #0x1 92 subs r6, r6, #0x1
93 bne 1b 93 bne 1b
94 94
95 /* clear ddr_phy reset */ 95 /* clear ddr_phy reset */
96 ldr r6, =0x1000 96 ldr r6, =0x1000
97 ldr r7, [r2, r6] 97 ldr r7, [r2, r6]
98 orr r7, r7, #0x3 98 orr r7, r7, #0x3
99 str r7, [r2, r6] 99 str r7, [r2, r6]
100 ldr r7, [r2, r6] 100 ldr r7, [r2, r6]
101 bic r7, r7, #0x1 101 bic r7, r7, #0x1
102 str r7, [r2, r6] 102 str r7, [r2, r6]
103 103
104 /* restore DDRC */ 104 /* restore DDRC */
105 ldr r6, =0x0 105 ldr r6, =0x0
106 ldr r7, =0x03040008 106 ldr r7, =0x03040008
107 str r7, [r3, r6] 107 str r7, [r3, r6]
108 108
109 ldr r6, =0x1a0 109 ldr r6, =0x1a0
110 ldr r7, =0x80400003 110 ldr r7, =0x80400003
111 str r7, [r3, r6] 111 str r7, [r3, r6]
112 112
113 ldr r6, =0x1a4 113 ldr r6, =0x1a4
114 ldr r7, =0x00100020 114 ldr r7, =0x00100020
115 str r7, [r3, r6] 115 str r7, [r3, r6]
116 116
117 ldr r6, =0x1a8 117 ldr r6, =0x1a8
118 ldr r7, =0x80100004 118 ldr r7, =0x80100004
119 str r7, [r3, r6] 119 str r7, [r3, r6]
120 120
121 ldr r6, =0x64 121 ldr r6, =0x64
122 ldr r7, =0x00200038 122 ldr r7, =0x00200038
123 str r7, [r3, r6] 123 str r7, [r3, r6]
124 124
125 ldr r6, =0xd0 125 ldr r6, =0xd0
126 ldr r7, =0xc0350001 126 ldr r7, =0xc0350001
127 str r7, [r3, r6] 127 str r7, [r3, r6]
128 128
129 ldr r6, =0xdc 129 ldr r6, =0xdc
130 ldr r7, =0x00C3000A 130 ldr r7, =0x00C3000A
131 str r7, [r3, r6] 131 str r7, [r3, r6]
132 132
133 ldr r6, =0xe0 133 ldr r6, =0xe0
134 ldr r7, =0x00010000 134 ldr r7, =0x00010000
135 str r7, [r3, r6] 135 str r7, [r3, r6]
136 136
137 ldr r6, =0xe4 137 ldr r6, =0xe4
138 ldr r7, =0x00110006 138 ldr r7, =0x00110006
139 str r7, [r3, r6] 139 str r7, [r3, r6]
140 140
141 ldr r6, =0xf4 141 ldr r6, =0xf4
142 ldr r7, =0x0000033F 142 ldr r7, =0x0000033F
143 str r7, [r3, r6] 143 str r7, [r3, r6]
144 144
145 ldr r6, =0x100 145 ldr r6, =0x100
146 ldr r7, =0x0A0E110B 146 ldr r7, =0x0A0E110B
147 str r7, [r3, r6] 147 str r7, [r3, r6]
148 148
149 ldr r6, =0x104 149 ldr r6, =0x104
150 ldr r7, =0x00020211 150 ldr r7, =0x00020211
151 str r7, [r3, r6] 151 str r7, [r3, r6]
152 152
153 ldr r6, =0x108 153 ldr r6, =0x108
154 ldr r7, =0x03060707 154 ldr r7, =0x03060708
155 str r7, [r3, r6] 155 str r7, [r3, r6]
156 156
157 ldr r6, =0x10c 157 ldr r6, =0x10c
158 ldr r7, =0x00A0500C 158 ldr r7, =0x00A0500C
159 str r7, [r3, r6] 159 str r7, [r3, r6]
160 160
161 ldr r6, =0x110 161 ldr r6, =0x110
162 ldr r7, =0x05020307 162 ldr r7, =0x05020307
163 str r7, [r3, r6] 163 str r7, [r3, r6]
164 164
165 ldr r6, =0x114 165 ldr r6, =0x114
166 ldr r7, =0x02020404 166 ldr r7, =0x02020404
167 str r7, [r3, r6] 167 str r7, [r3, r6]
168 168
169 ldr r6, =0x118 169 ldr r6, =0x118
170 ldr r7, =0x02020003 170 ldr r7, =0x02020003
171 str r7, [r3, r6] 171 str r7, [r3, r6]
172 172
173 ldr r6, =0x11c 173 ldr r6, =0x11c
174 ldr r7, =0x00000202 174 ldr r7, =0x00000202
175 str r7, [r3, r6] 175 str r7, [r3, r6]
176 176
177 ldr r6, =0x120
178 ldr r7, =0x00000202
179 str r7, [r3, r6]
180
177 ldr r6, =0x180 181 ldr r6, =0x180
178 ldr r7, =0x00600018 182 ldr r7, =0x00600018
179 str r7, [r3, r6] 183 str r7, [r3, r6]
180 184
181 ldr r6, =0x184 185 ldr r6, =0x184
182 ldr r7, =0x00e00100 186 ldr r7, =0x00e00100
183 str r7, [r3, r6] 187 str r7, [r3, r6]
184 188
185 ldr r6, =0x190 189 ldr r6, =0x190
186 ldr r7, =0x02098205 190 ldr r7, =0x02098205
187 str r7, [r3, r6] 191 str r7, [r3, r6]
188 192
189 ldr r6, =0x194 193 ldr r6, =0x194
190 ldr r7, =0x00060303 194 ldr r7, =0x00060303
191 str r7, [r3, r6] 195 str r7, [r3, r6]
192 196
193 ldr r6, =0x200 197 ldr r6, =0x200
194 ldr r7, =0x00000016 198 ldr r7, =0x00000016
195 str r7, [r3, r6] 199 str r7, [r3, r6]
196 200
197 ldr r6, =0x204 201 ldr r6, =0x204
198 ldr r7, =0x00171717 202 ldr r7, =0x00171717
199 str r7, [r3, r6] 203 str r7, [r3, r6]
200 204
205 ldr r6, =0x210
206 ldr r7, =0xF00
207 str r7, [r3, r6]
208
201 ldr r6, =0x214 209 ldr r6, =0x214
202 ldr r7, =0x05050505 210 ldr r7, =0x05050505
203 str r7, [r3, r6] 211 str r7, [r3, r6]
204 212
205 ldr r6, =0x218 213 ldr r6, =0x218
206 ldr r7, =0x0F0F0505 214 ldr r7, =0x0F0F0505
207 str r7, [r3, r6] 215 str r7, [r3, r6]
208 216
209 ldr r6, =0x240 217 ldr r6, =0x240
210 ldr r7, =0x06000601 218 ldr r7, =0x06000601
211 str r7, [r3, r6] 219 str r7, [r3, r6]
212 220
213 ldr r6, =0x244 221 ldr r6, =0x244
214 ldr r7, =0x00000000 222 ldr r7, =0x00000000
215 str r7, [r3, r6] 223 str r7, [r3, r6]
216 224
217 ldr r7, =0x20 225 ldr r7, =0x20
218 str r7, [r3, #0x30] 226 str r7, [r3, #0x30]
219 ldr r7, =0x0 227 ldr r7, =0x0
220 str r7, [r3, #0x1b0] 228 str r7, [r3, #0x1b0]
221 229
222 /* do PHY, clear ddr_phy reset */ 230 /* do PHY, clear ddr_phy reset */
223 ldr r6, =0x1000 231 ldr r6, =0x1000
224 ldr r7, [r2, r6] 232 ldr r7, [r2, r6]
225 bic r7, r7, #0x2 233 bic r7, r7, #0x2
226 str r7, [r2, r6] 234 str r7, [r2, r6]
227 235
228 ldr r7, [r1, #0x800] 236 ldr r7, [r1, #0x800]
229 and r7, r7, #0xFF 237 and r7, r7, #0xFF
230 cmp r7, #0x11 238 cmp r7, #0x11
231 bne 2f 239 bne 2f
232 240
233 /* for TO1.1 */ 241 /* for TO1.1 */
234 ldr r7, [r11] 242 ldr r7, [r11]
235 bic r7, r7, #(1 << 27) 243 bic r7, r7, #(1 << 27)
236 str r7, [r11] 244 str r7, [r11]
237 ldr r7, [r11] 245 ldr r7, [r11]
238 bic r7, r7, #(1 << 29) 246 bic r7, r7, #(1 << 29)
239 str r7, [r11] 247 str r7, [r11]
240 2: 248 2:
241 /* clear/set bit30 of SNVS_MISC_CTRL to ensure exit from ddr retention */ 249 /* clear/set bit30 of SNVS_MISC_CTRL to ensure exit from ddr retention */
242 ldr r7, =(0x1 << 30) 250 ldr r7, =(0x1 << 30)
243 str r7, [r1, #0x388] 251 str r7, [r1, #0x388]
244 ldr r7, =(0x1 << 30) 252 ldr r7, =(0x1 << 30)
245 str r7, [r1, #0x384] 253 str r7, [r1, #0x384]
246 254
247 /* need to delay ~5mS */ 255 /* need to delay ~5mS */
248 ldr r6, =0x100000 256 ldr r6, =0x100000
249 3: 257 3:
250 subs r6, r6, #0x1 258 subs r6, r6, #0x1
251 bne 3b 259 bne 3b
252 260
253 /* restore DDR PHY */ 261 /* restore DDR PHY */
254 ldr r6, =0x0 262 ldr r6, =0x0
255 ldr r7, =0x17421E40 263 ldr r7, =0x17421E40
256 str r7, [r4, r6] 264 str r7, [r4, r6]
257 265
258 ldr r6, =0x4 266 ldr r6, =0x4
259 ldr r7, =0x10210100 267 ldr r7, =0x10210100
260 str r7, [r4, r6] 268 str r7, [r4, r6]
261 269
262 ldr r6, =0x8 270 ldr r6, =0x8
263 ldr r7, =0x00010000 271 ldr r7, =0x00010000
264 str r7, [r4, r6] 272 str r7, [r4, r6]
265 273
266 ldr r6, =0x10 274 ldr r6, =0x10
267 ldr r7, =0x0007080C 275 ldr r7, =0x0007080C
276 str r7, [r4, r6]
277
278 ldr r6, =0xb0
279 ldr r7, =0x1010007e
268 str r7, [r4, r6] 280 str r7, [r4, r6]
269 281
270 ldr r7, [r1, #0x800] 282 ldr r7, [r1, #0x800]
271 and r7, r7, #0xFF 283 and r7, r7, #0xFF
272 cmp r7, #0x11 284 cmp r7, #0x11
273 bne 4f 285 bne 4f
274 286
275 ldr r6, =0x7c 287 ldr r6, =0x7c
276 ldr r7, =0x1c1c1c1c 288 ldr r7, =0x1c1c1c1c
277 str r7, [r4, r6] 289 str r7, [r4, r6]
278 290
279 ldr r6, =0x80 291 ldr r6, =0x80
280 ldr r7, =0x1c1c1c1c 292 ldr r7, =0x1c1c1c1c
281 str r7, [r4, r6] 293 str r7, [r4, r6]
282 294
283 ldr r6, =0x84 295 ldr r6, =0x84
284 ldr r7, =0x30301c1c 296 ldr r7, =0x30301c1c
285 str r7, [r4, r6] 297 str r7, [r4, r6]
286 298
287 ldr r6, =0x88 299 ldr r6, =0x88
288 ldr r7, =0x00000030 300 ldr r7, =0x00000030
289 str r7, [r4, r6] 301 str r7, [r4, r6]
290 302
291 ldr r6, =0x6c 303 ldr r6, =0x6c
292 ldr r7, =0x30303030 304 ldr r7, =0x30303030
293 str r7, [r4, r6] 305 str r7, [r4, r6]
294 306
295 4: 307 4:
296 ldr r6, =0x1c 308 ldr r6, =0x1c
297 ldr r7, =0x01010000 309 ldr r7, =0x01010000
298 str r7, [r4, r6] 310 str r7, [r4, r6]
299 311
300 ldr r6, =0x9c 312 ldr r6, =0x9c
301 ldr r7, =0x0DB60D6E 313 ldr r7, =0x0DB60D6E
302 str r7, [r4, r6] 314 str r7, [r4, r6]
303 315
304 ldr r6, =0x20 316 ldr r6, =0x20
305 ldr r7, =0x0a0a0a0a 317 ldr r7, =0x0a0a0a0a
306 str r7, [r4, r6] 318 str r7, [r4, r6]
307 319
308 ldr r6, =0x30 320 ldr r6, =0x30
309 ldr r7, =0x06060606 321 ldr r7, =0x06060606
310 str r7, [r4, r6] 322 str r7, [r4, r6]
311 323
312 ldr r6, =0x50 324 ldr r6, =0x50
313 ldr r7, =0x01000008 325 ldr r7, =0x01000008
314 str r7, [r4, r6] 326 str r7, [r4, r6]
315 327
316 ldr r6, =0x50 328 ldr r6, =0x50
317 ldr r7, =0x00000008 329 ldr r7, =0x00000008
318 str r7, [r4, r6] 330 str r7, [r4, r6]
319 331
320 ldr r6, =0xc0 332 ldr r6, =0xc0
321 ldr r7, =0x0e407304 333 ldr r7, =0x0e407304
322 str r7, [r4, r6] 334 str r7, [r4, r6]
323 335
324 ldr r6, =0xc0 336 ldr r6, =0xc0
325 ldr r7, =0x0e447304 337 ldr r7, =0x0e447304
326 str r7, [r4, r6] 338 str r7, [r4, r6]
327 339
328 ldr r6, =0xc0 340 ldr r6, =0xc0
329 ldr r7, =0x0e447306 341 ldr r7, =0x0e447306
330 str r7, [r4, r6] 342 str r7, [r4, r6]
331 343
332 ldr r6, =0xc0 344 ldr r6, =0xc0
333 ldr r7, =0x0e4c7304 345 ldr r7, =0x0e4c7304
334 str r7, [r4, r6] 346 str r7, [r4, r6]
335 347
336 ldr r6, =0xc0 348 ldr r6, =0xc0
337 ldr r7, =0x0e487306 349 ldr r7, =0x0e487306
338 str r7, [r4, r6] 350 str r7, [r4, r6]
339 351
340 ldr r7, =0x0 352 ldr r7, =0x0
341 add r9, r10, #0x4000 353 add r9, r10, #0x4000
342 str r7, [r9, #0x130] 354 str r7, [r9, #0x130]
343 355
344 ldr r7, =0x170 356 ldr r7, =0x170
345 orr r7, r7, #0x8 357 orr r7, r7, #0x8
346 str r7, [r11, #0x20] 358 str r7, [r11, #0x20]
347 359
348 ldr r7, =0x2 360 ldr r7, =0x2
349 add r9, r10, #0x4000 361 add r9, r10, #0x4000
350 str r7, [r9, #0x130] 362 str r7, [r9, #0x130]
351 363
352 ldr r7, =0xf 364 ldr r7, =0xf
353 str r7, [r4, #0x18] 365 str r7, [r4, #0x18]
354 366
355 /* wait until self-refresh mode entered */ 367 /* wait until self-refresh mode entered */
356 11: 368 11:
357 ldr r7, [r3, #0x4] 369 ldr r7, [r3, #0x4]
358 and r7, r7, #0x3 370 and r7, r7, #0x3
359 cmp r7, #0x3 371 cmp r7, #0x3
360 bne 11b 372 bne 11b
361 ldr r7, =0x0 373 ldr r7, =0x0
362 str r7, [r3, #0x320] 374 str r7, [r3, #0x320]
363 ldr r7, =0x1 375 ldr r7, =0x1
364 str r7, [r3, #0x1b0] 376 str r7, [r3, #0x1b0]
365 ldr r7, =0x1 377 ldr r7, =0x1
366 str r7, [r3, #0x320] 378 str r7, [r3, #0x320]
367 12: 379 12:
368 ldr r7, [r3, #0x324] 380 ldr r7, [r3, #0x324]
369 and r7, r7, #0x1 381 and r7, r7, #0x1
370 cmp r7, #0x1 382 cmp r7, #0x1
371 bne 12b 383 bne 12b
372 13: 384 13:
373 ldr r7, [r3, #0x4] 385 ldr r7, [r3, #0x4]
374 and r7, r7, #0x20 386 and r7, r7, #0x20
375 cmp r7, #0x20 387 cmp r7, #0x20
376 bne 13b 388 bne 13b
377 389
378 /* let DDR out of self-refresh */ 390 /* let DDR out of self-refresh */
379 ldr r7, =0x0 391 ldr r7, =0x0
380 str r7, [r3, #0x30] 392 str r7, [r3, #0x30]
381 14: 393 14:
382 ldr r7, [r3, #0x4] 394 ldr r7, [r3, #0x4]
383 and r7, r7, #0x30 395 and r7, r7, #0x30
384 cmp r7, #0x0 396 cmp r7, #0x0
385 bne 14b 397 bne 14b
386 398
387 15: 399 15:
388 ldr r7, [r3, #0x4] 400 ldr r7, [r3, #0x4]
389 and r7, r7, #0x3 401 and r7, r7, #0x3
390 cmp r7, #0x1 402 cmp r7, #0x1
391 bne 15b 403 bne 15b
392 404
393 /* enable port */ 405 /* enable port */
394 ldr r7, =0x1 406 ldr r7, =0x1
395 str r7, [r3, #0x490] 407 str r7, [r3, #0x490]
396 408
397 /* jump to kernel resume */ 409 /* jump to kernel resume */
398 ldr r1, =0x30270000 410 ldr r1, =0x30270000
399 ldr r7, [r1] 411 ldr r7, [r1]
400 412
401 mov pc, r7 413 mov pc, r7
402 16: 414 16:
403 /* Configure ocram_epdc */ 415 /* Configure ocram_epdc */
404 ldr r0, =IOMUXC_GPR_BASE_ADDR 416 ldr r0, =IOMUXC_GPR_BASE_ADDR
405 ldr r1, =0x4f400005 417 ldr r1, =0x4f400005
406 str r1, [r0, #0x4] 418 str r1, [r0, #0x4]
407 419
408 /* clear/set bit30 of SNVS_MISC_CTRL to ensure exit from ddr retention */ 420 /* clear/set bit30 of SNVS_MISC_CTRL to ensure exit from ddr retention */
409 ldr r0, =ANATOP_BASE_ADDR 421 ldr r0, =ANATOP_BASE_ADDR
410 ldr r1, =(0x1 << 30) 422 ldr r1, =(0x1 << 30)
411 str r1, [r0, #0x388] 423 str r1, [r0, #0x388]
412 str r1, [r0, #0x384] 424 str r1, [r0, #0x384]
413 425
414 ldr r0, =SRC_BASE_ADDR 426 ldr r0, =SRC_BASE_ADDR
415 ldr r1, =0x2 427 ldr r1, =0x2
416 ldr r2, =0x1000 428 ldr r2, =0x1000
417 str r1, [r0, r2] 429 str r1, [r0, r2]
418 430
419 ldr r0, =DDRC_IPS_BASE_ADDR 431 ldr r0, =DDRC_IPS_BASE_ADDR
420 ldr r1, =0x03040008 432 ldr r1, =0x03040008
421 str r1, [r0] 433 str r1, [r0]
422 ldr r1, =0x00200038 434 ldr r1, =0x00200038
423 str r1, [r0, #0x64] 435 str r1, [r0, #0x64]
424 ldr r1, =0x1 436 ldr r1, =0x1
425 str r1, [r0, #0x490] 437 str r1, [r0, #0x490]
426 ldr r1, =0x00350001 438 ldr r1, =0x00350001
427 str r1, [r0, #0xd0] 439 str r1, [r0, #0xd0]
428 ldr r1, =0x00c3000a 440 ldr r1, =0x00c3000a
429 str r1, [r0, #0xdc] 441 str r1, [r0, #0xdc]
430 ldr r1, =0x00010000 442 ldr r1, =0x00010000
431 str r1, [r0, #0xe0] 443 str r1, [r0, #0xe0]
432 ldr r1, =0x00110006 444 ldr r1, =0x00110006
433 str r1, [r0, #0xe4] 445 str r1, [r0, #0xe4]
434 ldr r1, =0x33f 446 ldr r1, =0x33f
435 str r1, [r0, #0xf4] 447 str r1, [r0, #0xf4]
436 ldr r1, =0x0a0e110b 448 ldr r1, =0x0a0e110b
437 str r1, [r0, #0x100] 449 str r1, [r0, #0x100]
438 ldr r1, =0x00020211 450 ldr r1, =0x00020211
439 str r1, [r0, #0x104] 451 str r1, [r0, #0x104]
440 ldr r1, =0x03060708 452 ldr r1, =0x03060708
441 str r1, [r0, #0x108] 453 str r1, [r0, #0x108]
442 ldr r1, =0x00a0500c 454 ldr r1, =0x00a0500c
443 str r1, [r0, #0x10c] 455 str r1, [r0, #0x10c]
444 ldr r1, =0x05020307 456 ldr r1, =0x05020307
445 str r1, [r0, #0x110] 457 str r1, [r0, #0x110]
446 ldr r1, =0x02020404 458 ldr r1, =0x02020404
447 str r1, [r0, #0x114] 459 str r1, [r0, #0x114]
448 ldr r1, =0x02020003 460 ldr r1, =0x02020003
449 str r1, [r0, #0x118] 461 str r1, [r0, #0x118]
450 ldr r1, =0x00000202 462 ldr r1, =0x00000202
451 str r1, [r0, #0x11c] 463 str r1, [r0, #0x11c]
452 ldr r1, =0x00000202 464 ldr r1, =0x00000202
453 str r1, [r0, #0x120] 465 str r1, [r0, #0x120]
454 ldr r1, =0x00600018 466 ldr r1, =0x00600018
455 str r1, [r0, #0x180] 467 str r1, [r0, #0x180]
456 ldr r1, =0x00e00100 468 ldr r1, =0x00e00100
457 str r1, [r0, #0x184] 469 str r1, [r0, #0x184]
458 ldr r1, =0x02098205 470 ldr r1, =0x02098205
459 str r1, [r0, #0x190] 471 str r1, [r0, #0x190]
460 ldr r1, =0x00060303 472 ldr r1, =0x00060303
461 str r1, [r0, #0x194] 473 str r1, [r0, #0x194]
462 ldr r1, =0x80400003 474 ldr r1, =0x80400003
463 str r1, [r0, #0x1a0] 475 str r1, [r0, #0x1a0]
464 ldr r1, =0x00100020 476 ldr r1, =0x00100020
465 str r1, [r0, #0x1a4] 477 str r1, [r0, #0x1a4]
466 ldr r1, =0x80100004 478 ldr r1, =0x80100004
467 str r1, [r0, #0x1a8] 479 str r1, [r0, #0x1a8]
468 480
469 ldr r1, =0x00000016 481 ldr r1, =0x00000016
470 str r1, [r0, #0x200] 482 str r1, [r0, #0x200]
471 ldr r1, =0x00171717 483 ldr r1, =0x00171717
472 str r1, [r0, #0x204] 484 str r1, [r0, #0x204]
473 ldr r1, =0x00000f00 485 ldr r1, =0x00000f00
474 str r1, [r0, #0x210] 486 str r1, [r0, #0x210]
475 ldr r1, =0x05050505 487 ldr r1, =0x05050505
476 str r1, [r0, #0x214] 488 str r1, [r0, #0x214]
477 ldr r1, =0x0f0f0505 489 ldr r1, =0x0f0f0505
478 str r1, [r0, #0x218] 490 str r1, [r0, #0x218]
479 491
480 ldr r1, =0x06000601 492 ldr r1, =0x06000601
481 str r1, [r0, #0x240] 493 str r1, [r0, #0x240]
482 mov r1, #0x0 494 mov r1, #0x0
483 str r1, [r0, #0x244] 495 str r1, [r0, #0x244]
484 496
485 ldr r0, =SRC_BASE_ADDR 497 ldr r0, =SRC_BASE_ADDR
486 mov r1, #0x0 498 mov r1, #0x0
487 ldr r2, =0x1000 499 ldr r2, =0x1000
488 str r1, [r0, r2] 500 str r1, [r0, r2]
489 501
490 ldr r0, =DDRPHY_IPS_BASE_ADDR 502 ldr r0, =DDRPHY_IPS_BASE_ADDR
491 ldr r1, =0x17421e40 503 ldr r1, =0x17421e40
492 str r1, [r0] 504 str r1, [r0]
493 ldr r1, =0x10210100 505 ldr r1, =0x10210100
494 str r1, [r0, #0x4] 506 str r1, [r0, #0x4]
495 ldr r1, =0x00010000 507 ldr r1, =0x00010000
496 str r1, [r0, #0x8] 508 str r1, [r0, #0x8]
497 ldr r1, =0x0007080c 509 ldr r1, =0x0007080c
498 str r1, [r0, #0x10] 510 str r1, [r0, #0x10]
499 imx7d_ddrphy_latency_setting 511 imx7d_ddrphy_latency_setting
500 ldr r1, =0x1010007e 512 ldr r1, =0x1010007e
501 str r1, [r0, #0xb0] 513 str r1, [r0, #0xb0]
502 ldr r1, =0x01010000 514 ldr r1, =0x01010000
503 str r1, [r0, #0x1c] 515 str r1, [r0, #0x1c]
504 ldr r1, =0x0db60d6e 516 ldr r1, =0x0db60d6e
505 str r1, [r0, #0x9c] 517 str r1, [r0, #0x9c]
506 518
507 ldr r1, =0x06060606 519 ldr r1, =0x06060606
508 str r1, [r0, #0x30] 520 str r1, [r0, #0x30]
509 ldr r1, =0x0a0a0a0a 521 ldr r1, =0x0a0a0a0a
510 str r1, [r0, #0x20] 522 str r1, [r0, #0x20]
511 ldr r1, =0x01000008 523 ldr r1, =0x01000008
512 str r1, [r0, #0x50] 524 str r1, [r0, #0x50]
513 ldr r1, =0x00000008 525 ldr r1, =0x00000008
514 str r1, [r0, #0x50] 526 str r1, [r0, #0x50]
515 527
516 ldr r1, =0x0000000f 528 ldr r1, =0x0000000f
517 str r1, [r0, #0x18] 529 str r1, [r0, #0x18]
518 ldr r1, =0x1e487304 530 ldr r1, =0x1e487304
519 str r1, [r0, #0xc0] 531 str r1, [r0, #0xc0]
520 ldr r1, =0x1e487304 532 ldr r1, =0x1e487304
521 str r1, [r0, #0xc0] 533 str r1, [r0, #0xc0]
522 ldr r1, =0x1e487306 534 ldr r1, =0x1e487306
523 str r1, [r0, #0xc0] 535 str r1, [r0, #0xc0]
524 ldr r1, =0x1e4c7304 536 ldr r1, =0x1e4c7304
525 str r1, [r0, #0xc0] 537 str r1, [r0, #0xc0]
526 538
527 wait_zq: 539 wait_zq:
528 ldr r1, [r0, #0xc4] 540 ldr r1, [r0, #0xc4]
529 tst r1, #0x1 541 tst r1, #0x1
530 beq wait_zq 542 beq wait_zq
531 543
532 ldr r1, =0x1e487304 544 ldr r1, =0x1e487304
533 str r1, [r0, #0xc0] 545 str r1, [r0, #0xc0]
534 546
535 ldr r0, =CCM_BASE_ADDR 547 ldr r0, =CCM_BASE_ADDR
536 mov r1, #0x0 548 mov r1, #0x0
537 ldr r2, =0x4130 549 ldr r2, =0x4130
538 str r1, [r0, r2] 550 str r1, [r0, r2]
539 ldr r0, =IOMUXC_GPR_BASE_ADDR 551 ldr r0, =IOMUXC_GPR_BASE_ADDR
540 mov r1, #0x178 552 mov r1, #0x178
541 str r1, [r0, #0x20] 553 str r1, [r0, #0x20]
542 ldr r0, =CCM_BASE_ADDR 554 ldr r0, =CCM_BASE_ADDR
543 mov r1, #0x2 555 mov r1, #0x2
544 ldr r2, =0x4130 556 ldr r2, =0x4130
545 str r1, [r0, r2] 557 str r1, [r0, r2]
546 558
547 ldr r0, =DDRC_IPS_BASE_ADDR 559 ldr r0, =DDRC_IPS_BASE_ADDR
548 wait_stat: 560 wait_stat:
549 ldr r1, [r0, #0x4] 561 ldr r1, [r0, #0x4]
550 tst r1, #0x1 562 tst r1, #0x1
551 beq wait_stat 563 beq wait_stat
552 .endm 564 .endm
553 565
554 .macro imx7_clock_gating 566 .macro imx7_clock_gating
555 .endm 567 .endm
556 568
557 .macro imx7_qos_setting 569 .macro imx7_qos_setting
558 .endm 570 .endm
559 571
560 .macro imx7_ddr_setting 572 .macro imx7_ddr_setting
561 imx7d_12x12_lpddr3_arm2_setting 573 imx7d_12x12_lpddr3_arm2_setting
562 .endm 574 .endm
563 575
564 /* include the common plugin code here */ 576 /* include the common plugin code here */
565 #include <asm/arch/mx7_plugin.S> 577 #include <asm/arch/mx7_plugin.S>
566 578