Eric Lee / smarc-uboot

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Commit 3c5b20f1b7c6687813d193033adddf0f93a3335d

Authored by Masahiro Yamada
Committed by Tom Rini
1 parent ceaf499b50
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

mpc8xx: remove ELPT860 board support 

This board is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: The LEOX team <team@leox.org>

Showing 13 changed files with 1 additions and 2036 deletions Side-by-side Diff

arch/powerpc/cpu/mpc8xx/Kconfig
Diff comments   View file @ 3c5b20f
... ... @@ -43,9 +43,6 @@
43 43 config TARGET_KUP4X
44 44 bool "Support KUP4X"
45 45  
46   -config TARGET_ELPT860
47   - bool "Support ELPT860"
48   -
49 46 config TARGET_TQM823L
50 47 bool "Support TQM823L"
51 48  
... ... @@ -84,7 +81,6 @@
84 81  
85 82 endchoice
86 83  
87   -source "board/LEOX/elpt860/Kconfig"
88 84 source "board/RRvision/Kconfig"
89 85 source "board/cogent/Kconfig"
90 86 source "board/esteem192e/Kconfig"
board/LEOX/elpt860/Kconfig
View file @ 3c5b20f
1   -if TARGET_ELPT860
2   -
3   -config SYS_BOARD
4   - default "elpt860"
5   -
6   -config SYS_VENDOR
7   - default "LEOX"
8   -
9   -config SYS_CONFIG_NAME
10   - default "ELPT860"
11   -
12   -endif
board/LEOX/elpt860/MAINTAINERS
View file @ 3c5b20f
1   -ELPT860 BOARD
2   -M: The LEOX team <team@leox.org>
3   -S: Maintained
4   -F: board/LEOX/elpt860/
5   -F: include/configs/ELPT860.h
6   -F: configs/ELPT860_defconfig
board/LEOX/elpt860/Makefile
View file @ 3c5b20f
1   -#######################################################################
2   -#
3   -# Copyright (C) 2000, 2001, 2002, 2003
4   -# The LEOX team <team@leox.org>, http://www.leox.org
5   -#
6   -# (C) Copyright 2006
7   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8   -#
9   -# LEOX.org is about the development of free hardware and software resources
10   -# for system on chip.
11   -#
12   -# Description: U-Boot port on the LEOX's ELPT860 CPU board
13   -# ~~~~~~~~~~~
14   -#
15   -#######################################################################
16   -#
17   -# SPDX-License-Identifier: GPL-2.0+
18   -#
19   -#######################################################################
20   -
21   -obj-y = elpt860.o flash.o
board/LEOX/elpt860/README.LEOX
View file @ 3c5b20f
1   -=============================================================================
2   -
3   - U-Boot port on the LEOX's ELPT860 CPU board
4   - -------------------------------------------
5   -
6   -LEOX.org is about the development of free hardware and software resources
7   - for system on chip.
8   -
9   -For more information, contact The LEOX team <team@leox.org>
10   -
11   -References:
12   -~~~~~~~~~~
13   - 1) Get the last stable release from denx.de:
14   - o ftp://ftp.denx.de/pub/u-boot/u-boot-0.2.0.tar.bz2
15   - 2) Get the current CVS snapshot:
16   - o cvs -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot login
17   - o cvs -z6 -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot co -P u-boot
18   -
19   -=============================================================================
20   -
21   -The ELPT860 CPU board has the following features:
22   -
23   -Processor: - MPC860T @ 50MHz
24   - - PowerPC Core
25   - - 65 MIPS
26   - - Caches: D->4KB, I->4KB
27   - - CPM: 4 SCCs, 2 SMCs
28   - - Ethernet 10/100
29   - - SPI, I2C, PCMCIA, Parallel
30   -
31   -CPU board: - DRAM: 16 MB
32   - - FLASH: 512 KB + (2 * 4 MB)
33   - - NVRAM: 128 KB
34   - - 1 Serial link
35   - - 2 Ethernet 10 BaseT Channels
36   -
37   -On power-up the processor jumps to the address of 0x02000100
38   -
39   -Thus, U-Boot is configured to reside in flash starting at the address of
40   -0x02001000. The environment space is located in NVRAM separately from
41   -U-Boot, at the address of 0x03000000.
42   -
43   -=============================================================================
44   -
45   - U-Boot test results
46   -
47   -=============================================================================
48   -
49   -##################################################
50   -# Operation on the serial console (SMC1)
51   -##############################
52   -
53   -U-Boot 0.2.2 (Jan 19 2003 - 11:08:39)
54   -
55   -CPU: XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present
56   - *** Warning: CPU Core has Silicon Bugs -- Check the Errata ***
57   -Board: ### No HW ID - assuming ELPT860
58   -DRAM: 16 MB
59   -FLASH: 512 kB
60   -In: serial
61   -Out: serial
62   -Err: serial
63   -Net: SCC ETHERNET
64   -
65   -Type "run nfsboot" to mount root filesystem over NFS
66   -
67   -Hit any key to stop autoboot: 0
68   -LEOX_elpt860: help
69   -askenv - get environment variables from stdin
70   -base - print or set address offset
71   -bdinfo - print Board Info structure
72   -bootm - boot application image from memory
73   -bootp - boot image via network using BootP/TFTP protocol
74   -bootd - boot default, i.e., run 'bootcmd'
75   -cmp - memory compare
76   -coninfo - print console devices and informations
77   -cp - memory copy
78   -crc32 - checksum calculation
79   -echo - echo args to console
80   -erase - erase FLASH memory
81   -flinfo - print FLASH memory information
82   -go - start application at address 'addr'
83   -help - print online help
84   -iminfo - print header information for application image
85   -loadb - load binary file over serial line (kermit mode)
86   -loads - load S-Record file over serial line
87   -loop - infinite loop on address range
88   -md - memory display
89   -mm - memory modify (auto-incrementing)
90   -mtest - simple RAM test
91   -mw - memory write (fill)
92   -nm - memory modify (constant address)
93   -printenv- print environment variables
94   -protect - enable or disable FLASH write protection
95   -rarpboot- boot image via network using RARP/TFTP protocol
96   -reset - Perform RESET of the CPU
97   -run - run commands in an environment variable
98   -saveenv - save environment variables to persistent storage
99   -setenv - set environment variables
100   -sleep - delay execution for some time
101   -source - run script from memory
102   -tftpboot- boot image via network using TFTP protocol
103   - and env variables ipaddr and serverip
104   -version - print monitor version
105   -? - alias for 'help'
106   -
107   -##################################################
108   -# Environment Variables (CONFIG_ENV_IS_IN_NVRAM)
109   -##############################
110   -
111   -LEOX_elpt860: printenv
112   -bootdelay=5
113   -loads_echo=1
114   -baudrate=9600
115   -stdin=serial
116   -stdout=serial
117   -stderr=serial
118   -ethaddr=00:03:ca:00:64:df
119   -ipaddr=192.168.0.30
120   -netmask=255.255.255.0
121   -serverip=192.168.0.1
122   -nfsserverip=192.168.0.1
123   -preboot=echo;echo Type "run nfsboot" to mount root filesystem over NFS;echo
124   -gatewayip=192.168.0.1
125   -ramargs=setenv bootargs root=/dev/ram rw
126   -rootargs=setenv rootpath /tftp/${ipaddr}
127   -nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${nfsserverip}:${rootpath}
128   -addip=setenv bootargs ${bootargs} ip=${ipaddr}:${nfsserverip}:${gatewayip}:${netmask}:${hostname}:eth0:
129   -ramboot=tftp 400000 /home/leox/pMulti;run ramargs;bootm
130   -nfsboot=tftp 400000 /home/leox/uImage;run rootargs;run nfsargs;run addip;bootm
131   -bootcmd=run ramboot
132   -clocks_in_mhz=1
133   -
134   -Environment size: 730/16380 bytes
135   -
136   -##################################################
137   -# Flash Memory Information
138   -##############################
139   -
140   -LEOX_elpt860: flinfo
141   -
142   -Bank # 1: AMD AM29F040 (4 Mbits)
143   - Size: 512 KB in 8 Sectors
144   - Sector Start Addresses:
145   - 02000000 (RO) 02010000 (RO) 02020000 (RO) 02030000 (RO) 02040000
146   - 02050000 02060000 02070000
147   -
148   -##################################################
149   -# Board Information Structure
150   -##############################
151   -
152   -LEOX_elpt860: bdinfo
153   -memstart = 0x00000000
154   -memsize = 0x01000000
155   -flashstart = 0x02000000
156   -flashsize = 0x00080000
157   -flashoffset = 0x00030000
158   -sramstart = 0x00000000
159   -sramsize = 0x00000000
160   -immr_base = 0xFF000000
161   -bootflags = 0x00000001
162   -intfreq = 50 MHz
163   -busfreq = 50 MHz
164   -ethaddr = 00:03:ca:00:64:df
165   -IP addr = 192.168.0.30
166   -baudrate = 9600 bps
167   -
168   -##################################################
169   -# Image Download and run over serial port
170   -# hello_world (S-Record image)
171   -# ===> 1) Enter "loads" command into U-Boot monitor
172   -# ===> 2) From TeraTerm's bar menu, Select 'File/Send file...'
173   -# Then select 'hello_world.srec' with the file browser
174   -##############################
175   -
176   -U-Boot 0.2.2 (Jan 19 2003 - 11:08:39)
177   -
178   -CPU: XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present
179   - *** Warning: CPU Core has Silicon Bugs -- Check the Errata ***
180   -Board: ### No HW ID - assuming ELPT860
181   -DRAM: 16 MB
182   -FLASH: 512 kB
183   -In: serial
184   -Out: serial
185   -Err: serial
186   -Net: SCC ETHERNET
187   -
188   -Type "run nfsboot" to mount root filesystem over NFS
189   -
190   -Hit any key to stop autoboot: 0
191   -LEOX_elpt860: loads
192   -## Ready for S-Record download ...
193   -S804040004F3050154000501709905014C000501388D
194   -## First Load Addr = 0x00040000
195   -## Last Load Addr = 0x0005018B
196   -## Total Size = 0x0001018C = 65932 Bytes
197   -## Start Addr = 0x00040004
198   -LEOX_elpt860: go 40004 This is a test !!!
199   -## Starting application at 0x00040004 ...
200   -Hello World
201   -argc = 6
202   -argv[0] = "40004"
203   -argv[1] = "This"
204   -argv[2] = "is"
205   -argv[3] = "a"
206   -argv[4] = "test"
207   -argv[5] = "!!!"
208   -argv[6] = "<NULL>"
209   -Hit any key to exit ...
210   -
211   -## Application terminated, rc = 0x0
212   -
213   -##################################################
214   -# Image download and run over ethernet interface
215   -# Linux-2.4.4 (uImage) + Root filesystem mounted over NFS
216   -##############################
217   -
218   -U-Boot 0.2.2 (Jan 19 2003 - 11:08:39)
219   -
220   -CPU: XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present
221   - *** Warning: CPU Core has Silicon Bugs -- Check the Errata ***
222   -Board: ### No HW ID - assuming ELPT860
223   -DRAM: 16 MB
224   -FLASH: 512 kB
225   -In: serial
226   -Out: serial
227   -Err: serial
228   -Net: SCC ETHERNET
229   -
230   -Type "run nfsboot" to mount root filesystem over NFS
231   -
232   -Hit any key to stop autoboot: 0
233   -LEOX_elpt860: run nfsboot
234   -ARP broadcast 1
235   -TFTP from server 192.168.0.1; our IP address is 192.168.0.30
236   -Filename '/home/leox/uImage'.
237   -Load address: 0x400000
238   -Loading: #################################################################
239   - #############################
240   -done
241   -Bytes transferred = 477294 (7486e hex)
242   -## Booting image at 00400000 ...
243   - Image Name: Linux-2.4.4
244   - Image Type: PowerPC Linux Kernel Image (gzip compressed)
245   - Data Size: 477230 Bytes = 466 kB = 0 MB
246   - Load Address: 00000000
247   - Entry Point: 00000000
248   - Verifying Checksum ... OK
249   - Uncompressing Kernel Image ... OK
250   -Linux version 2.4.4-rthal5 (leox@p5ak6650) (gcc version 2.95.3 20010315 (release/MontaVista)) #1 Wed Jul 3 10:23:53 CEST 2002
251   -On node 0 totalpages: 4096
252   -zone(0): 4096 pages.
253   -zone(1): 0 pages.
254   -zone(2): 0 pages.
255   -Kernel command line: root=/dev/nfs rw nfsroot=192.168.0.1:/tftp/192.168.0.30 ip=192.168.0.30:192.168.0.1:192.168.0.1:255.255.255.0::eth0:
256   -rtsched version <20010618.1050.24>
257   -Decrementer Frequency: 3125000
258   -Warning: real time clock seems stuck!
259   -Calibrating delay loop... 49.76 BogoMIPS
260   -Memory: 14720k available (928k kernel code, 384k data, 44k init, 0k highmem)
261   -Dentry-cache hash table entries: 2048 (order: 2, 16384 bytes)
262   -Buffer-cache hash table entries: 1024 (order: 0, 4096 bytes)
263   -Page-cache hash table entries: 4096 (order: 2, 16384 bytes)
264   -Inode-cache hash table entries: 1024 (order: 1, 8192 bytes)
265   -POSIX conformance testing by UNIFIX
266   -Linux NET4.0 for Linux 2.4
267   -Based upon Swansea University Computer Society NET3.039
268   -Starting kswapd v1.8
269   -CPM UART driver version 0.03
270   -ttyS0 on SMC1 at 0x0280, BRG1
271   -block: queued sectors max/low 9701kB/3233kB, 64 slots per queue
272   -RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
273   -eth0: CPM ENET Version 0.2 on SCC1, 00:03:ca:00:64:df
274   -NET4: Linux TCP/IP 1.0 for NET4.0
275   -IP Protocols: ICMP, UDP, TCP
276   -IP: routing cache hash table of 512 buckets, 4Kbytes
277   -TCP: Hash tables configured (established 1024 bind 1024)
278   -NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
279   -Looking up port of RPC 100003/2 on 192.168.0.1
280   -Looking up port of RPC 100005/2 on 192.168.0.1
281   -VFS: Mounted root (nfs filesystem).
282   -Freeing unused kernel memory: 44k init
283   -INIT: version 2.78 booting
284   - Welcome to DENX Embedded Linux Environment
285   - Press 'I' to enter interactive startup.
286   -Mounting proc filesystem: [ OK ]
287   -Configuring kernel parameters: [ OK ]
288   -Cannot access the Hardware Clock via any known method.
289   -Use the --debug option to see the details of our search for an access method.
290   -Setting clock : Wed Dec 31 19:00:11 EST 1969 [ OK ]
291   -Activating swap partitions: [ OK ]
292   -Setting hostname 192.168.0.30: [ OK ]
293   -Finding module dependencies:
294   -[ OK ]
295   -Checking filesystems
296   -Checking all file systems.
297   -[ OK ]
298   -Mounting local filesystems: [ OK ]
299   -Enabling swap space: [ OK ]
300   -INIT: Entering runlevel: 3
301   -Entering non-interactive startup
302   -Starting system logger: [ OK ]
303   -Starting kernel logger: [ OK ]
304   -Starting xinetd: [ OK ]
305   -
306   -192 login: root
307   -Last login: Wed Dec 31 19:00:41 on ttyS0
308   -bash-2.04#
309   -
310   -##################################################
311   -# Image download and run over ethernet interface
312   -# Linux-2.4.4 + Root filesystem mounted from RAM (pMulti)
313   -##############################
314   -
315   -U-Boot 0.2.2 (Jan 19 2003 - 11:08:39)
316   -
317   -CPU: XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present
318   - *** Warning: CPU Core has Silicon Bugs -- Check the Errata ***
319   -Board: ### No HW ID - assuming ELPT860
320   -DRAM: 16 MB
321   -FLASH: 512 kB
322   -In: serial
323   -Out: serial
324   -Err: serial
325   -Net: SCC ETHERNET
326   -
327   -Type "run nfsboot" to mount root filesystem over NFS
328   -
329   -Hit any key to stop autoboot: 0
330   -LEOX_elpt860: run ramboot
331   -ARP broadcast 1
332   -TFTP from server 192.168.0.1; our IP address is 192.168.0.30
333   -Filename '/home/leox/pMulti'.
334   -Load address: 0x400000
335   -Loading: #################################################################
336   - #################################################################
337   - #################################################################
338   - #################################################################
339   - #################################################################
340   - ########################################################
341   -done
342   -Bytes transferred = 1947816 (1db8a8 hex)
343   -## Booting image at 00400000 ...
344   - Image Name: linux-2.4.4-2002-03-21 Multiboot
345   - Image Type: PowerPC Linux Multi-File Image (gzip compressed)
346   - Data Size: 1947752 Bytes = 1902 kB = 1 MB
347   - Load Address: 00000000
348   - Entry Point: 00000000
349   - Contents:
350   - Image 0: 477230 Bytes = 466 kB = 0 MB
351   - Image 1: 1470508 Bytes = 1436 kB = 1 MB
352   - Verifying Checksum ... OK
353   - Uncompressing Multi-File Image ... OK
354   - Loading Ramdisk to 00e44000, end 00fab02c ... OK
355   -Linux version 2.4.4-rthal5 (leox@p5ak6650) (gcc version 2.95.3 20010315 (release/MontaVista)) #1 Wed Jul 3 10:23:53 CEST 2002
356   -On node 0 totalpages: 4096
357   -zone(0): 4096 pages.
358   -zone(1): 0 pages.
359   -zone(2): 0 pages.
360   -Kernel command line: root=/dev/ram rw
361   -rtsched version <20010618.1050.24>
362   -Decrementer Frequency: 3125000
363   -Warning: real time clock seems stuck!
364   -Calibrating delay loop... 49.76 BogoMIPS
365   -Memory: 13280k available (928k kernel code, 384k data, 44k init, 0k highmem)
366   -Dentry-cache hash table entries: 2048 (order: 2, 16384 bytes)
367   -Buffer-cache hash table entries: 1024 (order: 0, 4096 bytes)
368   -Page-cache hash table entries: 4096 (order: 2, 16384 bytes)
369   -Inode-cache hash table entries: 1024 (order: 1, 8192 bytes)
370   -POSIX conformance testing by UNIFIX
371   -Linux NET4.0 for Linux 2.4
372   -Based upon Swansea University Computer Society NET3.039
373   -Starting kswapd v1.8
374   -CPM UART driver version 0.03
375   -ttyS0 on SMC1 at 0x0280, BRG1
376   -block: queued sectors max/low 8741kB/2913kB, 64 slots per queue
377   -RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
378   -eth0: CPM ENET Version 0.2 on SCC1, 00:03:ca:00:64:df
379   -RAMDISK: Compressed image found at block 0
380   -Freeing initrd memory: 1436k freed
381   -NET4: Linux TCP/IP 1.0 for NET4.0
382   -IP Protocols: ICMP, UDP, TCP
383   -IP: routing cache hash table of 512 buckets, 4Kbytes
384   -TCP: Hash tables configured (established 1024 bind 1024)
385   -IP-Config: Incomplete network configuration information.
386   -NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
387   -VFS: Mounted root (ext2 filesystem).
388   -Freeing unused kernel memory: 44k init
389   -init started: BusyBox v0.60.2 (2002.07.01-12:06+0000) multi-call Configuring hostname
390   -Configuring lo...
391   -Configuring eth0...
392   -Configuring Gateway...
393   -
394   -Please press Enter to activate this console.
395   -
396   -ELPT860 login: root
397   -Password:
398   -Welcome to Linux-2.4.4 for ELPT CPU board (MPC860T @ 50MHz)
399   -
400   - a8888b.
401   - d888888b.
402   - 8P"YP"Y88
403   - _ _ 8|o||o|88
404   - | | |_| 8' .88
405   - | | _ ____ _ _ _ _ 8`._.' Y8.
406   - | | | | _ \| | | |\ \/ / d/ `8b.
407   - | |___ | | | | | |_| |/ \ .dP . Y8b.
408   - |_____||_|_| |_|\____|\_/\_/ d8:' " `::88b.
409   - d8" `Y88b
410   - :8P ' :888
411   - 8a. : _a88P
412   - ._/"Yaa_ : .| 88P|
413   - \ YP" `| 8P `.
414   - / \._____.d| .'
415   - `--..__)888888P`._.'
416   -login[21]: root login on `ttyS0'
417   -
418   -
419   -
420   -BusyBox v0.60.3 (2002.07.20-10:39+0000) Built-in shell (ash)
421   -Enter 'help' for a list of built-in commands.
422   -
423   -root@ELPT860:~ #
board/LEOX/elpt860/elpt860.c
View file @ 3c5b20f
1   -/*
2   -**=====================================================================
3   -**
4   -** Copyright (C) 2000, 2001, 2002, 2003
5   -** The LEOX team <team@leox.org>, http://www.leox.org
6   -**
7   -** LEOX.org is about the development of free hardware and software resources
8   -** for system on chip.
9   -**
10   -** Description: U-Boot port on the LEOX's ELPT860 CPU board
11   -** ~~~~~~~~~~~
12   -**
13   -**=====================================================================
14   -**
15   - * SPDX-License-Identifier: GPL-2.0+
16   -**
17   -**=====================================================================
18   -*/
19   -
20   -/*
21   -** Note 1: In this file, you have to provide the following functions:
22   -** ------
23   -** int board_early_init_f(void)
24   -** int checkboard(void)
25   -** phys_size_t initdram(int board_type)
26   -** called from 'board_init_f()' into 'common/board.c'
27   -**
28   -** void reset_phy(void)
29   -** called from 'board_init_r()' into 'common/board.c'
30   -*/
31   -
32   -#include <common.h>
33   -#include <mpc8xx.h>
34   -
35   -/* ------------------------------------------------------------------------- */
36   -
37   -static long int dram_size (long int, long int *, long int);
38   -
39   -/* ------------------------------------------------------------------------- */
40   -
41   -#define _NOT_USED_ 0xFFFFFFFF
42   -
43   -const uint init_sdram_table[] = {
44   - /*
45   - * Single Read. (Offset 0 in UPMA RAM)
46   - */
47   - 0x0FFCCC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04,
48   - 0xFFFFFC04, /* last */
49   - /*
50   - * SDRAM Initialization (offset 5 in UPMA RAM)
51   - *
52   - * This is no UPM entry point. The following definition uses
53   - * the remaining space to establish an initialization
54   - * sequence, which is executed by a RUN command.
55   - *
56   - */
57   - 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, /* last */
58   - /*
59   - * Burst Read. (Offset 8 in UPMA RAM)
60   - */
61   - 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
62   - 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
63   - 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
64   - 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, /* last */
65   - /*
66   - * Single Write. (Offset 18 in UPMA RAM)
67   - */
68   - 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04,
69   - 0xFFFFFC04, 0xFFFFFC04, 0x0FFFFC04, 0xFFFFFC04, /* last */
70   - /*
71   - * Burst Write. (Offset 20 in UPMA RAM)
72   - */
73   - 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
74   - 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
75   - 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC34, 0x0FAC0C34,
76   - 0xFFFFFC05, 0xFFFFFC04, 0x0FFCFC04, 0xFFFFFC05, /* last */
77   -};
78   -
79   -const uint sdram_table[] = {
80   - /*
81   - * Single Read. (Offset 0 in UPMA RAM)
82   - */
83   - 0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
84   - 0xFF0FFC00, /* last */
85   - /*
86   - * SDRAM Initialization (offset 5 in UPMA RAM)
87   - *
88   - * This is no UPM entry point. The following definition uses
89   - * the remaining space to establish an initialization
90   - * sequence, which is executed by a RUN command.
91   - *
92   - */
93   - 0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC05, /* last */
94   - /*
95   - * Burst Read. (Offset 8 in UPMA RAM)
96   - */
97   - 0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
98   - 0xF00FFC00, 0xF00FFC00, 0xF00FFC00, 0xFF0FFC00,
99   - 0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
100   - 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
101   - /*
102   - * Single Write. (Offset 18 in UPMA RAM)
103   - */
104   - 0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF0C00,
105   - 0xFF0FFC04, 0x0FFCCC04, 0xFFAFFC05, /* last */
106   - _NOT_USED_,
107   - /*
108   - * Burst Write. (Offset 20 in UPMA RAM)
109   - */
110   - 0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC00, 0x00AF0C00,
111   - 0xF00FFC00, 0xF00FFC00, 0xF00FFC04, 0x0FFCCC04,
112   - 0xFFAFFC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
113   - 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
114   - /*
115   - * Refresh (Offset 30 in UPMA RAM)
116   - */
117   - 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
118   - 0xFFFFFC05, 0xFFFFFC04, 0xFFFFFC05, _NOT_USED_,
119   - 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
120   - /*
121   - * Exception. (Offset 3c in UPMA RAM)
122   - */
123   - 0x0FFFFC34, 0x0FAC0C34, 0xFFFFFC05, 0xFFAFFC04, /* last */
124   -};
125   -
126   -/* ------------------------------------------------------------------------- */
127   -
128   -#define CONFIG_SYS_PC4 0x0800
129   -
130   -#define CONFIG_SYS_DS1 CONFIG_SYS_PC4
131   -
132   -/*
133   - * Very early board init code (fpga boot, etc.)
134   - */
135   -int board_early_init_f (void)
136   -{
137   - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
138   -
139   - /*
140   - * Light up the red led on ELPT860 pcb (DS1) (PCDAT)
141   - */
142   - immr->im_ioport.iop_pcdat &= ~CONFIG_SYS_DS1; /* PCDAT (DS1 = 0) */
143   - immr->im_ioport.iop_pcpar &= ~CONFIG_SYS_DS1; /* PCPAR (0=general purpose I/O) */
144   - immr->im_ioport.iop_pcdir |= CONFIG_SYS_DS1; /* PCDIR (I/O: 0=input, 1=output) */
145   -
146   - return (0); /* success */
147   -}
148   -
149   -/*
150   - * Check Board Identity:
151   - *
152   - * Test ELPT860 ID string
153   - *
154   - * Return 1 if no second DRAM bank, otherwise returns 0
155   - */
156   -
157   -int checkboard (void)
158   -{
159   - char buf[64];
160   - int i = getenv_f("serial#", buf, sizeof(buf));
161   -
162   - if ((i < 0) || strncmp(buf, "ELPT860", 7))
163   - printf ("### No HW ID - assuming ELPT860\n");
164   -
165   - return (0); /* success */
166   -}
167   -
168   -/* ------------------------------------------------------------------------- */
169   -
170   -phys_size_t initdram (int board_type)
171   -{
172   - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
173   - volatile memctl8xx_t *memctl = &immap->im_memctl;
174   - long int size8, size9;
175   - long int size_b0 = 0;
176   -
177   - /*
178   - * This sequence initializes SDRAM chips on ELPT860 board
179   - */
180   - upmconfig (UPMA, (uint *) init_sdram_table,
181   - sizeof (init_sdram_table) / sizeof (uint));
182   -
183   - memctl->memc_mptpr = 0x0200;
184   - memctl->memc_mamr = 0x18002111;
185   -
186   - memctl->memc_mar = 0x00000088;
187   - memctl->memc_mcr = 0x80002000; /* CS1: SDRAM bank 0 */
188   -
189   - upmconfig (UPMA, (uint *) sdram_table,
190   - sizeof (sdram_table) / sizeof (uint));
191   -
192   - /*
193   - * Preliminary prescaler for refresh (depends on number of
194   - * banks): This value is selected for four cycles every 62.4 us
195   - * with two SDRAM banks or four cycles every 31.2 us with one
196   - * bank. It will be adjusted after memory sizing.
197   - */
198   - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
199   -
200   - /*
201   - * The following value is used as an address (i.e. opcode) for
202   - * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
203   - * the port size is 32bit the SDRAM does NOT "see" the lower two
204   - * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
205   - * MICRON SDRAMs:
206   - * -> 0 00 010 0 010
207   - * | | | | +- Burst Length = 4
208   - * | | | +----- Burst Type = Sequential
209   - * | | +------- CAS Latency = 2
210   - * | +----------- Operating Mode = Standard
211   - * +-------------- Write Burst Mode = Programmed Burst Length
212   - */
213   - memctl->memc_mar = 0x00000088;
214   -
215   - /*
216   - * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
217   - * preliminary addresses - these have to be modified after the
218   - * SDRAM size has been determined.
219   - */
220   - memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
221   - memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
222   -
223   - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
224   -
225   - udelay (200);
226   -
227   - /* perform SDRAM initializsation sequence */
228   -
229   - memctl->memc_mcr = 0x80002105; /* CS1: SDRAM bank 0 */
230   - udelay (1);
231   - memctl->memc_mcr = 0x80002230; /* CS1: SDRAM bank 0 - execute twice */
232   - udelay (1);
233   -
234   - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
235   -
236   - udelay (1000);
237   -
238   - /*
239   - * Check Bank 0 Memory Size for re-configuration
240   - *
241   - * try 8 column mode
242   - */
243   - size8 = dram_size (CONFIG_SYS_MAMR_8COL,
244   - SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
245   -
246   - udelay (1000);
247   -
248   - /*
249   - * try 9 column mode
250   - */
251   - size9 = dram_size (CONFIG_SYS_MAMR_9COL,
252   - SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
253   -
254   - if (size8 < size9) { /* leave configuration at 9 columns */
255   - size_b0 = size9;
256   - /* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
257   - } else { /* back to 8 columns */
258   -
259   - size_b0 = size8;
260   - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
261   - udelay (500);
262   - /* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
263   - }
264   -
265   - udelay (1000);
266   -
267   - /*
268   - * Adjust refresh rate depending on SDRAM type, both banks
269   - * For types > 128 MBit leave it at the current (fast) rate
270   - */
271   - if (size_b0 < 0x02000000) {
272   - /* reduce to 15.6 us (62.4 us / quad) */
273   - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
274   - udelay (1000);
275   - }
276   -
277   - /*
278   - * Final mapping: map bigger bank first
279   - */
280   - memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
281   - memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
282   -
283   - {
284   - unsigned long reg;
285   -
286   - /* adjust refresh rate depending on SDRAM type, one bank */
287   - reg = memctl->memc_mptpr;
288   - reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
289   - memctl->memc_mptpr = reg;
290   - }
291   -
292   - udelay (10000);
293   -
294   - return (size_b0);
295   -}
296   -
297   -/* ------------------------------------------------------------------------- */
298   -
299   -/*
300   - * Check memory range for valid RAM. A simple memory test determines
301   - * the actually available RAM size between addresses `base' and
302   - * `base + maxsize'. Some (not all) hardware errors are detected:
303   - * - short between address lines
304   - * - short between data lines
305   - */
306   -
307   -static long int
308   -dram_size (long int mamr_value, long int *base, long int maxsize)
309   -{
310   - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
311   - volatile memctl8xx_t *memctl = &immap->im_memctl;
312   -
313   - memctl->memc_mamr = mamr_value;
314   -
315   - return (get_ram_size (base, maxsize));
316   -}
317   -
318   -/* ------------------------------------------------------------------------- */
319   -
320   -#define CONFIG_SYS_PA1 0x4000
321   -#define CONFIG_SYS_PA2 0x2000
322   -
323   -#define CONFIG_SYS_LBKs (CONFIG_SYS_PA2 | CONFIG_SYS_PA1)
324   -
325   -void reset_phy (void)
326   -{
327   - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
328   -
329   - /*
330   - * Ensure LBK LXT901 ethernet 1 & 2 = 0 ... for normal loopback in effect
331   - * and no AUI loopback
332   - */
333   - immr->im_ioport.iop_padat &= ~CONFIG_SYS_LBKs; /* PADAT (LBK eth 1&2 = 0) */
334   - immr->im_ioport.iop_papar &= ~CONFIG_SYS_LBKs; /* PAPAR (0=general purpose I/O) */
335   - immr->im_ioport.iop_padir |= CONFIG_SYS_LBKs; /* PADIR (I/O: 0=input, 1=output) */
336   -}
board/LEOX/elpt860/flash.c
View file @ 3c5b20f
1   -/*
2   -**=====================================================================
3   -**
4   -** Copyright (C) 2000, 2001, 2002, 2003
5   -** The LEOX team <team@leox.org>, http://www.leox.org
6   -**
7   -** LEOX.org is about the development of free hardware and software resources
8   -** for system on chip.
9   -**
10   -** Description: U-Boot port on the LEOX's ELPT860 CPU board
11   -** ~~~~~~~~~~~
12   -**
13   -**=====================================================================
14   -**
15   - * SPDX-License-Identifier: GPL-2.0+
16   -**
17   -**=====================================================================
18   -*/
19   -
20   -/*
21   -** Note 1: In this file, you have to provide the following variable:
22   -** ------
23   -** flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]
24   -** 'flash_info_t' structure is defined into 'include/flash.h'
25   -** and defined as extern into 'common/cmd_flash.c'
26   -**
27   -** Note 2: In this file, you have to provide the following functions:
28   -** ------
29   -** unsigned long flash_init(void)
30   -** called from 'board_init_r()' into 'common/board.c'
31   -**
32   -** void flash_print_info(flash_info_t *info)
33   -** called from 'do_flinfo()' into 'common/cmd_flash.c'
34   -**
35   -** int flash_erase(flash_info_t *info,
36   -** int s_first,
37   -** int s_last)
38   -** called from 'do_flerase()' & 'flash_sect_erase()' into 'common/cmd_flash.c'
39   -**
40   -** int write_buff (flash_info_t *info,
41   -** uchar *src,
42   -** ulong addr,
43   -** ulong cnt)
44   -** called from 'flash_write()' into 'common/cmd_flash.c'
45   -*/
46   -
47   -#include <common.h>
48   -#include <mpc8xx.h>
49   -
50   -
51   -#ifndef CONFIG_ENV_ADDR
52   -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
53   -#endif
54   -
55   -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
56   -
57   -/*-----------------------------------------------------------------------
58   - * Internal Functions
59   - */
60   -static void flash_get_offsets (ulong base, flash_info_t *info);
61   -static ulong flash_get_size (volatile unsigned char *addr, flash_info_t *info);
62   -
63   -static int write_word (flash_info_t *info, ulong dest, ulong data);
64   -static int write_byte (flash_info_t *info, ulong dest, uchar data);
65   -
66   -/*-----------------------------------------------------------------------
67   - */
68   -
69   -unsigned long
70   -flash_init (void)
71   -{
72   - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
73   - volatile memctl8xx_t *memctl = &immap->im_memctl;
74   - unsigned long size_b0;
75   - int i;
76   -
77   - /* Init: no FLASHes known */
78   - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i)
79   - {
80   - flash_info[i].flash_id = FLASH_UNKNOWN;
81   - }
82   -
83   - /* Static FLASH Bank configuration here - FIXME XXX */
84   -
85   - size_b0 = flash_get_size ((volatile unsigned char *)FLASH_BASE0_PRELIM,
86   - &flash_info[0]);
87   -
88   - if ( flash_info[0].flash_id == FLASH_UNKNOWN )
89   - {
90   - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
91   - size_b0, size_b0<<20);
92   - }
93   -
94   - /* Remap FLASH according to real size */
95   - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
96   - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_PS_8 | BR_V;
97   -
98   - /* Re-do sizing to get full correct info */
99   - size_b0 = flash_get_size ((volatile unsigned char *)CONFIG_SYS_FLASH_BASE,
100   - &flash_info[0]);
101   -
102   - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
103   -
104   -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
105   - /* monitor protection ON by default */
106   - flash_protect (FLAG_PROTECT_SET,
107   - CONFIG_SYS_MONITOR_BASE,
108   - CONFIG_SYS_MONITOR_BASE + monitor_flash_len-1,
109   - &flash_info[0]);
110   -#endif
111   -
112   -#ifdef CONFIG_ENV_IS_IN_FLASH
113   - /* ENV protection ON by default */
114   - flash_protect(FLAG_PROTECT_SET,
115   - CONFIG_ENV_ADDR,
116   - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE-1,
117   - &flash_info[0]);
118   -#endif
119   -
120   - flash_info[0].size = size_b0;
121   -
122   - return (size_b0);
123   -}
124   -
125   -/*-----------------------------------------------------------------------
126   - */
127   -static void
128   -flash_get_offsets (ulong base,
129   - flash_info_t *info)
130   -{
131   - int i;
132   -
133   -#define SECTOR_64KB 0x00010000
134   -
135   - /* set up sector start adress table */
136   - for (i = 0; i < info->sector_count; i++)
137   - {
138   - info->start[i] = base + (i * SECTOR_64KB);
139   - }
140   -}
141   -
142   -/*-----------------------------------------------------------------------
143   - */
144   -void
145   -flash_print_info (flash_info_t *info)
146   -{
147   - int i;
148   -
149   - if ( info->flash_id == FLASH_UNKNOWN )
150   - {
151   - printf ("missing or unknown FLASH type\n");
152   - return;
153   - }
154   -
155   - switch ( info->flash_id & FLASH_VENDMASK )
156   - {
157   - case FLASH_MAN_AMD: printf ("AMD "); break;
158   - case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
159   - case FLASH_MAN_STM: printf ("STM (Thomson) "); break;
160   - default: printf ("Unknown Vendor "); break;
161   - }
162   -
163   - switch ( info->flash_id & FLASH_TYPEMASK )
164   - {
165   - case FLASH_AM040: printf ("AM29F040 (4 Mbits)\n");
166   - break;
167   - default: printf ("Unknown Chip Type\n");
168   - break;
169   - }
170   -
171   - printf (" Size: %ld KB in %d Sectors\n",
172   - info->size >> 10, info->sector_count);
173   -
174   - printf (" Sector Start Addresses:");
175   - for (i=0; i<info->sector_count; ++i)
176   - {
177   - if ((i % 5) == 0)
178   - printf ("\n ");
179   - printf (" %08lX%s",
180   - info->start[i],
181   - info->protect[i] ? " (RO)" : " "
182   - );
183   - }
184   - printf ("\n");
185   -
186   - return;
187   -}
188   -
189   -/*-----------------------------------------------------------------------
190   - */
191   -
192   -
193   -/*-----------------------------------------------------------------------
194   - */
195   -
196   -/*
197   - * The following code cannot be run from FLASH!
198   - */
199   -
200   -static ulong
201   -flash_get_size (volatile unsigned char *addr,
202   - flash_info_t *info)
203   -{
204   - short i;
205   - uchar value;
206   - ulong base = (ulong)addr;
207   -
208   - /* Write auto select command: read Manufacturer ID */
209   - addr[0x0555] = 0xAA;
210   - addr[0x02AA] = 0x55;
211   - addr[0x0555] = 0x90;
212   -
213   - value = addr[0];
214   -
215   - switch ( value )
216   - {
217   - /* case AMD_MANUFACT: */
218   - case 0x01:
219   - info->flash_id = FLASH_MAN_AMD;
220   - break;
221   - /* case FUJ_MANUFACT: */
222   - case 0x04:
223   - info->flash_id = FLASH_MAN_FUJ;
224   - break;
225   - /* case STM_MANUFACT: */
226   - case 0x20:
227   - info->flash_id = FLASH_MAN_STM;
228   - break;
229   -
230   - default:
231   - info->flash_id = FLASH_UNKNOWN;
232   - info->sector_count = 0;
233   - info->size = 0;
234   - return (0); /* no or unknown flash */
235   - }
236   -
237   - value = addr[1]; /* device ID */
238   -
239   - switch ( value )
240   - {
241   - case STM_ID_F040B:
242   - case AMD_ID_F040B:
243   - info->flash_id += FLASH_AM040; /* 4 Mbits = 512k * 8 */
244   - info->sector_count = 8;
245   - info->size = 0x00080000;
246   - break;
247   -
248   - default:
249   - info->flash_id = FLASH_UNKNOWN;
250   - return (0); /* => no or unknown flash */
251   - }
252   -
253   - /* set up sector start adress table */
254   - for (i = 0; i < info->sector_count; i++)
255   - {
256   - info->start[i] = base + (i * 0x00010000);
257   - }
258   -
259   - /* check for protected sectors */
260   - for (i = 0; i < info->sector_count; i++)
261   - {
262   - /* read sector protection at sector address, (A7 .. A0) = 0x02 */
263   - /* D0 = 1 if protected */
264   - addr = (volatile unsigned char *)(info->start[i]);
265   - info->protect[i] = addr[2] & 1;
266   - }
267   -
268   - /*
269   - * Prevent writes to uninitialized FLASH.
270   - */
271   - if ( info->flash_id != FLASH_UNKNOWN )
272   - {
273   - addr = (volatile unsigned char *)info->start[0];
274   -
275   - *addr = 0xF0; /* reset bank */
276   - }
277   -
278   - return (info->size);
279   -}
280   -
281   -
282   -/*-----------------------------------------------------------------------
283   - */
284   -
285   -int
286   -flash_erase (flash_info_t *info,
287   - int s_first,
288   - int s_last)
289   -{
290   - volatile unsigned char *addr = (volatile unsigned char *)(info->start[0]);
291   - int flag, prot, sect, l_sect;
292   - ulong start, now, last;
293   -
294   - if ( (s_first < 0) || (s_first > s_last) )
295   - {
296   - if ( info->flash_id == FLASH_UNKNOWN )
297   - {
298   - printf ("- missing\n");
299   - }
300   - else
301   - {
302   - printf ("- no sectors to erase\n");
303   - }
304   - return ( 1 );
305   - }
306   -
307   - if ( (info->flash_id == FLASH_UNKNOWN) ||
308   - (info->flash_id > FLASH_AMD_COMP) )
309   - {
310   - printf ("Can't erase unknown flash type %08lx - aborted\n",
311   - info->flash_id);
312   - return ( 1 );
313   - }
314   -
315   - prot = 0;
316   - for (sect=s_first; sect<=s_last; ++sect)
317   - {
318   - if ( info->protect[sect] )
319   - {
320   - prot++;
321   - }
322   - }
323   -
324   - if ( prot )
325   - {
326   - printf ("- Warning: %d protected sectors will not be erased!\n", prot);
327   - }
328   - else
329   - {
330   - printf ("\n");
331   - }
332   -
333   - l_sect = -1;
334   -
335   - /* Disable interrupts which might cause a timeout here */
336   - flag = disable_interrupts();
337   -
338   - addr[0x0555] = 0xAA;
339   - addr[0x02AA] = 0x55;
340   - addr[0x0555] = 0x80;
341   - addr[0x0555] = 0xAA;
342   - addr[0x02AA] = 0x55;
343   -
344   - /* Start erase on unprotected sectors */
345   - for (sect = s_first; sect<=s_last; sect++)
346   - {
347   - if (info->protect[sect] == 0) /* not protected */
348   - {
349   - addr = (volatile unsigned char *)(info->start[sect]);
350   - addr[0] = 0x30;
351   - l_sect = sect;
352   - }
353   - }
354   -
355   - /* re-enable interrupts if necessary */
356   - if ( flag )
357   - enable_interrupts();
358   -
359   - /* wait at least 80us - let's wait 1 ms */
360   - udelay (1000);
361   -
362   - /*
363   - * We wait for the last triggered sector
364   - */
365   - if ( l_sect < 0 )
366   - goto DONE;
367   -
368   - start = get_timer (0);
369   - last = start;
370   - addr = (volatile unsigned char *)(info->start[l_sect]);
371   - while ( (addr[0] & 0x80) != 0x80 )
372   - {
373   - if ( (now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT )
374   - {
375   - printf ("Timeout\n");
376   - return ( 1 );
377   - }
378   - /* show that we're waiting */
379   - if ( (now - last) > 1000 ) /* every second */
380   - {
381   - putc ('.');
382   - last = now;
383   - }
384   - }
385   -
386   -DONE:
387   - /* reset to read mode */
388   - addr = (volatile unsigned char *)info->start[0];
389   - addr[0] = 0xF0; /* reset bank */
390   -
391   - printf (" done\n");
392   -
393   - return ( 0 );
394   -}
395   -
396   -/*-----------------------------------------------------------------------
397   - * Copy memory to flash, returns:
398   - * 0 - OK
399   - * 1 - write timeout
400   - * 2 - Flash not erased
401   - */
402   -
403   -int
404   -write_buff (flash_info_t *info,
405   - uchar *src,
406   - ulong addr,
407   - ulong cnt)
408   -{
409   - ulong cp, wp, data;
410   - uchar bdata;
411   - int i, l, rc;
412   -
413   - if ( (info->flash_id & FLASH_TYPEMASK) == FLASH_AM040 )
414   - {
415   - /* Width of the data bus: 8 bits */
416   -
417   - wp = addr;
418   -
419   - while ( cnt )
420   - {
421   - bdata = *src++;
422   -
423   - if ( (rc = write_byte(info, wp, bdata)) != 0 )
424   - {
425   - return (rc);
426   - }
427   -
428   - ++wp;
429   - --cnt;
430   - }
431   -
432   - return ( 0 );
433   - }
434   - else
435   - {
436   - /* Width of the data bus: 32 bits */
437   -
438   - wp = (addr & ~3); /* get lower word aligned address */
439   -
440   - /*
441   - * handle unaligned start bytes
442   - */
443   - if ( (l = addr - wp) != 0 )
444   - {
445   - data = 0;
446   - for (i=0, cp=wp; i<l; ++i, ++cp)
447   - {
448   - data = (data << 8) | (*(uchar *)cp);
449   - }
450   - for (; i<4 && cnt>0; ++i)
451   - {
452   - data = (data << 8) | *src++;
453   - --cnt;
454   - ++cp;
455   - }
456   - for (; cnt==0 && i<4; ++i, ++cp)
457   - {
458   - data = (data << 8) | (*(uchar *)cp);
459   - }
460   -
461   - if ( (rc = write_word(info, wp, data)) != 0 )
462   - {
463   - return (rc);
464   - }
465   - wp += 4;
466   - }
467   -
468   - /*
469   - * handle word aligned part
470   - */
471   - while ( cnt >= 4 )
472   - {
473   - data = 0;
474   - for (i=0; i<4; ++i)
475   - {
476   - data = (data << 8) | *src++;
477   - }
478   - if ( (rc = write_word(info, wp, data)) != 0 )
479   - {
480   - return (rc);
481   - }
482   - wp += 4;
483   - cnt -= 4;
484   - }
485   -
486   - if ( cnt == 0 )
487   - {
488   - return (0);
489   - }
490   -
491   - /*
492   - * handle unaligned tail bytes
493   - */
494   - data = 0;
495   - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp)
496   - {
497   - data = (data << 8) | *src++;
498   - --cnt;
499   - }
500   - for (; i<4; ++i, ++cp)
501   - {
502   - data = (data << 8) | (*(uchar *)cp);
503   - }
504   -
505   - return (write_word(info, wp, data));
506   - }
507   -}
508   -
509   -/*-----------------------------------------------------------------------
510   - * Write a word to Flash, returns:
511   - * 0 - OK
512   - * 1 - write timeout
513   - * 2 - Flash not erased
514   - */
515   -static int
516   -write_word (flash_info_t *info,
517   - ulong dest,
518   - ulong data)
519   -{
520   - vu_long *addr = (vu_long*)(info->start[0]);
521   - ulong start;
522   - int flag;
523   -
524   - /* Check if Flash is (sufficiently) erased */
525   - if ( (*((vu_long *)dest) & data) != data )
526   - {
527   - return (2);
528   - }
529   - /* Disable interrupts which might cause a timeout here */
530   - flag = disable_interrupts();
531   -
532   - addr[0x0555] = 0x00AA00AA;
533   - addr[0x02AA] = 0x00550055;
534   - addr[0x0555] = 0x00A000A0;
535   -
536   - *((vu_long *)dest) = data;
537   -
538   - /* re-enable interrupts if necessary */
539   - if ( flag )
540   - enable_interrupts();
541   -
542   - /* data polling for D7 */
543   - start = get_timer (0);
544   - while ( (*((vu_long *)dest) & 0x00800080) != (data & 0x00800080) )
545   - {
546   - if ( get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT )
547   - {
548   - return (1);
549   - }
550   - }
551   -
552   - return (0);
553   -}
554   -
555   -/*-----------------------------------------------------------------------
556   - * Write a byte to Flash, returns:
557   - * 0 - OK
558   - * 1 - write timeout
559   - * 2 - Flash not erased
560   - */
561   -static int
562   -write_byte (flash_info_t *info,
563   - ulong dest,
564   - uchar data)
565   -{
566   - volatile unsigned char *addr = (volatile unsigned char *)(info->start[0]);
567   - ulong start;
568   - int flag;
569   -
570   - /* Check if Flash is (sufficiently) erased */
571   - if ( (*((volatile unsigned char *)dest) & data) != data )
572   - {
573   - return (2);
574   - }
575   - /* Disable interrupts which might cause a timeout here */
576   - flag = disable_interrupts();
577   -
578   - addr[0x0555] = 0xAA;
579   - addr[0x02AA] = 0x55;
580   - addr[0x0555] = 0xA0;
581   -
582   - *((volatile unsigned char *)dest) = data;
583   -
584   - /* re-enable interrupts if necessary */
585   - if ( flag )
586   - enable_interrupts();
587   -
588   - /* data polling for D7 */
589   - start = get_timer (0);
590   - while ( (*((volatile unsigned char *)dest) & 0x80) != (data & 0x80) )
591   - {
592   - if ( get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT )
593   - {
594   - return (1);
595   - }
596   - }
597   -
598   - return (0);
599   -}
600   -
601   -/*-----------------------------------------------------------------------
602   - */
board/LEOX/elpt860/u-boot.lds
View file @ 3c5b20f
1   -/*
2   -**=====================================================================
3   -**
4   -** Copyright (C) 2000, 2001, 2002, 2003
5   -** The LEOX team <team@leox.org>, http://www.leox.org
6   -**
7   -** LEOX.org is about the development of free hardware and software resources
8   -** for system on chip.
9   -**
10   -** Description: U-Boot port on the LEOX's ELPT860 CPU board
11   -** ~~~~~~~~~~~
12   -**
13   -**=====================================================================
14   -**
15   - * SPDX-License-Identifier: GPL-2.0+
16   -**
17   -**=====================================================================
18   -*/
19   -
20   -OUTPUT_ARCH(powerpc)
21   -
22   -SECTIONS
23   -{
24   - /* Read-only sections, merged into text segment: */
25   - . = + SIZEOF_HEADERS;
26   - .text :
27   - {
28   - /* WARNING - the following is hand-optimized to fit within */
29   - /* the sector layout of our flash chips! XXX FIXME XXX */
30   -
31   - arch/powerpc/cpu/mpc8xx/start.o (.text*)
32   - arch/powerpc/cpu/mpc8xx/traps.o (.text*)
33   - common/built-in.o (.text*)
34   - arch/powerpc/cpu/mpc8xx/built-in.o (.text*)
35   - board/LEOX/elpt860/built-in.o (.text*)
36   - arch/powerpc/lib/built-in.o (.text*)
37   -
38   - . = env_offset;
39   - common/env_embedded.o (.text*)
40   -
41   - *(.text*)
42   - }
43   - _etext = .;
44   - PROVIDE (etext = .);
45   - .rodata :
46   - {
47   - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
48   - }
49   -
50   - /* Read-write section, merged into data segment: */
51   - . = (. + 0x00FF) & 0xFFFFFF00;
52   - _erotext = .;
53   - PROVIDE (erotext = .);
54   - .reloc :
55   - {
56   - _GOT2_TABLE_ = .;
57   - KEEP(*(.got2))
58   - KEEP(*(.got))
59   - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
60   - _FIXUP_TABLE_ = .;
61   - KEEP(*(.fixup))
62   - }
63   - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
64   - __fixup_entries = (. - _FIXUP_TABLE_)>>2;
65   -
66   - .data :
67   - {
68   - *(.data*)
69   - *(.sdata*)
70   - }
71   - _edata = .;
72   - PROVIDE (edata = .);
73   -
74   - . = .;
75   -
76   - . = ALIGN(4);
77   - .u_boot_list : {
78   - KEEP(*(SORT(.u_boot_list*)));
79   - }
80   -
81   - . = .;
82   - __start___ex_table = .;
83   - __ex_table : { *(__ex_table) }
84   - __stop___ex_table = .;
85   -
86   - . = ALIGN(256);
87   - __init_begin = .;
88   - .text.init : { *(.text.init) }
89   - .data.init : { *(.data.init) }
90   - . = ALIGN(256);
91   - __init_end = .;
92   -
93   - __bss_start = .;
94   - .bss (NOLOAD) :
95   - {
96   - *(.bss*)
97   - *(.sbss*)
98   - *(COMMON)
99   - . = ALIGN(4);
100   - }
101   - __bss_end = . ;
102   - PROVIDE (end = .);
103   -}
board/LEOX/elpt860/u-boot.lds.debug
View file @ 3c5b20f
1   -/*
2   -**=====================================================================
3   -**
4   -** Copyright (C) 2000, 2001, 2002, 2003
5   -** The LEOX team <team@leox.org>, http://www.leox.org
6   -**
7   -** LEOX.org is about the development of free hardware and software resources
8   -** for system on chip.
9   -**
10   -** Description: U-Boot port on the LEOX's ELPT860 CPU board
11   -** ~~~~~~~~~~~
12   -**
13   -**=====================================================================
14   -**
15   - * SPDX-License-Identifier: GPL-2.0+
16   -**
17   -**=====================================================================
18   -*/
19   -
20   -OUTPUT_ARCH(powerpc)
21   -/* Do we need any of these for elf?
22   - __DYNAMIC = 0; */
23   -SECTIONS
24   -{
25   - /* Read-only sections, merged into text segment: */
26   - . = + SIZEOF_HEADERS;
27   - .interp : { *(.interp) }
28   - .hash : { *(.hash) }
29   - .dynsym : { *(.dynsym) }
30   - .dynstr : { *(.dynstr) }
31   - .rel.text : { *(.rel.text) }
32   - .rela.text : { *(.rela.text) }
33   - .rel.data : { *(.rel.data) }
34   - .rela.data : { *(.rela.data) }
35   - .rel.rodata : { *(.rel.rodata) }
36   - .rela.rodata : { *(.rela.rodata) }
37   - .rel.got : { *(.rel.got) }
38   - .rela.got : { *(.rela.got) }
39   - .rel.ctors : { *(.rel.ctors) }
40   - .rela.ctors : { *(.rela.ctors) }
41   - .rel.dtors : { *(.rel.dtors) }
42   - .rela.dtors : { *(.rela.dtors) }
43   - .rel.bss : { *(.rel.bss) }
44   - .rela.bss : { *(.rela.bss) }
45   - .rel.plt : { *(.rel.plt) }
46   - .rela.plt : { *(.rela.plt) }
47   - .init : { *(.init) }
48   - .plt : { *(.plt) }
49   - .text :
50   - {
51   - /* WARNING - the following is hand-optimized to fit within */
52   - /* the sector layout of our flash chips! XXX FIXME XXX */
53   -
54   - arch/powerpc/cpu/mpc8xx/start.o (.text)
55   - common/dlmalloc.o (.text)
56   - lib/vsprintf.o (.text)
57   - lib/crc32.o (.text)
58   -
59   - . = env_offset;
60   - common/env_embedded.o (.text)
61   -
62   - *(.text)
63   - *(.got1)
64   - }
65   - _etext = .;
66   - PROVIDE (etext = .);
67   - .rodata :
68   - {
69   - *(.rodata)
70   - *(.rodata1)
71   - *(.rodata.str1.4)
72   - *(.eh_frame)
73   - }
74   - .fini : { *(.fini) } =0
75   - .ctors : { *(.ctors) }
76   - .dtors : { *(.dtors) }
77   -
78   - /* Read-write section, merged into data segment: */
79   - . = (. + 0x0FFF) & 0xFFFFF000;
80   - _erotext = .;
81   - PROVIDE (erotext = .);
82   - .reloc :
83   - {
84   - *(.got)
85   - _GOT2_TABLE_ = .;
86   - *(.got2)
87   - _FIXUP_TABLE_ = .;
88   - *(.fixup)
89   - }
90   - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
91   - __fixup_entries = (. - _FIXUP_TABLE_)>>2;
92   -
93   - .data :
94   - {
95   - *(.data)
96   - *(.data1)
97   - *(.sdata)
98   - *(.sdata2)
99   - *(.dynamic)
100   - CONSTRUCTORS
101   - }
102   - _edata = .;
103   - PROVIDE (edata = .);
104   -
105   - __start___ex_table = .;
106   - __ex_table : { *(__ex_table) }
107   - __stop___ex_table = .;
108   -
109   - . = ALIGN(4096);
110   - __init_begin = .;
111   - .text.init : { *(.text.init) }
112   - .data.init : { *(.data.init) }
113   - . = ALIGN(4096);
114   - __init_end = .;
115   -
116   - __bss_start = .;
117   - .bss :
118   - {
119   - *(.sbss) *(.scommon)
120   - *(.dynbss)
121   - *(.bss)
122   - *(COMMON)
123   - }
124   - __bss_end = . ;
125   - PROVIDE (end = .);
126   -}
configs/ELPT860_defconfig
View file @ 3c5b20f
1   -CONFIG_PPC=y
2   -CONFIG_8xx=y
3   -CONFIG_TARGET_ELPT860=y
doc/README.scrapyard
Diff comments   View file @ 3c5b20f
... ... @@ -12,6 +12,7 @@
12 12  
13 13 Board Arch CPU Commit Removed Last known maintainer/contact
14 14 =================================================================================================
  15 +ELPT860 powerpc mpc8xx - - The LEOX team <team@leox.org>
15 16 hmi1001 powerpc mpc5xxx - -
16 17 mucmc52 powerpc mpc5xxx - - Heiko Schocher <hs@denx.de>
17 18 uc101 powerpc mpc5xxx - - Heiko Schocher <hs@denx.de>
... ... @@ -456,32 +456,6 @@
456 456 #define SICR_ENET_CLKRT ((uint)0x00002c00)
457 457 #endif /* CONFIG_BSEIP */
458 458  
459   -/*** ELPT860 *********************************************************/
460   -
461   -#ifdef CONFIG_ELPT860
462   -/* Bits in parallel I/O port registers that have to be set/cleared
463   - * to configure the pins for SCC1 use.
464   - */
465   -# define PROFF_ENET PROFF_SCC1
466   -# define CPM_CR_ENET CPM_CR_CH_SCC1
467   -# define SCC_ENET 0
468   -
469   -# define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */
470   -# define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */
471   -# define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
472   -# define PA_ENET_TCLK ((ushort)0x0200) /* PA 6 */
473   -
474   -# define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */
475   -# define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */
476   -# define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */
477   -
478   -/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK1) to
479   - * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
480   - */
481   -# define SICR_ENET_MASK ((uint)0x000000FF)
482   -# define SICR_ENET_CLKRT ((uint)0x00000025)
483   -#endif /* CONFIG_ELPT860 */
484   -
485 459 /*** ESTEEM 192E **************************************************/
486 460 #ifdef CONFIG_ESTEEM192E
487 461 /* ESTEEM192E
include/configs/ELPT860.h
View file @ 3c5b20f
1   -/*
2   -**=====================================================================
3   -**
4   -** Copyright (C) 2000, 2001, 2002, 2003
5   -** The LEOX team <team@leox.org>, http://www.leox.org
6   -**
7   -** LEOX.org is about the development of free hardware and software resources
8   -** for system on chip.
9   -**
10   -** Description: U-Boot port on the LEOX's ELPT860 CPU board
11   -** ~~~~~~~~~~~
12   -**
13   -**=====================================================================
14   -**
15   - * SPDX-License-Identifier: GPL-2.0+
16   -**
17   -**=====================================================================
18   -*/
19   -
20   -/*
21   - * board/config.h - configuration options, board specific
22   - */
23   -
24   -#ifndef __CONFIG_H
25   -#define __CONFIG_H
26   -
27   -
28   -/*
29   - * High Level Configuration Options
30   - * (easy to change)
31   - */
32   -
33   -#define CONFIG_MPC860 1 /* It's a MPC860, in fact a 860T CPU */
34   -#define CONFIG_MPC860T 1
35   -#define CONFIG_ELPT860 1 /* ...on a LEOX's ELPT860 CPU board */
36   -
37   -#define CONFIG_SYS_TEXT_BASE 0x02000000
38   -
39   -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
40   -#undef CONFIG_8xx_CONS_SMC2
41   -#undef CONFIG_8xx_CONS_NONE
42   -
43   -#define CONFIG_CLOCKS_IN_MHZ 1 /* Clock passed to Linux (<2.4.5) in MHz */
44   -#define CONFIG_8xx_GCLK_FREQ 50000000 /* MPC860T runs at 50MHz */
45   -
46   -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
47   -
48   -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
49   -#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
50   -
51   -/* BOOT arguments */
52   -#define CONFIG_PREBOOT \
53   - "echo;" \
54   - "echo Type \"run nfsboot\" to mount root filesystem over NFS;" \
55   - "echo"
56   -
57   -#undef CONFIG_BOOTARGS
58   -
59   -#define CONFIG_EXTRA_ENV_SETTINGS \
60   - "ramargs=setenv bootargs root=/dev/ram rw\0" \
61   - "rootargs=setenv rootpath /tftp/${ipaddr}\0" \
62   - "nfsargs=setenv bootargs root=/dev/nfs rw " \
63   - "nfsroot=${serverip}:${rootpath}\0" \
64   - "addip=setenv bootargs ${bootargs} " \
65   - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
66   - ":${hostname}:eth0:off panic=1\0" \
67   - "ramboot=tftp 400000 /home/paugaml/pMulti;" \
68   - "run ramargs;bootm\0" \
69   - "nfsboot=tftp 400000 /home/paugaml/uImage;" \
70   - "run rootargs;run nfsargs;run addip;bootm\0" \
71   - ""
72   -#define CONFIG_BOOTCOMMAND "run ramboot"
73   -
74   -/*
75   - * BOOTP options
76   - */
77   -#define CONFIG_BOOTP_SUBNETMASK
78   -#define CONFIG_BOOTP_GATEWAY
79   -#define CONFIG_BOOTP_HOSTNAME
80   -#define CONFIG_BOOTP_BOOTPATH
81   -#define CONFIG_BOOTP_BOOTFILESIZE
82   -
83   -
84   -#undef CONFIG_WATCHDOG /* watchdog disabled */
85   -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
86   -#undef CONFIG_RTC_MPC8xx /* internal RTC MPC8xx unused */
87   -#define CONFIG_RTC_DS164x 1 /* RTC is a Dallas DS1646 */
88   -
89   -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
90   -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
91   -
92   -
93   -/*
94   - * Command line configuration.
95   - */
96   -#include <config_cmd_default.h>
97   -
98   -#define CONFIG_CMD_ASKENV
99   -#define CONFIG_CMD_DATE
100   -
101   -
102   -/*
103   - * Miscellaneous configurable options
104   - */
105   -#define CONFIG_SYS_LONGHELP /* undef to save memory */
106   -#define CONFIG_SYS_PROMPT "LEOX_elpt860: " /* Monitor Command Prompt */
107   -
108   -#if defined(CONFIG_CMD_KGDB)
109   -# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
110   -#else
111   -# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
112   -#endif
113   -
114   -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
115   -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
116   -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
117   -
118   -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
119   -#define CONFIG_SYS_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */
120   -
121   -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
122   -
123   -/*
124   - * Environment Variables and Storages
125   - */
126   -#define CONFIG_ENV_OVERWRITE 1 /* Allow Overwrite of serial# & ethaddr */
127   -
128   -#undef CONFIG_ENV_IS_IN_NVRAM /* Environment is in NVRAM */
129   -#undef CONFIG_ENV_IS_IN_EEPROM /* Environment is in I2C EEPROM */
130   -#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment is in FLASH */
131   -
132   -#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 bps */
133   -
134   -#define CONFIG_ETHADDR 00:01:77:00:60:40
135   -#define CONFIG_IPADDR 192.168.0.30
136   -#define CONFIG_NETMASK 255.255.255.0
137   -
138   -#define CONFIG_SERVERIP 192.168.0.1
139   -#define CONFIG_GATEWAYIP 192.168.0.1
140   -
141   -/*
142   - * Low Level Configuration Settings
143   - * (address mappings, register initial values, etc.)
144   - * You should know what you are doing if you make changes here.
145   - */
146   -
147   -/*-----------------------------------------------------------------------
148   - * Internal Memory Mapped Register
149   - */
150   -#define CONFIG_SYS_IMMR 0xFF000000
151   -
152   -/*-----------------------------------------------------------------------
153   - * Definitions for initial stack pointer and data area (in DPRAM)
154   - */
155   -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
156   -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
157   -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
158   -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
159   -
160   -/*-----------------------------------------------------------------------
161   - * Start addresses for the final memory configuration
162   - * (Set up by the startup code)
163   - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
164   - */
165   -#define CONFIG_SYS_SDRAM_BASE 0x00000000
166   -#define CONFIG_SYS_FLASH_BASE 0x02000000
167   -#define CONFIG_SYS_NVRAM_BASE 0x03000000
168   -
169   -#if defined(CONFIG_ENV_IS_IN_FLASH)
170   -# if defined(DEBUG)
171   -# define CONFIG_SYS_MONITOR_LEN (320 << 10) /* Reserve 320 kB for Monitor */
172   -# else
173   -# define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
174   -# endif
175   -#else
176   -# if defined(DEBUG)
177   -# define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
178   -# else
179   -# define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
180   -# endif
181   -#endif
182   -
183   -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
184   -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
185   -
186   -/*
187   - * For booting Linux, the board info and command line data
188   - * have to be in the first 8 MB of memory, since this is
189   - * the maximum mapped by the Linux kernel during initialization.
190   - */
191   -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
192   -
193   -/*-----------------------------------------------------------------------
194   - * FLASH organization
195   - */
196   -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
197   -#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
198   -
199   -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
200   -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
201   -
202   -#if defined(CONFIG_ENV_IS_IN_FLASH)
203   -# define CONFIG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */
204   -# define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
205   -#endif
206   -
207   -/*-----------------------------------------------------------------------
208   - * NVRAM organization
209   - */
210   -#define CONFIG_SYS_NVRAM_BASE_ADDR CONFIG_SYS_NVRAM_BASE /* Base address of NVRAM area */
211   -#define CONFIG_SYS_NVRAM_SIZE ((128*1024)-8) /* clock regs resident in the */
212   - /* 8 top NVRAM locations */
213   -
214   -#if defined(CONFIG_ENV_IS_IN_NVRAM)
215   -# define CONFIG_ENV_ADDR CONFIG_SYS_NVRAM_BASE /* Base address of NVRAM area */
216   -# define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
217   -#endif
218   -
219   -/*-----------------------------------------------------------------------
220   - * Cache Configuration
221   - */
222   -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
223   -
224   -#if defined(CONFIG_CMD_KGDB)
225   -# define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
226   -#endif
227   -
228   -/*-----------------------------------------------------------------------
229   - * SYPCR - System Protection Control 11-9
230   - * SYPCR can only be written once after reset!
231   - *-----------------------------------------------------------------------
232   - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
233   - */
234   -#if defined(CONFIG_WATCHDOG)
235   -# define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
236   - SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP)
237   -#else
238   -# define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
239   - SYPCR_SWP)
240   -#endif
241   -
242   -/*-----------------------------------------------------------------------
243   - * SUMCR - SIU Module Configuration 11-6
244   - *-----------------------------------------------------------------------
245   - * PCMCIA config., multi-function pin tri-state
246   - */
247   -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11)
248   -
249   -/*-----------------------------------------------------------------------
250   - * TBSCR - Time Base Status and Control 11-26
251   - *-----------------------------------------------------------------------
252   - * Clear Reference Interrupt Status, Timebase freezing enabled
253   - */
254   -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
255   -
256   -/*-----------------------------------------------------------------------
257   - * RTCSC - Real-Time Clock Status and Control Register 11-27
258   - *-----------------------------------------------------------------------
259   - * Once-per-Second Interrupt, Alarm Interrupt, RTC freezing enabled, RTC
260   - * enabled
261   - */
262   -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
263   -
264   -/*-----------------------------------------------------------------------
265   - * PISCR - Periodic Interrupt Status and Control 11-31
266   - *-----------------------------------------------------------------------
267   - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
268   - */
269   -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
270   -
271   -/*-----------------------------------------------------------------------
272   - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
273   - *-----------------------------------------------------------------------
274   - * Reset PLL lock status sticky bit, timer expired status bit and timer
275   - * interrupt status bit - leave PLL multiplication factor unchanged !
276   - */
277   -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
278   -
279   -/*-----------------------------------------------------------------------
280   - * SCCR - System Clock and reset Control Register 15-27
281   - *-----------------------------------------------------------------------
282   - * Set clock output, timebase and RTC source and divider,
283   - * power management and some other internal clocks
284   - */
285   -#define SCCR_MASK SCCR_EBDF11
286   -#define CONFIG_SYS_SCCR (SCCR_TBS | \
287   - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
288   - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
289   - SCCR_DFALCD00)
290   -
291   -/*-----------------------------------------------------------------------
292   - * Chip Selects + SDRAM timings + Memory Periodic Timer Prescaler
293   - *-----------------------------------------------------------------------
294   - *
295   - */
296   -#ifdef DEBUG
297   -# define CONFIG_SYS_DER 0xFFE7400F /* Debug Enable Register */
298   -#else
299   -# define CONFIG_SYS_DER 0
300   -#endif
301   -
302   -/*
303   - * Init Memory Controller:
304   - * ~~~~~~~~~~~~~~~~~~~~~~
305   - *
306   - * BR0 and OR0 (FLASH)
307   - */
308   -
309   -#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
310   -
311   -/* used to re-map FLASH both when starting from SRAM or FLASH:
312   - * restrict access enough to keep SRAM working (if any)
313   - * but not too much to meddle with FLASH accesses
314   - */
315   -#define CONFIG_SYS_PRELIM_OR_AM 0xFF000000 /* 16 MB between each CSx */
316   -
317   -/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 0, SCY = 8, EHTR = 0 */
318   -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV2 | OR_BI | OR_SCY_8_CLK)
319   -
320   -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
321   -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
322   -
323   -/*
324   - * BR1 and OR1 (SDRAM)
325   - *
326   - */
327   -#define SDRAM_BASE1_PRELIM CONFIG_SYS_SDRAM_BASE /* SDRAM bank #0 */
328   -#define SDRAM_MAX_SIZE 0x02000000 /* 32 MB MAX for CS1 */
329   -
330   -/* SDRAM timing: */
331   -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000000
332   -
333   -#define CONFIG_SYS_OR1_PRELIM ((2 * CONFIG_SYS_PRELIM_OR_AM) | CONFIG_SYS_OR_TIMING_SDRAM )
334   -#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
335   -
336   -/*
337   - * BR2 and OR2 (NVRAM)
338   - *
339   - */
340   -#define NVRAM_BASE1_PRELIM CONFIG_SYS_NVRAM_BASE /* NVRAM bank #0 */
341   -#define NVRAM_MAX_SIZE 0x00020000 /* 128 KB MAX for CS2 */
342   -
343   -#define CONFIG_SYS_OR2_PRELIM 0xFFF80160
344   -#define CONFIG_SYS_BR2_PRELIM ((NVRAM_BASE1_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
345   -
346   -/*
347   - * Memory Periodic Timer Prescaler
348   - */
349   -
350   -/* periodic timer for refresh */
351   -#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */
352   -
353   -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
354   -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
355   -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
356   -
357   -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
358   -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
359   -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
360   -
361   -/*
362   - * MAMR settings for SDRAM
363   - */
364   -
365   -/* 8 column SDRAM */
366   -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
367   - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
368   - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
369   -/* 9 column SDRAM */
370   -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
371   - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
372   - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
373   -
374   -#endif /* __CONFIG_H */