Eric Lee / smarc-uboot | Embedian Git Server

Commit 3c692f9706a1d85dc5fc518fa8503c1862f15088

Authored by Wolfgang Denk 2012-07-21 04:35:13 +0800

Exists in master and in 54 other branches

Merge branch 'master' of git://git.denx.de/u-boot-nds32

* 'master' of git://git.denx.de/u-boot-nds32:
  nds32: split common cache access from cpu into lib

Signed-off-by: Wolfgang Denk <wd@denx.de>

Showing 4 changed files Inline Diff

arch/nds32/cpu/n1213/ag101/cpu.c
arch/nds32/cpu/n1213/ag102/cpu.c
arch/nds32/lib/Makefile
arch/nds32/lib/cache.c

arch/nds32/cpu/n1213/ag101/cpu.c

Diff comments View file @ 3c692f9

1	/*	1	/*
2	* (C) Copyright 2002	2	* (C) Copyright 2002
3	* Sysgo Real-Time Solutions, GmbH <www.elinos.com>	3	* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4	* Marius Groeger <mgroeger@sysgo.de>	4	* Marius Groeger <mgroeger@sysgo.de>
5	*	5	*
6	* (C) Copyright 2002	6	* (C) Copyright 2002
7	* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>	7	* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
8	*	8	*
9	* Copyright (C) 2011 Andes Technology Corporation	9	* Copyright (C) 2011 Andes Technology Corporation
10	* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>	10	* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
11	* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>	11	* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
12	*	12	*
13	* See file CREDITS for list of people who contributed to this	13	* See file CREDITS for list of people who contributed to this
14	* project.	14	* project.
15	*	15	*
16	* This program is free software; you can redistribute it and/or	16	* This program is free software; you can redistribute it and/or
17	* modify it under the terms of the GNU General Public License as	17	* modify it under the terms of the GNU General Public License as
18	* published by the Free Software Foundation; either version 2 of	18	* published by the Free Software Foundation; either version 2 of
19	* the License, or (at your option) any later version.	19	* the License, or (at your option) any later version.
20	*	20	*
21	* This program is distributed in the hope that it will be useful,	21	* This program is distributed in the hope that it will be useful,
22	* but WITHOUT ANY WARRANTY; without even the implied warranty of	22	* but WITHOUT ANY WARRANTY; without even the implied warranty of
23	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	23	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24	* GNU General Public License for more details.	24	* GNU General Public License for more details.
25	*	25	*
26	* You should have received a copy of the GNU General Public License	26	* You should have received a copy of the GNU General Public License
27	* along with this program; if not, write to the Free Software	27	* along with this program; if not, write to the Free Software
28	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,	28	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29	* MA 02111-1307 USA	29	* MA 02111-1307 USA
30	*/	30	*/
31		31
32	/* CPU specific code */	32	/* CPU specific code */
33	#include <common.h>	33	#include <common.h>
34	#include <command.h>	34	#include <command.h>
35	#include <watchdog.h>	35	#include <watchdog.h>
36	#include <asm/cache.h>	36	#include <asm/cache.h>
37		37
38	#include <faraday/ftwdt010_wdt.h>	38	#include <faraday/ftwdt010_wdt.h>
39		39
40	/*	40	/*
41	* cleanup_before_linux() is called just before we call linux	41	* cleanup_before_linux() is called just before we call linux
42	* it prepares the processor for linux	42	* it prepares the processor for linux
43	*	43	*
44	* we disable interrupt and caches.	44	* we disable interrupt and caches.
45	*/	45	*/
46	int cleanup_before_linux(void)	46	int cleanup_before_linux(void)
47	{	47	{
48	disable_interrupts();	48	disable_interrupts();
49		49
50	#ifdef CONFIG_MMU	50	#ifdef CONFIG_MMU
51	/* turn off I/D-cache */	51	/* turn off I/D-cache */
52	icache_disable();	52	icache_disable();
53	dcache_disable();	53	dcache_disable();
54		54
55	/* flush I/D-cache */	55	/* flush I/D-cache */
56	invalidate_icac();	56	invalidate_icac();
57	invalidate_dcac();	57	invalidate_dcac();
58	#endif	58	#endif
59		59
60	return 0;	60	return 0;
61	}	61	}
62		62
63	int do_reset(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])	63	int do_reset(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
64	{	64	{
65	disable_interrupts();	65	disable_interrupts();
66		66
67	/*	67	/*
68	* reset to the base addr of andesboot.	68	* reset to the base addr of andesboot.
69	* currently no ROM loader at addr 0.	69	* currently no ROM loader at addr 0.
70	* do not use reset_cpu(0);	70	* do not use reset_cpu(0);
71	*/	71	*/
72	#ifdef CONFIG_FTWDT010_WATCHDOG	72	#ifdef CONFIG_FTWDT010_WATCHDOG
73	/*	73	/*
74	* workaround: if we use CONFIG_HW_WATCHDOG with ftwdt010, will lead	74	* workaround: if we use CONFIG_HW_WATCHDOG with ftwdt010, will lead
75	* automatic hardware reset when booting Linux.	75	* automatic hardware reset when booting Linux.
76	* Please do not use CONFIG_HW_WATCHDOG and WATCHDOG_RESET() here.	76	* Please do not use CONFIG_HW_WATCHDOG and WATCHDOG_RESET() here.
77	*/	77	*/
78	ftwdt010_wdt_reset();	78	ftwdt010_wdt_reset();
79	while (1)	79	while (1)
80	;	80	;
81	#endif /* CONFIG_FTWDT010_WATCHDOG */	81	#endif /* CONFIG_FTWDT010_WATCHDOG */
82		82
83	/NOTREACHED/	83	/NOTREACHED/
84	}	84	}
85
86	static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
87	{
88	if (cache == ICACHE)
89	return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
90	>> ICM_CFG_OFF_ISZ) - 1);
91	else
92	return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
93	>> DCM_CFG_OFF_DSZ) - 1);
94	}
95
96	void dcache_flush_range(unsigned long start, unsigned long end)
97	{
98	unsigned long line_size;
99
100	line_size = CACHE_LINE_SIZE(DCACHE);
101
102	while (end > start) {
103	__asm__ volatile ("\n\tcctl %0, L1D_VA_WB" : : "r"(start));
104	__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL" : : "r"(start));
105	start += line_size;
106	}
107	}
108
109	void icache_inval_range(unsigned long start, unsigned long end)
110	{
111	unsigned long line_size;
112
113	line_size = CACHE_LINE_SIZE(ICACHE);
114	while (end > start) {
115	__asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL" : : "r"(start));
116	start += line_size;
117	}
118	}
119
120	void flush_cache(unsigned long addr, unsigned long size)
121	{
122	dcache_flush_range(addr, addr + size);
123	icache_inval_range(addr, addr + size);
124	}
125
126	void icache_enable(void)
127	{
128	__asm__ __volatile__ (
129	"mfsr $p0, $mr8\n\t"
130	"ori $p0, $p0, 0x01\n\t"
131	"mtsr $p0, $mr8\n\t"
132	"isb\n\t"
133	);
134	}
135
136	void icache_disable(void)
137	{
138	__asm__ __volatile__ (
139	"mfsr $p0, $mr8\n\t"
140	"li $p1, ~0x01\n\t"
141	"and $p0, $p0, $p1\n\t"
142	"mtsr $p0, $mr8\n\t"
143	"isb\n\t"
144	);
145	}
146
147	int icache_status(void)
148	{
149	int ret;
150
151	__asm__ __volatile__ (
152	"mfsr $p0, $mr8\n\t"
153	"andi %0, $p0, 0x01\n\t"
154	: "=r" (ret)
155	:
156	: "memory"
157	);
158
159	return ret;
160	}
161
162	void dcache_enable(void)
163	{
164	__asm__ __volatile__ (
165	"mfsr $p0, $mr8\n\t"
166	"ori $p0, $p0, 0x02\n\t"
167	"mtsr $p0, $mr8\n\t"
168	"isb\n\t"
169	);
170	}
171
172	void dcache_disable(void)
173	{
174	__asm__ __volatile__ (
175	"mfsr $p0, $mr8\n\t"
176	"li $p1, ~0x02\n\t"
177	"and $p0, $p0, $p1\n\t"
178	"mtsr $p0, $mr8\n\t"
179	"isb\n\t"
180	);
181	}
182
183	int dcache_status(void)
184	{
185	int ret;
186
187	__asm__ __volatile__ (
188	"mfsr $p0, $mr8\n\t"
189	"andi %0, $p0, 0x02\n\t"
190	: "=r" (ret)
191	:
192	: "memory"
193	);
194
195	return ret;
196	}
197		85

arch/nds32/cpu/n1213/ag102/cpu.c

Diff comments View file @ 3c692f9

1	/*	1	/*
2	* (C) Copyright 2002	2	* (C) Copyright 2002
3	* Sysgo Real-Time Solutions, GmbH <www.elinos.com>	3	* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4	* Marius Groeger <mgroeger@sysgo.de>	4	* Marius Groeger <mgroeger@sysgo.de>
5	*	5	*
6	* (C) Copyright 2002	6	* (C) Copyright 2002
7	* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>	7	* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
8	*	8	*
9	* Copyright (C) 2011 Andes Technology Corporation	9	* Copyright (C) 2011 Andes Technology Corporation
10	* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>	10	* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
11	* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>	11	* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
12	*	12	*
13	* See file CREDITS for list of people who contributed to this	13	* See file CREDITS for list of people who contributed to this
14	* project.	14	* project.
15	*	15	*
16	* This program is free software; you can redistribute it and/or	16	* This program is free software; you can redistribute it and/or
17	* modify it under the terms of the GNU General Public License as	17	* modify it under the terms of the GNU General Public License as
18	* published by the Free Software Foundation; either version 2 of	18	* published by the Free Software Foundation; either version 2 of
19	* the License, or (at your option) any later version.	19	* the License, or (at your option) any later version.
20	*	20	*
21	* This program is distributed in the hope that it will be useful,	21	* This program is distributed in the hope that it will be useful,
22	* but WITHOUT ANY WARRANTY; without even the implied warranty of	22	* but WITHOUT ANY WARRANTY; without even the implied warranty of
23	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	23	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24	* GNU General Public License for more details.	24	* GNU General Public License for more details.
25	*	25	*
26	* You should have received a copy of the GNU General Public License	26	* You should have received a copy of the GNU General Public License
27	* along with this program; if not, write to the Free Software	27	* along with this program; if not, write to the Free Software
28	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,	28	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29	* MA 02111-1307 USA	29	* MA 02111-1307 USA
30	*/	30	*/
31		31
32	/* CPU specific code */	32	/* CPU specific code */
33	#include <common.h>	33	#include <common.h>
34	#include <command.h>	34	#include <command.h>
35	#include <watchdog.h>	35	#include <watchdog.h>
36	#include <asm/cache.h>	36	#include <asm/cache.h>
37		37
38	#include <faraday/ftwdt010_wdt.h>	38	#include <faraday/ftwdt010_wdt.h>
39		39
40	/*	40	/*
41	* cleanup_before_linux() is called just before we call linux	41	* cleanup_before_linux() is called just before we call linux
42	* it prepares the processor for linux	42	* it prepares the processor for linux
43	*	43	*
44	* we disable interrupt and caches.	44	* we disable interrupt and caches.
45	*/	45	*/
46	int cleanup_before_linux(void)	46	int cleanup_before_linux(void)
47	{	47	{
48	disable_interrupts();	48	disable_interrupts();
49		49
50	#ifdef CONFIG_MMU	50	#ifdef CONFIG_MMU
51	/* turn off I/D-cache */	51	/* turn off I/D-cache */
52	icache_disable();	52	icache_disable();
53	dcache_disable();	53	dcache_disable();
54		54
55	/* flush I/D-cache */	55	/* flush I/D-cache */
56	invalidate_icac();	56	invalidate_icac();
57	invalidate_dcac();	57	invalidate_dcac();
58	#endif	58	#endif
59		59
60	return 0;	60	return 0;
61	}	61	}
62		62
63	int do_reset(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])	63	int do_reset(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
64	{	64	{
65	disable_interrupts();	65	disable_interrupts();
66		66
67	/*	67	/*
68	* reset to the base addr of andesboot.	68	* reset to the base addr of andesboot.
69	* currently no ROM loader at addr 0.	69	* currently no ROM loader at addr 0.
70	* do not use reset_cpu(0);	70	* do not use reset_cpu(0);
71	*/	71	*/
72	#ifdef CONFIG_FTWDT010_WATCHDOG	72	#ifdef CONFIG_FTWDT010_WATCHDOG
73	/*	73	/*
74	* workaround: if we use CONFIG_HW_WATCHDOG with ftwdt010, will lead	74	* workaround: if we use CONFIG_HW_WATCHDOG with ftwdt010, will lead
75	* automatic hardware reset when booting Linux.	75	* automatic hardware reset when booting Linux.
76	* Please do not use CONFIG_HW_WATCHDOG and WATCHDOG_RESET() here.	76	* Please do not use CONFIG_HW_WATCHDOG and WATCHDOG_RESET() here.
77	*/	77	*/
78	ftwdt010_wdt_reset();	78	ftwdt010_wdt_reset();
79	#endif /* CONFIG_FTWDT010_WATCHDOG */	79	#endif /* CONFIG_FTWDT010_WATCHDOG */
80	hang();	80	hang();
81		81
82	/NOTREACHED/	82	/NOTREACHED/
83	}	83	}
84
85	static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
86	{
87	if (cache == ICACHE)
88	return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
89	>> ICM_CFG_OFF_ISZ) - 1);
90	else
91	return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
92	>> DCM_CFG_OFF_DSZ) - 1);
93	}
94
95	void dcache_flush_range(unsigned long start, unsigned long end)
96	{
97	unsigned long line_size;
98
99	line_size = CACHE_LINE_SIZE(DCACHE);
100
101	while (end > start) {
102	__asm__ volatile ("\n\tcctl %0, L1D_VA_WB" : : "r"(start));
103	__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL" : : "r"(start));
104	start += line_size;
105	}
106	}
107
108	void icache_inval_range(unsigned long start, unsigned long end)
109	{
110	unsigned long line_size;
111
112	line_size = CACHE_LINE_SIZE(ICACHE);
113	while (end > start) {
114	__asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL" : : "r"(start));
115	start += line_size;
116	}
117	}
118
119	void flush_cache(unsigned long addr, unsigned long size)
120	{
121	dcache_flush_range(addr, addr + size);
122	icache_inval_range(addr, addr + size);
123	}
124
125	void icache_enable(void)
126	{
127	__asm__ __volatile__ (
128	"mfsr $p0, $mr8\n\t"
129	"ori $p0, $p0, 0x01\n\t"
130	"mtsr $p0, $mr8\n\t"
131	"isb\n\t"
132	);
133	}
134
135	void icache_disable(void)
136	{
137	__asm__ __volatile__ (
138	"mfsr $p0, $mr8\n\t"
139	"li $p1, ~0x01\n\t"
140	"and $p0, $p0, $p1\n\t"
141	"mtsr $p0, $mr8\n\t"
142	"isb\n\t"
143	);
144	}
145
146	int icache_status(void)
147	{
148	int ret;
149
150	__asm__ __volatile__ (
151	"mfsr $p0, $mr8\n\t"
152	"andi %0, $p0, 0x01\n\t"
153	: "=r" (ret)
154	:
155	: "memory"
156	);
157
158	return ret;
159	}
160
161	void dcache_enable(void)
162	{
163	__asm__ __volatile__ (
164	"mfsr $p0, $mr8\n\t"
165	"ori $p0, $p0, 0x02\n\t"
166	"mtsr $p0, $mr8\n\t"
167	"isb\n\t"
168	);
169	}
170
171	void dcache_disable(void)
172	{
173	__asm__ __volatile__ (
174	"mfsr $p0, $mr8\n\t"
175	"li $p1, ~0x02\n\t"
176	"and $p0, $p0, $p1\n\t"
177	"mtsr $p0, $mr8\n\t"
178	"isb\n\t"
179	);
180	}
181
182	int dcache_status(void)
183	{
184	int ret;
185
186	__asm__ __volatile__ (
187	"mfsr $p0, $mr8\n\t"
188	"andi %0, $p0, 0x02\n\t"
189	: "=r" (ret)
190	:
191	: "memory"
192	);
193
194	return ret;
195	}
196		84

arch/nds32/lib/Makefile

Diff comments View file @ 3c692f9

arch/nds32/lib/cache.c

Diff comments View file @ 3c692f9

File was created	1	/*
	2	* Copyright (C) 2012 Andes Technology Corporation
	3	* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
	4	* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*
	20	*/
	21
	22	#include <common.h>
	23
	24	static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
	25	{
	26	if (cache == ICACHE)
	27	return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
	28	>> ICM_CFG_OFF_ISZ) - 1);
	29	else
	30	return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
	31	>> DCM_CFG_OFF_DSZ) - 1);
	32	}
	33
	34	void flush_dcache_range(unsigned long start, unsigned long end)
	35	{
	36	unsigned long line_size;
	37
	38	line_size = CACHE_LINE_SIZE(DCACHE);
	39
	40	while (end > start) {
	41	asm volatile (
	42	"\n\tcctl %0, L1D_VA_WB"
	43	"\n\tcctl %0, L1D_VA_INVAL"
	44	:
	45	: "r" (start)
	46	);
	47	start += line_size;
	48	}
	49	}
	50
	51	void invalidate_icache_range(unsigned long start, unsigned long end)
	52	{
	53	unsigned long line_size;
	54
	55	line_size = CACHE_LINE_SIZE(ICACHE);
	56	while (end > start) {
	57	asm volatile (
	58	"\n\tcctl %0, L1I_VA_INVAL"
	59	:
	60	: "r"(start)
	61	);
	62	start += line_size;
	63	}
	64	}
	65
	66	void invalidate_dcache_range(unsigned long start, unsigned long end)
	67	{
	68	unsigned long line_size;
	69
	70	line_size = CACHE_LINE_SIZE(DCACHE);
	71	while (end > start) {
	72	asm volatile (
	73	"\n\tcctl %0, L1D_VA_INVAL"
	74	:
	75	: "r"(start)
	76	);
	77	start += line_size;
	78	}
	79	}
	80
	81	void flush_cache(unsigned long addr, unsigned long size)
	82	{
	83	flush_dcache_range(addr, addr + size);
	84	invalidate_icache_range(addr, addr + size);
	85	}
	86
	87	void icache_enable(void)
	88	{
	89	asm volatile (
	90	"mfsr $p0, $mr8\n\t"
	91	"ori $p0, $p0, 0x01\n\t"
	92	"mtsr $p0, $mr8\n\t"
	93	"isb\n\t"
	94	);
	95	}
	96
	97	void icache_disable(void)
	98	{
	99	asm volatile (
	100	"mfsr $p0, $mr8\n\t"
	101	"li $p1, ~0x01\n\t"
	102	"and $p0, $p0, $p1\n\t"
	103	"mtsr $p0, $mr8\n\t"
	104	"isb\n\t"
	105	);
	106	}
	107
	108	int icache_status(void)
	109	{
	110	int ret;
	111
	112	asm volatile (
	113	"mfsr $p0, $mr8\n\t"
	114	"andi %0, $p0, 0x01\n\t"
	115	: "=r" (ret)
	116	:
	117	: "memory"
	118	);
	119
	120	return ret;
	121	}
	122
	123	void dcache_enable(void)
	124	{
	125	asm volatile (
	126	"mfsr $p0, $mr8\n\t"
	127	"ori $p0, $p0, 0x02\n\t"
	128	"mtsr $p0, $mr8\n\t"
	129	"isb\n\t"
	130	);
	131	}
	132
	133	void dcache_disable(void)
	134	{
	135	asm volatile (
	136	"mfsr $p0, $mr8\n\t"
	137	"li $p1, ~0x02\n\t"
	138	"and $p0, $p0, $p1\n\t"
	139	"mtsr $p0, $mr8\n\t"
	140	"isb\n\t"
	141	);
	142	}
	143
	144	int dcache_status(void)
	145	{
	146	int ret;
	147
	148	asm volatile (
	149	"mfsr $p0, $mr8\n\t"
	150	"andi %0, $p0, 0x02\n\t"
	151	: "=r" (ret)
	152	:
	153	: "memory"
	154	);
	155
	156	return ret;
	157	}
	158

1	#	1	#
2	# (C) Copyright 2000-2006	2	# (C) Copyright 2000-2006
3	# Wolfgang Denk, DENX Software Engineering, wd@denx.de.	3	# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4	#	4	#
5	# Copyright (C) 2011 Andes Technology Corporation	5	# Copyright (C) 2011 Andes Technology Corporation
6	# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>	6	# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
7	# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>	7	# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
8	#	8	#
9	# See file CREDITS for list of people who contributed to this	9	# See file CREDITS for list of people who contributed to this
10	# project.	10	# project.
11	#	11	#
12	# This program is free software; you can redistribute it and/or	12	# This program is free software; you can redistribute it and/or
13	# modify it under the terms of the GNU General Public License as	13	# modify it under the terms of the GNU General Public License as
14	# published by the Free Software Foundation; either version 2 of	14	# published by the Free Software Foundation; either version 2 of
15	# the License, or (at your option) any later version.	15	# the License, or (at your option) any later version.
16	#	16	#
17	# This program is distributed in the hope that it will be useful,	17	# This program is distributed in the hope that it will be useful,
18	# but WITHOUT ANY WARRANTY; without even the implied warranty of	18	# but WITHOUT ANY WARRANTY; without even the implied warranty of
19	# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	19	# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20	# GNU General Public License for more details.	20	# GNU General Public License for more details.
21	#	21	#
22	# You should have received a copy of the GNU General Public License	22	# You should have received a copy of the GNU General Public License
23	# along with this program; if not, write to the Free Software	23	# along with this program; if not, write to the Free Software
24	# Foundation, Inc., 59 Temple Place, Suite 330, Boston,	24	# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25	# MA 02111-1307 USA	25	# MA 02111-1307 USA
26	#	26	#
27		27
28	include $(TOPDIR)/config.mk	28	include $(TOPDIR)/config.mk
29		29
30	LIB = $(obj)lib$(ARCH).o	30	LIB = $(obj)lib$(ARCH).o
31		31
32	OBJS := board.o bootm.o interrupts.o	32	OBJS := board.o bootm.o cache.o interrupts.o
33		33
34	all: $(LIB)	34	all: $(LIB)
35		35
36	$(LIB): $(OBJS) $(SOBJS)	36	$(LIB): $(OBJS) $(SOBJS)
37	$(call cmd_link_o_target, $(OBJS))	37	$(call cmd_link_o_target, $(OBJS))
38		38
39	#########################################################################	39	#########################################################################
40		40
41	# defines $(obj).depend target	41	# defines $(obj).depend target
42	include $(SRCTREE)/rules.mk	42	include $(SRCTREE)/rules.mk
43		43
44	sinclude $(obj).depend	44	sinclude $(obj).depend
45		45
46	#########################################################################	46	#########################################################################
47		47