Eric Lee / smarc-uboot

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Commit 3c692f9706a1d85dc5fc518fa8503c1862f15088

Authored by Wolfgang Denk
2 parents 546910f85f 8d732840ba
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Merge branch 'master' of git://git.denx.de/u-boot-nds32 

* 'master' of git://git.denx.de/u-boot-nds32:
  nds32: split common cache access from cpu into lib

Signed-off-by: Wolfgang Denk <wd@denx.de>

Showing 4 changed files Side-by-side Diff

arch/nds32/cpu/n1213/ag101/cpu.c
Diff comments   View file @ 3c692f9
... ... @@ -82,116 +82,4 @@
82 82  
83 83 /*NOTREACHED*/
84 84 }
85   -
86   -static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
87   -{
88   - if (cache == ICACHE)
89   - return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
90   - >> ICM_CFG_OFF_ISZ) - 1);
91   - else
92   - return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
93   - >> DCM_CFG_OFF_DSZ) - 1);
94   -}
95   -
96   -void dcache_flush_range(unsigned long start, unsigned long end)
97   -{
98   - unsigned long line_size;
99   -
100   - line_size = CACHE_LINE_SIZE(DCACHE);
101   -
102   - while (end > start) {
103   - __asm__ volatile ("\n\tcctl %0, L1D_VA_WB" : : "r"(start));
104   - __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL" : : "r"(start));
105   - start += line_size;
106   - }
107   -}
108   -
109   -void icache_inval_range(unsigned long start, unsigned long end)
110   -{
111   - unsigned long line_size;
112   -
113   - line_size = CACHE_LINE_SIZE(ICACHE);
114   - while (end > start) {
115   - __asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL" : : "r"(start));
116   - start += line_size;
117   - }
118   -}
119   -
120   -void flush_cache(unsigned long addr, unsigned long size)
121   -{
122   - dcache_flush_range(addr, addr + size);
123   - icache_inval_range(addr, addr + size);
124   -}
125   -
126   -void icache_enable(void)
127   -{
128   - __asm__ __volatile__ (
129   - "mfsr $p0, $mr8\n\t"
130   - "ori $p0, $p0, 0x01\n\t"
131   - "mtsr $p0, $mr8\n\t"
132   - "isb\n\t"
133   - );
134   -}
135   -
136   -void icache_disable(void)
137   -{
138   - __asm__ __volatile__ (
139   - "mfsr $p0, $mr8\n\t"
140   - "li $p1, ~0x01\n\t"
141   - "and $p0, $p0, $p1\n\t"
142   - "mtsr $p0, $mr8\n\t"
143   - "isb\n\t"
144   - );
145   -}
146   -
147   -int icache_status(void)
148   -{
149   - int ret;
150   -
151   - __asm__ __volatile__ (
152   - "mfsr $p0, $mr8\n\t"
153   - "andi %0, $p0, 0x01\n\t"
154   - : "=r" (ret)
155   - :
156   - : "memory"
157   - );
158   -
159   - return ret;
160   -}
161   -
162   -void dcache_enable(void)
163   -{
164   - __asm__ __volatile__ (
165   - "mfsr $p0, $mr8\n\t"
166   - "ori $p0, $p0, 0x02\n\t"
167   - "mtsr $p0, $mr8\n\t"
168   - "isb\n\t"
169   - );
170   -}
171   -
172   -void dcache_disable(void)
173   -{
174   - __asm__ __volatile__ (
175   - "mfsr $p0, $mr8\n\t"
176   - "li $p1, ~0x02\n\t"
177   - "and $p0, $p0, $p1\n\t"
178   - "mtsr $p0, $mr8\n\t"
179   - "isb\n\t"
180   - );
181   -}
182   -
183   -int dcache_status(void)
184   -{
185   - int ret;
186   -
187   - __asm__ __volatile__ (
188   - "mfsr $p0, $mr8\n\t"
189   - "andi %0, $p0, 0x02\n\t"
190   - : "=r" (ret)
191   - :
192   - : "memory"
193   - );
194   -
195   - return ret;
196   -}
arch/nds32/cpu/n1213/ag102/cpu.c
Diff comments   View file @ 3c692f9
... ... @@ -81,116 +81,4 @@
81 81  
82 82 /*NOTREACHED*/
83 83 }
84   -
85   -static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
86   -{
87   - if (cache == ICACHE)
88   - return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
89   - >> ICM_CFG_OFF_ISZ) - 1);
90   - else
91   - return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
92   - >> DCM_CFG_OFF_DSZ) - 1);
93   -}
94   -
95   -void dcache_flush_range(unsigned long start, unsigned long end)
96   -{
97   - unsigned long line_size;
98   -
99   - line_size = CACHE_LINE_SIZE(DCACHE);
100   -
101   - while (end > start) {
102   - __asm__ volatile ("\n\tcctl %0, L1D_VA_WB" : : "r"(start));
103   - __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL" : : "r"(start));
104   - start += line_size;
105   - }
106   -}
107   -
108   -void icache_inval_range(unsigned long start, unsigned long end)
109   -{
110   - unsigned long line_size;
111   -
112   - line_size = CACHE_LINE_SIZE(ICACHE);
113   - while (end > start) {
114   - __asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL" : : "r"(start));
115   - start += line_size;
116   - }
117   -}
118   -
119   -void flush_cache(unsigned long addr, unsigned long size)
120   -{
121   - dcache_flush_range(addr, addr + size);
122   - icache_inval_range(addr, addr + size);
123   -}
124   -
125   -void icache_enable(void)
126   -{
127   - __asm__ __volatile__ (
128   - "mfsr $p0, $mr8\n\t"
129   - "ori $p0, $p0, 0x01\n\t"
130   - "mtsr $p0, $mr8\n\t"
131   - "isb\n\t"
132   - );
133   -}
134   -
135   -void icache_disable(void)
136   -{
137   - __asm__ __volatile__ (
138   - "mfsr $p0, $mr8\n\t"
139   - "li $p1, ~0x01\n\t"
140   - "and $p0, $p0, $p1\n\t"
141   - "mtsr $p0, $mr8\n\t"
142   - "isb\n\t"
143   - );
144   -}
145   -
146   -int icache_status(void)
147   -{
148   - int ret;
149   -
150   - __asm__ __volatile__ (
151   - "mfsr $p0, $mr8\n\t"
152   - "andi %0, $p0, 0x01\n\t"
153   - : "=r" (ret)
154   - :
155   - : "memory"
156   - );
157   -
158   - return ret;
159   -}
160   -
161   -void dcache_enable(void)
162   -{
163   - __asm__ __volatile__ (
164   - "mfsr $p0, $mr8\n\t"
165   - "ori $p0, $p0, 0x02\n\t"
166   - "mtsr $p0, $mr8\n\t"
167   - "isb\n\t"
168   - );
169   -}
170   -
171   -void dcache_disable(void)
172   -{
173   - __asm__ __volatile__ (
174   - "mfsr $p0, $mr8\n\t"
175   - "li $p1, ~0x02\n\t"
176   - "and $p0, $p0, $p1\n\t"
177   - "mtsr $p0, $mr8\n\t"
178   - "isb\n\t"
179   - );
180   -}
181   -
182   -int dcache_status(void)
183   -{
184   - int ret;
185   -
186   - __asm__ __volatile__ (
187   - "mfsr $p0, $mr8\n\t"
188   - "andi %0, $p0, 0x02\n\t"
189   - : "=r" (ret)
190   - :
191   - : "memory"
192   - );
193   -
194   - return ret;
195   -}
arch/nds32/lib/Makefile
Diff comments   View file @ 3c692f9
... ... @@ -29,7 +29,7 @@
29 29  
30 30 LIB = $(obj)lib$(ARCH).o
31 31  
32   -OBJS := board.o bootm.o interrupts.o
  32 +OBJS := board.o bootm.o cache.o interrupts.o
33 33  
34 34 all: $(LIB)
35 35  
arch/nds32/lib/cache.c
Diff comments   View file @ 3c692f9
  1 +/*
  2 + * Copyright (C) 2012 Andes Technology Corporation
  3 + * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
  4 + * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
  5 + *
  6 + * This program is free software; you can redistribute it and/or modify
  7 + * it under the terms of the GNU General Public License as published by
  8 + * the Free Software Foundation; either version 2 of the License, or
  9 + * (at your option) any later version.
  10 + *
  11 + * This program is distributed in the hope that it will be useful,
  12 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14 + * GNU General Public License for more details.
  15 + *
  16 + * You should have received a copy of the GNU General Public License
  17 + * along with this program; if not, write to the Free Software
  18 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19 + *
  20 + */
  21 +
  22 +#include <common.h>
  23 +
  24 +static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
  25 +{
  26 + if (cache == ICACHE)
  27 + return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
  28 + >> ICM_CFG_OFF_ISZ) - 1);
  29 + else
  30 + return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
  31 + >> DCM_CFG_OFF_DSZ) - 1);
  32 +}
  33 +
  34 +void flush_dcache_range(unsigned long start, unsigned long end)
  35 +{
  36 + unsigned long line_size;
  37 +
  38 + line_size = CACHE_LINE_SIZE(DCACHE);
  39 +
  40 + while (end > start) {
  41 + asm volatile (
  42 + "\n\tcctl %0, L1D_VA_WB"
  43 + "\n\tcctl %0, L1D_VA_INVAL"
  44 + :
  45 + : "r" (start)
  46 + );
  47 + start += line_size;
  48 + }
  49 +}
  50 +
  51 +void invalidate_icache_range(unsigned long start, unsigned long end)
  52 +{
  53 + unsigned long line_size;
  54 +
  55 + line_size = CACHE_LINE_SIZE(ICACHE);
  56 + while (end > start) {
  57 + asm volatile (
  58 + "\n\tcctl %0, L1I_VA_INVAL"
  59 + :
  60 + : "r"(start)
  61 + );
  62 + start += line_size;
  63 + }
  64 +}
  65 +
  66 +void invalidate_dcache_range(unsigned long start, unsigned long end)
  67 +{
  68 + unsigned long line_size;
  69 +
  70 + line_size = CACHE_LINE_SIZE(DCACHE);
  71 + while (end > start) {
  72 + asm volatile (
  73 + "\n\tcctl %0, L1D_VA_INVAL"
  74 + :
  75 + : "r"(start)
  76 + );
  77 + start += line_size;
  78 + }
  79 +}
  80 +
  81 +void flush_cache(unsigned long addr, unsigned long size)
  82 +{
  83 + flush_dcache_range(addr, addr + size);
  84 + invalidate_icache_range(addr, addr + size);
  85 +}
  86 +
  87 +void icache_enable(void)
  88 +{
  89 + asm volatile (
  90 + "mfsr $p0, $mr8\n\t"
  91 + "ori $p0, $p0, 0x01\n\t"
  92 + "mtsr $p0, $mr8\n\t"
  93 + "isb\n\t"
  94 + );
  95 +}
  96 +
  97 +void icache_disable(void)
  98 +{
  99 + asm volatile (
  100 + "mfsr $p0, $mr8\n\t"
  101 + "li $p1, ~0x01\n\t"
  102 + "and $p0, $p0, $p1\n\t"
  103 + "mtsr $p0, $mr8\n\t"
  104 + "isb\n\t"
  105 + );
  106 +}
  107 +
  108 +int icache_status(void)
  109 +{
  110 + int ret;
  111 +
  112 + asm volatile (
  113 + "mfsr $p0, $mr8\n\t"
  114 + "andi %0, $p0, 0x01\n\t"
  115 + : "=r" (ret)
  116 + :
  117 + : "memory"
  118 + );
  119 +
  120 + return ret;
  121 +}
  122 +
  123 +void dcache_enable(void)
  124 +{
  125 + asm volatile (
  126 + "mfsr $p0, $mr8\n\t"
  127 + "ori $p0, $p0, 0x02\n\t"
  128 + "mtsr $p0, $mr8\n\t"
  129 + "isb\n\t"
  130 + );
  131 +}
  132 +
  133 +void dcache_disable(void)
  134 +{
  135 + asm volatile (
  136 + "mfsr $p0, $mr8\n\t"
  137 + "li $p1, ~0x02\n\t"
  138 + "and $p0, $p0, $p1\n\t"
  139 + "mtsr $p0, $mr8\n\t"
  140 + "isb\n\t"
  141 + );
  142 +}
  143 +
  144 +int dcache_status(void)
  145 +{
  146 + int ret;
  147 +
  148 + asm volatile (
  149 + "mfsr $p0, $mr8\n\t"
  150 + "andi %0, $p0, 0x02\n\t"
  151 + : "=r" (ret)
  152 + :
  153 + : "memory"
  154 + );
  155 +
  156 + return ret;
  157 +}