MIPS: Jz4740: Add qi_lb60 board support

Add support for the qi_lb60 (a.k.a QI Ben NanoNote) clamshell device from Qi hardware: http://en.qi-hardware.com/wiki/Ben_NanoNote http://en.qi-hardware.com/wiki/Main_Page http://en.wikipedia.org/wiki/Qi_hardware This Jz4740-based clamshell device does not use NOR flash to boot. The initial bring-up assumes that U-Boot is directly loaded into SDRAM using USB boot tool, and starts from 0x80100000. About USB boot tool ------------------- Jz4740 is one of the XBurst processors with USB boot functionality supported. The CPU can boot from a small ROM in the LSI, initialize CPU and USB module, then wait for USB commands from the USB host. We can send 8 KB binary data to the CPU cache using USB boot tool. USB boot tool is available to the public at Ingenic website. Also there is an alternative Debian package named xburst-tools. Signed-off-by: Xiangfu Liu <xiangfu@openmobilefree.net> Acked-by: Daniel <zpxu@ingenic.cn> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>

MIPS: Jz4740: Add qi_lb60 board support
Add support for the qi_lb60 (a.k.a QI Ben NanoNote) clamshell device from Qi hardware: http://en.qi-hardware.com/wiki/Ben_NanoNote http://en.qi-hardware.com/wiki/Main_Page http://en.wikipedia.org/wiki/Qi_hardware This Jz4740-based clamshell device does not use NOR flash to boot. The initial bring-up assumes that U-Boot is directly loaded into SDRAM using USB boot tool, and starts from 0x80100000. About USB boot tool ------------------- Jz4740 is one of the XBurst processors with USB boot functionality supported. The CPU can boot from a small ROM in the LSI, initialize CPU and USB module, then wait for USB commands from the USB host. We can send 8 KB binary data to the CPU cache using USB boot tool. USB boot tool is available to the public at Ingenic website. Also there is an alternative Debian package named xburst-tools. Signed-off-by: Xiangfu Liu <xiangfu@openmobilefree.net> Acked-by: Daniel <zpxu@ingenic.cn> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
Xiangfu Liu · Shinya Kuribayashi
1 parent 3a6591a86a
Showing 8 changed files with 460 additions and 1 deletions Side-by-side Diff
MAINTAINERS
MAKEALL
board/qi/qi_lb60/Makefile
board/qi/qi_lb60/config.mk
board/qi/qi_lb60/qi_lb60.c
board/qi/qi_lb60/u-boot.lds
boards.cfg
include/configs/qi_lb60.h
@@ -928,6 +928,10 @@
  
 	vct_xxx		MIPS32 4Kc
  
+Xiangfu Liu <xiangfu@openmobilefree.net>
+
+	qi_lb60		MIPS32 (XBurst Jz4740 SoC)
+
 #########################################################################
 # Nios-II Systems:							#
 #									#
@@ -400,7 +400,9 @@
 ## MIPS Systems		(little endian)
 #########################################################################
  
-LIST_mips4kc_el=""
+LIST_mips4kc_el="	\
+	qi_lb60		\
+"
  
 LIST_mips5kc_el=""
  
+#
+# (C) Copyright 2006
+# Ingenic Semiconductor, <jlwei@ingenic.cn>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
+#
+# (C) Copyright 2006 Qi Hardware, Inc.
+# Author: Xiangfu Liu <xiangfu.z@gmail.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Qi Hardware, Inc. Ben NanoNote (QI_LB60)
+#
+
+ifndef TEXT_BASE
+# ROM version
+# TEXT_BASE = 0x88000000
+
+# RAM version
+TEXT_BASE = 0x80100000
+endif
+/*
+ * Authors: Xiangfu Liu <xiangfu@sharism.cc>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 3 of the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/jz4740.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void gpio_init(void)
+{
+	unsigned int i;
+
+	/* Initialize NAND Flash Pins */
+	__gpio_as_nand();
+
+	/* Initialize SDRAM pins */
+	__gpio_as_sdram_16bit_4720();
+
+	/* Initialize LCD pins */
+	__gpio_as_lcd_18bit();
+
+	/* Initialize MSC pins */
+	__gpio_as_msc();
+
+	/* Initialize Other pins */
+	for (i = 0; i < 7; i++) {
+		__gpio_as_input(GPIO_KEYIN_BASE + i);
+		__gpio_enable_pull(GPIO_KEYIN_BASE + i);
+	}
+
+	for (i = 0; i < 8; i++) {
+		__gpio_as_output(GPIO_KEYOUT_BASE + i);
+		__gpio_clear_pin(GPIO_KEYOUT_BASE + i);
+	}
+
+	__gpio_as_input(GPIO_KEYIN_8);
+	__gpio_enable_pull(GPIO_KEYIN_8);
+
+	/* enable the TP4, TP5 as UART0 */
+	__gpio_jtag_to_uart0();
+
+	__gpio_as_output(GPIO_AUDIO_POP);
+	__gpio_set_pin(GPIO_AUDIO_POP);
+
+	__gpio_as_output(GPIO_LCD_CS);
+	__gpio_clear_pin(GPIO_LCD_CS);
+
+	__gpio_as_output(GPIO_AMP_EN);
+	__gpio_clear_pin(GPIO_AMP_EN);
+
+	__gpio_as_output(GPIO_SDPW_EN);
+	__gpio_disable_pull(GPIO_SDPW_EN);
+	__gpio_clear_pin(GPIO_SDPW_EN);
+
+	__gpio_as_input(GPIO_SD_DETECT);
+	__gpio_disable_pull(GPIO_SD_DETECT);
+
+	__gpio_as_input(GPIO_USB_DETECT);
+	__gpio_enable_pull(GPIO_USB_DETECT);
+}
+
+static void cpm_init(void)
+{
+	struct jz4740_cpm *cpm = (struct jz4740_cpm *)JZ4740_CPM_BASE;
+	uint32_t reg = readw(&cpm->clkgr);
+
+	reg |=	CPM_CLKGR_IPU |
+		CPM_CLKGR_CIM |
+		CPM_CLKGR_I2C |
+		CPM_CLKGR_SSI |
+		CPM_CLKGR_UART1 |
+		CPM_CLKGR_SADC |
+		CPM_CLKGR_UHC |
+		CPM_CLKGR_UDC |
+		CPM_CLKGR_AIC1;
+
+	writew(reg, &cpm->clkgr);
+}
+
+int board_early_init_f(void)
+{
+	gpio_init();
+	cpm_init();
+	calc_clocks();	/* calc the clocks */
+	rtc_init();	/* init rtc on any reset */
+
+	return 0;
+}
+
+/* U-Boot common routines */
+int checkboard(void)
+{
+	printf("Board: Qi LB60 (Ingenic XBurst Jz4740 SoC, Speed %ld MHz)\n",
+	       gd->cpu_clk / 1000000);
+
+	return 0;
+}
+/*
+ * (C) Copyright 2006
+ * Ingenic Semiconductor, <jlwei@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
+
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+	  *(.text*)
+	}
+
+	. = ALIGN(4);
+	.rodata  : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data  : { *(.data*) }
+
+	. = .;
+	_gp = ALIGN(16) + 0x7ff0;
+
+	__got_start = .;
+	.got  : { *(.got) }
+	__got_end = .;
+
+	.sdata  : { *(.sdata*) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	uboot_end_data = .;
+	num_got_entries = (__got_end - __got_start) >> 2;
+
+	. = ALIGN(4);
+	.sbss  : { *(.sbss*) }
+	.bss  : { *(.bss*) . = ALIGN(4); }
+	uboot_end = .;
+}
@@ -302,6 +302,7 @@
 vct_platinumavc_small        mips        mips32      vct                 micronas       -           vct:VCT_PLATINUMAVC,VCT_SMALL_IMAGE
 vct_platinumavc_onenand      mips        mips32      vct                 micronas       -           vct:VCT_PLATINUMAVC,VCT_ONENAND
 vct_platinumavc_onenand_small mips       mips32      vct                 micronas       -           vct:VCT_PLATINUMAVC,VCT_ONENAND,VCT_SMALL_IMAGE
+qi_lb60                      mips        xburst      qi_lb60             qi
 nios2-generic                nios2       nios2       nios2-generic       altera
 PCI5441                      nios2       nios2       pci5441             psyent
 PK1C20                       nios2       nios2       pk1c20              psyent
+/*
+ * Authors: Xiangfu Liu <xiangfu.z@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 3 of the License, or (at your option) any later version.
+ */
+
+#ifndef __CONFIG_QI_LB60_H
+#define __CONFIG_QI_LB60_H
+
+#define CONFIG_MIPS32		/* MIPS32 CPU core */
+#define CONFIG_JZSOC		/* Jz SoC */
+#define CONFIG_JZ4740		/* Jz4740 SoC */
+#define CONFIG_NAND_JZ4740
+
+#define CONFIG_SYS_CPU_SPEED	336000000	/* CPU clock: 336 MHz */
+#define CONFIG_SYS_EXTAL	12000000	/* EXTAL freq: 12 MHz */
+#define CONFIG_SYS_HZ		(CONFIG_SYS_EXTAL / 256) /* incrementer freq */
+#define CONFIG_SYS_MIPS_TIMER_FREQ	CONFIG_SYS_CPU_SPEED
+
+#define CONFIG_SYS_UART_BASE	JZ4740_UART0_BASE /* Base of the UART channel */
+#define CONFIG_BAUDRATE		57600
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_FLASH_BASE	0 /* init flash_base as 0 */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAUL)
+#define CONFIG_BOOTDELAY	0
+#define CONFIG_BOOTARGS		"mem=32M console=tty0 console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
+#define CONFIG_BOOTCOMMAND	"nand read 0x80600000 0x400000 0x200000;bootm"
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_BOOTD	/* bootd			*/
+#define CONFIG_CMD_CONSOLE	/* coninfo			*/
+#define CONFIG_CMD_ECHO		/* echo arguments		*/
+
+#define CONFIG_CMD_LOADB	/* loadb			*/
+#define CONFIG_CMD_LOADS	/* loads			*/
+#define CONFIG_CMD_MEMORY	/* md mm nm mw cp cmp crc base loop mtest */
+#define CONFIG_CMD_MISC		/* Misc functions like sleep etc*/
+#define CONFIG_CMD_RUN		/* run command in env variable	*/
+#define CONFIG_CMD_SAVEENV	/* saveenv			*/
+#define CONFIG_CMD_SETGETDCR	/* DCR support on 4xx		*/
+#define CONFIG_CMD_SOURCE	/* "source" command support	*/
+#define CONFIG_CMD_NAND
+
+/*
+ * Serial download configuration
+ */
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT "NanoNote# "
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+#define CONFIG_SYS_BOOTPARAMS_LEN	(128 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000	/* Cached addr */
+#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
+#define CONFIG_SYS_LOAD_ADDR		0x80600000
+#define CONFIG_SYS_MEMTEST_START	0x80100000
+#define CONFIG_SYS_MEMTEST_END		0x80800000
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_NAND		/* use NAND for environment vars */
+
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+/*
+ * if board nand flash is 1GB, set to 1
+ * if board nand flash is 2GB, set to 2
+ * for change the PAGE_SIZE and BLOCK_SIZE
+ * will delete when there is no 1GB flash
+ */
+#define NANONOTE_NAND_SIZE	2
+
+#define CONFIG_SYS_NAND_PAGE_SIZE	(2048 * NANONOTE_NAND_SIZE)
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(256 * NANONOTE_NAND_SIZE << 10)
+/* nand bad block was marked at this page in a block, start from 0 */
+#define CONFIG_SYS_NAND_BADBLOCK_PAGE	127
+#define CONFIG_SYS_NAND_PAGE_COUNT	128
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
+/* ECC offset position in oob area, default value is 6 if it isn't defined */
+#define CONFIG_SYS_NAND_ECC_POS		(6 * NANONOTE_NAND_SIZE)
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	9
+#define CONFIG_SYS_NAND_ECCSTEPS	\
+	(CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
+#define CONFIG_SYS_NAND_ECCTOTAL	\
+	(CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
+#define CONFIG_SYS_NAND_ECCPOS		\
+		{12, 13, 14, 15, 16, 17, 18, 19,\
+		20, 21, 22, 23, 24, 25, 26, 27, \
+		28, 29, 30, 31, 32, 33, 34, 35, \
+		36, 37, 38, 39, 40, 41, 42, 43, \
+		44, 45, 46, 47, 48, 49, 50, 51, \
+		52, 53, 54, 55, 56, 57, 58, 59, \
+		60, 61, 62, 63, 64, 65, 66, 67, \
+		68, 69, 70, 71, 72, 73, 74, 75, \
+		76, 77, 78, 79, 80, 81, 82, 83}
+
+#define CONFIG_SYS_NAND_OOBSIZE		128
+#define CONFIG_SYS_NAND_BASE		0xB8000000
+#define CONFIG_SYS_ONENAND_BASE		CONFIG_SYS_NAND_BASE
+#define NAND_MAX_CHIPS			1
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_SELECT_DEVICE	1 /* nand driver supports mutipl.*/
+#define CONFIG_NAND_SPL_TEXT_BASE	0x80000000
+
+/*
+ * IPL (Initial Program Loader, integrated inside CPU)
+ * Will load first 8k from NAND (SPL) into cache and execute it from there.
+ *
+ * SPL (Secondary Program Loader)
+ * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
+ * has to fit into 8kByte. It sets up the CPU and configures the SDRAM
+ * controller and the NAND controller so that the special U-Boot image can be
+ * loaded from NAND to SDRAM.
+ *
+ * NUB (NAND U-Boot)
+ * This NAND U-Boot (NUB) is a special U-Boot version which can be started
+ * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
+ *
+ */
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x80100000 /* Load NUB to this addr */
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
+/* Start NUB from this addr*/
+
+/*
+ * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
+ */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) /* Offset to RAM U-Boot image */
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */
+
+#define CONFIG_ENV_SIZE		(4 << 10)
+#define CONFIG_ENV_OFFSET	\
+	(CONFIG_SYS_NAND_BLOCK_SIZE + CONFIG_SYS_NAND_U_BOOT_SIZE)
+#define CONFIG_ENV_OFFSET_REDUND \
+	(CONFIG_ENV_OFFSET  + CONFIG_SYS_NAND_BLOCK_SIZE)
+
+#define CONFIG_SYS_TEXT_BASE	0x80100000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+
+/*
+ * SDRAM Info.
+ */
+#define CONFIG_NR_DRAM_BANKS	1
+
+/*
+ * Cache Configuration
+ */
+#define CONFIG_SYS_DCACHE_SIZE	16384
+#define CONFIG_SYS_ICACHE_SIZE	16384
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
+/*
+ * GPIO definition
+ */
+#define GPIO_LCD_CS	(2 * 32 + 21)
+#define GPIO_AMP_EN	(3 * 32 + 4)
+
+#define GPIO_SDPW_EN	(3 * 32 + 2)
+#define GPIO_SD_DETECT	(3 * 32 + 0)
+
+#define GPIO_BUZZ_PWM	(3 * 32 + 27)
+#define GPIO_USB_DETECT	(3 * 32 + 28)
+
+#define GPIO_AUDIO_POP	(1 * 32 + 29)
+#define GPIO_COB_TEST	(1 * 32 + 30)
+
+#define GPIO_KEYOUT_BASE	(2 * 32 + 10)
+#define GPIO_KEYIN_BASE	(3 * 32 + 18)
+#define GPIO_KEYIN_8	(3 * 32 + 26)
+
+#define GPIO_SD_CD_N	GPIO_SD_DETECT		/* SD Card insert detect */
+#define GPIO_SD_VCC_EN_N	GPIO_SDPW_EN	/* SD Card Power Enable */
+
+#define SPEN	GPIO_LCD_CS	/* LCDCS :Serial command enable      */
+#define SPDA	(2 * 32 + 22)	/* LCDSCL:Serial command clock input */
+#define SPCK	(2 * 32 + 23)	/* LCDSDA:Serial command data input  */
+
+/* SDRAM paramters */
+#define SDRAM_BW16		1	/* Data bus width: 0-32bit, 1-16bit */
+#define SDRAM_BANK4		1	/* Banks each chip: 0-2bank, 1-4bank */
+#define SDRAM_ROW		13	/* Row address: 11 to 13 */
+#define SDRAM_COL		9	/* Column address: 8 to 12 */
+#define SDRAM_CASL		2	/* CAS latency: 2 or 3 */
+
+/* SDRAM Timings, unit: ns */
+#define SDRAM_TRAS		45	/* RAS# Active Time */
+#define SDRAM_RCD		20	/* RAS# to CAS# Delay */
+#define SDRAM_TPC		20	/* RAS# Precharge Time */
+#define SDRAM_TRWL		7	/* Write Latency Time */
+#define SDRAM_TREF		15625	/* Refresh period: 8192 cycles/64ms */
+
+#endif
...	...	@@ -928,6 +928,10 @@
928	928
929	929	vct_xxx MIPS32 4Kc
930	930
	931	+Xiangfu Liu <xiangfu@openmobilefree.net>
	932	+
	933	+ qi_lb60 MIPS32 (XBurst Jz4740 SoC)
	934	+
931	935	#########################################################################
932	936	# Nios-II Systems: #
933	937	# #
...	...	@@ -400,7 +400,9 @@
400	400	## MIPS Systems (little endian)
401	401	#########################################################################
402	402
403		-LIST_mips4kc_el=""
	403	+LIST_mips4kc_el=" \
	404	+ qi_lb60 \
	405	+"
404	406
405	407	LIST_mips5kc_el=""
406	408
	1	+#
	2	+# (C) Copyright 2006
	3	+# Ingenic Semiconductor, <jlwei@ingenic.cn>
	4	+#
	5	+# This program is free software; you can redistribute it and/or
	6	+# modify it under the terms of the GNU General Public License as
	7	+# published by the Free Software Foundation; either version 2 of
	8	+# the License, or (at your option) any later version.
	9	+#
	10	+# This program is distributed in the hope that it will be useful,
	11	+# but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	+# GNU General Public License for more details.
	14	+#
	15	+# You should have received a copy of the GNU General Public License
	16	+# along with this program; if not, write to the Free Software
	17	+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	18	+# MA 02111-1307 USA
	19	+#
	20	+
	21	+include $(TOPDIR)/config.mk
	22	+
	23	+LIB = $(obj)lib$(BOARD).o
	24	+
	25	+COBJS := $(BOARD).o
	26	+
	27	+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
	28	+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
	29	+
	30	+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
	31	+ $(call cmd_link_o_target, $(OBJS))
	32	+
	33	+clean:
	34	+ rm -f $(SOBJS) $(OBJS)
	35	+
	36	+distclean: clean
	37	+ rm -f $(LIB) core *.bak $(obj).depend
	38	+#########################################################################
	39	+
	40	+# defines $(obj).depend target
	41	+include $(SRCTREE)/rules.mk
	42	+
	43	+sinclude $(obj).depend
	44	+
	45	+#########################################################################
	1	+#
	2	+# (C) Copyright 2006 Qi Hardware, Inc.
	3	+# Author: Xiangfu Liu <xiangfu.z@gmail.com>
	4	+#
	5	+# This program is free software; you can redistribute it and/or
	6	+# modify it under the terms of the GNU General Public License as
	7	+# published by the Free Software Foundation; either version 2 of
	8	+# the License, or (at your option) any later version.
	9	+#
	10	+# This program is distributed in the hope that it will be useful,
	11	+# but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	+# GNU General Public License for more details.
	14	+#
	15	+# You should have received a copy of the GNU General Public License
	16	+# along with this program; if not, write to the Free Software
	17	+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	18	+# MA 02111-1307 USA
	19	+#
	20	+
	21	+#
	22	+# Qi Hardware, Inc. Ben NanoNote (QI_LB60)
	23	+#
	24	+
	25	+ifndef TEXT_BASE
	26	+# ROM version
	27	+# TEXT_BASE = 0x88000000
	28	+
	29	+# RAM version
	30	+TEXT_BASE = 0x80100000
	31	+endif
	1	+/*
	2	+ * Authors: Xiangfu Liu <xiangfu@sharism.cc>
	3	+ *
	4	+ * This program is free software; you can redistribute it and/or
	5	+ * modify it under the terms of the GNU General Public License
	6	+ * as published by the Free Software Foundation; either version
	7	+ * 3 of the License, or (at your option) any later version.
	8	+ */
	9	+
	10	+#include <common.h>
	11	+#include <asm/io.h>
	12	+#include <asm/jz4740.h>
	13	+
	14	+DECLARE_GLOBAL_DATA_PTR;
	15	+
	16	+static void gpio_init(void)
	17	+{
	18	+ unsigned int i;
	19	+
	20	+ /* Initialize NAND Flash Pins */
	21	+ __gpio_as_nand();
	22	+
	23	+ /* Initialize SDRAM pins */
	24	+ __gpio_as_sdram_16bit_4720();
	25	+
	26	+ /* Initialize LCD pins */
	27	+ __gpio_as_lcd_18bit();
	28	+
	29	+ /* Initialize MSC pins */
	30	+ __gpio_as_msc();
	31	+
	32	+ /* Initialize Other pins */
	33	+ for (i = 0; i < 7; i++) {
	34	+ __gpio_as_input(GPIO_KEYIN_BASE + i);
	35	+ __gpio_enable_pull(GPIO_KEYIN_BASE + i);
	36	+ }
	37	+
	38	+ for (i = 0; i < 8; i++) {
	39	+ __gpio_as_output(GPIO_KEYOUT_BASE + i);
	40	+ __gpio_clear_pin(GPIO_KEYOUT_BASE + i);
	41	+ }
	42	+
	43	+ __gpio_as_input(GPIO_KEYIN_8);
	44	+ __gpio_enable_pull(GPIO_KEYIN_8);
	45	+
	46	+ /* enable the TP4, TP5 as UART0 */
	47	+ __gpio_jtag_to_uart0();
	48	+
	49	+ __gpio_as_output(GPIO_AUDIO_POP);
	50	+ __gpio_set_pin(GPIO_AUDIO_POP);
	51	+
	52	+ __gpio_as_output(GPIO_LCD_CS);
	53	+ __gpio_clear_pin(GPIO_LCD_CS);
	54	+
	55	+ __gpio_as_output(GPIO_AMP_EN);
	56	+ __gpio_clear_pin(GPIO_AMP_EN);
	57	+
	58	+ __gpio_as_output(GPIO_SDPW_EN);
	59	+ __gpio_disable_pull(GPIO_SDPW_EN);
	60	+ __gpio_clear_pin(GPIO_SDPW_EN);
	61	+
	62	+ __gpio_as_input(GPIO_SD_DETECT);
	63	+ __gpio_disable_pull(GPIO_SD_DETECT);
	64	+
	65	+ __gpio_as_input(GPIO_USB_DETECT);
	66	+ __gpio_enable_pull(GPIO_USB_DETECT);
	67	+}
	68	+
	69	+static void cpm_init(void)
	70	+{
	71	+ struct jz4740_cpm cpm = (struct jz4740_cpm )JZ4740_CPM_BASE;
	72	+ uint32_t reg = readw(&cpm->clkgr);
	73	+
	74	+ reg \|= CPM_CLKGR_IPU \|
	75	+ CPM_CLKGR_CIM \|
	76	+ CPM_CLKGR_I2C \|
	77	+ CPM_CLKGR_SSI \|
	78	+ CPM_CLKGR_UART1 \|
	79	+ CPM_CLKGR_SADC \|
	80	+ CPM_CLKGR_UHC \|
	81	+ CPM_CLKGR_UDC \|
	82	+ CPM_CLKGR_AIC1;
	83	+
	84	+ writew(reg, &cpm->clkgr);
	85	+}
	86	+
	87	+int board_early_init_f(void)
	88	+{
	89	+ gpio_init();
	90	+ cpm_init();
	91	+ calc_clocks(); /* calc the clocks */
	92	+ rtc_init(); /* init rtc on any reset */
	93	+
	94	+ return 0;
	95	+}
	96	+
	97	+/* U-Boot common routines */
	98	+int checkboard(void)
	99	+{
	100	+ printf("Board: Qi LB60 (Ingenic XBurst Jz4740 SoC, Speed %ld MHz)\n",
	101	+ gd->cpu_clk / 1000000);
	102	+
	103	+ return 0;
	104	+}
	1	+/*
	2	+ * (C) Copyright 2006
	3	+ * Ingenic Semiconductor, <jlwei@ingenic.cn>
	4	+ *
	5	+ * This program is free software; you can redistribute it and/or
	6	+ * modify it under the terms of the GNU General Public License as
	7	+ * published by the Free Software Foundation; either version 2 of
	8	+ * the License, or (at your option) any later version.
	9	+ *
	10	+ * This program is distributed in the hope that it will be useful,
	11	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	+ * GNU General Public License for more details.
	14	+ *
	15	+ * You should have received a copy of the GNU General Public License
	16	+ * along with this program; if not, write to the Free Software
	17	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	18	+ * MA 02111-1307 USA
	19	+ */
	20	+
	21	+OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
	22	+
	23	+OUTPUT_ARCH(mips)
	24	+ENTRY(_start)
	25	+SECTIONS
	26	+{
	27	+ . = 0x00000000;
	28	+
	29	+ . = ALIGN(4);
	30	+ .text :
	31	+ {
	32	+ (.text)
	33	+ }
	34	+
	35	+ . = ALIGN(4);
	36	+ .rodata : { (SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata))) }
	37	+
	38	+ . = ALIGN(4);
	39	+ .data : { (.data) }
	40	+
	41	+ . = .;
	42	+ _gp = ALIGN(16) + 0x7ff0;
	43	+
	44	+ __got_start = .;
	45	+ .got : { *(.got) }
	46	+ __got_end = .;
	47	+
	48	+ .sdata : { (.sdata) }
	49	+
	50	+ __u_boot_cmd_start = .;
	51	+ .u_boot_cmd : { *(.u_boot_cmd) }
	52	+ __u_boot_cmd_end = .;
	53	+
	54	+ uboot_end_data = .;
	55	+ num_got_entries = (__got_end - __got_start) >> 2;
	56	+
	57	+ . = ALIGN(4);
	58	+ .sbss : { (.sbss) }
	59	+ .bss : { (.bss) . = ALIGN(4); }
	60	+ uboot_end = .;
	61	+}
...	...	@@ -302,6 +302,7 @@
302	302	vct_platinumavc_small mips mips32 vct micronas - vct:VCT_PLATINUMAVC,VCT_SMALL_IMAGE
303	303	vct_platinumavc_onenand mips mips32 vct micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND
304	304	vct_platinumavc_onenand_small mips mips32 vct micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND,VCT_SMALL_IMAGE
	305	+qi_lb60 mips xburst qi_lb60 qi
305	306	nios2-generic nios2 nios2 nios2-generic altera
306	307	PCI5441 nios2 nios2 pci5441 psyent
307	308	PK1C20 nios2 nios2 pk1c20 psyent
	1	+/*
	2	+ * Authors: Xiangfu Liu <xiangfu.z@gmail.com>
	3	+ *
	4	+ * This program is free software; you can redistribute it and/or
	5	+ * modify it under the terms of the GNU General Public License
	6	+ * as published by the Free Software Foundation; either version
	7	+ * 3 of the License, or (at your option) any later version.
	8	+ */
	9	+
	10	+#ifndef __CONFIG_QI_LB60_H
	11	+#define __CONFIG_QI_LB60_H
	12	+
	13	+#define CONFIG_MIPS32 /* MIPS32 CPU core */
	14	+#define CONFIG_JZSOC /* Jz SoC */
	15	+#define CONFIG_JZ4740 /* Jz4740 SoC */
	16	+#define CONFIG_NAND_JZ4740
	17	+
	18	+#define CONFIG_SYS_CPU_SPEED 336000000 /* CPU clock: 336 MHz */
	19	+#define CONFIG_SYS_EXTAL 12000000 /* EXTAL freq: 12 MHz */
	20	+#define CONFIG_SYS_HZ (CONFIG_SYS_EXTAL / 256) /* incrementer freq */
	21	+#define CONFIG_SYS_MIPS_TIMER_FREQ CONFIG_SYS_CPU_SPEED
	22	+
	23	+#define CONFIG_SYS_UART_BASE JZ4740_UART0_BASE /* Base of the UART channel */
	24	+#define CONFIG_BAUDRATE 57600
	25	+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	26	+
	27	+#define CONFIG_SKIP_LOWLEVEL_INIT
	28	+#define CONFIG_BOARD_EARLY_INIT_F
	29	+#define CONFIG_SYS_NO_FLASH
	30	+#define CONFIG_SYS_FLASH_BASE 0 /* init flash_base as 0 */
	31	+#define CONFIG_ENV_OVERWRITE
	32	+
	33	+#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAUL)
	34	+#define CONFIG_BOOTDELAY 0
	35	+#define CONFIG_BOOTARGS "mem=32M console=tty0 console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
	36	+#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm"
	37	+
	38	+/*
	39	+ * Command line configuration.
	40	+ */
	41	+#define CONFIG_CMD_BOOTD /* bootd */
	42	+#define CONFIG_CMD_CONSOLE /* coninfo */
	43	+#define CONFIG_CMD_ECHO /* echo arguments */
	44	+
	45	+#define CONFIG_CMD_LOADB /* loadb */
	46	+#define CONFIG_CMD_LOADS /* loads */
	47	+#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
	48	+#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/
	49	+#define CONFIG_CMD_RUN /* run command in env variable */
	50	+#define CONFIG_CMD_SAVEENV /* saveenv */
	51	+#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
	52	+#define CONFIG_CMD_SOURCE /* "source" command support */
	53	+#define CONFIG_CMD_NAND
	54	+
	55	+/*
	56	+ * Serial download configuration
	57	+ */
	58	+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	59	+
	60	+/*
	61	+ * Miscellaneous configurable options
	62	+ */
	63	+#define CONFIG_SYS_MAXARGS 16
	64	+#define CONFIG_SYS_LONGHELP
	65	+#define CONFIG_SYS_PROMPT "NanoNote# "
	66	+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	67	+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	68	+
	69	+#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
	70	+#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
	71	+
	72	+#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
	73	+#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
	74	+#define CONFIG_SYS_LOAD_ADDR 0x80600000
	75	+#define CONFIG_SYS_MEMTEST_START 0x80100000
	76	+#define CONFIG_SYS_MEMTEST_END 0x80800000
	77	+
	78	+/*
	79	+ * Environment
	80	+ */
	81	+#define CONFIG_ENV_IS_IN_NAND /* use NAND for environment vars */
	82	+
	83	+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	84	+/*
	85	+ * if board nand flash is 1GB, set to 1
	86	+ * if board nand flash is 2GB, set to 2
	87	+ * for change the PAGE_SIZE and BLOCK_SIZE
	88	+ * will delete when there is no 1GB flash
	89	+ */
	90	+#define NANONOTE_NAND_SIZE 2
	91	+
	92	+#define CONFIG_SYS_NAND_PAGE_SIZE (2048 * NANONOTE_NAND_SIZE)
	93	+#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * NANONOTE_NAND_SIZE << 10)
	94	+/* nand bad block was marked at this page in a block, start from 0 */
	95	+#define CONFIG_SYS_NAND_BADBLOCK_PAGE 127
	96	+#define CONFIG_SYS_NAND_PAGE_COUNT 128
	97	+#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
	98	+/* ECC offset position in oob area, default value is 6 if it isn't defined */
	99	+#define CONFIG_SYS_NAND_ECC_POS (6 * NANONOTE_NAND_SIZE)
	100	+#define CONFIG_SYS_NAND_ECCSIZE 512
	101	+#define CONFIG_SYS_NAND_ECCBYTES 9
	102	+#define CONFIG_SYS_NAND_ECCSTEPS \
	103	+ (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
	104	+#define CONFIG_SYS_NAND_ECCTOTAL \
	105	+ (CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
	106	+#define CONFIG_SYS_NAND_ECCPOS \
	107	+ {12, 13, 14, 15, 16, 17, 18, 19,\
	108	+ 20, 21, 22, 23, 24, 25, 26, 27, \
	109	+ 28, 29, 30, 31, 32, 33, 34, 35, \
	110	+ 36, 37, 38, 39, 40, 41, 42, 43, \
	111	+ 44, 45, 46, 47, 48, 49, 50, 51, \
	112	+ 52, 53, 54, 55, 56, 57, 58, 59, \
	113	+ 60, 61, 62, 63, 64, 65, 66, 67, \
	114	+ 68, 69, 70, 71, 72, 73, 74, 75, \
	115	+ 76, 77, 78, 79, 80, 81, 82, 83}
	116	+
	117	+#define CONFIG_SYS_NAND_OOBSIZE 128
	118	+#define CONFIG_SYS_NAND_BASE 0xB8000000
	119	+#define CONFIG_SYS_ONENAND_BASE CONFIG_SYS_NAND_BASE
	120	+#define NAND_MAX_CHIPS 1
	121	+#define CONFIG_SYS_MAX_NAND_DEVICE 1
	122	+#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl.*/
	123	+#define CONFIG_NAND_SPL_TEXT_BASE 0x80000000
	124	+
	125	+/*
	126	+ * IPL (Initial Program Loader, integrated inside CPU)
	127	+ * Will load first 8k from NAND (SPL) into cache and execute it from there.
	128	+ *
	129	+ * SPL (Secondary Program Loader)
	130	+ * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
	131	+ * has to fit into 8kByte. It sets up the CPU and configures the SDRAM
	132	+ * controller and the NAND controller so that the special U-Boot image can be
	133	+ * loaded from NAND to SDRAM.
	134	+ *
	135	+ * NUB (NAND U-Boot)
	136	+ * This NAND U-Boot (NUB) is a special U-Boot version which can be started
	137	+ * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
	138	+ *
	139	+ */
	140	+#define CONFIG_SYS_NAND_U_BOOT_DST 0x80100000 /* Load NUB to this addr */
	141	+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
	142	+/* Start NUB from this addr*/
	143	+
	144	+/*
	145	+ * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
	146	+ */
	147	+#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) /* Offset to RAM U-Boot image */
	148	+#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */
	149	+
	150	+#define CONFIG_ENV_SIZE (4 << 10)
	151	+#define CONFIG_ENV_OFFSET \
	152	+ (CONFIG_SYS_NAND_BLOCK_SIZE + CONFIG_SYS_NAND_U_BOOT_SIZE)
	153	+#define CONFIG_ENV_OFFSET_REDUND \
	154	+ (CONFIG_ENV_OFFSET + CONFIG_SYS_NAND_BLOCK_SIZE)
	155	+
	156	+#define CONFIG_SYS_TEXT_BASE 0x80100000
	157	+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
	158	+
	159	+/*
	160	+ * SDRAM Info.
	161	+ */
	162	+#define CONFIG_NR_DRAM_BANKS 1
	163	+
	164	+/*
	165	+ * Cache Configuration
	166	+ */
	167	+#define CONFIG_SYS_DCACHE_SIZE 16384
	168	+#define CONFIG_SYS_ICACHE_SIZE 16384
	169	+#define CONFIG_SYS_CACHELINE_SIZE 32
	170	+
	171	+/*
	172	+ * GPIO definition
	173	+ */
	174	+#define GPIO_LCD_CS (2 * 32 + 21)
	175	+#define GPIO_AMP_EN (3 * 32 + 4)
	176	+
	177	+#define GPIO_SDPW_EN (3 * 32 + 2)
	178	+#define GPIO_SD_DETECT (3 * 32 + 0)
	179	+
	180	+#define GPIO_BUZZ_PWM (3 * 32 + 27)
	181	+#define GPIO_USB_DETECT (3 * 32 + 28)
	182	+
	183	+#define GPIO_AUDIO_POP (1 * 32 + 29)
	184	+#define GPIO_COB_TEST (1 * 32 + 30)
	185	+
	186	+#define GPIO_KEYOUT_BASE (2 * 32 + 10)
	187	+#define GPIO_KEYIN_BASE (3 * 32 + 18)
	188	+#define GPIO_KEYIN_8 (3 * 32 + 26)
	189	+
	190	+#define GPIO_SD_CD_N GPIO_SD_DETECT /* SD Card insert detect */
	191	+#define GPIO_SD_VCC_EN_N GPIO_SDPW_EN /* SD Card Power Enable */
	192	+
	193	+#define SPEN GPIO_LCD_CS /* LCDCS :Serial command enable */
	194	+#define SPDA (2 * 32 + 22) /* LCDSCL:Serial command clock input */
	195	+#define SPCK (2 * 32 + 23) /* LCDSDA:Serial command data input */
	196	+
	197	+/* SDRAM paramters */
	198	+#define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */
	199	+#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */
	200	+#define SDRAM_ROW 13 /* Row address: 11 to 13 */
	201	+#define SDRAM_COL 9 /* Column address: 8 to 12 */
	202	+#define SDRAM_CASL 2 /* CAS latency: 2 or 3 */
	203	+
	204	+/* SDRAM Timings, unit: ns */
	205	+#define SDRAM_TRAS 45 /* RAS# Active Time */
	206	+#define SDRAM_RCD 20 /* RAS# to CAS# Delay */
	207	+#define SDRAM_TPC 20 /* RAS# Precharge Time */
	208	+#define SDRAM_TRWL 7 /* Write Latency Time */
	209	+#define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */
	210	+
	211	+#endif