Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit 3cbc7b878ba6352bb0ae21213394844f3a9b3e9d

Authored by Dinh Nguyen
Committed by Marek Vasut
1 parent e1df080b0d
Exists in v2017.01-smarct4x and in 30 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

arm: socfpga: rename socfpga_cyclone5 and socfpga_arria5 config files 

Rename the socfpga_cyclone5.h to socfpga_cyclone5_socdk.h, and
socfpga_arria.h to socfpga_arria5_socdk.h. This matches the other SoCFPGA
board config files.

Suggested-by: Marek Vasut <marex@denx.de>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>

Showing 5 changed files with 196 additions and 196 deletions Side-by-side Diff

arch/arm/mach-socfpga/Kconfig
Diff comments   View file @ 3cbc7b8
... ... @@ -50,8 +50,8 @@
50 50 default "socfpga"
51 51  
52 52 config SYS_CONFIG_NAME
53   - default "socfpga_arria5" if TARGET_SOCFPGA_ARRIA5_SOCDK
54   - default "socfpga_cyclone5" if TARGET_SOCFPGA_CYCLONE5_SOCDK
  53 + default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
  54 + default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
55 55 default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
56 56 default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
57 57 default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
include/configs/socfpga_arria5.h
View file @ 3cbc7b8
1   -/*
2   - * Copyright (C) 2014 Marek Vasut <marex@denx.de>
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - */
6   -#ifndef __CONFIG_SOCFPGA_ARRIA5_H__
7   -#define __CONFIG_SOCFPGA_ARRIA5_H__
8   -
9   -#include <asm/arch/socfpga_base_addrs.h>
10   -
11   -/* U-Boot Commands */
12   -#define CONFIG_SYS_NO_FLASH
13   -#define CONFIG_DOS_PARTITION
14   -#define CONFIG_FAT_WRITE
15   -#define CONFIG_HW_WATCHDOG
16   -
17   -#define CONFIG_CMD_ASKENV
18   -#define CONFIG_CMD_BOOTZ
19   -#define CONFIG_CMD_CACHE
20   -#define CONFIG_CMD_DFU
21   -#define CONFIG_CMD_DHCP
22   -#define CONFIG_CMD_EXT4
23   -#define CONFIG_CMD_EXT4_WRITE
24   -#define CONFIG_CMD_FAT
25   -#define CONFIG_CMD_FS_GENERIC
26   -#define CONFIG_CMD_GPIO
27   -#define CONFIG_CMD_GREPENV
28   -#define CONFIG_CMD_MII
29   -#define CONFIG_CMD_MMC
30   -#define CONFIG_CMD_PING
31   -#define CONFIG_CMD_USB
32   -#define CONFIG_CMD_USB_MASS_STORAGE
33   -
34   -/* Memory configurations */
35   -#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
36   -
37   -/* Booting Linux */
38   -#define CONFIG_BOOTDELAY 3
39   -#define CONFIG_BOOTFILE "zImage"
40   -#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
41   -#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
42   -#define CONFIG_BOOTCOMMAND "run ramboot"
43   -#else
44   -#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
45   -#endif
46   -#define CONFIG_LOADADDR 0x01000000
47   -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
48   -
49   -/* Ethernet on SoC (EMAC) */
50   -#if defined(CONFIG_CMD_NET)
51   -
52   -/* PHY */
53   -#define CONFIG_PHY_MICREL
54   -#define CONFIG_PHY_MICREL_KSZ9021
55   -#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew"
56   -#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0
57   -#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew"
58   -#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0
59   -
60   -#endif
61   -
62   -/* USB */
63   -#ifdef CONFIG_CMD_USB
64   -#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
65   -#endif
66   -#define CONFIG_G_DNL_MANUFACTURER "Altera"
67   -
68   -/* Extra Environment */
69   -#define CONFIG_HOSTNAME socfpga_arria5
70   -
71   -#define CONFIG_EXTRA_ENV_SETTINGS \
72   - "verify=n\0" \
73   - "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
74   - "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
75   - "bootm ${loadaddr} - ${fdt_addr}\0" \
76   - "bootimage=zImage\0" \
77   - "fdt_addr=100\0" \
78   - "fdtimage=socfpga.dtb\0" \
79   - "fsloadcmd=ext2load\0" \
80   - "bootm ${loadaddr} - ${fdt_addr}\0" \
81   - "mmcroot=/dev/mmcblk0p2\0" \
82   - "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
83   - " root=${mmcroot} rw rootwait;" \
84   - "bootz ${loadaddr} - ${fdt_addr}\0" \
85   - "mmcload=mmc rescan;" \
86   - "load mmc 0:1 ${loadaddr} ${bootimage};" \
87   - "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
88   - "qspiroot=/dev/mtdblock0\0" \
89   - "qspirootfstype=jffs2\0" \
90   - "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
91   - " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
92   - "bootm ${loadaddr} - ${fdt_addr}\0"
93   -
94   -/* The rest of the configuration is shared */
95   -#include <configs/socfpga_common.h>
96   -
97   -#endif /* __CONFIG_SOCFPGA_ARRIA5_H__ */
include/configs/socfpga_arria5_socdk.h
Diff comments   View file @ 3cbc7b8
  1 +/*
  2 + * Copyright (C) 2014 Marek Vasut <marex@denx.de>
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +#ifndef __CONFIG_SOCFPGA_ARRIA5_H__
  7 +#define __CONFIG_SOCFPGA_ARRIA5_H__
  8 +
  9 +#include <asm/arch/socfpga_base_addrs.h>
  10 +
  11 +/* U-Boot Commands */
  12 +#define CONFIG_SYS_NO_FLASH
  13 +#define CONFIG_DOS_PARTITION
  14 +#define CONFIG_FAT_WRITE
  15 +#define CONFIG_HW_WATCHDOG
  16 +
  17 +#define CONFIG_CMD_ASKENV
  18 +#define CONFIG_CMD_BOOTZ
  19 +#define CONFIG_CMD_CACHE
  20 +#define CONFIG_CMD_DFU
  21 +#define CONFIG_CMD_DHCP
  22 +#define CONFIG_CMD_EXT4
  23 +#define CONFIG_CMD_EXT4_WRITE
  24 +#define CONFIG_CMD_FAT
  25 +#define CONFIG_CMD_FS_GENERIC
  26 +#define CONFIG_CMD_GPIO
  27 +#define CONFIG_CMD_GREPENV
  28 +#define CONFIG_CMD_MII
  29 +#define CONFIG_CMD_MMC
  30 +#define CONFIG_CMD_PING
  31 +#define CONFIG_CMD_USB
  32 +#define CONFIG_CMD_USB_MASS_STORAGE
  33 +
  34 +/* Memory configurations */
  35 +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
  36 +
  37 +/* Booting Linux */
  38 +#define CONFIG_BOOTDELAY 3
  39 +#define CONFIG_BOOTFILE "zImage"
  40 +#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
  41 +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
  42 +#define CONFIG_BOOTCOMMAND "run ramboot"
  43 +#else
  44 +#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
  45 +#endif
  46 +#define CONFIG_LOADADDR 0x01000000
  47 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
  48 +
  49 +/* Ethernet on SoC (EMAC) */
  50 +#if defined(CONFIG_CMD_NET)
  51 +
  52 +/* PHY */
  53 +#define CONFIG_PHY_MICREL
  54 +#define CONFIG_PHY_MICREL_KSZ9021
  55 +#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew"
  56 +#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0
  57 +#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew"
  58 +#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0
  59 +
  60 +#endif
  61 +
  62 +/* USB */
  63 +#ifdef CONFIG_CMD_USB
  64 +#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
  65 +#endif
  66 +#define CONFIG_G_DNL_MANUFACTURER "Altera"
  67 +
  68 +/* Extra Environment */
  69 +#define CONFIG_HOSTNAME socfpga_arria5
  70 +
  71 +#define CONFIG_EXTRA_ENV_SETTINGS \
  72 + "verify=n\0" \
  73 + "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  74 + "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
  75 + "bootm ${loadaddr} - ${fdt_addr}\0" \
  76 + "bootimage=zImage\0" \
  77 + "fdt_addr=100\0" \
  78 + "fdtimage=socfpga.dtb\0" \
  79 + "fsloadcmd=ext2load\0" \
  80 + "bootm ${loadaddr} - ${fdt_addr}\0" \
  81 + "mmcroot=/dev/mmcblk0p2\0" \
  82 + "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
  83 + " root=${mmcroot} rw rootwait;" \
  84 + "bootz ${loadaddr} - ${fdt_addr}\0" \
  85 + "mmcload=mmc rescan;" \
  86 + "load mmc 0:1 ${loadaddr} ${bootimage};" \
  87 + "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
  88 + "qspiroot=/dev/mtdblock0\0" \
  89 + "qspirootfstype=jffs2\0" \
  90 + "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
  91 + " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
  92 + "bootm ${loadaddr} - ${fdt_addr}\0"
  93 +
  94 +/* The rest of the configuration is shared */
  95 +#include <configs/socfpga_common.h>
  96 +
  97 +#endif /* __CONFIG_SOCFPGA_ARRIA5_H__ */
include/configs/socfpga_cyclone5.h
View file @ 3cbc7b8
1   -/*
2   - * Copyright (C) 2014 Marek Vasut <marex@denx.de>
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - */
6   -#ifndef __CONFIG_SOCFPGA_CYCLONE5_H__
7   -#define __CONFIG_SOCFPGA_CYCLONE5_H__
8   -
9   -#include <asm/arch/socfpga_base_addrs.h>
10   -
11   -/* U-Boot Commands */
12   -#define CONFIG_SYS_NO_FLASH
13   -#define CONFIG_DOS_PARTITION
14   -#define CONFIG_FAT_WRITE
15   -#define CONFIG_HW_WATCHDOG
16   -
17   -#define CONFIG_CMD_ASKENV
18   -#define CONFIG_CMD_BOOTZ
19   -#define CONFIG_CMD_CACHE
20   -#define CONFIG_CMD_DFU
21   -#define CONFIG_CMD_DHCP
22   -#define CONFIG_CMD_EXT4
23   -#define CONFIG_CMD_EXT4_WRITE
24   -#define CONFIG_CMD_FAT
25   -#define CONFIG_CMD_FS_GENERIC
26   -#define CONFIG_CMD_GPIO
27   -#define CONFIG_CMD_GREPENV
28   -#define CONFIG_CMD_MII
29   -#define CONFIG_CMD_MMC
30   -#define CONFIG_CMD_PING
31   -#define CONFIG_CMD_USB
32   -#define CONFIG_CMD_USB_MASS_STORAGE
33   -
34   -/* Memory configurations */
35   -#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
36   -
37   -/* Booting Linux */
38   -#define CONFIG_BOOTDELAY 3
39   -#define CONFIG_BOOTFILE "zImage"
40   -#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
41   -#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
42   -#define CONFIG_BOOTCOMMAND "run ramboot"
43   -#else
44   -#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
45   -#endif
46   -#define CONFIG_LOADADDR 0x01000000
47   -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
48   -
49   -/* Ethernet on SoC (EMAC) */
50   -#if defined(CONFIG_CMD_NET)
51   -
52   -/* PHY */
53   -#define CONFIG_PHY_MICREL
54   -#define CONFIG_PHY_MICREL_KSZ9021
55   -#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew"
56   -#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0
57   -#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew"
58   -#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0
59   -
60   -#endif
61   -
62   -/* USB */
63   -#ifdef CONFIG_CMD_USB
64   -#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
65   -#endif
66   -#define CONFIG_G_DNL_MANUFACTURER "Altera"
67   -
68   -/* Extra Environment */
69   -#define CONFIG_HOSTNAME socfpga_cyclone5
70   -
71   -#define CONFIG_EXTRA_ENV_SETTINGS \
72   - "verify=n\0" \
73   - "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
74   - "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
75   - "bootm ${loadaddr} - ${fdt_addr}\0" \
76   - "bootimage=zImage\0" \
77   - "fdt_addr=100\0" \
78   - "fdtimage=socfpga.dtb\0" \
79   - "fsloadcmd=ext2load\0" \
80   - "bootm ${loadaddr} - ${fdt_addr}\0" \
81   - "mmcroot=/dev/mmcblk0p2\0" \
82   - "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
83   - " root=${mmcroot} rw rootwait;" \
84   - "bootz ${loadaddr} - ${fdt_addr}\0" \
85   - "mmcload=mmc rescan;" \
86   - "load mmc 0:1 ${loadaddr} ${bootimage};" \
87   - "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
88   - "qspiroot=/dev/mtdblock0\0" \
89   - "qspirootfstype=jffs2\0" \
90   - "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
91   - " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
92   - "bootm ${loadaddr} - ${fdt_addr}\0"
93   -
94   -/* The rest of the configuration is shared */
95   -#include <configs/socfpga_common.h>
96   -
97   -#endif /* __CONFIG_SOCFPGA_CYCLONE5_H__ */
include/configs/socfpga_cyclone5_socdk.h
Diff comments   View file @ 3cbc7b8
  1 +/*
  2 + * Copyright (C) 2014 Marek Vasut <marex@denx.de>
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +#ifndef __CONFIG_SOCFPGA_CYCLONE5_H__
  7 +#define __CONFIG_SOCFPGA_CYCLONE5_H__
  8 +
  9 +#include <asm/arch/socfpga_base_addrs.h>
  10 +
  11 +/* U-Boot Commands */
  12 +#define CONFIG_SYS_NO_FLASH
  13 +#define CONFIG_DOS_PARTITION
  14 +#define CONFIG_FAT_WRITE
  15 +#define CONFIG_HW_WATCHDOG
  16 +
  17 +#define CONFIG_CMD_ASKENV
  18 +#define CONFIG_CMD_BOOTZ
  19 +#define CONFIG_CMD_CACHE
  20 +#define CONFIG_CMD_DFU
  21 +#define CONFIG_CMD_DHCP
  22 +#define CONFIG_CMD_EXT4
  23 +#define CONFIG_CMD_EXT4_WRITE
  24 +#define CONFIG_CMD_FAT
  25 +#define CONFIG_CMD_FS_GENERIC
  26 +#define CONFIG_CMD_GPIO
  27 +#define CONFIG_CMD_GREPENV
  28 +#define CONFIG_CMD_MII
  29 +#define CONFIG_CMD_MMC
  30 +#define CONFIG_CMD_PING
  31 +#define CONFIG_CMD_USB
  32 +#define CONFIG_CMD_USB_MASS_STORAGE
  33 +
  34 +/* Memory configurations */
  35 +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
  36 +
  37 +/* Booting Linux */
  38 +#define CONFIG_BOOTDELAY 3
  39 +#define CONFIG_BOOTFILE "zImage"
  40 +#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
  41 +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
  42 +#define CONFIG_BOOTCOMMAND "run ramboot"
  43 +#else
  44 +#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
  45 +#endif
  46 +#define CONFIG_LOADADDR 0x01000000
  47 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
  48 +
  49 +/* Ethernet on SoC (EMAC) */
  50 +#if defined(CONFIG_CMD_NET)
  51 +
  52 +/* PHY */
  53 +#define CONFIG_PHY_MICREL
  54 +#define CONFIG_PHY_MICREL_KSZ9021
  55 +#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew"
  56 +#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0
  57 +#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew"
  58 +#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0
  59 +
  60 +#endif
  61 +
  62 +/* USB */
  63 +#ifdef CONFIG_CMD_USB
  64 +#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
  65 +#endif
  66 +#define CONFIG_G_DNL_MANUFACTURER "Altera"
  67 +
  68 +/* Extra Environment */
  69 +#define CONFIG_HOSTNAME socfpga_cyclone5
  70 +
  71 +#define CONFIG_EXTRA_ENV_SETTINGS \
  72 + "verify=n\0" \
  73 + "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  74 + "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
  75 + "bootm ${loadaddr} - ${fdt_addr}\0" \
  76 + "bootimage=zImage\0" \
  77 + "fdt_addr=100\0" \
  78 + "fdtimage=socfpga.dtb\0" \
  79 + "fsloadcmd=ext2load\0" \
  80 + "bootm ${loadaddr} - ${fdt_addr}\0" \
  81 + "mmcroot=/dev/mmcblk0p2\0" \
  82 + "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
  83 + " root=${mmcroot} rw rootwait;" \
  84 + "bootz ${loadaddr} - ${fdt_addr}\0" \
  85 + "mmcload=mmc rescan;" \
  86 + "load mmc 0:1 ${loadaddr} ${bootimage};" \
  87 + "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
  88 + "qspiroot=/dev/mtdblock0\0" \
  89 + "qspirootfstype=jffs2\0" \
  90 + "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
  91 + " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
  92 + "bootm ${loadaddr} - ${fdt_addr}\0"
  93 +
  94 +/* The rest of the configuration is shared */
  95 +#include <configs/socfpga_common.h>
  96 +
  97 +#endif /* __CONFIG_SOCFPGA_CYCLONE5_H__ */