Commit 3cbeb0f004db555c58e81de24e23ff0b84d46ddc
Committed by
Stefano Babic
1 parent
053b795e30
Exists in
v2017.01-smarct4x
and in
40 other branches
RiOTboard and MarSBoard: add new boards support
RiOTboard is produced by Embest/Element 14 and is based on i.MX6 Solo The following features are tested : - UART2 (console) - eMMC - SDCard - uSDCard - Ethernet - USB Host (through 4 ports hub) - HDMI output - I2C 1/2/3 - LVDS TFT with LCD8000-97C from Embest/Element 14 Boot on eMMC and through USB loader are tested. For more informations on this board : http://www.riotboard.org/ MarSBoard is produced by Embest/Element 14 and is based on i.MX6 Dual The following features are tested : - UART2 (console) - eMMC - uSDCard - Ethernet - USB Host (through 2 ports hub) - HDMI output - I2C 1/2 - SPI NOR Flash - LVDS TFT with LCD8000-97C from Embest/Element 14 Boot on SPI NOR and through USB loader are tested. For more informations on this board : http://www.embest-tech.com/shop/star/marsboard.html Both boards are supported by the same code base as they are based on a common trunk of schematics. Signed-off-by: Eric Bénard <eric@eukrea.com> Acked-by: Stefano Babic <sbabic@denx.de>
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board/embest/mx6boards/Makefile
board/embest/mx6boards/mx6boards.c
1 | +/* | |
2 | + * Copyright (C) 2014 Eukréa Electromatique | |
3 | + * Author: Eric Bénard <eric@eukrea.com> | |
4 | + * Fabio Estevam <fabio.estevam@freescale.com> | |
5 | + * Jon Nettleton <jon.nettleton@gmail.com> | |
6 | + * | |
7 | + * based on sabresd.c which is : | |
8 | + * Copyright (C) 2012 Freescale Semiconductor, Inc. | |
9 | + * and on hummingboard.c which is : | |
10 | + * Copyright (C) 2013 SolidRun ltd. | |
11 | + * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>. | |
12 | + * | |
13 | + * SPDX-License-Identifier: GPL-2.0+ | |
14 | + */ | |
15 | + | |
16 | +#include <asm/arch/clock.h> | |
17 | +#include <asm/arch/sys_proto.h> | |
18 | +#include <asm/arch/imx-regs.h> | |
19 | +#include <asm/arch/iomux.h> | |
20 | +#include <asm/arch/mx6-pins.h> | |
21 | +#include <asm/errno.h> | |
22 | +#include <asm/gpio.h> | |
23 | +#include <asm/imx-common/iomux-v3.h> | |
24 | +#include <asm/imx-common/boot_mode.h> | |
25 | +#include <asm/imx-common/mxc_i2c.h> | |
26 | +#include <asm/imx-common/video.h> | |
27 | +#include <i2c.h> | |
28 | +#include <mmc.h> | |
29 | +#include <fsl_esdhc.h> | |
30 | +#include <miiphy.h> | |
31 | +#include <netdev.h> | |
32 | +#include <asm/arch/mxc_hdmi.h> | |
33 | +#include <asm/arch/crm_regs.h> | |
34 | +#include <linux/fb.h> | |
35 | +#include <ipu_pixfmt.h> | |
36 | +#include <asm/io.h> | |
37 | +#include <asm/arch/sys_proto.h> | |
38 | +DECLARE_GLOBAL_DATA_PTR; | |
39 | + | |
40 | +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ | |
41 | + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ | |
42 | + PAD_CTL_SRE_FAST | PAD_CTL_HYS) | |
43 | + | |
44 | +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ | |
45 | + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ | |
46 | + PAD_CTL_SRE_FAST | PAD_CTL_HYS) | |
47 | + | |
48 | +#define USDHC_PAD_CLK_CTRL (PAD_CTL_SPEED_LOW | \ | |
49 | + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \ | |
50 | + PAD_CTL_HYS) | |
51 | + | |
52 | +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ | |
53 | + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) | |
54 | + | |
55 | +#define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \ | |
56 | + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) | |
57 | + | |
58 | +#define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \ | |
59 | + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) | |
60 | + | |
61 | +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ | |
62 | + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ | |
63 | + PAD_CTL_ODE | PAD_CTL_SRE_FAST) | |
64 | + | |
65 | +#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ | |
66 | + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) | |
67 | + | |
68 | +static int board_type = -1; | |
69 | +#define BOARD_IS_MARSBOARD 0 | |
70 | +#define BOARD_IS_RIOTBOARD 1 | |
71 | + | |
72 | +int dram_init(void) | |
73 | +{ | |
74 | + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); | |
75 | + | |
76 | + return 0; | |
77 | +} | |
78 | + | |
79 | +static iomux_v3_cfg_t const uart2_pads[] = { | |
80 | + MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | |
81 | + MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | |
82 | +}; | |
83 | + | |
84 | +static void setup_iomux_uart(void) | |
85 | +{ | |
86 | + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); | |
87 | +} | |
88 | + | |
89 | +iomux_v3_cfg_t const enet_pads[] = { | |
90 | + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
91 | + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
92 | + /* GPIO16 -> AR8035 25MHz */ | |
93 | + MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL), | |
94 | + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL), | |
95 | + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
96 | + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
97 | + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
98 | + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
99 | + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
100 | + /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ | |
101 | + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK), | |
102 | + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
103 | + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), | |
104 | + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), | |
105 | + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
106 | + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
107 | + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), | |
108 | + /* AR8035 PHY Reset */ | |
109 | + MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), | |
110 | + /* AR8035 PHY Interrupt */ | |
111 | + MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
112 | +}; | |
113 | + | |
114 | +static void setup_iomux_enet(void) | |
115 | +{ | |
116 | + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); | |
117 | + | |
118 | + /* Reset AR8035 PHY */ | |
119 | + gpio_direction_output(IMX_GPIO_NR(3, 31) , 0); | |
120 | + mdelay(2); | |
121 | + gpio_set_value(IMX_GPIO_NR(3, 31), 1); | |
122 | +} | |
123 | + | |
124 | +int mx6_rgmii_rework(struct phy_device *phydev) | |
125 | +{ | |
126 | + /* from linux/arch/arm/mach-imx/mach-imx6q.c : | |
127 | + * Ar803x phy SmartEEE feature cause link status generates glitch, | |
128 | + * which cause ethernet link down/up issue, so disable SmartEEE | |
129 | + */ | |
130 | + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); | |
131 | + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d); | |
132 | + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003); | |
133 | + | |
134 | + return 0; | |
135 | +} | |
136 | + | |
137 | +int board_phy_config(struct phy_device *phydev) | |
138 | +{ | |
139 | + mx6_rgmii_rework(phydev); | |
140 | + | |
141 | + if (phydev->drv->config) | |
142 | + phydev->drv->config(phydev); | |
143 | + | |
144 | + return 0; | |
145 | +} | |
146 | + | |
147 | +iomux_v3_cfg_t const usdhc2_pads[] = { | |
148 | + MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL), | |
149 | + MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
150 | + MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
151 | + MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
152 | + MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
153 | + MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
154 | + MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */ | |
155 | + MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ | |
156 | +}; | |
157 | + | |
158 | +iomux_v3_cfg_t const usdhc3_pads[] = { | |
159 | + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL), | |
160 | + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
161 | + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
162 | + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
163 | + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
164 | + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
165 | +}; | |
166 | + | |
167 | +iomux_v3_cfg_t const riotboard_usdhc3_pads[] = { | |
168 | + MX6_PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */ | |
169 | + MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ | |
170 | +}; | |
171 | + | |
172 | +iomux_v3_cfg_t const usdhc4_pads[] = { | |
173 | + MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL), | |
174 | + MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
175 | + MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
176 | + MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
177 | + MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
178 | + MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
179 | + /* eMMC RST */ | |
180 | + MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
181 | +}; | |
182 | + | |
183 | +#ifdef CONFIG_FSL_ESDHC | |
184 | +struct fsl_esdhc_cfg usdhc_cfg[3] = { | |
185 | + {USDHC2_BASE_ADDR}, | |
186 | + {USDHC3_BASE_ADDR}, | |
187 | + {USDHC4_BASE_ADDR}, | |
188 | +}; | |
189 | + | |
190 | +#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) | |
191 | +#define USDHC3_CD_GPIO IMX_GPIO_NR(7, 0) | |
192 | + | |
193 | +int board_mmc_getcd(struct mmc *mmc) | |
194 | +{ | |
195 | + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; | |
196 | + int ret = 0; | |
197 | + | |
198 | + switch (cfg->esdhc_base) { | |
199 | + case USDHC2_BASE_ADDR: | |
200 | + ret = !gpio_get_value(USDHC2_CD_GPIO); | |
201 | + break; | |
202 | + case USDHC3_BASE_ADDR: | |
203 | + if (board_type == BOARD_IS_RIOTBOARD) | |
204 | + ret = !gpio_get_value(USDHC3_CD_GPIO); | |
205 | + else if (board_type == BOARD_IS_MARSBOARD) | |
206 | + ret = 1; /* eMMC/uSDHC3 is always present */ | |
207 | + break; | |
208 | + case USDHC4_BASE_ADDR: | |
209 | + ret = 1; /* eMMC/uSDHC4 is always present */ | |
210 | + break; | |
211 | + } | |
212 | + | |
213 | + return ret; | |
214 | +} | |
215 | + | |
216 | +int board_mmc_init(bd_t *bis) | |
217 | +{ | |
218 | + s32 status = 0; | |
219 | + int i; | |
220 | + | |
221 | + /* | |
222 | + * According to the board_mmc_init() the following map is done: | |
223 | + * (U-boot device node) (Physical Port) | |
224 | + * ** RiOTboard : | |
225 | + * mmc0 SDCard slot (bottom) | |
226 | + * mmc1 uSDCard slot (top) | |
227 | + * mmc2 eMMC | |
228 | + * ** MarSBoard : | |
229 | + * mmc0 uSDCard slot (bottom) | |
230 | + * mmc1 eMMC | |
231 | + */ | |
232 | + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { | |
233 | + switch (i) { | |
234 | + case 0: | |
235 | + imx_iomux_v3_setup_multiple_pads( | |
236 | + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); | |
237 | + gpio_direction_input(USDHC2_CD_GPIO); | |
238 | + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); | |
239 | + usdhc_cfg[0].max_bus_width = 4; | |
240 | + break; | |
241 | + case 1: | |
242 | + imx_iomux_v3_setup_multiple_pads( | |
243 | + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); | |
244 | + if (board_type == BOARD_IS_RIOTBOARD) { | |
245 | + imx_iomux_v3_setup_multiple_pads( | |
246 | + riotboard_usdhc3_pads, | |
247 | + ARRAY_SIZE(riotboard_usdhc3_pads)); | |
248 | + gpio_direction_input(USDHC3_CD_GPIO); | |
249 | + gpio_direction_output(IMX_GPIO_NR(7, 8) , 0); | |
250 | + udelay(250); | |
251 | + gpio_set_value(IMX_GPIO_NR(7, 8), 1); | |
252 | + } | |
253 | + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); | |
254 | + usdhc_cfg[1].max_bus_width = 4; | |
255 | + break; | |
256 | + case 2: | |
257 | + imx_iomux_v3_setup_multiple_pads( | |
258 | + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); | |
259 | + usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); | |
260 | + usdhc_cfg[2].max_bus_width = 4; | |
261 | + gpio_direction_output(IMX_GPIO_NR(6, 8) , 0); | |
262 | + udelay(250); | |
263 | + gpio_set_value(IMX_GPIO_NR(6, 8), 1); | |
264 | + break; | |
265 | + default: | |
266 | + printf("Warning: you configured more USDHC controllers" | |
267 | + "(%d) then supported by the board (%d)\n", | |
268 | + i + 1, CONFIG_SYS_FSL_USDHC_NUM); | |
269 | + return status; | |
270 | + } | |
271 | + | |
272 | + status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]); | |
273 | + } | |
274 | + | |
275 | + return status; | |
276 | +} | |
277 | +#endif | |
278 | + | |
279 | +#ifdef CONFIG_MXC_SPI | |
280 | +iomux_v3_cfg_t const ecspi1_pads[] = { | |
281 | + MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), | |
282 | + MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), | |
283 | + MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), | |
284 | + MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
285 | +}; | |
286 | + | |
287 | +static void setup_spi(void) | |
288 | +{ | |
289 | + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); | |
290 | +} | |
291 | +#endif | |
292 | + | |
293 | +struct i2c_pads_info i2c_pad_info1 = { | |
294 | + .scl = { | |
295 | + .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | |
296 | + | MUX_PAD_CTRL(I2C_PAD_CTRL), | |
297 | + .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | |
298 | + | MUX_PAD_CTRL(I2C_PAD_CTRL), | |
299 | + .gp = IMX_GPIO_NR(5, 27) | |
300 | + }, | |
301 | + .sda = { | |
302 | + .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | |
303 | + | MUX_PAD_CTRL(I2C_PAD_CTRL), | |
304 | + .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | |
305 | + | MUX_PAD_CTRL(I2C_PAD_CTRL), | |
306 | + .gp = IMX_GPIO_NR(5, 26) | |
307 | + } | |
308 | +}; | |
309 | + | |
310 | +struct i2c_pads_info i2c_pad_info2 = { | |
311 | + .scl = { | |
312 | + .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | |
313 | + | MUX_PAD_CTRL(I2C_PAD_CTRL), | |
314 | + .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | |
315 | + | MUX_PAD_CTRL(I2C_PAD_CTRL), | |
316 | + .gp = IMX_GPIO_NR(4, 12) | |
317 | + }, | |
318 | + .sda = { | |
319 | + .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | |
320 | + | MUX_PAD_CTRL(I2C_PAD_CTRL), | |
321 | + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | |
322 | + | MUX_PAD_CTRL(I2C_PAD_CTRL), | |
323 | + .gp = IMX_GPIO_NR(4, 13) | |
324 | + } | |
325 | +}; | |
326 | + | |
327 | +struct i2c_pads_info i2c_pad_info3 = { | |
328 | + .scl = { | |
329 | + .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | |
330 | + | MUX_PAD_CTRL(I2C_PAD_CTRL), | |
331 | + .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | |
332 | + | MUX_PAD_CTRL(I2C_PAD_CTRL), | |
333 | + .gp = IMX_GPIO_NR(1, 5) | |
334 | + }, | |
335 | + .sda = { | |
336 | + .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | |
337 | + | MUX_PAD_CTRL(I2C_PAD_CTRL), | |
338 | + .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | |
339 | + | MUX_PAD_CTRL(I2C_PAD_CTRL), | |
340 | + .gp = IMX_GPIO_NR(1, 6) | |
341 | + } | |
342 | +}; | |
343 | + | |
344 | +iomux_v3_cfg_t const tft_pads_riot[] = { | |
345 | + /* LCD_PWR_EN */ | |
346 | + MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
347 | + /* TOUCH_INT */ | |
348 | + MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
349 | + /* LED_PWR_EN */ | |
350 | + MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
351 | + /* BL LEVEL */ | |
352 | + MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
353 | +}; | |
354 | + | |
355 | +iomux_v3_cfg_t const tft_pads_mars[] = { | |
356 | + /* LCD_PWR_EN */ | |
357 | + MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
358 | + /* TOUCH_INT */ | |
359 | + MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
360 | + /* LED_PWR_EN */ | |
361 | + MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
362 | + /* BL LEVEL (PWM4) */ | |
363 | + MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
364 | +}; | |
365 | + | |
366 | +#if defined(CONFIG_VIDEO_IPUV3) | |
367 | + | |
368 | +static void enable_lvds(struct display_info_t const *dev) | |
369 | +{ | |
370 | + struct iomuxc *iomux = (struct iomuxc *) | |
371 | + IOMUXC_BASE_ADDR; | |
372 | + setbits_le32(&iomux->gpr[2], | |
373 | + IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT); | |
374 | + /* set backlight level to ON */ | |
375 | + if (board_type == BOARD_IS_RIOTBOARD) | |
376 | + gpio_direction_output(IMX_GPIO_NR(1, 18) , 1); | |
377 | + else if (board_type == BOARD_IS_MARSBOARD) | |
378 | + gpio_direction_output(IMX_GPIO_NR(2, 10) , 1); | |
379 | +} | |
380 | + | |
381 | +static void disable_lvds(struct display_info_t const *dev) | |
382 | +{ | |
383 | + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; | |
384 | + | |
385 | + /* set backlight level to OFF */ | |
386 | + if (board_type == BOARD_IS_RIOTBOARD) | |
387 | + gpio_direction_output(IMX_GPIO_NR(1, 18) , 0); | |
388 | + else if (board_type == BOARD_IS_MARSBOARD) | |
389 | + gpio_direction_output(IMX_GPIO_NR(2, 10) , 0); | |
390 | + | |
391 | + clrbits_le32(&iomux->gpr[2], | |
392 | + IOMUXC_GPR2_LVDS_CH0_MODE_MASK); | |
393 | +} | |
394 | + | |
395 | +static int detect_hdmi(struct display_info_t const *dev) | |
396 | +{ | |
397 | + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; | |
398 | + return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT; | |
399 | +} | |
400 | + | |
401 | +static void do_enable_hdmi(struct display_info_t const *dev) | |
402 | +{ | |
403 | + disable_lvds(dev); | |
404 | + imx_enable_hdmi_phy(); | |
405 | +} | |
406 | + | |
407 | +static int detect_i2c(struct display_info_t const *dev) | |
408 | +{ | |
409 | + return (0 == i2c_set_bus_num(dev->bus)) && | |
410 | + (0 == i2c_probe(dev->addr)); | |
411 | +} | |
412 | + | |
413 | +struct display_info_t const displays[] = {{ | |
414 | + .bus = -1, | |
415 | + .addr = 0, | |
416 | + .pixfmt = IPU_PIX_FMT_RGB24, | |
417 | + .detect = detect_hdmi, | |
418 | + .enable = do_enable_hdmi, | |
419 | + .mode = { | |
420 | + .name = "HDMI", | |
421 | + .refresh = 60, | |
422 | + .xres = 1024, | |
423 | + .yres = 768, | |
424 | + .pixclock = 15385, | |
425 | + .left_margin = 220, | |
426 | + .right_margin = 40, | |
427 | + .upper_margin = 21, | |
428 | + .lower_margin = 7, | |
429 | + .hsync_len = 60, | |
430 | + .vsync_len = 10, | |
431 | + .sync = FB_SYNC_EXT, | |
432 | + .vmode = FB_VMODE_NONINTERLACED | |
433 | +} }, { | |
434 | + .bus = 2, | |
435 | + .addr = 0x1, | |
436 | + .pixfmt = IPU_PIX_FMT_LVDS666, | |
437 | + .detect = detect_i2c, | |
438 | + .enable = enable_lvds, | |
439 | + .mode = { | |
440 | + .name = "LCD8000-97C", | |
441 | + .refresh = 60, | |
442 | + .xres = 1024, | |
443 | + .yres = 768, | |
444 | + .pixclock = 15385, | |
445 | + .left_margin = 100, | |
446 | + .right_margin = 200, | |
447 | + .upper_margin = 10, | |
448 | + .lower_margin = 20, | |
449 | + .hsync_len = 20, | |
450 | + .vsync_len = 8, | |
451 | + .sync = FB_SYNC_EXT, | |
452 | + .vmode = FB_VMODE_NONINTERLACED | |
453 | +} } }; | |
454 | +size_t display_count = ARRAY_SIZE(displays); | |
455 | + | |
456 | +static void setup_display(void) | |
457 | +{ | |
458 | + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
459 | + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; | |
460 | + int reg; | |
461 | + | |
462 | + enable_ipu_clock(); | |
463 | + imx_setup_hdmi(); | |
464 | + | |
465 | + /* Turn on LDB0, IPU,IPU DI0 clocks */ | |
466 | + setbits_le32(&mxc_ccm->CCGR3, | |
467 | + MXC_CCM_CCGR3_LDB_DI0_MASK); | |
468 | + | |
469 | + /* set LDB0 clk select to 011/011 */ | |
470 | + clrsetbits_le32(&mxc_ccm->cs2cdr, | |
471 | + MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK, | |
472 | + (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)); | |
473 | + | |
474 | + setbits_le32(&mxc_ccm->cscmr2, | |
475 | + MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); | |
476 | + | |
477 | + setbits_le32(&mxc_ccm->chsccdr, | |
478 | + (CHSCCDR_CLK_SEL_LDB_DI0 | |
479 | + << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)); | |
480 | + | |
481 | + reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES | |
482 | + | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW | |
483 | + | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG | |
484 | + | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT | |
485 | + | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG | |
486 | + | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | |
487 | + | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED | |
488 | + | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; | |
489 | + writel(reg, &iomux->gpr[2]); | |
490 | + | |
491 | + clrsetbits_le32(&iomux->gpr[3], | |
492 | + IOMUXC_GPR3_LVDS0_MUX_CTL_MASK | | |
493 | + IOMUXC_GPR3_HDMI_MUX_CTL_MASK, | |
494 | + IOMUXC_GPR3_MUX_SRC_IPU1_DI0 | |
495 | + << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); | |
496 | +} | |
497 | +#endif /* CONFIG_VIDEO_IPUV3 */ | |
498 | + | |
499 | +/* | |
500 | + * Do not overwrite the console | |
501 | + * Use always serial for U-Boot console | |
502 | + */ | |
503 | +int overwrite_console(void) | |
504 | +{ | |
505 | + return 1; | |
506 | +} | |
507 | + | |
508 | +int board_eth_init(bd_t *bis) | |
509 | +{ | |
510 | + setup_iomux_enet(); | |
511 | + | |
512 | + return cpu_eth_init(bis); | |
513 | +} | |
514 | + | |
515 | +int board_early_init_f(void) | |
516 | +{ | |
517 | + u32 cputype = cpu_type(get_cpu_rev()); | |
518 | + | |
519 | + switch (cputype) { | |
520 | + case MXC_CPU_MX6SOLO: | |
521 | + board_type = BOARD_IS_RIOTBOARD; | |
522 | + break; | |
523 | + case MXC_CPU_MX6D: | |
524 | + board_type = BOARD_IS_MARSBOARD; | |
525 | + break; | |
526 | + } | |
527 | + | |
528 | + setup_iomux_uart(); | |
529 | + | |
530 | + if (board_type == BOARD_IS_RIOTBOARD) | |
531 | + imx_iomux_v3_setup_multiple_pads( | |
532 | + tft_pads_riot, ARRAY_SIZE(tft_pads_riot)); | |
533 | + else if (board_type == BOARD_IS_MARSBOARD) | |
534 | + imx_iomux_v3_setup_multiple_pads( | |
535 | + tft_pads_mars, ARRAY_SIZE(tft_pads_mars)); | |
536 | +#if defined(CONFIG_VIDEO_IPUV3) | |
537 | + /* power ON LCD */ | |
538 | + gpio_direction_output(IMX_GPIO_NR(1, 29) , 1); | |
539 | + /* touch interrupt is an input */ | |
540 | + gpio_direction_input(IMX_GPIO_NR(6, 14)); | |
541 | + /* power ON backlight */ | |
542 | + gpio_direction_output(IMX_GPIO_NR(6, 15) , 1); | |
543 | + /* set backlight level to off */ | |
544 | + if (board_type == BOARD_IS_RIOTBOARD) | |
545 | + gpio_direction_output(IMX_GPIO_NR(1, 18) , 0); | |
546 | + else if (board_type == BOARD_IS_MARSBOARD) | |
547 | + gpio_direction_output(IMX_GPIO_NR(2, 10) , 0); | |
548 | + setup_display(); | |
549 | +#endif | |
550 | + | |
551 | + return 0; | |
552 | +} | |
553 | + | |
554 | +int board_init(void) | |
555 | +{ | |
556 | + /* address of boot parameters */ | |
557 | + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; | |
558 | + /* i2c1 : PMIC, Audio codec on RiOT, Expansion connector on MarS */ | |
559 | + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); | |
560 | + /* i2c2 : HDMI EDID */ | |
561 | + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); | |
562 | + /* i2c3 : LVDS, Expansion connector */ | |
563 | + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3); | |
564 | +#ifdef CONFIG_MXC_SPI | |
565 | + setup_spi(); | |
566 | +#endif | |
567 | + return 0; | |
568 | +} | |
569 | + | |
570 | +#ifdef CONFIG_CMD_BMODE | |
571 | +static const struct boot_mode riotboard_boot_modes[] = { | |
572 | + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, | |
573 | + {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, | |
574 | + {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, | |
575 | + {NULL, 0}, | |
576 | +}; | |
577 | +static const struct boot_mode marsboard_boot_modes[] = { | |
578 | + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, | |
579 | + {"emmc", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, | |
580 | + {NULL, 0}, | |
581 | +}; | |
582 | +#endif | |
583 | + | |
584 | +int board_late_init(void) | |
585 | +{ | |
586 | +#ifdef CONFIG_CMD_BMODE | |
587 | + if (board_type == BOARD_IS_RIOTBOARD) | |
588 | + add_board_boot_modes(riotboard_boot_modes); | |
589 | + else if (board_type == BOARD_IS_RIOTBOARD) | |
590 | + add_board_boot_modes(marsboard_boot_modes); | |
591 | +#endif | |
592 | + | |
593 | + return 0; | |
594 | +} | |
595 | + | |
596 | +int checkboard(void) | |
597 | +{ | |
598 | + puts("Board: "); | |
599 | + if (board_type == BOARD_IS_MARSBOARD) | |
600 | + puts("MarSBoard\n"); | |
601 | + else if (board_type == BOARD_IS_RIOTBOARD) | |
602 | + puts("RIoTboard\n"); | |
603 | + else | |
604 | + printf("unknown - cputype : %02x\n", cpu_type(get_cpu_rev())); | |
605 | + | |
606 | + return 0; | |
607 | +} |
boards.cfg
... | ... | @@ -328,6 +328,8 @@ |
328 | 328 | Active arm armv7 mx6 gateworks gw_ventana gwventanaq1g gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6Q,DDR_MB=1024 Tim Harvey <tharvey@gateworks.com> |
329 | 329 | Active arm armv7 mx6 gateworks gw_ventana gwventanaq1gspi gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6Q,DDR_MB=1024,SPI_FLASH Tim Harvey <tharvey@gateworks.com> |
330 | 330 | Active arm armv7 mx6 solidrun hummingboard hummingboard_solo hummingboard:IMX_CONFIG=board/solidrun/hummingboard/solo.cfg,MX6S,DDR_MB=512 Jon Nettleton <jon.nettleton@gmail.com> |
331 | +Active arm armv7 mx6 embest mx6boards riotboard embestmx6boards:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024,ENV_IS_IN_MMC Eric Bénard <eric@eukrea.com> | |
332 | +Active arm armv7 mx6 embest mx6boards marsboard embestmx6boards:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,ENV_IS_IN_SPI_FLASH Eric Bénard <eric@eukrea.com> | |
331 | 333 | Active arm armv7 omap3 - overo omap3_overo - Steve Sakoman <sakoman@gmail.com> |
332 | 334 | Active arm armv7 omap3 - pandora omap3_pandora - Grazvydas Ignotas <notasas@gmail.com> |
333 | 335 | Active arm armv7 omap3 8dtech eco5pk eco5pk - Raphael Assenat <raph@8d.com> |
include/configs/embestmx6boards.h
1 | +/* | |
2 | + * Copyright (C) 2014 Eukréa Electromatique | |
3 | + * Author: Eric Bénard <eric@eukrea.com> | |
4 | + * | |
5 | + * Configuration settings for the Embest RIoTboard | |
6 | + * | |
7 | + * based on mx6*sabre*.h which are : | |
8 | + * Copyright (C) 2012 Freescale Semiconductor, Inc. | |
9 | + * | |
10 | + * SPDX-License-Identifier: GPL-2.0+ | |
11 | + */ | |
12 | + | |
13 | +#ifndef __RIOTBOARD_CONFIG_H | |
14 | +#define __RIOTBOARD_CONFIG_H | |
15 | + | |
16 | +#include <asm/arch/imx-regs.h> | |
17 | +#include <asm/imx-common/gpio.h> | |
18 | + | |
19 | +#include "mx6_common.h" | |
20 | +#include <linux/sizes.h> | |
21 | + | |
22 | +#define CONFIG_MXC_UART_BASE UART2_BASE | |
23 | +#define CONFIG_CONSOLE_DEV "ttymxc0" | |
24 | +#define CONFIG_MMCROOT "/dev/mmcblk1p2" | |
25 | + | |
26 | +#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) | |
27 | + | |
28 | +#define CONFIG_MX6 | |
29 | + | |
30 | +#define CONFIG_DISPLAY_CPUINFO | |
31 | +#define CONFIG_DISPLAY_BOARDINFO | |
32 | + | |
33 | +#define CONFIG_CMDLINE_TAG | |
34 | +#define CONFIG_SETUP_MEMORY_TAGS | |
35 | +#define CONFIG_INITRD_TAG | |
36 | +#define CONFIG_REVISION_TAG | |
37 | + | |
38 | +/* Size of malloc() pool */ | |
39 | +#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) | |
40 | + | |
41 | +#define CONFIG_BOARD_EARLY_INIT_F | |
42 | +#define CONFIG_BOARD_LATE_INIT | |
43 | +#define CONFIG_MXC_GPIO | |
44 | + | |
45 | +#define CONFIG_MXC_UART | |
46 | + | |
47 | +#define CONFIG_CMD_FUSE | |
48 | +#ifdef CONFIG_CMD_FUSE | |
49 | +#define CONFIG_MXC_OCOTP | |
50 | +#endif | |
51 | + | |
52 | +/* I2C Configs */ | |
53 | +#define CONFIG_CMD_I2C | |
54 | +#define CONFIG_SYS_I2C | |
55 | +#define CONFIG_SYS_I2C_MXC | |
56 | +#define CONFIG_SYS_I2C_SPEED 100000 | |
57 | + | |
58 | +/* USB Configs */ | |
59 | +#define CONFIG_CMD_USB | |
60 | +#define CONFIG_USB_EHCI | |
61 | +#define CONFIG_USB_EHCI_MX6 | |
62 | +#define CONFIG_USB_STORAGE | |
63 | +#define CONFIG_USB_HOST_ETHER | |
64 | +#define CONFIG_USB_ETHER_ASIX | |
65 | +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 | |
66 | +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ | |
67 | +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) | |
68 | +#define CONFIG_MXC_USB_FLAGS 0 | |
69 | + | |
70 | +/* MMC Configs */ | |
71 | +#define CONFIG_FSL_ESDHC | |
72 | +#define CONFIG_FSL_USDHC | |
73 | +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 | |
74 | + | |
75 | +#define CONFIG_MMC | |
76 | +#define CONFIG_CMD_MMC | |
77 | +#define CONFIG_GENERIC_MMC | |
78 | +#define CONFIG_BOUNCE_BUFFER | |
79 | +#define CONFIG_CMD_EXT2 | |
80 | +#define CONFIG_CMD_FAT | |
81 | +#define CONFIG_DOS_PARTITION | |
82 | + | |
83 | +#define CONFIG_CMD_PING | |
84 | +#define CONFIG_CMD_DHCP | |
85 | +#define CONFIG_CMD_MII | |
86 | +#define CONFIG_CMD_NET | |
87 | +#define CONFIG_FEC_MXC | |
88 | +#define CONFIG_MII | |
89 | +#define IMX_FEC_BASE ENET_BASE_ADDR | |
90 | +#define CONFIG_FEC_XCV_TYPE RGMII | |
91 | +#define CONFIG_ETHPRIME "FEC" | |
92 | +#define CONFIG_FEC_MXC_PHYADDR 4 | |
93 | + | |
94 | +#define CONFIG_PHYLIB | |
95 | +#define CONFIG_PHY_ATHEROS | |
96 | + | |
97 | +#define CONFIG_CMD_SF | |
98 | +#ifdef CONFIG_CMD_SF | |
99 | +#define CONFIG_SPI_FLASH | |
100 | +#define CONFIG_SPI_FLASH_SST | |
101 | +#define CONFIG_MXC_SPI | |
102 | +#define CONFIG_SF_DEFAULT_BUS 0 | |
103 | +#define CONFIG_SF_DEFAULT_CS (0 | (IMX_GPIO_NR(2, 30) << 8)) | |
104 | +#define CONFIG_SF_DEFAULT_SPEED 20000000 | |
105 | +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 | |
106 | +#endif | |
107 | + | |
108 | +/* allow to overwrite serial and ethaddr */ | |
109 | +#define CONFIG_ENV_OVERWRITE | |
110 | +#define CONFIG_CONS_INDEX 1 | |
111 | +#define CONFIG_BAUDRATE 115200 | |
112 | + | |
113 | +/* Command definition */ | |
114 | +#include <config_cmd_default.h> | |
115 | + | |
116 | +#define CONFIG_CMD_BMODE | |
117 | +#define CONFIG_CMD_BOOTZ | |
118 | +#define CONFIG_CMD_SETEXPR | |
119 | +#undef CONFIG_CMD_IMLS | |
120 | + | |
121 | +#define CONFIG_BOOTDELAY 1 | |
122 | + | |
123 | +#define CONFIG_LOADADDR 0x12000000 | |
124 | +#define CONFIG_SYS_TEXT_BASE 0x17800000 | |
125 | + | |
126 | +#ifdef CONFIG_SUPPORT_EMMC_BOOT | |
127 | +#define EMMC_ENV \ | |
128 | + "emmcdev=2\0" \ | |
129 | + "update_emmc_firmware=" \ | |
130 | + "if test ${ip_dyn} = yes; then " \ | |
131 | + "setenv get_cmd dhcp; " \ | |
132 | + "else " \ | |
133 | + "setenv get_cmd tftp; " \ | |
134 | + "fi; " \ | |
135 | + "if ${get_cmd} ${update_sd_firmware_filename}; then " \ | |
136 | + "if mmc dev ${emmcdev}; then " \ | |
137 | + "setexpr fw_sz ${filesize} / 0x200; " \ | |
138 | + "setexpr fw_sz ${fw_sz} + 1; " \ | |
139 | + "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ | |
140 | + "fi; " \ | |
141 | + "fi\0" | |
142 | +#else | |
143 | +#define EMMC_ENV "" | |
144 | +#endif | |
145 | + | |
146 | +#ifdef CONFIG_CMD_SF | |
147 | +#define SF_ENV \ | |
148 | + "update_spi_firmware=" \ | |
149 | + "if test ${ip_dyn} = yes; then " \ | |
150 | + "setenv get_cmd dhcp; " \ | |
151 | + "else " \ | |
152 | + "setenv get_cmd tftp; " \ | |
153 | + "fi; " \ | |
154 | + "if ${get_cmd} ${update_spi_firmware_filename}; then " \ | |
155 | + "if sf probe; then " \ | |
156 | + "sf erase 0 0xc0000; " \ | |
157 | + "sf write ${loadaddr} 0x400 ${filesize}; " \ | |
158 | + "fi; " \ | |
159 | + "fi\0" | |
160 | +#else | |
161 | +#define SF_ENV "" | |
162 | +#endif | |
163 | + | |
164 | +#define CONFIG_EXTRA_ENV_SETTINGS \ | |
165 | + "script=boot.scr\0" \ | |
166 | + "image=zImage\0" \ | |
167 | + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ | |
168 | + "fdt_addr=0x18000000\0" \ | |
169 | + "boot_fdt=try\0" \ | |
170 | + "ip_dyn=yes\0" \ | |
171 | + "console=" CONFIG_CONSOLE_DEV "\0" \ | |
172 | + "fdt_high=0xffffffff\0" \ | |
173 | + "initrd_high=0xffffffff\0" \ | |
174 | + "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ | |
175 | + "mmcpart=1\0" \ | |
176 | + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ | |
177 | + "update_sd_firmware=" \ | |
178 | + "if test ${ip_dyn} = yes; then " \ | |
179 | + "setenv get_cmd dhcp; " \ | |
180 | + "else " \ | |
181 | + "setenv get_cmd tftp; " \ | |
182 | + "fi; " \ | |
183 | + "if mmc dev ${mmcdev}; then " \ | |
184 | + "if ${get_cmd} ${update_sd_firmware_filename}; then " \ | |
185 | + "setexpr fw_sz ${filesize} / 0x200; " \ | |
186 | + "setexpr fw_sz ${fw_sz} + 1; " \ | |
187 | + "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ | |
188 | + "fi; " \ | |
189 | + "fi\0" \ | |
190 | + EMMC_ENV \ | |
191 | + SF_ENV \ | |
192 | + "mmcargs=setenv bootargs console=${console},${baudrate} " \ | |
193 | + "root=${mmcroot}\0" \ | |
194 | + "loadbootscript=" \ | |
195 | + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ | |
196 | + "bootscript=echo Running bootscript from mmc ...; " \ | |
197 | + "source\0" \ | |
198 | + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ | |
199 | + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ | |
200 | + "mmcboot=echo Booting from mmc ...; " \ | |
201 | + "run mmcargs; " \ | |
202 | + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ | |
203 | + "if run loadfdt; then " \ | |
204 | + "bootz ${loadaddr} - ${fdt_addr}; " \ | |
205 | + "else " \ | |
206 | + "if test ${boot_fdt} = try; then " \ | |
207 | + "bootz; " \ | |
208 | + "else " \ | |
209 | + "echo WARN: Cannot load the DT; " \ | |
210 | + "fi; " \ | |
211 | + "fi; " \ | |
212 | + "else " \ | |
213 | + "bootz; " \ | |
214 | + "fi;\0" \ | |
215 | + "netargs=setenv bootargs console=${console},${baudrate} " \ | |
216 | + "root=/dev/nfs " \ | |
217 | + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ | |
218 | + "netboot=echo Booting from net ...; " \ | |
219 | + "run netargs; " \ | |
220 | + "if test ${ip_dyn} = yes; then " \ | |
221 | + "setenv get_cmd dhcp; " \ | |
222 | + "else " \ | |
223 | + "setenv get_cmd tftp; " \ | |
224 | + "fi; " \ | |
225 | + "${get_cmd} ${image}; " \ | |
226 | + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ | |
227 | + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ | |
228 | + "bootz ${loadaddr} - ${fdt_addr}; " \ | |
229 | + "else " \ | |
230 | + "if test ${boot_fdt} = try; then " \ | |
231 | + "bootz; " \ | |
232 | + "else " \ | |
233 | + "echo WARN: Cannot load the DT; " \ | |
234 | + "fi; " \ | |
235 | + "fi; " \ | |
236 | + "else " \ | |
237 | + "bootz; " \ | |
238 | + "fi;\0" | |
239 | + | |
240 | +#define CONFIG_BOOTCOMMAND \ | |
241 | + "mmc dev ${mmcdev};" \ | |
242 | + "if mmc rescan; then " \ | |
243 | + "if run loadbootscript; then " \ | |
244 | + "run bootscript; " \ | |
245 | + "else " \ | |
246 | + "if run loadimage; then " \ | |
247 | + "run mmcboot; " \ | |
248 | + "else run netboot; " \ | |
249 | + "fi; " \ | |
250 | + "fi; " \ | |
251 | + "else run netboot; fi" | |
252 | + | |
253 | +#define CONFIG_ARP_TIMEOUT 200UL | |
254 | + | |
255 | +/* Miscellaneous configurable options */ | |
256 | +#define CONFIG_SYS_LONGHELP | |
257 | +#define CONFIG_SYS_HUSH_PARSER | |
258 | +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
259 | +#define CONFIG_AUTO_COMPLETE | |
260 | +#define CONFIG_SYS_CBSIZE 256 | |
261 | + | |
262 | +/* Print Buffer Size */ | |
263 | +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
264 | +#define CONFIG_SYS_MAXARGS 16 | |
265 | +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
266 | + | |
267 | +#define CONFIG_SYS_MEMTEST_START 0x10000000 | |
268 | +#define CONFIG_SYS_MEMTEST_END 0x10010000 | |
269 | +#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 | |
270 | + | |
271 | +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR | |
272 | + | |
273 | +#define CONFIG_CMDLINE_EDITING | |
274 | +#define CONFIG_STACKSIZE (128 * 1024) | |
275 | + | |
276 | +/* Physical Memory Map */ | |
277 | +#define CONFIG_NR_DRAM_BANKS 1 | |
278 | +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR | |
279 | + | |
280 | +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM | |
281 | +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR | |
282 | +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE | |
283 | + | |
284 | +#define CONFIG_SYS_INIT_SP_OFFSET \ | |
285 | + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
286 | +#define CONFIG_SYS_INIT_SP_ADDR \ | |
287 | + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
288 | + | |
289 | +/* FLASH and environment organization */ | |
290 | +#define CONFIG_SYS_NO_FLASH | |
291 | + | |
292 | +#define CONFIG_ENV_SIZE (8 * 1024) | |
293 | + | |
294 | +#if defined(CONFIG_ENV_IS_IN_MMC) | |
295 | +/* RiOTboard */ | |
296 | +#define CONFIG_DEFAULT_FDT_FILE "imx6s-riotboard.dtb" | |
297 | +#define CONFIG_SYS_FSL_USDHC_NUM 3 | |
298 | +#define CONFIG_SYS_MMC_ENV_DEV 2 /* SDHC4 */ | |
299 | +#define CONFIG_ENV_OFFSET (6 * 64 * 1024) | |
300 | +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ | |
301 | +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) | |
302 | +/* MarSBoard */ | |
303 | +#define CONFIG_DEFAULT_FDT_FILE "imx6q-marsboard.dtb" | |
304 | +#define CONFIG_SYS_FSL_USDHC_NUM 2 | |
305 | +#define CONFIG_ENV_OFFSET (768 * 1024) | |
306 | +#define CONFIG_ENV_SECT_SIZE (8 * 1024) | |
307 | +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS | |
308 | +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS | |
309 | +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE | |
310 | +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED | |
311 | +#endif | |
312 | + | |
313 | +#define CONFIG_OF_LIBFDT | |
314 | + | |
315 | +#ifndef CONFIG_SYS_DCACHE_OFF | |
316 | +#define CONFIG_CMD_CACHE | |
317 | +#endif | |
318 | + | |
319 | +/* Framebuffer */ | |
320 | +#define CONFIG_VIDEO | |
321 | +#define CONFIG_VIDEO_IPUV3 | |
322 | +#define CONFIG_CFB_CONSOLE | |
323 | +#define CONFIG_VGA_AS_SINGLE_DEVICE | |
324 | +#define CONFIG_SYS_CONSOLE_IS_IN_ENV | |
325 | +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE | |
326 | +#define CONFIG_VIDEO_BMP_RLE8 | |
327 | +#define CONFIG_SPLASH_SCREEN | |
328 | +#define CONFIG_SPLASH_SCREEN_ALIGN | |
329 | +#define CONFIG_BMP_16BPP | |
330 | +#define CONFIG_VIDEO_LOGO | |
331 | +#define CONFIG_VIDEO_BMP_LOGO | |
332 | +#define CONFIG_IPUV3_CLK 260000000 | |
333 | +#define CONFIG_IMX_HDMI | |
334 | +#define CONFIG_IMX_VIDEO_SKIP | |
335 | + | |
336 | +#endif /* __RIOTBOARD_CONFIG_H */ |