x86: Support booting SeaBIOS

SeaBIOS is an open source implementation of a 16-bit x86 BIOS. It can run in an emulator or natively on x86 hardware with the use of coreboot. With SeaBIOS's help, we can boot some OSes that require 16-bit BIOS services like Windows/DOS. As U-Boot, we have to manually create a table where SeaBIOS gets system information (eg: E820) from. The table unfortunately has to follow the coreboot table format as SeaBIOS currently supports booting as a coreboot payload. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>

x86: Support booting SeaBIOS
SeaBIOS is an open source implementation of a 16-bit x86 BIOS. It can run in an emulator or natively on x86 hardware with the use of coreboot. With SeaBIOS's help, we can boot some OSes that require 16-bit BIOS services like Windows/DOS. As U-Boot, we have to manually create a table where SeaBIOS gets system information (eg: E820) from. The table unfortunately has to follow the coreboot table format as SeaBIOS currently supports booting as a coreboot payload. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng
1 parent 26f9a9b73a
Showing 3 changed files with 28 additions and 0 deletions Side-by-side Diff
arch/x86/Kconfig
arch/x86/include/asm/tables.h
arch/x86/lib/tables.c
@@ -449,6 +449,16 @@
 config DM_KEYBOARD
 	default y
  
+config SEABIOS
+	bool "Support booting SeaBIOS"
+	help
+	  SeaBIOS is an open source implementation of a 16-bit X86 BIOS.
+	  It can run in an emulator or natively on X86 hardware with the use
+	  of coreboot/U-Boot. By turning on this option, U-Boot prepares
+	  all the configuration tables that are necessary to boot SeaBIOS.
+
+	  Check http://www.seabios.org/SeaBIOS for details.
+
 source "arch/x86/lib/efi/Kconfig"
  
 endmenu
@@ -16,6 +16,9 @@
  
 #define ROM_TABLE_ALIGN	1024
  
+/* SeaBIOS expects coreboot tables at address range 0x0000-0x1000 */
+#define CB_TABLE_ADDR	0x800
+
 /**
  * table_compute_checksum() - Compute a table checksum
  *
@@ -10,6 +10,7 @@
 #include <asm/smbios.h>
 #include <asm/tables.h>
 #include <asm/acpi_table.h>
+#include <asm/coreboot_tables.h>
  
 /**
  * Function prototype to write a specific configuration table
  
  
  
  
  
@@ -67,23 +68,37 @@
 {
 	u32 rom_table_start = ROM_TABLE_ADDR;
 	u32 rom_table_end;
+#ifdef CONFIG_SEABIOS
 	u32 high_table, table_size;
+	struct memory_area cfg_tables[ARRAY_SIZE(table_write_funcs) + 1];
+#endif
 	int i;
  
 	for (i = 0; i < ARRAY_SIZE(table_write_funcs); i++) {
 		rom_table_end = table_write_funcs[i](rom_table_start);
 		rom_table_end = ALIGN(rom_table_end, ROM_TABLE_ALIGN);
  
+#ifdef CONFIG_SEABIOS
 		table_size = rom_table_end - rom_table_start;
 		high_table = (u32)memalign(ROM_TABLE_ALIGN, table_size);
 		if (high_table) {
 			memset((void *)high_table, 0, table_size);
 			table_write_funcs[i](high_table);
+
+			cfg_tables[i].start = high_table;
+			cfg_tables[i].size = table_size;
 		} else {
 			printf("%d: no memory for configuration tables\n", i);
 		}
+#endif
  
 		rom_table_start = rom_table_end;
 	}
+
+#ifdef CONFIG_SEABIOS
+	/* make sure the last item is zero */
+	cfg_tables[i].size = 0;
+	write_coreboot_table(CB_TABLE_ADDR, cfg_tables);
+#endif
 }
...	...	@@ -449,6 +449,16 @@
449	449	config DM_KEYBOARD
450	450	default y
451	451
	452	+config SEABIOS
	453	+ bool "Support booting SeaBIOS"
	454	+ help
	455	+ SeaBIOS is an open source implementation of a 16-bit X86 BIOS.
	456	+ It can run in an emulator or natively on X86 hardware with the use
	457	+ of coreboot/U-Boot. By turning on this option, U-Boot prepares
	458	+ all the configuration tables that are necessary to boot SeaBIOS.
	459	+
	460	+ Check http://www.seabios.org/SeaBIOS for details.
	461	+
452	462	source "arch/x86/lib/efi/Kconfig"
453	463
454	464	endmenu
...	...	@@ -16,6 +16,9 @@
16	16
17	17	#define ROM_TABLE_ALIGN 1024
18	18
	19	+/* SeaBIOS expects coreboot tables at address range 0x0000-0x1000 */
	20	+#define CB_TABLE_ADDR 0x800
	21	+
19	22	/**
20	23	* table_compute_checksum() - Compute a table checksum
21	24	*
...	...	@@ -10,6 +10,7 @@
10	10	#include <asm/smbios.h>
11	11	#include <asm/tables.h>
12	12	#include <asm/acpi_table.h>
	13	+#include <asm/coreboot_tables.h>
13	14
14	15	/**
15	16	* Function prototype to write a specific configuration table
16	17
17	18
18	19
19	20
20	21
...	...	@@ -67,23 +68,37 @@
67	68	{
68	69	u32 rom_table_start = ROM_TABLE_ADDR;
69	70	u32 rom_table_end;
	71	+#ifdef CONFIG_SEABIOS
70	72	u32 high_table, table_size;
	73	+ struct memory_area cfg_tables[ARRAY_SIZE(table_write_funcs) + 1];
	74	+#endif
71	75	int i;
72	76
73	77	for (i = 0; i < ARRAY_SIZE(table_write_funcs); i++) {
74	78	rom_table_end = table_write_funcs[i](rom_table_start);
75	79	rom_table_end = ALIGN(rom_table_end, ROM_TABLE_ALIGN);
76	80
	81	+#ifdef CONFIG_SEABIOS
77	82	table_size = rom_table_end - rom_table_start;
78	83	high_table = (u32)memalign(ROM_TABLE_ALIGN, table_size);
79	84	if (high_table) {
80	85	memset((void *)high_table, 0, table_size);
81	86	table_write_funcs[i](high_table);
	87	+
	88	+ cfg_tables[i].start = high_table;
	89	+ cfg_tables[i].size = table_size;
82	90	} else {
83	91	printf("%d: no memory for configuration tables\n", i);
84	92	}
	93	+#endif
85	94
86	95	rom_table_start = rom_table_end;
87	96	}
	97	+
	98	+#ifdef CONFIG_SEABIOS
	99	+ /* make sure the last item is zero */
	100	+ cfg_tables[i].size = 0;
	101	+ write_coreboot_table(CB_TABLE_ADDR, cfg_tables);
	102	+#endif
88	103	}