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Commit 3d357619a509eb2b39dc5056731ca08bc2b23e62

Authored by Masahiro Yamada
Committed by Tom Rini
1 parent af93082760
Exists in v2017.01-smarct4x and in 38 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

ARM: davinci: move SoC headers to mach-davinci/include/mach 

Move arch/arm/include/asm/arch-davinci/*
  -> arch/arm/mach-davinci/include/mach/*

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>

Showing 32 changed files with 1587 additions and 1587 deletions Side-by-side Diff

arch/arm/include/asm/arch-davinci/aintc_defs.h
View file @ 3d35761
1   -/*
2   - * Copyright (C) 2011
3   - * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -#ifndef _DV_AINTC_DEFS_H_
8   -#define _DV_AINTC_DEFS_H_
9   -
10   -struct dv_aintc_regs {
11   - unsigned int fiq0; /* 0x00 */
12   - unsigned int fiq1; /* 0x04 */
13   - unsigned int irq0; /* 0x08 */
14   - unsigned int irq1; /* 0x0c */
15   - unsigned int fiqentry; /* 0x10 */
16   - unsigned int irqentry; /* 0x14 */
17   - unsigned int eint0; /* 0x18 */
18   - unsigned int eint1; /* 0x1c */
19   - unsigned int intctl; /* 0x20 */
20   - unsigned int eabase; /* 0x24 */
21   - unsigned char rsvd0[8]; /* 0x28 */
22   - unsigned int intpri0; /* 0x30 */
23   - unsigned int intpri1; /* 0x34 */
24   - unsigned int intpri2; /* 0x38 */
25   - unsigned int intpri3; /* 0x3c */
26   - unsigned int intpri4; /* 0x40 */
27   - unsigned int intpri5; /* 0x44 */
28   - unsigned int intpri6; /* 0x48 */
29   - unsigned int intpri7; /* 0x4c */
30   -};
31   -
32   -#define dv_aintc_regs ((struct dv_aintc_regs *)DAVINCI_ARM_INTC_BASE)
33   -
34   -#define DV_AINTC_INTCTL_IDMODE (1 << 2)
35   -
36   -#endif /* _DV_AINTC_DEFS_H_ */
arch/arm/include/asm/arch-davinci/da850_lowlevel.h
View file @ 3d35761
1   -/*
2   - * SoC-specific lowlevel code for DA850
3   - *
4   - * Copyright (C) 2011
5   - * Heiko Schocher, DENX Software Engineering, hs@denx.de.
6   - *
7   - * SPDX-License-Identifier: GPL-2.0+
8   - */
9   -#ifndef __DA850_LOWLEVEL_H
10   -#define __DA850_LOWLEVEL_H
11   -
12   -#include <asm/arch/pinmux_defs.h>
13   -
14   -/* pinmux_resource[] vector is defined in the board specific file */
15   -extern const struct pinmux_resource pinmuxes[];
16   -extern const int pinmuxes_size;
17   -
18   -extern const struct lpsc_resource lpsc[];
19   -extern const int lpsc_size;
20   -
21   -/* NOR Boot Configuration Word Field Descriptions */
22   -#define DA850_NORBOOT_COPY_XK(X) ((X - 1) << 8)
23   -#define DA850_NORBOOT_METHOD_DIRECT (1 << 4)
24   -#define DA850_NORBOOT_16BIT (1 << 0)
25   -
26   -#define dv_maskbits(addr, val) \
27   - writel((readl(addr) & val), addr)
28   -
29   -void da850_lpc_transition(unsigned char pscnum, unsigned char module,
30   - unsigned char domain, unsigned char state);
31   -void da850_psc_init(void);
32   -void da850_pinmux_ctl(unsigned long offset, unsigned long mask,
33   - unsigned long value);
34   -
35   -#endif /* #ifndef __DA850_LOWLEVEL_H */
arch/arm/include/asm/arch-davinci/da8xx-usb.h
View file @ 3d35761
1   -/*
2   - * da8xx-usb.h -- TI's DA8xx platform specific usb wrapper definitions.
3   - *
4   - * Author: Ajay Kumar Gupta <ajay.gupta@ti.com>
5   - *
6   - * Based on drivers/usb/musb/davinci.h
7   - *
8   - * Copyright (C) 2009 Texas Instruments Incorporated
9   - *
10   - * SPDX-License-Identifier: GPL-2.0+
11   - */
12   -#ifndef __DA8XX_MUSB_H__
13   -#define __DA8XX_MUSB_H__
14   -
15   -#include <asm/arch/hardware.h>
16   -#include <asm/arch/gpio.h>
17   -
18   -/* Base address of da8xx usb0 wrapper */
19   -#define DA8XX_USB_OTG_BASE 0x01E00000
20   -
21   -/* Base address of da8xx musb core */
22   -#define DA8XX_USB_OTG_CORE_BASE (DA8XX_USB_OTG_BASE + 0x400)
23   -
24   -/* Timeout for DA8xx usb module */
25   -#define DA8XX_USB_OTG_TIMEOUT 0x3FFFFFF
26   -
27   -/*
28   - * DA8xx platform USB wrapper register overlay.
29   - */
30   -struct da8xx_usb_regs {
31   - dv_reg revision;
32   - dv_reg control;
33   - dv_reg status;
34   - dv_reg emulation;
35   - dv_reg mode;
36   - dv_reg autoreq;
37   - dv_reg srpfixtime;
38   - dv_reg teardown;
39   - dv_reg intsrc;
40   - dv_reg intsrc_set;
41   - dv_reg intsrc_clr;
42   - dv_reg intmsk;
43   - dv_reg intmsk_set;
44   - dv_reg intmsk_clr;
45   - dv_reg intsrcmsk;
46   - dv_reg eoi;
47   - dv_reg intvector;
48   - dv_reg grndis_size[4];
49   -};
50   -
51   -#define da8xx_usb_regs ((struct da8xx_usb_regs *)DA8XX_USB_OTG_BASE)
52   -
53   -/* DA8XX interrupt bits definitions */
54   -#define DA8XX_USB_TX_ENDPTS_MASK 0x1f /* ep0 + 4 tx */
55   -#define DA8XX_USB_RX_ENDPTS_MASK 0x1e /* 4 rx */
56   -#define DA8XX_USB_TXINT_SHIFT 0
57   -#define DA8XX_USB_RXINT_SHIFT 8
58   -
59   -#define DA8XX_USB_USBINT_MASK 0x01ff0000 /* 8 Mentor, DRVVBUS */
60   -#define DA8XX_USB_TXINT_MASK \
61   - (DA8XX_USB_TX_ENDPTS_MASK << DA8XX_USB_TXINT_SHIFT)
62   -#define DA8XX_USB_RXINT_MASK \
63   - (DA8XX_USB_RX_ENDPTS_MASK << DA8XX_USB_RXINT_SHIFT)
64   -
65   -/* DA8xx CFGCHIP2 (USB 2.0 PHY Control) register bits */
66   -#define CFGCHIP2_PHYCLKGD (1 << 17)
67   -#define CFGCHIP2_VBUSSENSE (1 << 16)
68   -#define CFGCHIP2_RESET (1 << 15)
69   -#define CFGCHIP2_OTGMODE (3 << 13)
70   -#define CFGCHIP2_NO_OVERRIDE (0 << 13)
71   -#define CFGCHIP2_FORCE_HOST (1 << 13)
72   -#define CFGCHIP2_FORCE_DEVICE (2 << 13)
73   -#define CFGCHIP2_FORCE_HOST_VBUS_LOW (3 << 13)
74   -#define CFGCHIP2_USB1PHYCLKMUX (1 << 12)
75   -#define CFGCHIP2_USB2PHYCLKMUX (1 << 11)
76   -#define CFGCHIP2_PHYPWRDN (1 << 10)
77   -#define CFGCHIP2_OTGPWRDN (1 << 9)
78   -#define CFGCHIP2_DATPOL (1 << 8)
79   -#define CFGCHIP2_USB1SUSPENDM (1 << 7)
80   -#define CFGCHIP2_PHY_PLLON (1 << 6) /* override PLL suspend */
81   -#define CFGCHIP2_SESENDEN (1 << 5) /* Vsess_end comparator */
82   -#define CFGCHIP2_VBDTCTEN (1 << 4) /* Vbus comparator */
83   -#define CFGCHIP2_REFFREQ (0xf << 0)
84   -#define CFGCHIP2_REFFREQ_12MHZ (1 << 0)
85   -#define CFGCHIP2_REFFREQ_24MHZ (2 << 0)
86   -#define CFGCHIP2_REFFREQ_48MHZ (3 << 0)
87   -
88   -#define DA8XX_USB_VBUS_GPIO (1 << 15)
89   -
90   -int usb_phy_on(void);
91   -void usb_phy_off(void);
92   -
93   -#endif /* __DA8XX_MUSB_H__ */
arch/arm/include/asm/arch-davinci/davinci_misc.h
View file @ 3d35761
1   -/*
2   - * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - */
6   -
7   -#ifndef __MISC_H
8   -#define __MISC_H
9   -
10   -/* pin muxer definitions */
11   -#define PIN_MUX_NUM_FIELDS 8 /* Per register */
12   -#define PIN_MUX_FIELD_SIZE 4 /* n in bits */
13   -#define PIN_MUX_FIELD_MASK ((1 << PIN_MUX_FIELD_SIZE) - 1)
14   -
15   -/* pin definition */
16   -struct pinmux_config {
17   - dv_reg *mux; /* Address of mux register */
18   - unsigned char value; /* Value to set in field */
19   - unsigned char field; /* field number */
20   -};
21   -
22   -/* pin table definition */
23   -struct pinmux_resource {
24   - const struct pinmux_config *pins;
25   - const int n_pins;
26   -};
27   -
28   -#define PINMUX_ITEM(item) { \
29   - .pins = item, \
30   - .n_pins = ARRAY_SIZE(item) \
31   - }
32   -
33   -struct lpsc_resource {
34   - const int lpsc_no;
35   -};
36   -
37   -int dvevm_read_mac_address(uint8_t *buf);
38   -void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr);
39   -int davinci_configure_pin_mux(const struct pinmux_config *pins, int n_pins);
40   -int davinci_configure_pin_mux_items(const struct pinmux_resource *item,
41   - int n_items);
42   -#if defined(CONFIG_DRIVER_TI_EMAC) && defined(CONFIG_SOC_DA8XX)
43   -void davinci_emac_mii_mode_sel(int mode_sel);
44   -#endif
45   -#if defined(CONFIG_SOC_DA8XX)
46   -void irq_init(void);
47   -int da8xx_configure_lpsc_items(const struct lpsc_resource *item,
48   - const int n_items);
49   -#endif
50   -
51   -#endif /* __MISC_H */
arch/arm/include/asm/arch-davinci/ddr2_defs.h
View file @ 3d35761
1   -/*
2   - * Copyright (C) 2011
3   - * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -#ifndef _DV_DDR2_DEFS_H_
8   -#define _DV_DDR2_DEFS_H_
9   -
10   -/*
11   - * DDR2 Memory Ctrl Register structure
12   - * See sprueh7d.pdf for more details.
13   - */
14   -struct dv_ddr2_regs_ctrl {
15   - unsigned char rsvd0[4]; /* 0x00 */
16   - unsigned int sdrstat; /* 0x04 */
17   - unsigned int sdbcr; /* 0x08 */
18   - unsigned int sdrcr; /* 0x0C */
19   - unsigned int sdtimr; /* 0x10 */
20   - unsigned int sdtimr2; /* 0x14 */
21   - unsigned char rsvd1[4]; /* 0x18 */
22   - unsigned int sdbcr2; /* 0x1C */
23   - unsigned int pbbpr; /* 0x20 */
24   - unsigned char rsvd2[156]; /* 0x24 */
25   - unsigned int irr; /* 0xC0 */
26   - unsigned int imr; /* 0xC4 */
27   - unsigned int imsr; /* 0xC8 */
28   - unsigned int imcr; /* 0xCC */
29   - unsigned char rsvd3[20]; /* 0xD0 */
30   - unsigned int ddrphycr; /* 0xE4 */
31   - unsigned int ddrphycr2; /* 0xE8 */
32   - unsigned char rsvd4[4]; /* 0xEC */
33   -};
34   -
35   -#define DV_DDR_PHY_PWRDNEN 0x40
36   -#define DV_DDR_PHY_EXT_STRBEN 0x80
37   -#define DV_DDR_PHY_RD_LATENCY_SHIFT 0
38   -
39   -#define DV_DDR_SDTMR1_RFC_SHIFT 25
40   -#define DV_DDR_SDTMR1_RP_SHIFT 22
41   -#define DV_DDR_SDTMR1_RCD_SHIFT 19
42   -#define DV_DDR_SDTMR1_WR_SHIFT 16
43   -#define DV_DDR_SDTMR1_RAS_SHIFT 11
44   -#define DV_DDR_SDTMR1_RC_SHIFT 6
45   -#define DV_DDR_SDTMR1_RRD_SHIFT 3
46   -#define DV_DDR_SDTMR1_WTR_SHIFT 0
47   -
48   -#define DV_DDR_SDTMR2_RASMAX_SHIFT 27
49   -#define DV_DDR_SDTMR2_XP_SHIFT 25
50   -#define DV_DDR_SDTMR2_ODT_SHIFT 23
51   -#define DV_DDR_SDTMR2_XSNR_SHIFT 16
52   -#define DV_DDR_SDTMR2_XSRD_SHIFT 8
53   -#define DV_DDR_SDTMR2_RTP_SHIFT 5
54   -#define DV_DDR_SDTMR2_CKE_SHIFT 0
55   -
56   -#define DV_DDR_SDCR_DDR2TERM1_SHIFT 27
57   -#define DV_DDR_SDCR_IBANK_POS_SHIFT 26
58   -#define DV_DDR_SDCR_MSDRAMEN_SHIFT 25
59   -#define DV_DDR_SDCR_DDRDRIVE1_SHIFT 24
60   -#define DV_DDR_SDCR_BOOTUNLOCK_SHIFT 23
61   -#define DV_DDR_SDCR_DDR_DDQS_SHIFT 22
62   -#define DV_DDR_SDCR_DDR2EN_SHIFT 20
63   -#define DV_DDR_SDCR_DDRDRIVE0_SHIFT 18
64   -#define DV_DDR_SDCR_DDREN_SHIFT 17
65   -#define DV_DDR_SDCR_SDRAMEN_SHIFT 16
66   -#define DV_DDR_SDCR_TIMUNLOCK_SHIFT 15
67   -#define DV_DDR_SDCR_BUS_WIDTH_SHIFT 14
68   -#define DV_DDR_SDCR_CL_SHIFT 9
69   -#define DV_DDR_SDCR_IBANK_SHIFT 4
70   -#define DV_DDR_SDCR_PAGESIZE_SHIFT 0
71   -
72   -#define DV_DDR_SDRCR_LPMODEN (1 << 31)
73   -#define DV_DDR_SDRCR_MCLKSTOPEN (1 << 30)
74   -
75   -#define DV_DDR_SRCR_LPMODEN_SHIFT 31
76   -#define DV_DDR_SRCR_MCLKSTOPEN_SHIFT 30
77   -
78   -#define DV_DDR_BOOTUNLOCK (1 << DV_DDR_SDCR_BOOTUNLOCK_SHIFT)
79   -#define DV_DDR_TIMUNLOCK (1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT)
80   -
81   -#define dv_ddr2_regs_ctrl \
82   - ((struct dv_ddr2_regs_ctrl *)DAVINCI_DDR_EMIF_CTRL_BASE)
83   -
84   -#endif /* _DV_DDR2_DEFS_H_ */
arch/arm/include/asm/arch-davinci/dm365_lowlevel.h
View file @ 3d35761
1   -/*
2   - * SoC-specific lowlevel code for tms320dm365 and similar chips
3   - *
4   - * Copyright (C) 2011
5   - * Heiko Schocher, DENX Software Engineering, hs@denx.de.
6   - *
7   - * SPDX-License-Identifier: GPL-2.0+
8   - */
9   -#ifndef __DM365_LOWLEVEL_H
10   -#define __DM365_LOWLEVEL_H
11   -
12   -#include <common.h>
13   -#include <asm/arch/hardware.h>
14   -#include <asm/io.h>
15   -
16   -void dm365_waitloop(unsigned long loopcnt);
17   -int dm365_pll1_init(unsigned long pllmult, unsigned long prediv);
18   -int dm365_pll2_init(unsigned long pllm, unsigned long prediv);
19   -int dm365_ddr_setup(void);
20   -void dm365_psc_init(void);
21   -void dm365_pinmux_ctl(unsigned long offset, unsigned long mask,
22   - unsigned long value);
23   -void dm36x_lowlevel_init(ulong bootflag);
24   -
25   -#endif /* #ifndef __DM365_LOWLEVEL_H */
arch/arm/include/asm/arch-davinci/emac_defs.h
View file @ 3d35761
1   -/*
2   - * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
3   - *
4   - * Based on:
5   - *
6   - * ----------------------------------------------------------------------------
7   - *
8   - * dm644x_emac.h
9   - *
10   - * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM
11   - *
12   - * Copyright (C) 2005 Texas Instruments.
13   - *
14   - * ----------------------------------------------------------------------------
15   - *
16   - * SPDX-License-Identifier: GPL-2.0+
17   - *
18   - * Modifications:
19   - * ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot.
20   - */
21   -
22   -#ifndef _DM644X_EMAC_H_
23   -#define _DM644X_EMAC_H_
24   -
25   -#include <asm/arch/hardware.h>
26   -
27   -#ifdef CONFIG_SOC_DM365
28   -#define EMAC_BASE_ADDR (0x01d07000)
29   -#define EMAC_WRAPPER_BASE_ADDR (0x01d0a000)
30   -#define EMAC_WRAPPER_RAM_ADDR (0x01d08000)
31   -#define EMAC_MDIO_BASE_ADDR (0x01d0b000)
32   -#define DAVINCI_EMAC_VERSION2
33   -#elif defined(CONFIG_SOC_DA8XX)
34   -#define EMAC_BASE_ADDR DAVINCI_EMAC_CNTRL_REGS_BASE
35   -#define EMAC_WRAPPER_BASE_ADDR DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE
36   -#define EMAC_WRAPPER_RAM_ADDR DAVINCI_EMAC_WRAPPER_RAM_BASE
37   -#define EMAC_MDIO_BASE_ADDR DAVINCI_MDIO_CNTRL_REGS_BASE
38   -#define DAVINCI_EMAC_VERSION2
39   -#else
40   -#define EMAC_BASE_ADDR (0x01c80000)
41   -#define EMAC_WRAPPER_BASE_ADDR (0x01c81000)
42   -#define EMAC_WRAPPER_RAM_ADDR (0x01c82000)
43   -#define EMAC_MDIO_BASE_ADDR (0x01c84000)
44   -#endif
45   -
46   -#ifdef CONFIG_SOC_DM646X
47   -#define DAVINCI_EMAC_VERSION2
48   -#define DAVINCI_EMAC_GIG_ENABLE
49   -#endif
50   -
51   -#ifdef CONFIG_SOC_DM646X
52   -/* MDIO module input frequency */
53   -#define EMAC_MDIO_BUS_FREQ 76500000
54   -/* MDIO clock output frequency */
55   -#define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */
56   -#elif defined(CONFIG_SOC_DM365)
57   -/* MDIO module input frequency */
58   -#define EMAC_MDIO_BUS_FREQ 121500000
59   -/* MDIO clock output frequency */
60   -#define EMAC_MDIO_CLOCK_FREQ 2200000 /* 2.2 MHz */
61   -#elif defined(CONFIG_SOC_DA8XX)
62   -/* MDIO module input frequency */
63   -#define EMAC_MDIO_BUS_FREQ clk_get(DAVINCI_MDIO_CLKID)
64   -/* MDIO clock output frequency */
65   -#define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */
66   -#else
67   -/* MDIO module input frequency */
68   -#define EMAC_MDIO_BUS_FREQ 99000000 /* PLL/6 - 99 MHz */
69   -/* MDIO clock output frequency */
70   -#define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */
71   -#endif
72   -
73   -#define PHY_KSZ8873 (0x00221450)
74   -int ksz8873_is_phy_connected(int phy_addr);
75   -int ksz8873_get_link_speed(int phy_addr);
76   -int ksz8873_init_phy(int phy_addr);
77   -int ksz8873_auto_negotiate(int phy_addr);
78   -
79   -#define PHY_LXT972 (0x001378e2)
80   -int lxt972_is_phy_connected(int phy_addr);
81   -int lxt972_get_link_speed(int phy_addr);
82   -int lxt972_init_phy(int phy_addr);
83   -int lxt972_auto_negotiate(int phy_addr);
84   -
85   -#define PHY_DP83848 (0x20005c90)
86   -int dp83848_is_phy_connected(int phy_addr);
87   -int dp83848_get_link_speed(int phy_addr);
88   -int dp83848_init_phy(int phy_addr);
89   -int dp83848_auto_negotiate(int phy_addr);
90   -
91   -#define PHY_ET1011C (0x282f013)
92   -int et1011c_get_link_speed(int phy_addr);
93   -
94   -#endif /* _DM644X_EMAC_H_ */
arch/arm/include/asm/arch-davinci/gpio.h
View file @ 3d35761
1   -/*
2   - * Copyright (C) 2009 Texas Instruments Incorporated
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - */
6   -#ifndef _GPIO_DEFS_H_
7   -#define _GPIO_DEFS_H_
8   -
9   -#ifndef CONFIG_SOC_DA8XX
10   -#define DAVINCI_GPIO_BINTEN 0x01C67008
11   -#define DAVINCI_GPIO_BANK01 0x01C67010
12   -#define DAVINCI_GPIO_BANK23 0x01C67038
13   -#define DAVINCI_GPIO_BANK45 0x01C67060
14   -#define DAVINCI_GPIO_BANK67 0x01C67088
15   -
16   -#else /* CONFIG_SOC_DA8XX */
17   -#define DAVINCI_GPIO_BINTEN 0x01E26008
18   -#define DAVINCI_GPIO_BANK01 0x01E26010
19   -#define DAVINCI_GPIO_BANK23 0x01E26038
20   -#define DAVINCI_GPIO_BANK45 0x01E26060
21   -#define DAVINCI_GPIO_BANK67 0x01E26088
22   -#define DAVINCI_GPIO_BANK8 0x01E260B0
23   -#endif /* CONFIG_SOC_DA8XX */
24   -
25   -struct davinci_gpio {
26   - unsigned int dir;
27   - unsigned int out_data;
28   - unsigned int set_data;
29   - unsigned int clr_data;
30   - unsigned int in_data;
31   - unsigned int set_rising;
32   - unsigned int clr_rising;
33   - unsigned int set_falling;
34   - unsigned int clr_falling;
35   - unsigned int intstat;
36   -};
37   -
38   -struct davinci_gpio_bank {
39   - int num_gpio;
40   - unsigned int irq_num;
41   - unsigned int irq_mask;
42   - unsigned long *in_use;
43   - unsigned long base;
44   -};
45   -
46   -#define davinci_gpio_bank01 ((struct davinci_gpio *)DAVINCI_GPIO_BANK01)
47   -#define davinci_gpio_bank23 ((struct davinci_gpio *)DAVINCI_GPIO_BANK23)
48   -#define davinci_gpio_bank45 ((struct davinci_gpio *)DAVINCI_GPIO_BANK45)
49   -#define davinci_gpio_bank67 ((struct davinci_gpio *)DAVINCI_GPIO_BANK67)
50   -#define davinci_gpio_bank8 ((struct davinci_gpio *)DAVINCI_GPIO_BANK8)
51   -
52   -#define gpio_status() gpio_info()
53   -#define GPIO_NAME_SIZE 20
54   -#if defined(CONFIG_SOC_DM644X)
55   -/* GPIO0 to GPIO53, omit the V3.3 volts one */
56   -#define MAX_NUM_GPIOS 70
57   -#elif defined(CONFIG_SOC_DA8XX) && !defined(CONFIG_SOC_DA850)
58   -#define MAX_NUM_GPIOS 128
59   -#else
60   -#define MAX_NUM_GPIOS 144
61   -#endif
62   -#define GPIO_BANK(gp) (davinci_gpio_bank01 + ((gp) >> 5))
63   -#define GPIO_BIT(gp) ((gp) & 0x1F)
64   -
65   -void gpio_info(void);
66   -
67   -#endif
arch/arm/include/asm/arch-davinci/hardware.h
View file @ 3d35761
1   -/*
2   - * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
3   - *
4   - * Based on:
5   - *
6   - * -------------------------------------------------------------------------
7   - *
8   - * linux/include/asm-arm/arch-davinci/hardware.h
9   - *
10   - * Copyright (C) 2006 Texas Instruments.
11   - *
12   - * SPDX-License-Identifier: GPL-2.0+
13   - */
14   -#ifndef __ASM_ARCH_HARDWARE_H
15   -#define __ASM_ARCH_HARDWARE_H
16   -
17   -#include <config.h>
18   -#include <linux/sizes.h>
19   -
20   -#define REG(addr) (*(volatile unsigned int *)(addr))
21   -#define REG_P(addr) ((volatile unsigned int *)(addr))
22   -
23   -typedef volatile unsigned int dv_reg;
24   -typedef volatile unsigned int * dv_reg_p;
25   -
26   -/*
27   - * Base register addresses
28   - *
29   - * NOTE: some of these DM6446-specific addresses DO NOT WORK
30   - * on other DaVinci chips. Double check them before you try
31   - * using the addresses ... or PSC module identifiers, etc.
32   - */
33   -#ifndef CONFIG_SOC_DA8XX
34   -
35   -#define DAVINCI_DMA_3PCC_BASE (0x01c00000)
36   -#define DAVINCI_DMA_3PTC0_BASE (0x01c10000)
37   -#define DAVINCI_DMA_3PTC1_BASE (0x01c10400)
38   -#define DAVINCI_UART0_BASE (0x01c20000)
39   -#define DAVINCI_UART1_BASE (0x01c20400)
40   -#define DAVINCI_TIMER3_BASE (0x01c20800)
41   -#define DAVINCI_I2C_BASE (0x01c21000)
42   -#define DAVINCI_TIMER0_BASE (0x01c21400)
43   -#define DAVINCI_TIMER1_BASE (0x01c21800)
44   -#define DAVINCI_WDOG_BASE (0x01c21c00)
45   -#define DAVINCI_PWM0_BASE (0x01c22000)
46   -#define DAVINCI_PWM1_BASE (0x01c22400)
47   -#define DAVINCI_PWM2_BASE (0x01c22800)
48   -#define DAVINCI_TIMER4_BASE (0x01c23800)
49   -#define DAVINCI_SYSTEM_MODULE_BASE (0x01c40000)
50   -#define DAVINCI_PLL_CNTRL0_BASE (0x01c40800)
51   -#define DAVINCI_PLL_CNTRL1_BASE (0x01c40c00)
52   -#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01c41000)
53   -#define DAVINCI_ARM_INTC_BASE (0x01c48000)
54   -#define DAVINCI_USB_OTG_BASE (0x01c64000)
55   -#define DAVINCI_CFC_ATA_BASE (0x01c66000)
56   -#define DAVINCI_SPI_BASE (0x01c66800)
57   -#define DAVINCI_GPIO_BASE (0x01c67000)
58   -#define DAVINCI_VPSS_REGS_BASE (0x01c70000)
59   -#if !defined(CONFIG_SOC_DM646X)
60   -#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000)
61   -#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000)
62   -#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000)
63   -#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000)
64   -#endif
65   -#define DAVINCI_DDR_BASE (0x80000000)
66   -
67   -#ifdef CONFIG_SOC_DM644X
68   -#define DAVINCI_UART2_BASE 0x01c20800
69   -#define DAVINCI_UHPI_BASE 0x01c67800
70   -#define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01c80000
71   -#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01c81000
72   -#define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01c82000
73   -#define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01c84000
74   -#define DAVINCI_IMCOP_BASE 0x01cc0000
75   -#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e00000
76   -#define DAVINCI_VLYNQ_BASE 0x01e01000
77   -#define DAVINCI_ASP_BASE 0x01e02000
78   -#define DAVINCI_MMC_SD_BASE 0x01e10000
79   -#define DAVINCI_MS_BASE 0x01e20000
80   -#define DAVINCI_VLYNQ_REMOTE_BASE 0x0c000000
81   -
82   -#elif defined(CONFIG_SOC_DM355)
83   -#define DAVINCI_MMC_SD1_BASE 0x01e00000
84   -#define DAVINCI_ASP0_BASE 0x01e02000
85   -#define DAVINCI_ASP1_BASE 0x01e04000
86   -#define DAVINCI_UART2_BASE 0x01e06000
87   -#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e10000
88   -#define DAVINCI_MMC_SD0_BASE 0x01e11000
89   -
90   -#elif defined(CONFIG_SOC_DM365)
91   -#define DAVINCI_MMC_SD1_BASE 0x01d00000
92   -#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01d10000
93   -#define DAVINCI_MMC_SD0_BASE 0x01d11000
94   -#define DAVINCI_DDR_EMIF_CTRL_BASE 0x20000000
95   -#define DAVINCI_SPI0_BASE 0x01c66000
96   -#define DAVINCI_SPI1_BASE 0x01c66800
97   -
98   -#elif defined(CONFIG_SOC_DM646X)
99   -#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x20008000
100   -#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x42000000
101   -#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE 0x44000000
102   -#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x46000000
103   -#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x48000000
104   -
105   -#endif
106   -
107   -#else /* CONFIG_SOC_DA8XX */
108   -
109   -#define DAVINCI_UART0_BASE 0x01c42000
110   -#define DAVINCI_UART1_BASE 0x01d0c000
111   -#define DAVINCI_UART2_BASE 0x01d0d000
112   -#define DAVINCI_I2C0_BASE 0x01c22000
113   -#define DAVINCI_I2C1_BASE 0x01e28000
114   -#define DAVINCI_TIMER0_BASE 0x01c20000
115   -#define DAVINCI_TIMER1_BASE 0x01c21000
116   -#define DAVINCI_WDOG_BASE 0x01c21000
117   -#define DAVINCI_RTC_BASE 0x01c23000
118   -#define DAVINCI_PLL_CNTRL0_BASE 0x01c11000
119   -#define DAVINCI_PLL_CNTRL1_BASE 0x01e1a000
120   -#define DAVINCI_PSC0_BASE 0x01c10000
121   -#define DAVINCI_PSC1_BASE 0x01e27000
122   -#define DAVINCI_SPI0_BASE 0x01c41000
123   -#define DAVINCI_USB_OTG_BASE 0x01e00000
124   -#define DAVINCI_SPI1_BASE (cpu_is_da830() ? \
125   - 0x01e12000 : 0x01f0e000)
126   -#define DAVINCI_GPIO_BASE 0x01e26000
127   -#define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01e23000
128   -#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01e22000
129   -#define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01e20000
130   -#define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01e24000
131   -#define DAVINCI_SYSCFG1_BASE 0x01e2c000
132   -#define DAVINCI_MMC_SD0_BASE 0x01c40000
133   -#define DAVINCI_MMC_SD1_BASE 0x01e1b000
134   -#define DAVINCI_TIMER2_BASE 0x01f0c000
135   -#define DAVINCI_TIMER3_BASE 0x01f0d000
136   -#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x68000000
137   -#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x40000000
138   -#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x60000000
139   -#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x62000000
140   -#define DAVINCI_ASYNC_EMIF_DATA_CE4_BASE 0x64000000
141   -#define DAVINCI_ASYNC_EMIF_DATA_CE5_BASE 0x66000000
142   -#define DAVINCI_DDR_EMIF_CTRL_BASE 0xb0000000
143   -#define DAVINCI_DDR_EMIF_DATA_BASE 0xc0000000
144   -#define DAVINCI_INTC_BASE 0xfffee000
145   -#define DAVINCI_BOOTCFG_BASE 0x01c14000
146   -#define DAVINCI_LCD_CNTL_BASE 0x01e13000
147   -#define DAVINCI_L3CBARAM_BASE 0x80000000
148   -#define JTAG_ID_REG (DAVINCI_BOOTCFG_BASE + 0x18)
149   -#define CHIP_REV_ID_REG (DAVINCI_BOOTCFG_BASE + 0x24)
150   -#define HOST1CFG (DAVINCI_BOOTCFG_BASE + 0x44)
151   -#define PSC0_MDCTL (DAVINCI_PSC0_BASE + 0xa00)
152   -
153   -#define GPIO_BANK0_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x10)
154   -#define GPIO_BANK0_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x14)
155   -#define GPIO_BANK0_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x18)
156   -#define GPIO_BANK0_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x1c)
157   -#define GPIO_BANK2_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x38)
158   -#define GPIO_BANK2_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x3c)
159   -#define GPIO_BANK2_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x40)
160   -#define GPIO_BANK2_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x44)
161   -#define GPIO_BANK6_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x88)
162   -#define GPIO_BANK6_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x8c)
163   -#define GPIO_BANK6_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x90)
164   -#define GPIO_BANK6_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x94)
165   -#endif /* CONFIG_SOC_DA8XX */
166   -
167   -/* Power and Sleep Controller (PSC) Domains */
168   -#define DAVINCI_GPSC_ARMDOMAIN 0
169   -#define DAVINCI_GPSC_DSPDOMAIN 1
170   -
171   -#ifndef CONFIG_SOC_DA8XX
172   -
173   -#define DAVINCI_LPSC_VPSSMSTR 0
174   -#define DAVINCI_LPSC_VPSSSLV 1
175   -#define DAVINCI_LPSC_TPCC 2
176   -#define DAVINCI_LPSC_TPTC0 3
177   -#define DAVINCI_LPSC_TPTC1 4
178   -#define DAVINCI_LPSC_EMAC 5
179   -#define DAVINCI_LPSC_EMAC_WRAPPER 6
180   -#define DAVINCI_LPSC_MDIO 7
181   -#define DAVINCI_LPSC_IEEE1394 8
182   -#define DAVINCI_LPSC_USB 9
183   -#define DAVINCI_LPSC_ATA 10
184   -#define DAVINCI_LPSC_VLYNQ 11
185   -#define DAVINCI_LPSC_UHPI 12
186   -#define DAVINCI_LPSC_DDR_EMIF 13
187   -#define DAVINCI_LPSC_AEMIF 14
188   -#define DAVINCI_LPSC_MMC_SD 15
189   -#define DAVINCI_LPSC_MEMSTICK 16
190   -#define DAVINCI_LPSC_McBSP 17
191   -#define DAVINCI_LPSC_I2C 18
192   -#define DAVINCI_LPSC_UART0 19
193   -#define DAVINCI_LPSC_UART1 20
194   -#define DAVINCI_LPSC_UART2 21
195   -#define DAVINCI_LPSC_SPI 22
196   -#define DAVINCI_LPSC_PWM0 23
197   -#define DAVINCI_LPSC_PWM1 24
198   -#define DAVINCI_LPSC_PWM2 25
199   -#define DAVINCI_LPSC_GPIO 26
200   -#define DAVINCI_LPSC_TIMER0 27
201   -#define DAVINCI_LPSC_TIMER1 28
202   -#define DAVINCI_LPSC_TIMER2 29
203   -#define DAVINCI_LPSC_SYSTEM_SUBSYS 30
204   -#define DAVINCI_LPSC_ARM 31
205   -#define DAVINCI_LPSC_SCR2 32
206   -#define DAVINCI_LPSC_SCR3 33
207   -#define DAVINCI_LPSC_SCR4 34
208   -#define DAVINCI_LPSC_CROSSBAR 35
209   -#define DAVINCI_LPSC_CFG27 36
210   -#define DAVINCI_LPSC_CFG3 37
211   -#define DAVINCI_LPSC_CFG5 38
212   -#define DAVINCI_LPSC_GEM 39
213   -#define DAVINCI_LPSC_IMCOP 40
214   -#define DAVINCI_LPSC_VPSSMASTER 47
215   -#define DAVINCI_LPSC_MJCP 50
216   -#define DAVINCI_LPSC_HDVICP 51
217   -
218   -#define DAVINCI_DM646X_LPSC_EMAC 14
219   -#define DAVINCI_DM646X_LPSC_UART0 26
220   -#define DAVINCI_DM646X_LPSC_I2C 31
221   -#define DAVINCI_DM646X_LPSC_TIMER0 34
222   -
223   -#else /* CONFIG_SOC_DA8XX */
224   -
225   -#define DAVINCI_LPSC_TPCC 0
226   -#define DAVINCI_LPSC_TPTC0 1
227   -#define DAVINCI_LPSC_TPTC1 2
228   -#define DAVINCI_LPSC_AEMIF 3
229   -#define DAVINCI_LPSC_SPI0 4
230   -#define DAVINCI_LPSC_MMC_SD 5
231   -#define DAVINCI_LPSC_AINTC 6
232   -#define DAVINCI_LPSC_ARM_RAM_ROM 7
233   -#define DAVINCI_LPSC_SECCTL_KEYMGR 8
234   -#define DAVINCI_LPSC_UART0 9
235   -#define DAVINCI_LPSC_SCR0 10
236   -#define DAVINCI_LPSC_SCR1 11
237   -#define DAVINCI_LPSC_SCR2 12
238   -#define DAVINCI_LPSC_DMAX 13
239   -#define DAVINCI_LPSC_ARM 14
240   -#define DAVINCI_LPSC_GEM 15
241   -
242   -/* for LPSCs in PSC1, offset from 32 for differentiation */
243   -#define DAVINCI_LPSC_PSC1_BASE 32
244   -#define DAVINCI_LPSC_USB20 (DAVINCI_LPSC_PSC1_BASE + 1)
245   -#define DAVINCI_LPSC_USB11 (DAVINCI_LPSC_PSC1_BASE + 2)
246   -#define DAVINCI_LPSC_GPIO (DAVINCI_LPSC_PSC1_BASE + 3)
247   -#define DAVINCI_LPSC_UHPI (DAVINCI_LPSC_PSC1_BASE + 4)
248   -#define DAVINCI_LPSC_EMAC (DAVINCI_LPSC_PSC1_BASE + 5)
249   -#define DAVINCI_LPSC_DDR_EMIF (DAVINCI_LPSC_PSC1_BASE + 6)
250   -#define DAVINCI_LPSC_McASP0 (DAVINCI_LPSC_PSC1_BASE + 7)
251   -#define DAVINCI_LPSC_SPI1 (DAVINCI_LPSC_PSC1_BASE + 10)
252   -#define DAVINCI_LPSC_I2C1 (DAVINCI_LPSC_PSC1_BASE + 11)
253   -#define DAVINCI_LPSC_UART1 (DAVINCI_LPSC_PSC1_BASE + 12)
254   -#define DAVINCI_LPSC_UART2 (DAVINCI_LPSC_PSC1_BASE + 13)
255   -#define DAVINCI_LPSC_LCDC (DAVINCI_LPSC_PSC1_BASE + 16)
256   -#define DAVINCI_LPSC_ePWM (DAVINCI_LPSC_PSC1_BASE + 17)
257   -#define DAVINCI_LPSC_MMCSD1 (DAVINCI_LPSC_PSC1_BASE + 18)
258   -#define DAVINCI_LPSC_eCAP (DAVINCI_LPSC_PSC1_BASE + 20)
259   -#define DAVINCI_LPSC_L3_CBA_RAM (DAVINCI_LPSC_PSC1_BASE + 31)
260   -
261   -/* DA830-specific peripherals */
262   -#define DAVINCI_LPSC_McASP1 (DAVINCI_LPSC_PSC1_BASE + 8)
263   -#define DAVINCI_LPSC_McASP2 (DAVINCI_LPSC_PSC1_BASE + 9)
264   -#define DAVINCI_LPSC_eQEP (DAVINCI_LPSC_PSC1_BASE + 21)
265   -#define DAVINCI_LPSC_SCR8 (DAVINCI_LPSC_PSC1_BASE + 24)
266   -#define DAVINCI_LPSC_SCR7 (DAVINCI_LPSC_PSC1_BASE + 25)
267   -#define DAVINCI_LPSC_SCR12 (DAVINCI_LPSC_PSC1_BASE + 26)
268   -
269   -/* DA850-specific peripherals */
270   -#define DAVINCI_LPSC_TPCC1 (DAVINCI_LPSC_PSC1_BASE + 0)
271   -#define DAVINCI_LPSC_SATA (DAVINCI_LPSC_PSC1_BASE + 8)
272   -#define DAVINCI_LPSC_VPIF (DAVINCI_LPSC_PSC1_BASE + 9)
273   -#define DAVINCI_LPSC_McBSP0 (DAVINCI_LPSC_PSC1_BASE + 14)
274   -#define DAVINCI_LPSC_McBSP1 (DAVINCI_LPSC_PSC1_BASE + 15)
275   -#define DAVINCI_LPSC_MMC_SD1 (DAVINCI_LPSC_PSC1_BASE + 18)
276   -#define DAVINCI_LPSC_uPP (DAVINCI_LPSC_PSC1_BASE + 19)
277   -#define DAVINCI_LPSC_TPTC2 (DAVINCI_LPSC_PSC1_BASE + 21)
278   -#define DAVINCI_LPSC_SCR_F0 (DAVINCI_LPSC_PSC1_BASE + 24)
279   -#define DAVINCI_LPSC_SCR_F1 (DAVINCI_LPSC_PSC1_BASE + 25)
280   -#define DAVINCI_LPSC_SCR_F2 (DAVINCI_LPSC_PSC1_BASE + 26)
281   -#define DAVINCI_LPSC_SCR_F6 (DAVINCI_LPSC_PSC1_BASE + 27)
282   -#define DAVINCI_LPSC_SCR_F7 (DAVINCI_LPSC_PSC1_BASE + 28)
283   -#define DAVINCI_LPSC_SCR_F8 (DAVINCI_LPSC_PSC1_BASE + 29)
284   -#define DAVINCI_LPSC_BR_F7 (DAVINCI_LPSC_PSC1_BASE + 30)
285   -
286   -#endif /* CONFIG_SOC_DA8XX */
287   -
288   -void lpsc_on(unsigned int id);
289   -void lpsc_syncreset(unsigned int id);
290   -void lpsc_disable(unsigned int id);
291   -void dsp_on(void);
292   -
293   -void davinci_enable_uart0(void);
294   -void davinci_enable_emac(void);
295   -void davinci_enable_i2c(void);
296   -void davinci_errata_workarounds(void);
297   -
298   -#ifndef CONFIG_SOC_DA8XX
299   -
300   -/* Some PSC defines */
301   -#define PSC_CHP_SHRTSW (0x01c40038)
302   -#define PSC_GBLCTL (0x01c41010)
303   -#define PSC_EPCPR (0x01c41070)
304   -#define PSC_EPCCR (0x01c41078)
305   -#define PSC_PTCMD (0x01c41120)
306   -#define PSC_PTSTAT (0x01c41128)
307   -#define PSC_PDSTAT (0x01c41200)
308   -#define PSC_PDSTAT1 (0x01c41204)
309   -#define PSC_PDCTL (0x01c41300)
310   -#define PSC_PDCTL1 (0x01c41304)
311   -
312   -#define PSC_MDCTL_BASE (0x01c41a00)
313   -#define PSC_MDSTAT_BASE (0x01c41800)
314   -
315   -#define VDD3P3V_PWDN (0x01c40048)
316   -#define UART0_PWREMU_MGMT (0x01c20030)
317   -
318   -#define PSC_SILVER_BULLET (0x01c41a20)
319   -
320   -#else /* CONFIG_SOC_DA8XX */
321   -
322   -#define PSC_ENABLE 0x3
323   -#define PSC_DISABLE 0x2
324   -#define PSC_SYNCRESET 0x1
325   -#define PSC_SWRSTDISABLE 0x0
326   -
327   -#define PSC_PSC0_MODULE_ID_CNT 16
328   -#define PSC_PSC1_MODULE_ID_CNT 32
329   -
330   -#define UART0_PWREMU_MGMT (0x01c42030)
331   -
332   -struct davinci_psc_regs {
333   - dv_reg revid;
334   - dv_reg rsvd0[71];
335   - dv_reg ptcmd;
336   - dv_reg rsvd1;
337   - dv_reg ptstat;
338   - dv_reg rsvd2[437];
339   - union {
340   - struct {
341   - dv_reg mdstat[PSC_PSC0_MODULE_ID_CNT];
342   - dv_reg rsvd3[112];
343   - dv_reg mdctl[PSC_PSC0_MODULE_ID_CNT];
344   - } psc0;
345   - struct {
346   - dv_reg mdstat[PSC_PSC1_MODULE_ID_CNT];
347   - dv_reg rsvd3[96];
348   - dv_reg mdctl[PSC_PSC1_MODULE_ID_CNT];
349   - } psc1;
350   - };
351   -};
352   -
353   -#define davinci_psc0_regs ((struct davinci_psc_regs *)DAVINCI_PSC0_BASE)
354   -#define davinci_psc1_regs ((struct davinci_psc_regs *)DAVINCI_PSC1_BASE)
355   -
356   -#endif /* CONFIG_SOC_DA8XX */
357   -
358   -#define PSC_MDSTAT_STATE 0x3f
359   -#define PSC_MDCTL_NEXT 0x07
360   -
361   -#ifndef CONFIG_SOC_DA8XX
362   -
363   -/* Miscellania... */
364   -#define VBPR (0x20000020)
365   -
366   -/* NOTE: system control modules are *highly* chip-specific, both
367   - * as to register content (e.g. for muxing) and which registers exist.
368   - */
369   -#define PINMUX0 0x01c40000
370   -#define PINMUX1 0x01c40004
371   -#define PINMUX2 0x01c40008
372   -#define PINMUX3 0x01c4000c
373   -#define PINMUX4 0x01c40010
374   -
375   -struct davinci_uart_ctrl_regs {
376   - dv_reg revid1;
377   - dv_reg res;
378   - dv_reg pwremu_mgmt;
379   - dv_reg mdr;
380   -};
381   -
382   -#define DAVINCI_UART_CTRL_BASE 0x28
383   -
384   -/* UART PWREMU_MGMT definitions */
385   -#define DAVINCI_UART_PWREMU_MGMT_FREE (1 << 0)
386   -#define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13)
387   -#define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14)
388   -
389   -#else /* CONFIG_SOC_DA8XX */
390   -
391   -struct davinci_pllc_regs {
392   - dv_reg revid;
393   - dv_reg rsvd1[56];
394   - dv_reg rstype;
395   - dv_reg rsvd2[6];
396   - dv_reg pllctl;
397   - dv_reg ocsel;
398   - dv_reg rsvd3[2];
399   - dv_reg pllm;
400   - dv_reg prediv;
401   - dv_reg plldiv1;
402   - dv_reg plldiv2;
403   - dv_reg plldiv3;
404   - dv_reg oscdiv;
405   - dv_reg postdiv;
406   - dv_reg rsvd4[3];
407   - dv_reg pllcmd;
408   - dv_reg pllstat;
409   - dv_reg alnctl;
410   - dv_reg dchange;
411   - dv_reg cken;
412   - dv_reg ckstat;
413   - dv_reg systat;
414   - dv_reg rsvd5[3];
415   - dv_reg plldiv4;
416   - dv_reg plldiv5;
417   - dv_reg plldiv6;
418   - dv_reg plldiv7;
419   - dv_reg rsvd6[32];
420   - dv_reg emucnt0;
421   - dv_reg emucnt1;
422   -};
423   -
424   -#define davinci_pllc0_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE)
425   -#define davinci_pllc1_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL1_BASE)
426   -#define DAVINCI_PLLC_DIV_MASK 0x1f
427   -
428   -/*
429   - * A clock ID is a 32-bit number where bit 16 represents the PLL controller
430   - * (clear is PLLC0, set is PLLC1) and the low 16 bits represent the divisor,
431   - * counting from 1. Clock IDs may be passed to clk_get().
432   - */
433   -
434   -/* flags to select PLL controller */
435   -#define DAVINCI_PLLC0_FLAG (0)
436   -#define DAVINCI_PLLC1_FLAG (1 << 16)
437   -
438   -enum davinci_clk_ids {
439   - /*
440   - * Clock IDs for PLL outputs. Each may be switched on/off
441   - * independently, and each may map to one or more peripherals.
442   - */
443   - DAVINCI_PLL0_SYSCLK2 = DAVINCI_PLLC0_FLAG | 2,
444   - DAVINCI_PLL0_SYSCLK4 = DAVINCI_PLLC0_FLAG | 4,
445   - DAVINCI_PLL0_SYSCLK6 = DAVINCI_PLLC0_FLAG | 6,
446   - DAVINCI_PLL1_SYSCLK1 = DAVINCI_PLLC1_FLAG | 1,
447   - DAVINCI_PLL1_SYSCLK2 = DAVINCI_PLLC1_FLAG | 2,
448   -
449   - /* map peripherals to clock IDs */
450   - DAVINCI_ARM_CLKID = DAVINCI_PLL0_SYSCLK6,
451   - DAVINCI_DDR_CLKID = DAVINCI_PLL1_SYSCLK1,
452   - DAVINCI_MDIO_CLKID = DAVINCI_PLL0_SYSCLK4,
453   - DAVINCI_MMC_CLKID = DAVINCI_PLL0_SYSCLK2,
454   - DAVINCI_SPI0_CLKID = DAVINCI_PLL0_SYSCLK2,
455   - DAVINCI_MMCSD_CLKID = DAVINCI_PLL0_SYSCLK2,
456   -
457   - /* special clock ID - output of PLL multiplier */
458   - DAVINCI_PLLM_CLKID = 0x0FF,
459   -
460   - /* special clock ID - output of PLL post divisor */
461   - DAVINCI_PLLC_CLKID = 0x100,
462   -
463   - /* special clock ID - PLL bypass */
464   - DAVINCI_AUXCLK_CLKID = 0x101,
465   -};
466   -
467   -#define DAVINCI_UART2_CLKID (cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \
468   - : get_async3_src())
469   -
470   -#define DAVINCI_SPI1_CLKID (cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \
471   - : get_async3_src())
472   -
473   -int clk_get(enum davinci_clk_ids id);
474   -
475   -/* Boot config */
476   -struct davinci_syscfg_regs {
477   - dv_reg revid;
478   - dv_reg rsvd[13];
479   - dv_reg kick0;
480   - dv_reg kick1;
481   - dv_reg rsvd1[52];
482   - dv_reg mstpri[3];
483   - dv_reg rsvd2;
484   - dv_reg pinmux[20];
485   - dv_reg suspsrc;
486   - dv_reg chipsig;
487   - dv_reg chipsig_clr;
488   - dv_reg cfgchip0;
489   - dv_reg cfgchip1;
490   - dv_reg cfgchip2;
491   - dv_reg cfgchip3;
492   - dv_reg cfgchip4;
493   -};
494   -
495   -#define davinci_syscfg_regs \
496   - ((struct davinci_syscfg_regs *)DAVINCI_BOOTCFG_BASE)
497   -
498   -#define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
499   -
500   -/* Emulation suspend bits */
501   -#define DAVINCI_SYSCFG_SUSPSRC_EMAC (1 << 5)
502   -#define DAVINCI_SYSCFG_SUSPSRC_I2C (1 << 16)
503   -#define DAVINCI_SYSCFG_SUSPSRC_SPI0 (1 << 21)
504   -#define DAVINCI_SYSCFG_SUSPSRC_SPI1 (1 << 22)
505   -#define DAVINCI_SYSCFG_SUSPSRC_UART0 (1 << 18)
506   -#define DAVINCI_SYSCFG_SUSPSRC_UART2 (1 << 20)
507   -#define DAVINCI_SYSCFG_SUSPSRC_TIMER0 (1 << 27)
508   -
509   -struct davinci_syscfg1_regs {
510   - dv_reg vtpio_ctl;
511   - dv_reg ddr_slew;
512   - dv_reg deepsleep;
513   - dv_reg pupd_ena;
514   - dv_reg pupd_sel;
515   - dv_reg rxactive;
516   - dv_reg pwrdwn;
517   -};
518   -
519   -#define davinci_syscfg1_regs \
520   - ((struct davinci_syscfg1_regs *)DAVINCI_SYSCFG1_BASE)
521   -
522   -#define DDR_SLEW_CMOSEN_BIT 4
523   -#define DDR_SLEW_DDR_PDENA_BIT 5
524   -
525   -#define VTP_POWERDWN (1 << 6)
526   -#define VTP_LOCK (1 << 7)
527   -#define VTP_CLKRZ (1 << 13)
528   -#define VTP_READY (1 << 15)
529   -#define VTP_IOPWRDWN (1 << 14)
530   -
531   -#define DV_SYSCFG_KICK0_UNLOCK 0x83e70b13
532   -#define DV_SYSCFG_KICK1_UNLOCK 0x95a4f1e0
533   -
534   -/* Interrupt controller */
535   -struct davinci_aintc_regs {
536   - dv_reg revid;
537   - dv_reg cr;
538   - dv_reg dummy0[2];
539   - dv_reg ger;
540   - dv_reg dummy1[219];
541   - dv_reg ecr1;
542   - dv_reg ecr2;
543   - dv_reg ecr3;
544   - dv_reg dummy2[1117];
545   - dv_reg hier;
546   -};
547   -
548   -#define davinci_aintc_regs ((struct davinci_aintc_regs *)DAVINCI_INTC_BASE)
549   -
550   -struct davinci_uart_ctrl_regs {
551   - dv_reg revid1;
552   - dv_reg revid2;
553   - dv_reg pwremu_mgmt;
554   - dv_reg mdr;
555   -};
556   -
557   -#define DAVINCI_UART_CTRL_BASE 0x28
558   -#define DAVINCI_UART0_CTRL_ADDR (DAVINCI_UART0_BASE + DAVINCI_UART_CTRL_BASE)
559   -#define DAVINCI_UART1_CTRL_ADDR (DAVINCI_UART1_BASE + DAVINCI_UART_CTRL_BASE)
560   -#define DAVINCI_UART2_CTRL_ADDR (DAVINCI_UART2_BASE + DAVINCI_UART_CTRL_BASE)
561   -
562   -#define davinci_uart0_ctrl_regs \
563   - ((struct davinci_uart_ctrl_regs *)DAVINCI_UART0_CTRL_ADDR)
564   -#define davinci_uart1_ctrl_regs \
565   - ((struct davinci_uart_ctrl_regs *)DAVINCI_UART1_CTRL_ADDR)
566   -#define davinci_uart2_ctrl_regs \
567   - ((struct davinci_uart_ctrl_regs *)DAVINCI_UART2_CTRL_ADDR)
568   -
569   -/* UART PWREMU_MGMT definitions */
570   -#define DAVINCI_UART_PWREMU_MGMT_FREE (1 << 0)
571   -#define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13)
572   -#define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14)
573   -
574   -static inline int cpu_is_da830(void)
575   -{
576   - unsigned int jtag_id = REG(JTAG_ID_REG);
577   - unsigned short part_no = (jtag_id >> 12) & 0xffff;
578   -
579   - return ((part_no == 0xb7df) ? 1 : 0);
580   -}
581   -static inline int cpu_is_da850(void)
582   -{
583   - unsigned int jtag_id = REG(JTAG_ID_REG);
584   - unsigned short part_no = (jtag_id >> 12) & 0xffff;
585   -
586   - return ((part_no == 0xb7d1) ? 1 : 0);
587   -}
588   -
589   -static inline enum davinci_clk_ids get_async3_src(void)
590   -{
591   - return (REG(&davinci_syscfg_regs->cfgchip3) & 0x10) ?
592   - DAVINCI_PLL1_SYSCLK2 : DAVINCI_PLL0_SYSCLK2;
593   -}
594   -
595   -#endif /* CONFIG_SOC_DA8XX */
596   -
597   -#if defined(CONFIG_SOC_DM365)
598   -#include <asm/arch/aintc_defs.h>
599   -#include <asm/arch/ddr2_defs.h>
600   -#include <asm/arch/gpio.h>
601   -#include <asm/arch/pll_defs.h>
602   -#include <asm/arch/psc_defs.h>
603   -#include <asm/arch/syscfg_defs.h>
604   -#include <asm/arch/timer_defs.h>
605   -
606   -#define TMPBUF 0x00017ff8
607   -#define TMPSTATUS 0x00017ff0
608   -#define DV_TMPBUF_VAL 0x591b3ed7
609   -#define FLAG_PORRST 0x00000001
610   -#define FLAG_WDTRST 0x00000002
611   -#define FLAG_FLGON 0x00000004
612   -#define FLAG_FLGOFF 0x00000010
613   -
614   -#endif
615   -
616   -#endif /* __ASM_ARCH_HARDWARE_H */
arch/arm/include/asm/arch-davinci/i2c_defs.h
View file @ 3d35761
1   -/*
2   - * (C) Copyright 2004-2014
3   - * Texas Instruments, <www.ti.com>
4   - *
5   - * Some changes copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6   - *
7   - * SPDX-License-Identifier: GPL-2.0+
8   - */
9   -#ifndef _I2C_DEFS_H_
10   -#define _I2C_DEFS_H_
11   -
12   -#ifndef CONFIG_SOC_DA8XX
13   -#define I2C_BASE 0x01c21000
14   -#else
15   -#define I2C_BASE 0x01c22000
16   -#endif
17   -
18   -#endif
arch/arm/include/asm/arch-davinci/pinmux_defs.h
View file @ 3d35761
1   -/*
2   - * Pinmux configurations for the DAxxx SoCs
3   - *
4   - * Copyright (C) 2011 OMICRON electronics GmbH
5   - *
6   - * SPDX-License-Identifier: GPL-2.0+
7   - */
8   -
9   -#ifndef __ASM_ARCH_PINMUX_DEFS_H
10   -#define __ASM_ARCH_PINMUX_DEFS_H
11   -
12   -#include <asm/arch/davinci_misc.h>
13   -#include <config.h>
14   -
15   -/* SPI0 pin muxer settings */
16   -extern const struct pinmux_config spi0_pins_base[3];
17   -extern const struct pinmux_config spi0_pins_scs0[1];
18   -extern const struct pinmux_config spi0_pins_ena[1];
19   -
20   -/* SPI1 pin muxer settings */
21   -extern const struct pinmux_config spi1_pins_base[3];
22   -extern const struct pinmux_config spi1_pins_scs0[1];
23   -
24   -/* UART pin muxer settings */
25   -extern const struct pinmux_config uart0_pins_txrx[2];
26   -extern const struct pinmux_config uart0_pins_rtscts[2];
27   -extern const struct pinmux_config uart1_pins_txrx[2];
28   -extern const struct pinmux_config uart2_pins_txrx[2];
29   -extern const struct pinmux_config uart2_pins_rtscts[2];
30   -
31   -/* EMAC pin muxer settings*/
32   -extern const struct pinmux_config emac_pins_rmii[8];
33   -extern const struct pinmux_config emac_pins_rmii_clk_source[1];
34   -extern const struct pinmux_config emac_pins_mii[15];
35   -extern const struct pinmux_config emac_pins_mdio[2];
36   -
37   -/* I2C pin muxer settings */
38   -extern const struct pinmux_config i2c0_pins[2];
39   -extern const struct pinmux_config i2c1_pins[2];
40   -
41   -/* EMIFA pin muxer settings */
42   -extern const struct pinmux_config emifa_pins[40];
43   -extern const struct pinmux_config emifa_pins_cs0[1];
44   -extern const struct pinmux_config emifa_pins_cs2[1];
45   -extern const struct pinmux_config emifa_pins_cs3[1];
46   -extern const struct pinmux_config emifa_pins_cs4[1];
47   -extern const struct pinmux_config emifa_pins_nand[12];
48   -extern const struct pinmux_config emifa_pins_nor[43];
49   -
50   -/* USB pin mux setting */
51   -extern const struct pinmux_config usb_pins[1];
52   -
53   -/* MMC pin muxer settings */
54   -extern const struct pinmux_config mmc0_pins_8bit[10];
55   -extern const struct pinmux_config mmc0_pins[6];
56   -
57   -#endif
arch/arm/include/asm/arch-davinci/pll_defs.h
View file @ 3d35761
1   -/*
2   - * Copyright (C) 2011
3   - * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -#ifndef _DV_PLL_DEFS_H_
8   -#define _DV_PLL_DEFS_H_
9   -
10   -struct dv_pll_regs {
11   - unsigned int pid; /* 0x00 */
12   - unsigned char rsvd0[224]; /* 0x04 */
13   - unsigned int rstype; /* 0xe4 */
14   - unsigned char rsvd1[24]; /* 0xe8 */
15   - unsigned int pllctl; /* 0x100 */
16   - unsigned char rsvd2[4]; /* 0x104 */
17   - unsigned int secctl; /* 0x108 */
18   - unsigned int rv; /* 0x10c */
19   - unsigned int pllm; /* 0x110 */
20   - unsigned int prediv; /* 0x114 */
21   - unsigned int plldiv1; /* 0x118 */
22   - unsigned int plldiv2; /* 0x11c */
23   - unsigned int plldiv3; /* 0x120 */
24   - unsigned int oscdiv1; /* 0x124 */
25   - unsigned int postdiv; /* 0x128 */
26   - unsigned int bpdiv; /* 0x12c */
27   - unsigned char rsvd5[8]; /* 0x130 */
28   - unsigned int pllcmd; /* 0x138 */
29   - unsigned int pllstat; /* 0x13c */
30   - unsigned int alnctl; /* 0x140 */
31   - unsigned int dchange; /* 0x144 */
32   - unsigned int cken; /* 0x148 */
33   - unsigned int ckstat; /* 0x14c */
34   - unsigned int systat; /* 0x150 */
35   - unsigned char rsvd6[12]; /* 0x154 */
36   - unsigned int plldiv4; /* 0x160 */
37   - unsigned int plldiv5; /* 0x164 */
38   - unsigned int plldiv6; /* 0x168 */
39   - unsigned int plldiv7; /* 0x16C */
40   - unsigned int plldiv8; /* 0x170 */
41   - unsigned int plldiv9; /* 0x174 */
42   -};
43   -
44   -#define PLL_MASTER_LOCK (1 << 4)
45   -
46   -#define PLLCTL_CLOCK_MODE_SHIFT 8
47   -#define PLLCTL_PLLEN (1 << 0)
48   -#define PLLCTL_PLLPWRDN (1 << 1)
49   -#define PLLCTL_PLLRST (1 << 3)
50   -#define PLLCTL_PLLDIS (1 << 4)
51   -#define PLLCTL_PLLENSRC (1 << 5)
52   -#define PLLCTL_RES_9 (1 << 8)
53   -#define PLLCTL_EXTCLKSRC (1 << 9)
54   -
55   -#define PLL_DIVEN (1 << 15)
56   -#define PLL_POSTDEN PLL_DIVEN
57   -
58   -#define PLL_SCSCFG3_DIV45PENA (1 << 2)
59   -#define PLL_SCSCFG3_EMA_CLKSRC (1 << 1)
60   -
61   -#define PLL_RSTYPE_POR (1 << 0)
62   -#define PLL_RSTYPE_XWRST (1 << 1)
63   -
64   -#define PLLSECCTL_TINITZ (1 << 16)
65   -#define PLLSECCTL_TENABLE (1 << 17)
66   -#define PLLSECCTL_TENABLEDIV (1 << 18)
67   -#define PLLSECCTL_STOPMODE (1 << 22)
68   -
69   -#define PLLCMD_GOSET (1 << 0)
70   -#define PLLCMD_GOSTAT (1 << 0)
71   -
72   -#define PLL0_LOCK 0x07000000
73   -#define PLL1_LOCK 0x07000000
74   -
75   -#define dv_pll0_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL0_BASE)
76   -#define dv_pll1_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL1_BASE)
77   -
78   -#define ARM_PLLDIV (offsetof(struct dv_pll_regs, plldiv2))
79   -#define DDR_PLLDIV (offsetof(struct dv_pll_regs, plldiv7))
80   -#define SPI_PLLDIV (offsetof(struct dv_pll_regs, plldiv4))
81   -
82   -unsigned int davinci_clk_get(unsigned int div);
83   -#endif /* _DV_PLL_DEFS_H_ */
arch/arm/include/asm/arch-davinci/psc_defs.h
View file @ 3d35761
1   -/*
2   - * Copyright (C) 2011
3   - * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -#ifndef _DV_PSC_DEFS_H_
8   -#define _DV_PSC_DEFS_H_
9   -
10   -/*
11   - * Power/Sleep Ctrl Register structure
12   - * See sprufb3.pdf, Chapter 7
13   - */
14   -struct dv_psc_regs {
15   - unsigned int pid; /* 0x000 */
16   - unsigned char rsvd0[16]; /* 0x004 */
17   - unsigned char rsvd1[4]; /* 0x014 */
18   - unsigned int inteval; /* 0x018 */
19   - unsigned char rsvd2[36]; /* 0x01C */
20   - unsigned int merrpr0; /* 0x040 */
21   - unsigned int merrpr1; /* 0x044 */
22   - unsigned char rsvd3[8]; /* 0x048 */
23   - unsigned int merrcr0; /* 0x050 */
24   - unsigned int merrcr1; /* 0x054 */
25   - unsigned char rsvd4[8]; /* 0x058 */
26   - unsigned int perrpr; /* 0x060 */
27   - unsigned char rsvd5[4]; /* 0x064 */
28   - unsigned int perrcr; /* 0x068 */
29   - unsigned char rsvd6[4]; /* 0x06C */
30   - unsigned int epcpr; /* 0x070 */
31   - unsigned char rsvd7[4]; /* 0x074 */
32   - unsigned int epccr; /* 0x078 */
33   - unsigned char rsvd8[144]; /* 0x07C */
34   - unsigned char rsvd9[20]; /* 0x10C */
35   - unsigned int ptcmd; /* 0x120 */
36   - unsigned char rsvd10[4]; /* 0x124 */
37   - unsigned int ptstat; /* 0x128 */
38   - unsigned char rsvd11[212]; /* 0x12C */
39   - unsigned int pdstat0; /* 0x200 */
40   - unsigned int pdstat1; /* 0x204 */
41   - unsigned char rsvd12[248]; /* 0x208 */
42   - unsigned int pdctl0; /* 0x300 */
43   - unsigned int pdctl1; /* 0x304 */
44   - unsigned char rsvd13[536]; /* 0x308 */
45   - unsigned int mckout0; /* 0x520 */
46   - unsigned int mckout1; /* 0x524 */
47   - unsigned char rsvd14[728]; /* 0x528 */
48   - unsigned int mdstat[52]; /* 0x800 */
49   - unsigned char rsvd15[304]; /* 0x8D0 */
50   - unsigned int mdctl[52]; /* 0xA00 */
51   -};
52   -
53   -/* PSC constants */
54   -#define EMURSTIE_MASK (0x00000200)
55   -
56   -#define PD0 (0)
57   -
58   -#define PSC_ENABLE (0x3)
59   -#define PSC_DISABLE (0x2)
60   -#define PSC_SYNCRESET (0x1)
61   -#define PSC_SWRSTDISABLE (0x0)
62   -
63   -#define PSC_GOSTAT (1 << 0)
64   -#define PSC_MD_STATE_MSK (0x1f)
65   -
66   -#define PSC_CMD_GO (1 << 0)
67   -
68   -#define dv_psc_regs ((struct dv_psc_regs *)DAVINCI_PWR_SLEEP_CNTRL_BASE)
69   -
70   -#endif /* _DV_PSC_DEFS_H_ */
arch/arm/include/asm/arch-davinci/sdmmc_defs.h
View file @ 3d35761
1   -/*
2   - * Davinci MMC Controller Defines - Based on Linux davinci_mmc.c
3   - *
4   - * Copyright (C) 2010 Texas Instruments Incorporated
5   - *
6   - * SPDX-License-Identifier: GPL-2.0+
7   - */
8   -
9   -#ifndef _SDMMC_DEFS_H_
10   -#define _SDMMC_DEFS_H_
11   -
12   -#include <asm/arch/hardware.h>
13   -
14   -/* MMC Control Reg fields */
15   -#define MMCCTL_DATRST (1 << 0)
16   -#define MMCCTL_CMDRST (1 << 1)
17   -#define MMCCTL_WIDTH_4_BIT (1 << 2)
18   -#define MMCCTL_DATEG_DISABLED (0 << 6)
19   -#define MMCCTL_DATEG_RISING (1 << 6)
20   -#define MMCCTL_DATEG_FALLING (2 << 6)
21   -#define MMCCTL_DATEG_BOTH (3 << 6)
22   -#define MMCCTL_PERMDR_LE (0 << 9)
23   -#define MMCCTL_PERMDR_BE (1 << 9)
24   -#define MMCCTL_PERMDX_LE (0 << 10)
25   -#define MMCCTL_PERMDX_BE (1 << 10)
26   -
27   -/* MMC Clock Control Reg fields */
28   -#define MMCCLK_CLKEN (1 << 8)
29   -#define MMCCLK_CLKRT_MASK (0xFF << 0)
30   -
31   -/* MMC Status Reg0 fields */
32   -#define MMCST0_DATDNE (1 << 0)
33   -#define MMCST0_BSYDNE (1 << 1)
34   -#define MMCST0_RSPDNE (1 << 2)
35   -#define MMCST0_TOUTRD (1 << 3)
36   -#define MMCST0_TOUTRS (1 << 4)
37   -#define MMCST0_CRCWR (1 << 5)
38   -#define MMCST0_CRCRD (1 << 6)
39   -#define MMCST0_CRCRS (1 << 7)
40   -#define MMCST0_DXRDY (1 << 9)
41   -#define MMCST0_DRRDY (1 << 10)
42   -#define MMCST0_DATED (1 << 11)
43   -#define MMCST0_TRNDNE (1 << 12)
44   -
45   -#define MMCST0_ERR_MASK (0x00F8)
46   -
47   -/* MMC Status Reg1 fields */
48   -#define MMCST1_BUSY (1 << 0)
49   -#define MMCST1_CLKSTP (1 << 1)
50   -#define MMCST1_DXEMP (1 << 2)
51   -#define MMCST1_DRFUL (1 << 3)
52   -#define MMCST1_DAT3ST (1 << 4)
53   -#define MMCST1_FIFOEMP (1 << 5)
54   -#define MMCST1_FIFOFUL (1 << 6)
55   -
56   -/* MMC INT Mask Reg fields */
57   -#define MMCIM_EDATDNE (1 << 0)
58   -#define MMCIM_EBSYDNE (1 << 1)
59   -#define MMCIM_ERSPDNE (1 << 2)
60   -#define MMCIM_ETOUTRD (1 << 3)
61   -#define MMCIM_ETOUTRS (1 << 4)
62   -#define MMCIM_ECRCWR (1 << 5)
63   -#define MMCIM_ECRCRD (1 << 6)
64   -#define MMCIM_ECRCRS (1 << 7)
65   -#define MMCIM_EDXRDY (1 << 9)
66   -#define MMCIM_EDRRDY (1 << 10)
67   -#define MMCIM_EDATED (1 << 11)
68   -#define MMCIM_ETRNDNE (1 << 12)
69   -
70   -#define MMCIM_MASKALL (0xFFFFFFFF)
71   -
72   -/* MMC Resp Tout Reg fields */
73   -#define MMCTOR_TOR_MASK (0xFF) /* dont write to reg, | it */
74   -#define MMCTOR_TOD_20_16_SHIFT (8)
75   -
76   -/* MMC Data Read Tout Reg fields */
77   -#define MMCTOD_TOD_0_15_MASK (0xFFFF)
78   -
79   -/* MMC Block len Reg fields */
80   -#define MMCBLEN_BLEN_MASK (0xFFF)
81   -
82   -/* MMC Num Blocks Reg fields */
83   -#define MMCNBLK_NBLK_MASK (0xFFFF)
84   -#define MMCNBLK_NBLK_MAX (0xFFFF)
85   -
86   -/* MMC Num Blocks Counter Reg fields */
87   -#define MMCNBLC_NBLC_MASK (0xFFFF)
88   -
89   -/* MMC Cmd Reg fields */
90   -#define MMCCMD_CMD_MASK (0x3F)
91   -#define MMCCMD_PPLEN (1 << 7)
92   -#define MMCCMD_BSYEXP (1 << 8)
93   -#define MMCCMD_RSPFMT_NONE (0 << 9)
94   -#define MMCCMD_RSPFMT_R1567 (1 << 9)
95   -#define MMCCMD_RSPFMT_R2 (2 << 9)
96   -#define MMCCMD_RSPFMT_R3 (3 << 9)
97   -#define MMCCMD_DTRW (1 << 11)
98   -#define MMCCMD_STRMTP (1 << 12)
99   -#define MMCCMD_WDATX (1 << 13)
100   -#define MMCCMD_INITCK (1 << 14)
101   -#define MMCCMD_DCLR (1 << 15)
102   -#define MMCCMD_DMATRIG (1 << 16)
103   -
104   -/* FIFO control Reg fields */
105   -#define MMCFIFOCTL_FIFORST (1 << 0)
106   -#define MMCFIFOCTL_FIFODIR (1 << 1)
107   -#define MMCFIFOCTL_FIFOLEV (1 << 2)
108   -#define MMCFIFOCTL_ACCWD_4 (0 << 3) /* access width of 4 bytes */
109   -#define MMCFIFOCTL_ACCWD_3 (1 << 3) /* access width of 3 bytes */
110   -#define MMCFIFOCTL_ACCWD_2 (2 << 3) /* access width of 2 bytes */
111   -#define MMCFIFOCTL_ACCWD_1 (3 << 3) /* access width of 1 byte */
112   -
113   -/* Davinci MMC Register definitions */
114   -struct davinci_mmc_regs {
115   - dv_reg mmcctl;
116   - dv_reg mmcclk;
117   - dv_reg mmcst0;
118   - dv_reg mmcst1;
119   - dv_reg mmcim;
120   - dv_reg mmctor;
121   - dv_reg mmctod;
122   - dv_reg mmcblen;
123   - dv_reg mmcnblk;
124   - dv_reg mmcnblc;
125   - dv_reg mmcdrr;
126   - dv_reg mmcdxr;
127   - dv_reg mmccmd;
128   - dv_reg mmcarghl;
129   - dv_reg mmcrsp01;
130   - dv_reg mmcrsp23;
131   - dv_reg mmcrsp45;
132   - dv_reg mmcrsp67;
133   - dv_reg mmcdrsp;
134   - dv_reg mmcetok;
135   - dv_reg mmccidx;
136   - dv_reg mmcckc;
137   - dv_reg mmctorc;
138   - dv_reg mmctodc;
139   - dv_reg mmcblnc;
140   - dv_reg sdioctl;
141   - dv_reg sdiost0;
142   - dv_reg sdioien;
143   - dv_reg sdioist;
144   - dv_reg mmcfifoctl;
145   -};
146   -
147   -/* Davinci MMC board definitions */
148   -struct davinci_mmc {
149   - struct davinci_mmc_regs *reg_base; /* Register base address */
150   - uint input_clk; /* Input clock to MMC controller */
151   - uint host_caps; /* Host capabilities */
152   - uint voltages; /* Host supported voltages */
153   - uint version; /* MMC Controller version */
154   - struct mmc_config cfg;
155   -};
156   -
157   -enum {
158   - MMC_CTLR_VERSION_1 = 0, /* DM644x and DM355 */
159   - MMC_CTLR_VERSION_2, /* DA830 */
160   -};
161   -
162   -int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host);
163   -
164   -#endif /* _SDMMC_DEFS_H */
arch/arm/include/asm/arch-davinci/syscfg_defs.h
View file @ 3d35761
1   -/*
2   - * Copyright (C) 2011
3   - * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -#ifndef _DV_SYSCFG_DEFS_H_
8   -#define _DV_SYSCFG_DEFS_H_
9   -
10   -#ifndef CONFIG_SOC_DA8XX
11   -/* System Control Module register structure for DM365 */
12   -struct dv_sys_module_regs {
13   - unsigned int pinmux[5]; /* 0x00 */
14   - unsigned int bootcfg; /* 0x14 */
15   - unsigned int arm_intmux; /* 0x18 */
16   - unsigned int edma_evtmux; /* 0x1C */
17   - unsigned int ddr_slew; /* 0x20 */
18   - unsigned int clkout; /* 0x24 */
19   - unsigned int device_id; /* 0x28 */
20   - unsigned int vdac_config; /* 0x2C */
21   - unsigned int timer64_ctl; /* 0x30 */
22   - unsigned int usbbphy_ctl; /* 0x34 */
23   - unsigned int misc; /* 0x38 */
24   - unsigned int mstpri[2]; /* 0x3C */
25   - unsigned int vpss_clkctl; /* 0x44 */
26   - unsigned int peri_clkctl; /* 0x48 */
27   - unsigned int deepsleep; /* 0x4C */
28   - unsigned int dft_enable; /* 0x50 */
29   - unsigned int debounce[8]; /* 0x54 */
30   - unsigned int vtpiocr; /* 0x74 */
31   - unsigned int pupdctl0; /* 0x78 */
32   - unsigned int pupdctl1; /* 0x7C */
33   - unsigned int hdimcopbt; /* 0x80 */
34   - unsigned int pll0_config; /* 0x84 */
35   - unsigned int pll1_config; /* 0x88 */
36   -};
37   -
38   -#define VPTIO_RDY (1 << 15)
39   -#define VPTIO_IOPWRDN (1 << 14)
40   -#define VPTIO_CLRZ (1 << 13)
41   -#define VPTIO_LOCK (1 << 7)
42   -#define VPTIO_PWRDN (1 << 6)
43   -
44   -#define VPSS_CLK_CTL_VPSS_CLKMD (1 << 7)
45   -
46   -#define dv_sys_module_regs \
47   - ((struct dv_sys_module_regs *)DAVINCI_SYSTEM_MODULE_BASE)
48   -
49   -#endif /* !CONFIG_SOC_DA8XX */
50   -#endif /* _DV_SYSCFG_DEFS_H_ */
arch/arm/include/asm/arch-davinci/timer_defs.h
View file @ 3d35761
1   -/*
2   - * Copyright (C) 2011 DENX Software Engineering GmbH
3   - * Heiko Schocher <hs@denx.de>
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -#ifndef _TIMER_DEFS_H_
8   -#define _TIMER_DEFS_H_
9   -
10   -struct davinci_timer {
11   - u_int32_t pid12;
12   - u_int32_t emumgt;
13   - u_int32_t na1;
14   - u_int32_t na2;
15   - u_int32_t tim12;
16   - u_int32_t tim34;
17   - u_int32_t prd12;
18   - u_int32_t prd34;
19   - u_int32_t tcr;
20   - u_int32_t tgcr;
21   - u_int32_t wdtcr;
22   -};
23   -
24   -#define DV_TIMER_TCR_ENAMODE_MASK 3
25   -
26   -#define DV_TIMER_TCR_ENAMODE12_SHIFT 6
27   -#define DV_TIMER_TCR_CLKSRC12_SHIFT 8
28   -#define DV_TIMER_TCR_READRSTMODE12_SHIFT 10
29   -#define DV_TIMER_TCR_CAPMODE12_SHIFT 11
30   -#define DV_TIMER_TCR_CAPVTMODE12_SHIFT 12
31   -#define DV_TIMER_TCR_ENAMODE34_SHIFT 22
32   -#define DV_TIMER_TCR_CLKSRC34_SHIFT 24
33   -#define DV_TIMER_TCR_READRSTMODE34_SHIFT 26
34   -#define DV_TIMER_TCR_CAPMODE34_SHIFT 27
35   -#define DV_TIMER_TCR_CAPEVTMODE12_SHIFT 28
36   -
37   -#define DV_WDT_ENABLE_SYS_RESET 0x00020000
38   -#define DV_WDT_TRIGGER_SYS_RESET 0x00020002
39   -
40   -#ifdef CONFIG_HW_WATCHDOG
41   -void davinci_hw_watchdog_enable(void);
42   -void davinci_hw_watchdog_reset(void);
43   -#endif
44   -#endif /* _TIMER_DEFS_H_ */
arch/arm/mach-davinci/include/mach/aintc_defs.h
Diff comments   View file @ 3d35761
  1 +/*
  2 + * Copyright (C) 2011
  3 + * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +#ifndef _DV_AINTC_DEFS_H_
  8 +#define _DV_AINTC_DEFS_H_
  9 +
  10 +struct dv_aintc_regs {
  11 + unsigned int fiq0; /* 0x00 */
  12 + unsigned int fiq1; /* 0x04 */
  13 + unsigned int irq0; /* 0x08 */
  14 + unsigned int irq1; /* 0x0c */
  15 + unsigned int fiqentry; /* 0x10 */
  16 + unsigned int irqentry; /* 0x14 */
  17 + unsigned int eint0; /* 0x18 */
  18 + unsigned int eint1; /* 0x1c */
  19 + unsigned int intctl; /* 0x20 */
  20 + unsigned int eabase; /* 0x24 */
  21 + unsigned char rsvd0[8]; /* 0x28 */
  22 + unsigned int intpri0; /* 0x30 */
  23 + unsigned int intpri1; /* 0x34 */
  24 + unsigned int intpri2; /* 0x38 */
  25 + unsigned int intpri3; /* 0x3c */
  26 + unsigned int intpri4; /* 0x40 */
  27 + unsigned int intpri5; /* 0x44 */
  28 + unsigned int intpri6; /* 0x48 */
  29 + unsigned int intpri7; /* 0x4c */
  30 +};
  31 +
  32 +#define dv_aintc_regs ((struct dv_aintc_regs *)DAVINCI_ARM_INTC_BASE)
  33 +
  34 +#define DV_AINTC_INTCTL_IDMODE (1 << 2)
  35 +
  36 +#endif /* _DV_AINTC_DEFS_H_ */
arch/arm/mach-davinci/include/mach/da850_lowlevel.h
Diff comments   View file @ 3d35761
  1 +/*
  2 + * SoC-specific lowlevel code for DA850
  3 + *
  4 + * Copyright (C) 2011
  5 + * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  6 + *
  7 + * SPDX-License-Identifier: GPL-2.0+
  8 + */
  9 +#ifndef __DA850_LOWLEVEL_H
  10 +#define __DA850_LOWLEVEL_H
  11 +
  12 +#include <asm/arch/pinmux_defs.h>
  13 +
  14 +/* pinmux_resource[] vector is defined in the board specific file */
  15 +extern const struct pinmux_resource pinmuxes[];
  16 +extern const int pinmuxes_size;
  17 +
  18 +extern const struct lpsc_resource lpsc[];
  19 +extern const int lpsc_size;
  20 +
  21 +/* NOR Boot Configuration Word Field Descriptions */
  22 +#define DA850_NORBOOT_COPY_XK(X) ((X - 1) << 8)
  23 +#define DA850_NORBOOT_METHOD_DIRECT (1 << 4)
  24 +#define DA850_NORBOOT_16BIT (1 << 0)
  25 +
  26 +#define dv_maskbits(addr, val) \
  27 + writel((readl(addr) & val), addr)
  28 +
  29 +void da850_lpc_transition(unsigned char pscnum, unsigned char module,
  30 + unsigned char domain, unsigned char state);
  31 +void da850_psc_init(void);
  32 +void da850_pinmux_ctl(unsigned long offset, unsigned long mask,
  33 + unsigned long value);
  34 +
  35 +#endif /* #ifndef __DA850_LOWLEVEL_H */
arch/arm/mach-davinci/include/mach/da8xx-usb.h
Diff comments   View file @ 3d35761
  1 +/*
  2 + * da8xx-usb.h -- TI's DA8xx platform specific usb wrapper definitions.
  3 + *
  4 + * Author: Ajay Kumar Gupta <ajay.gupta@ti.com>
  5 + *
  6 + * Based on drivers/usb/musb/davinci.h
  7 + *
  8 + * Copyright (C) 2009 Texas Instruments Incorporated
  9 + *
  10 + * SPDX-License-Identifier: GPL-2.0+
  11 + */
  12 +#ifndef __DA8XX_MUSB_H__
  13 +#define __DA8XX_MUSB_H__
  14 +
  15 +#include <asm/arch/hardware.h>
  16 +#include <asm/arch/gpio.h>
  17 +
  18 +/* Base address of da8xx usb0 wrapper */
  19 +#define DA8XX_USB_OTG_BASE 0x01E00000
  20 +
  21 +/* Base address of da8xx musb core */
  22 +#define DA8XX_USB_OTG_CORE_BASE (DA8XX_USB_OTG_BASE + 0x400)
  23 +
  24 +/* Timeout for DA8xx usb module */
  25 +#define DA8XX_USB_OTG_TIMEOUT 0x3FFFFFF
  26 +
  27 +/*
  28 + * DA8xx platform USB wrapper register overlay.
  29 + */
  30 +struct da8xx_usb_regs {
  31 + dv_reg revision;
  32 + dv_reg control;
  33 + dv_reg status;
  34 + dv_reg emulation;
  35 + dv_reg mode;
  36 + dv_reg autoreq;
  37 + dv_reg srpfixtime;
  38 + dv_reg teardown;
  39 + dv_reg intsrc;
  40 + dv_reg intsrc_set;
  41 + dv_reg intsrc_clr;
  42 + dv_reg intmsk;
  43 + dv_reg intmsk_set;
  44 + dv_reg intmsk_clr;
  45 + dv_reg intsrcmsk;
  46 + dv_reg eoi;
  47 + dv_reg intvector;
  48 + dv_reg grndis_size[4];
  49 +};
  50 +
  51 +#define da8xx_usb_regs ((struct da8xx_usb_regs *)DA8XX_USB_OTG_BASE)
  52 +
  53 +/* DA8XX interrupt bits definitions */
  54 +#define DA8XX_USB_TX_ENDPTS_MASK 0x1f /* ep0 + 4 tx */
  55 +#define DA8XX_USB_RX_ENDPTS_MASK 0x1e /* 4 rx */
  56 +#define DA8XX_USB_TXINT_SHIFT 0
  57 +#define DA8XX_USB_RXINT_SHIFT 8
  58 +
  59 +#define DA8XX_USB_USBINT_MASK 0x01ff0000 /* 8 Mentor, DRVVBUS */
  60 +#define DA8XX_USB_TXINT_MASK \
  61 + (DA8XX_USB_TX_ENDPTS_MASK << DA8XX_USB_TXINT_SHIFT)
  62 +#define DA8XX_USB_RXINT_MASK \
  63 + (DA8XX_USB_RX_ENDPTS_MASK << DA8XX_USB_RXINT_SHIFT)
  64 +
  65 +/* DA8xx CFGCHIP2 (USB 2.0 PHY Control) register bits */
  66 +#define CFGCHIP2_PHYCLKGD (1 << 17)
  67 +#define CFGCHIP2_VBUSSENSE (1 << 16)
  68 +#define CFGCHIP2_RESET (1 << 15)
  69 +#define CFGCHIP2_OTGMODE (3 << 13)
  70 +#define CFGCHIP2_NO_OVERRIDE (0 << 13)
  71 +#define CFGCHIP2_FORCE_HOST (1 << 13)
  72 +#define CFGCHIP2_FORCE_DEVICE (2 << 13)
  73 +#define CFGCHIP2_FORCE_HOST_VBUS_LOW (3 << 13)
  74 +#define CFGCHIP2_USB1PHYCLKMUX (1 << 12)
  75 +#define CFGCHIP2_USB2PHYCLKMUX (1 << 11)
  76 +#define CFGCHIP2_PHYPWRDN (1 << 10)
  77 +#define CFGCHIP2_OTGPWRDN (1 << 9)
  78 +#define CFGCHIP2_DATPOL (1 << 8)
  79 +#define CFGCHIP2_USB1SUSPENDM (1 << 7)
  80 +#define CFGCHIP2_PHY_PLLON (1 << 6) /* override PLL suspend */
  81 +#define CFGCHIP2_SESENDEN (1 << 5) /* Vsess_end comparator */
  82 +#define CFGCHIP2_VBDTCTEN (1 << 4) /* Vbus comparator */
  83 +#define CFGCHIP2_REFFREQ (0xf << 0)
  84 +#define CFGCHIP2_REFFREQ_12MHZ (1 << 0)
  85 +#define CFGCHIP2_REFFREQ_24MHZ (2 << 0)
  86 +#define CFGCHIP2_REFFREQ_48MHZ (3 << 0)
  87 +
  88 +#define DA8XX_USB_VBUS_GPIO (1 << 15)
  89 +
  90 +int usb_phy_on(void);
  91 +void usb_phy_off(void);
  92 +
  93 +#endif /* __DA8XX_MUSB_H__ */
arch/arm/mach-davinci/include/mach/davinci_misc.h
Diff comments   View file @ 3d35761
  1 +/*
  2 + * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef __MISC_H
  8 +#define __MISC_H
  9 +
  10 +/* pin muxer definitions */
  11 +#define PIN_MUX_NUM_FIELDS 8 /* Per register */
  12 +#define PIN_MUX_FIELD_SIZE 4 /* n in bits */
  13 +#define PIN_MUX_FIELD_MASK ((1 << PIN_MUX_FIELD_SIZE) - 1)
  14 +
  15 +/* pin definition */
  16 +struct pinmux_config {
  17 + dv_reg *mux; /* Address of mux register */
  18 + unsigned char value; /* Value to set in field */
  19 + unsigned char field; /* field number */
  20 +};
  21 +
  22 +/* pin table definition */
  23 +struct pinmux_resource {
  24 + const struct pinmux_config *pins;
  25 + const int n_pins;
  26 +};
  27 +
  28 +#define PINMUX_ITEM(item) { \
  29 + .pins = item, \
  30 + .n_pins = ARRAY_SIZE(item) \
  31 + }
  32 +
  33 +struct lpsc_resource {
  34 + const int lpsc_no;
  35 +};
  36 +
  37 +int dvevm_read_mac_address(uint8_t *buf);
  38 +void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr);
  39 +int davinci_configure_pin_mux(const struct pinmux_config *pins, int n_pins);
  40 +int davinci_configure_pin_mux_items(const struct pinmux_resource *item,
  41 + int n_items);
  42 +#if defined(CONFIG_DRIVER_TI_EMAC) && defined(CONFIG_SOC_DA8XX)
  43 +void davinci_emac_mii_mode_sel(int mode_sel);
  44 +#endif
  45 +#if defined(CONFIG_SOC_DA8XX)
  46 +void irq_init(void);
  47 +int da8xx_configure_lpsc_items(const struct lpsc_resource *item,
  48 + const int n_items);
  49 +#endif
  50 +
  51 +#endif /* __MISC_H */
arch/arm/mach-davinci/include/mach/ddr2_defs.h
Diff comments   View file @ 3d35761
  1 +/*
  2 + * Copyright (C) 2011
  3 + * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +#ifndef _DV_DDR2_DEFS_H_
  8 +#define _DV_DDR2_DEFS_H_
  9 +
  10 +/*
  11 + * DDR2 Memory Ctrl Register structure
  12 + * See sprueh7d.pdf for more details.
  13 + */
  14 +struct dv_ddr2_regs_ctrl {
  15 + unsigned char rsvd0[4]; /* 0x00 */
  16 + unsigned int sdrstat; /* 0x04 */
  17 + unsigned int sdbcr; /* 0x08 */
  18 + unsigned int sdrcr; /* 0x0C */
  19 + unsigned int sdtimr; /* 0x10 */
  20 + unsigned int sdtimr2; /* 0x14 */
  21 + unsigned char rsvd1[4]; /* 0x18 */
  22 + unsigned int sdbcr2; /* 0x1C */
  23 + unsigned int pbbpr; /* 0x20 */
  24 + unsigned char rsvd2[156]; /* 0x24 */
  25 + unsigned int irr; /* 0xC0 */
  26 + unsigned int imr; /* 0xC4 */
  27 + unsigned int imsr; /* 0xC8 */
  28 + unsigned int imcr; /* 0xCC */
  29 + unsigned char rsvd3[20]; /* 0xD0 */
  30 + unsigned int ddrphycr; /* 0xE4 */
  31 + unsigned int ddrphycr2; /* 0xE8 */
  32 + unsigned char rsvd4[4]; /* 0xEC */
  33 +};
  34 +
  35 +#define DV_DDR_PHY_PWRDNEN 0x40
  36 +#define DV_DDR_PHY_EXT_STRBEN 0x80
  37 +#define DV_DDR_PHY_RD_LATENCY_SHIFT 0
  38 +
  39 +#define DV_DDR_SDTMR1_RFC_SHIFT 25
  40 +#define DV_DDR_SDTMR1_RP_SHIFT 22
  41 +#define DV_DDR_SDTMR1_RCD_SHIFT 19
  42 +#define DV_DDR_SDTMR1_WR_SHIFT 16
  43 +#define DV_DDR_SDTMR1_RAS_SHIFT 11
  44 +#define DV_DDR_SDTMR1_RC_SHIFT 6
  45 +#define DV_DDR_SDTMR1_RRD_SHIFT 3
  46 +#define DV_DDR_SDTMR1_WTR_SHIFT 0
  47 +
  48 +#define DV_DDR_SDTMR2_RASMAX_SHIFT 27
  49 +#define DV_DDR_SDTMR2_XP_SHIFT 25
  50 +#define DV_DDR_SDTMR2_ODT_SHIFT 23
  51 +#define DV_DDR_SDTMR2_XSNR_SHIFT 16
  52 +#define DV_DDR_SDTMR2_XSRD_SHIFT 8
  53 +#define DV_DDR_SDTMR2_RTP_SHIFT 5
  54 +#define DV_DDR_SDTMR2_CKE_SHIFT 0
  55 +
  56 +#define DV_DDR_SDCR_DDR2TERM1_SHIFT 27
  57 +#define DV_DDR_SDCR_IBANK_POS_SHIFT 26
  58 +#define DV_DDR_SDCR_MSDRAMEN_SHIFT 25
  59 +#define DV_DDR_SDCR_DDRDRIVE1_SHIFT 24
  60 +#define DV_DDR_SDCR_BOOTUNLOCK_SHIFT 23
  61 +#define DV_DDR_SDCR_DDR_DDQS_SHIFT 22
  62 +#define DV_DDR_SDCR_DDR2EN_SHIFT 20
  63 +#define DV_DDR_SDCR_DDRDRIVE0_SHIFT 18
  64 +#define DV_DDR_SDCR_DDREN_SHIFT 17
  65 +#define DV_DDR_SDCR_SDRAMEN_SHIFT 16
  66 +#define DV_DDR_SDCR_TIMUNLOCK_SHIFT 15
  67 +#define DV_DDR_SDCR_BUS_WIDTH_SHIFT 14
  68 +#define DV_DDR_SDCR_CL_SHIFT 9
  69 +#define DV_DDR_SDCR_IBANK_SHIFT 4
  70 +#define DV_DDR_SDCR_PAGESIZE_SHIFT 0
  71 +
  72 +#define DV_DDR_SDRCR_LPMODEN (1 << 31)
  73 +#define DV_DDR_SDRCR_MCLKSTOPEN (1 << 30)
  74 +
  75 +#define DV_DDR_SRCR_LPMODEN_SHIFT 31
  76 +#define DV_DDR_SRCR_MCLKSTOPEN_SHIFT 30
  77 +
  78 +#define DV_DDR_BOOTUNLOCK (1 << DV_DDR_SDCR_BOOTUNLOCK_SHIFT)
  79 +#define DV_DDR_TIMUNLOCK (1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT)
  80 +
  81 +#define dv_ddr2_regs_ctrl \
  82 + ((struct dv_ddr2_regs_ctrl *)DAVINCI_DDR_EMIF_CTRL_BASE)
  83 +
  84 +#endif /* _DV_DDR2_DEFS_H_ */
arch/arm/mach-davinci/include/mach/dm365_lowlevel.h
Diff comments   View file @ 3d35761
  1 +/*
  2 + * SoC-specific lowlevel code for tms320dm365 and similar chips
  3 + *
  4 + * Copyright (C) 2011
  5 + * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  6 + *
  7 + * SPDX-License-Identifier: GPL-2.0+
  8 + */
  9 +#ifndef __DM365_LOWLEVEL_H
  10 +#define __DM365_LOWLEVEL_H
  11 +
  12 +#include <common.h>
  13 +#include <asm/arch/hardware.h>
  14 +#include <asm/io.h>
  15 +
  16 +void dm365_waitloop(unsigned long loopcnt);
  17 +int dm365_pll1_init(unsigned long pllmult, unsigned long prediv);
  18 +int dm365_pll2_init(unsigned long pllm, unsigned long prediv);
  19 +int dm365_ddr_setup(void);
  20 +void dm365_psc_init(void);
  21 +void dm365_pinmux_ctl(unsigned long offset, unsigned long mask,
  22 + unsigned long value);
  23 +void dm36x_lowlevel_init(ulong bootflag);
  24 +
  25 +#endif /* #ifndef __DM365_LOWLEVEL_H */
arch/arm/mach-davinci/include/mach/emac_defs.h
Diff comments   View file @ 3d35761
  1 +/*
  2 + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
  3 + *
  4 + * Based on:
  5 + *
  6 + * ----------------------------------------------------------------------------
  7 + *
  8 + * dm644x_emac.h
  9 + *
  10 + * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM
  11 + *
  12 + * Copyright (C) 2005 Texas Instruments.
  13 + *
  14 + * ----------------------------------------------------------------------------
  15 + *
  16 + * SPDX-License-Identifier: GPL-2.0+
  17 + *
  18 + * Modifications:
  19 + * ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot.
  20 + */
  21 +
  22 +#ifndef _DM644X_EMAC_H_
  23 +#define _DM644X_EMAC_H_
  24 +
  25 +#include <asm/arch/hardware.h>
  26 +
  27 +#ifdef CONFIG_SOC_DM365
  28 +#define EMAC_BASE_ADDR (0x01d07000)
  29 +#define EMAC_WRAPPER_BASE_ADDR (0x01d0a000)
  30 +#define EMAC_WRAPPER_RAM_ADDR (0x01d08000)
  31 +#define EMAC_MDIO_BASE_ADDR (0x01d0b000)
  32 +#define DAVINCI_EMAC_VERSION2
  33 +#elif defined(CONFIG_SOC_DA8XX)
  34 +#define EMAC_BASE_ADDR DAVINCI_EMAC_CNTRL_REGS_BASE
  35 +#define EMAC_WRAPPER_BASE_ADDR DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE
  36 +#define EMAC_WRAPPER_RAM_ADDR DAVINCI_EMAC_WRAPPER_RAM_BASE
  37 +#define EMAC_MDIO_BASE_ADDR DAVINCI_MDIO_CNTRL_REGS_BASE
  38 +#define DAVINCI_EMAC_VERSION2
  39 +#else
  40 +#define EMAC_BASE_ADDR (0x01c80000)
  41 +#define EMAC_WRAPPER_BASE_ADDR (0x01c81000)
  42 +#define EMAC_WRAPPER_RAM_ADDR (0x01c82000)
  43 +#define EMAC_MDIO_BASE_ADDR (0x01c84000)
  44 +#endif
  45 +
  46 +#ifdef CONFIG_SOC_DM646X
  47 +#define DAVINCI_EMAC_VERSION2
  48 +#define DAVINCI_EMAC_GIG_ENABLE
  49 +#endif
  50 +
  51 +#ifdef CONFIG_SOC_DM646X
  52 +/* MDIO module input frequency */
  53 +#define EMAC_MDIO_BUS_FREQ 76500000
  54 +/* MDIO clock output frequency */
  55 +#define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */
  56 +#elif defined(CONFIG_SOC_DM365)
  57 +/* MDIO module input frequency */
  58 +#define EMAC_MDIO_BUS_FREQ 121500000
  59 +/* MDIO clock output frequency */
  60 +#define EMAC_MDIO_CLOCK_FREQ 2200000 /* 2.2 MHz */
  61 +#elif defined(CONFIG_SOC_DA8XX)
  62 +/* MDIO module input frequency */
  63 +#define EMAC_MDIO_BUS_FREQ clk_get(DAVINCI_MDIO_CLKID)
  64 +/* MDIO clock output frequency */
  65 +#define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */
  66 +#else
  67 +/* MDIO module input frequency */
  68 +#define EMAC_MDIO_BUS_FREQ 99000000 /* PLL/6 - 99 MHz */
  69 +/* MDIO clock output frequency */
  70 +#define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */
  71 +#endif
  72 +
  73 +#define PHY_KSZ8873 (0x00221450)
  74 +int ksz8873_is_phy_connected(int phy_addr);
  75 +int ksz8873_get_link_speed(int phy_addr);
  76 +int ksz8873_init_phy(int phy_addr);
  77 +int ksz8873_auto_negotiate(int phy_addr);
  78 +
  79 +#define PHY_LXT972 (0x001378e2)
  80 +int lxt972_is_phy_connected(int phy_addr);
  81 +int lxt972_get_link_speed(int phy_addr);
  82 +int lxt972_init_phy(int phy_addr);
  83 +int lxt972_auto_negotiate(int phy_addr);
  84 +
  85 +#define PHY_DP83848 (0x20005c90)
  86 +int dp83848_is_phy_connected(int phy_addr);
  87 +int dp83848_get_link_speed(int phy_addr);
  88 +int dp83848_init_phy(int phy_addr);
  89 +int dp83848_auto_negotiate(int phy_addr);
  90 +
  91 +#define PHY_ET1011C (0x282f013)
  92 +int et1011c_get_link_speed(int phy_addr);
  93 +
  94 +#endif /* _DM644X_EMAC_H_ */
arch/arm/mach-davinci/include/mach/gpio.h
Diff comments   View file @ 3d35761
  1 +/*
  2 + * Copyright (C) 2009 Texas Instruments Incorporated
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +#ifndef _GPIO_DEFS_H_
  7 +#define _GPIO_DEFS_H_
  8 +
  9 +#ifndef CONFIG_SOC_DA8XX
  10 +#define DAVINCI_GPIO_BINTEN 0x01C67008
  11 +#define DAVINCI_GPIO_BANK01 0x01C67010
  12 +#define DAVINCI_GPIO_BANK23 0x01C67038
  13 +#define DAVINCI_GPIO_BANK45 0x01C67060
  14 +#define DAVINCI_GPIO_BANK67 0x01C67088
  15 +
  16 +#else /* CONFIG_SOC_DA8XX */
  17 +#define DAVINCI_GPIO_BINTEN 0x01E26008
  18 +#define DAVINCI_GPIO_BANK01 0x01E26010
  19 +#define DAVINCI_GPIO_BANK23 0x01E26038
  20 +#define DAVINCI_GPIO_BANK45 0x01E26060
  21 +#define DAVINCI_GPIO_BANK67 0x01E26088
  22 +#define DAVINCI_GPIO_BANK8 0x01E260B0
  23 +#endif /* CONFIG_SOC_DA8XX */
  24 +
  25 +struct davinci_gpio {
  26 + unsigned int dir;
  27 + unsigned int out_data;
  28 + unsigned int set_data;
  29 + unsigned int clr_data;
  30 + unsigned int in_data;
  31 + unsigned int set_rising;
  32 + unsigned int clr_rising;
  33 + unsigned int set_falling;
  34 + unsigned int clr_falling;
  35 + unsigned int intstat;
  36 +};
  37 +
  38 +struct davinci_gpio_bank {
  39 + int num_gpio;
  40 + unsigned int irq_num;
  41 + unsigned int irq_mask;
  42 + unsigned long *in_use;
  43 + unsigned long base;
  44 +};
  45 +
  46 +#define davinci_gpio_bank01 ((struct davinci_gpio *)DAVINCI_GPIO_BANK01)
  47 +#define davinci_gpio_bank23 ((struct davinci_gpio *)DAVINCI_GPIO_BANK23)
  48 +#define davinci_gpio_bank45 ((struct davinci_gpio *)DAVINCI_GPIO_BANK45)
  49 +#define davinci_gpio_bank67 ((struct davinci_gpio *)DAVINCI_GPIO_BANK67)
  50 +#define davinci_gpio_bank8 ((struct davinci_gpio *)DAVINCI_GPIO_BANK8)
  51 +
  52 +#define gpio_status() gpio_info()
  53 +#define GPIO_NAME_SIZE 20
  54 +#if defined(CONFIG_SOC_DM644X)
  55 +/* GPIO0 to GPIO53, omit the V3.3 volts one */
  56 +#define MAX_NUM_GPIOS 70
  57 +#elif defined(CONFIG_SOC_DA8XX) && !defined(CONFIG_SOC_DA850)
  58 +#define MAX_NUM_GPIOS 128
  59 +#else
  60 +#define MAX_NUM_GPIOS 144
  61 +#endif
  62 +#define GPIO_BANK(gp) (davinci_gpio_bank01 + ((gp) >> 5))
  63 +#define GPIO_BIT(gp) ((gp) & 0x1F)
  64 +
  65 +void gpio_info(void);
  66 +
  67 +#endif
arch/arm/mach-davinci/include/mach/hardware.h
Diff comments   View file @ 3d35761
  1 +/*
  2 + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
  3 + *
  4 + * Based on:
  5 + *
  6 + * -------------------------------------------------------------------------
  7 + *
  8 + * linux/include/asm-arm/arch-davinci/hardware.h
  9 + *
  10 + * Copyright (C) 2006 Texas Instruments.
  11 + *
  12 + * SPDX-License-Identifier: GPL-2.0+
  13 + */
  14 +#ifndef __ASM_ARCH_HARDWARE_H
  15 +#define __ASM_ARCH_HARDWARE_H
  16 +
  17 +#include <config.h>
  18 +#include <linux/sizes.h>
  19 +
  20 +#define REG(addr) (*(volatile unsigned int *)(addr))
  21 +#define REG_P(addr) ((volatile unsigned int *)(addr))
  22 +
  23 +typedef volatile unsigned int dv_reg;
  24 +typedef volatile unsigned int * dv_reg_p;
  25 +
  26 +/*
  27 + * Base register addresses
  28 + *
  29 + * NOTE: some of these DM6446-specific addresses DO NOT WORK
  30 + * on other DaVinci chips. Double check them before you try
  31 + * using the addresses ... or PSC module identifiers, etc.
  32 + */
  33 +#ifndef CONFIG_SOC_DA8XX
  34 +
  35 +#define DAVINCI_DMA_3PCC_BASE (0x01c00000)
  36 +#define DAVINCI_DMA_3PTC0_BASE (0x01c10000)
  37 +#define DAVINCI_DMA_3PTC1_BASE (0x01c10400)
  38 +#define DAVINCI_UART0_BASE (0x01c20000)
  39 +#define DAVINCI_UART1_BASE (0x01c20400)
  40 +#define DAVINCI_TIMER3_BASE (0x01c20800)
  41 +#define DAVINCI_I2C_BASE (0x01c21000)
  42 +#define DAVINCI_TIMER0_BASE (0x01c21400)
  43 +#define DAVINCI_TIMER1_BASE (0x01c21800)
  44 +#define DAVINCI_WDOG_BASE (0x01c21c00)
  45 +#define DAVINCI_PWM0_BASE (0x01c22000)
  46 +#define DAVINCI_PWM1_BASE (0x01c22400)
  47 +#define DAVINCI_PWM2_BASE (0x01c22800)
  48 +#define DAVINCI_TIMER4_BASE (0x01c23800)
  49 +#define DAVINCI_SYSTEM_MODULE_BASE (0x01c40000)
  50 +#define DAVINCI_PLL_CNTRL0_BASE (0x01c40800)
  51 +#define DAVINCI_PLL_CNTRL1_BASE (0x01c40c00)
  52 +#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01c41000)
  53 +#define DAVINCI_ARM_INTC_BASE (0x01c48000)
  54 +#define DAVINCI_USB_OTG_BASE (0x01c64000)
  55 +#define DAVINCI_CFC_ATA_BASE (0x01c66000)
  56 +#define DAVINCI_SPI_BASE (0x01c66800)
  57 +#define DAVINCI_GPIO_BASE (0x01c67000)
  58 +#define DAVINCI_VPSS_REGS_BASE (0x01c70000)
  59 +#if !defined(CONFIG_SOC_DM646X)
  60 +#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000)
  61 +#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000)
  62 +#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000)
  63 +#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000)
  64 +#endif
  65 +#define DAVINCI_DDR_BASE (0x80000000)
  66 +
  67 +#ifdef CONFIG_SOC_DM644X
  68 +#define DAVINCI_UART2_BASE 0x01c20800
  69 +#define DAVINCI_UHPI_BASE 0x01c67800
  70 +#define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01c80000
  71 +#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01c81000
  72 +#define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01c82000
  73 +#define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01c84000
  74 +#define DAVINCI_IMCOP_BASE 0x01cc0000
  75 +#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e00000
  76 +#define DAVINCI_VLYNQ_BASE 0x01e01000
  77 +#define DAVINCI_ASP_BASE 0x01e02000
  78 +#define DAVINCI_MMC_SD_BASE 0x01e10000
  79 +#define DAVINCI_MS_BASE 0x01e20000
  80 +#define DAVINCI_VLYNQ_REMOTE_BASE 0x0c000000
  81 +
  82 +#elif defined(CONFIG_SOC_DM355)
  83 +#define DAVINCI_MMC_SD1_BASE 0x01e00000
  84 +#define DAVINCI_ASP0_BASE 0x01e02000
  85 +#define DAVINCI_ASP1_BASE 0x01e04000
  86 +#define DAVINCI_UART2_BASE 0x01e06000
  87 +#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e10000
  88 +#define DAVINCI_MMC_SD0_BASE 0x01e11000
  89 +
  90 +#elif defined(CONFIG_SOC_DM365)
  91 +#define DAVINCI_MMC_SD1_BASE 0x01d00000
  92 +#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01d10000
  93 +#define DAVINCI_MMC_SD0_BASE 0x01d11000
  94 +#define DAVINCI_DDR_EMIF_CTRL_BASE 0x20000000
  95 +#define DAVINCI_SPI0_BASE 0x01c66000
  96 +#define DAVINCI_SPI1_BASE 0x01c66800
  97 +
  98 +#elif defined(CONFIG_SOC_DM646X)
  99 +#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x20008000
  100 +#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x42000000
  101 +#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE 0x44000000
  102 +#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x46000000
  103 +#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x48000000
  104 +
  105 +#endif
  106 +
  107 +#else /* CONFIG_SOC_DA8XX */
  108 +
  109 +#define DAVINCI_UART0_BASE 0x01c42000
  110 +#define DAVINCI_UART1_BASE 0x01d0c000
  111 +#define DAVINCI_UART2_BASE 0x01d0d000
  112 +#define DAVINCI_I2C0_BASE 0x01c22000
  113 +#define DAVINCI_I2C1_BASE 0x01e28000
  114 +#define DAVINCI_TIMER0_BASE 0x01c20000
  115 +#define DAVINCI_TIMER1_BASE 0x01c21000
  116 +#define DAVINCI_WDOG_BASE 0x01c21000
  117 +#define DAVINCI_RTC_BASE 0x01c23000
  118 +#define DAVINCI_PLL_CNTRL0_BASE 0x01c11000
  119 +#define DAVINCI_PLL_CNTRL1_BASE 0x01e1a000
  120 +#define DAVINCI_PSC0_BASE 0x01c10000
  121 +#define DAVINCI_PSC1_BASE 0x01e27000
  122 +#define DAVINCI_SPI0_BASE 0x01c41000
  123 +#define DAVINCI_USB_OTG_BASE 0x01e00000
  124 +#define DAVINCI_SPI1_BASE (cpu_is_da830() ? \
  125 + 0x01e12000 : 0x01f0e000)
  126 +#define DAVINCI_GPIO_BASE 0x01e26000
  127 +#define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01e23000
  128 +#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01e22000
  129 +#define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01e20000
  130 +#define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01e24000
  131 +#define DAVINCI_SYSCFG1_BASE 0x01e2c000
  132 +#define DAVINCI_MMC_SD0_BASE 0x01c40000
  133 +#define DAVINCI_MMC_SD1_BASE 0x01e1b000
  134 +#define DAVINCI_TIMER2_BASE 0x01f0c000
  135 +#define DAVINCI_TIMER3_BASE 0x01f0d000
  136 +#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x68000000
  137 +#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x40000000
  138 +#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x60000000
  139 +#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x62000000
  140 +#define DAVINCI_ASYNC_EMIF_DATA_CE4_BASE 0x64000000
  141 +#define DAVINCI_ASYNC_EMIF_DATA_CE5_BASE 0x66000000
  142 +#define DAVINCI_DDR_EMIF_CTRL_BASE 0xb0000000
  143 +#define DAVINCI_DDR_EMIF_DATA_BASE 0xc0000000
  144 +#define DAVINCI_INTC_BASE 0xfffee000
  145 +#define DAVINCI_BOOTCFG_BASE 0x01c14000
  146 +#define DAVINCI_LCD_CNTL_BASE 0x01e13000
  147 +#define DAVINCI_L3CBARAM_BASE 0x80000000
  148 +#define JTAG_ID_REG (DAVINCI_BOOTCFG_BASE + 0x18)
  149 +#define CHIP_REV_ID_REG (DAVINCI_BOOTCFG_BASE + 0x24)
  150 +#define HOST1CFG (DAVINCI_BOOTCFG_BASE + 0x44)
  151 +#define PSC0_MDCTL (DAVINCI_PSC0_BASE + 0xa00)
  152 +
  153 +#define GPIO_BANK0_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x10)
  154 +#define GPIO_BANK0_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x14)
  155 +#define GPIO_BANK0_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x18)
  156 +#define GPIO_BANK0_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x1c)
  157 +#define GPIO_BANK2_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x38)
  158 +#define GPIO_BANK2_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x3c)
  159 +#define GPIO_BANK2_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x40)
  160 +#define GPIO_BANK2_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x44)
  161 +#define GPIO_BANK6_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x88)
  162 +#define GPIO_BANK6_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x8c)
  163 +#define GPIO_BANK6_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x90)
  164 +#define GPIO_BANK6_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x94)
  165 +#endif /* CONFIG_SOC_DA8XX */
  166 +
  167 +/* Power and Sleep Controller (PSC) Domains */
  168 +#define DAVINCI_GPSC_ARMDOMAIN 0
  169 +#define DAVINCI_GPSC_DSPDOMAIN 1
  170 +
  171 +#ifndef CONFIG_SOC_DA8XX
  172 +
  173 +#define DAVINCI_LPSC_VPSSMSTR 0
  174 +#define DAVINCI_LPSC_VPSSSLV 1
  175 +#define DAVINCI_LPSC_TPCC 2
  176 +#define DAVINCI_LPSC_TPTC0 3
  177 +#define DAVINCI_LPSC_TPTC1 4
  178 +#define DAVINCI_LPSC_EMAC 5
  179 +#define DAVINCI_LPSC_EMAC_WRAPPER 6
  180 +#define DAVINCI_LPSC_MDIO 7
  181 +#define DAVINCI_LPSC_IEEE1394 8
  182 +#define DAVINCI_LPSC_USB 9
  183 +#define DAVINCI_LPSC_ATA 10
  184 +#define DAVINCI_LPSC_VLYNQ 11
  185 +#define DAVINCI_LPSC_UHPI 12
  186 +#define DAVINCI_LPSC_DDR_EMIF 13
  187 +#define DAVINCI_LPSC_AEMIF 14
  188 +#define DAVINCI_LPSC_MMC_SD 15
  189 +#define DAVINCI_LPSC_MEMSTICK 16
  190 +#define DAVINCI_LPSC_McBSP 17
  191 +#define DAVINCI_LPSC_I2C 18
  192 +#define DAVINCI_LPSC_UART0 19
  193 +#define DAVINCI_LPSC_UART1 20
  194 +#define DAVINCI_LPSC_UART2 21
  195 +#define DAVINCI_LPSC_SPI 22
  196 +#define DAVINCI_LPSC_PWM0 23
  197 +#define DAVINCI_LPSC_PWM1 24
  198 +#define DAVINCI_LPSC_PWM2 25
  199 +#define DAVINCI_LPSC_GPIO 26
  200 +#define DAVINCI_LPSC_TIMER0 27
  201 +#define DAVINCI_LPSC_TIMER1 28
  202 +#define DAVINCI_LPSC_TIMER2 29
  203 +#define DAVINCI_LPSC_SYSTEM_SUBSYS 30
  204 +#define DAVINCI_LPSC_ARM 31
  205 +#define DAVINCI_LPSC_SCR2 32
  206 +#define DAVINCI_LPSC_SCR3 33
  207 +#define DAVINCI_LPSC_SCR4 34
  208 +#define DAVINCI_LPSC_CROSSBAR 35
  209 +#define DAVINCI_LPSC_CFG27 36
  210 +#define DAVINCI_LPSC_CFG3 37
  211 +#define DAVINCI_LPSC_CFG5 38
  212 +#define DAVINCI_LPSC_GEM 39
  213 +#define DAVINCI_LPSC_IMCOP 40
  214 +#define DAVINCI_LPSC_VPSSMASTER 47
  215 +#define DAVINCI_LPSC_MJCP 50
  216 +#define DAVINCI_LPSC_HDVICP 51
  217 +
  218 +#define DAVINCI_DM646X_LPSC_EMAC 14
  219 +#define DAVINCI_DM646X_LPSC_UART0 26
  220 +#define DAVINCI_DM646X_LPSC_I2C 31
  221 +#define DAVINCI_DM646X_LPSC_TIMER0 34
  222 +
  223 +#else /* CONFIG_SOC_DA8XX */
  224 +
  225 +#define DAVINCI_LPSC_TPCC 0
  226 +#define DAVINCI_LPSC_TPTC0 1
  227 +#define DAVINCI_LPSC_TPTC1 2
  228 +#define DAVINCI_LPSC_AEMIF 3
  229 +#define DAVINCI_LPSC_SPI0 4
  230 +#define DAVINCI_LPSC_MMC_SD 5
  231 +#define DAVINCI_LPSC_AINTC 6
  232 +#define DAVINCI_LPSC_ARM_RAM_ROM 7
  233 +#define DAVINCI_LPSC_SECCTL_KEYMGR 8
  234 +#define DAVINCI_LPSC_UART0 9
  235 +#define DAVINCI_LPSC_SCR0 10
  236 +#define DAVINCI_LPSC_SCR1 11
  237 +#define DAVINCI_LPSC_SCR2 12
  238 +#define DAVINCI_LPSC_DMAX 13
  239 +#define DAVINCI_LPSC_ARM 14
  240 +#define DAVINCI_LPSC_GEM 15
  241 +
  242 +/* for LPSCs in PSC1, offset from 32 for differentiation */
  243 +#define DAVINCI_LPSC_PSC1_BASE 32
  244 +#define DAVINCI_LPSC_USB20 (DAVINCI_LPSC_PSC1_BASE + 1)
  245 +#define DAVINCI_LPSC_USB11 (DAVINCI_LPSC_PSC1_BASE + 2)
  246 +#define DAVINCI_LPSC_GPIO (DAVINCI_LPSC_PSC1_BASE + 3)
  247 +#define DAVINCI_LPSC_UHPI (DAVINCI_LPSC_PSC1_BASE + 4)
  248 +#define DAVINCI_LPSC_EMAC (DAVINCI_LPSC_PSC1_BASE + 5)
  249 +#define DAVINCI_LPSC_DDR_EMIF (DAVINCI_LPSC_PSC1_BASE + 6)
  250 +#define DAVINCI_LPSC_McASP0 (DAVINCI_LPSC_PSC1_BASE + 7)
  251 +#define DAVINCI_LPSC_SPI1 (DAVINCI_LPSC_PSC1_BASE + 10)
  252 +#define DAVINCI_LPSC_I2C1 (DAVINCI_LPSC_PSC1_BASE + 11)
  253 +#define DAVINCI_LPSC_UART1 (DAVINCI_LPSC_PSC1_BASE + 12)
  254 +#define DAVINCI_LPSC_UART2 (DAVINCI_LPSC_PSC1_BASE + 13)
  255 +#define DAVINCI_LPSC_LCDC (DAVINCI_LPSC_PSC1_BASE + 16)
  256 +#define DAVINCI_LPSC_ePWM (DAVINCI_LPSC_PSC1_BASE + 17)
  257 +#define DAVINCI_LPSC_MMCSD1 (DAVINCI_LPSC_PSC1_BASE + 18)
  258 +#define DAVINCI_LPSC_eCAP (DAVINCI_LPSC_PSC1_BASE + 20)
  259 +#define DAVINCI_LPSC_L3_CBA_RAM (DAVINCI_LPSC_PSC1_BASE + 31)
  260 +
  261 +/* DA830-specific peripherals */
  262 +#define DAVINCI_LPSC_McASP1 (DAVINCI_LPSC_PSC1_BASE + 8)
  263 +#define DAVINCI_LPSC_McASP2 (DAVINCI_LPSC_PSC1_BASE + 9)
  264 +#define DAVINCI_LPSC_eQEP (DAVINCI_LPSC_PSC1_BASE + 21)
  265 +#define DAVINCI_LPSC_SCR8 (DAVINCI_LPSC_PSC1_BASE + 24)
  266 +#define DAVINCI_LPSC_SCR7 (DAVINCI_LPSC_PSC1_BASE + 25)
  267 +#define DAVINCI_LPSC_SCR12 (DAVINCI_LPSC_PSC1_BASE + 26)
  268 +
  269 +/* DA850-specific peripherals */
  270 +#define DAVINCI_LPSC_TPCC1 (DAVINCI_LPSC_PSC1_BASE + 0)
  271 +#define DAVINCI_LPSC_SATA (DAVINCI_LPSC_PSC1_BASE + 8)
  272 +#define DAVINCI_LPSC_VPIF (DAVINCI_LPSC_PSC1_BASE + 9)
  273 +#define DAVINCI_LPSC_McBSP0 (DAVINCI_LPSC_PSC1_BASE + 14)
  274 +#define DAVINCI_LPSC_McBSP1 (DAVINCI_LPSC_PSC1_BASE + 15)
  275 +#define DAVINCI_LPSC_MMC_SD1 (DAVINCI_LPSC_PSC1_BASE + 18)
  276 +#define DAVINCI_LPSC_uPP (DAVINCI_LPSC_PSC1_BASE + 19)
  277 +#define DAVINCI_LPSC_TPTC2 (DAVINCI_LPSC_PSC1_BASE + 21)
  278 +#define DAVINCI_LPSC_SCR_F0 (DAVINCI_LPSC_PSC1_BASE + 24)
  279 +#define DAVINCI_LPSC_SCR_F1 (DAVINCI_LPSC_PSC1_BASE + 25)
  280 +#define DAVINCI_LPSC_SCR_F2 (DAVINCI_LPSC_PSC1_BASE + 26)
  281 +#define DAVINCI_LPSC_SCR_F6 (DAVINCI_LPSC_PSC1_BASE + 27)
  282 +#define DAVINCI_LPSC_SCR_F7 (DAVINCI_LPSC_PSC1_BASE + 28)
  283 +#define DAVINCI_LPSC_SCR_F8 (DAVINCI_LPSC_PSC1_BASE + 29)
  284 +#define DAVINCI_LPSC_BR_F7 (DAVINCI_LPSC_PSC1_BASE + 30)
  285 +
  286 +#endif /* CONFIG_SOC_DA8XX */
  287 +
  288 +void lpsc_on(unsigned int id);
  289 +void lpsc_syncreset(unsigned int id);
  290 +void lpsc_disable(unsigned int id);
  291 +void dsp_on(void);
  292 +
  293 +void davinci_enable_uart0(void);
  294 +void davinci_enable_emac(void);
  295 +void davinci_enable_i2c(void);
  296 +void davinci_errata_workarounds(void);
  297 +
  298 +#ifndef CONFIG_SOC_DA8XX
  299 +
  300 +/* Some PSC defines */
  301 +#define PSC_CHP_SHRTSW (0x01c40038)
  302 +#define PSC_GBLCTL (0x01c41010)
  303 +#define PSC_EPCPR (0x01c41070)
  304 +#define PSC_EPCCR (0x01c41078)
  305 +#define PSC_PTCMD (0x01c41120)
  306 +#define PSC_PTSTAT (0x01c41128)
  307 +#define PSC_PDSTAT (0x01c41200)
  308 +#define PSC_PDSTAT1 (0x01c41204)
  309 +#define PSC_PDCTL (0x01c41300)
  310 +#define PSC_PDCTL1 (0x01c41304)
  311 +
  312 +#define PSC_MDCTL_BASE (0x01c41a00)
  313 +#define PSC_MDSTAT_BASE (0x01c41800)
  314 +
  315 +#define VDD3P3V_PWDN (0x01c40048)
  316 +#define UART0_PWREMU_MGMT (0x01c20030)
  317 +
  318 +#define PSC_SILVER_BULLET (0x01c41a20)
  319 +
  320 +#else /* CONFIG_SOC_DA8XX */
  321 +
  322 +#define PSC_ENABLE 0x3
  323 +#define PSC_DISABLE 0x2
  324 +#define PSC_SYNCRESET 0x1
  325 +#define PSC_SWRSTDISABLE 0x0
  326 +
  327 +#define PSC_PSC0_MODULE_ID_CNT 16
  328 +#define PSC_PSC1_MODULE_ID_CNT 32
  329 +
  330 +#define UART0_PWREMU_MGMT (0x01c42030)
  331 +
  332 +struct davinci_psc_regs {
  333 + dv_reg revid;
  334 + dv_reg rsvd0[71];
  335 + dv_reg ptcmd;
  336 + dv_reg rsvd1;
  337 + dv_reg ptstat;
  338 + dv_reg rsvd2[437];
  339 + union {
  340 + struct {
  341 + dv_reg mdstat[PSC_PSC0_MODULE_ID_CNT];
  342 + dv_reg rsvd3[112];
  343 + dv_reg mdctl[PSC_PSC0_MODULE_ID_CNT];
  344 + } psc0;
  345 + struct {
  346 + dv_reg mdstat[PSC_PSC1_MODULE_ID_CNT];
  347 + dv_reg rsvd3[96];
  348 + dv_reg mdctl[PSC_PSC1_MODULE_ID_CNT];
  349 + } psc1;
  350 + };
  351 +};
  352 +
  353 +#define davinci_psc0_regs ((struct davinci_psc_regs *)DAVINCI_PSC0_BASE)
  354 +#define davinci_psc1_regs ((struct davinci_psc_regs *)DAVINCI_PSC1_BASE)
  355 +
  356 +#endif /* CONFIG_SOC_DA8XX */
  357 +
  358 +#define PSC_MDSTAT_STATE 0x3f
  359 +#define PSC_MDCTL_NEXT 0x07
  360 +
  361 +#ifndef CONFIG_SOC_DA8XX
  362 +
  363 +/* Miscellania... */
  364 +#define VBPR (0x20000020)
  365 +
  366 +/* NOTE: system control modules are *highly* chip-specific, both
  367 + * as to register content (e.g. for muxing) and which registers exist.
  368 + */
  369 +#define PINMUX0 0x01c40000
  370 +#define PINMUX1 0x01c40004
  371 +#define PINMUX2 0x01c40008
  372 +#define PINMUX3 0x01c4000c
  373 +#define PINMUX4 0x01c40010
  374 +
  375 +struct davinci_uart_ctrl_regs {
  376 + dv_reg revid1;
  377 + dv_reg res;
  378 + dv_reg pwremu_mgmt;
  379 + dv_reg mdr;
  380 +};
  381 +
  382 +#define DAVINCI_UART_CTRL_BASE 0x28
  383 +
  384 +/* UART PWREMU_MGMT definitions */
  385 +#define DAVINCI_UART_PWREMU_MGMT_FREE (1 << 0)
  386 +#define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13)
  387 +#define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14)
  388 +
  389 +#else /* CONFIG_SOC_DA8XX */
  390 +
  391 +struct davinci_pllc_regs {
  392 + dv_reg revid;
  393 + dv_reg rsvd1[56];
  394 + dv_reg rstype;
  395 + dv_reg rsvd2[6];
  396 + dv_reg pllctl;
  397 + dv_reg ocsel;
  398 + dv_reg rsvd3[2];
  399 + dv_reg pllm;
  400 + dv_reg prediv;
  401 + dv_reg plldiv1;
  402 + dv_reg plldiv2;
  403 + dv_reg plldiv3;
  404 + dv_reg oscdiv;
  405 + dv_reg postdiv;
  406 + dv_reg rsvd4[3];
  407 + dv_reg pllcmd;
  408 + dv_reg pllstat;
  409 + dv_reg alnctl;
  410 + dv_reg dchange;
  411 + dv_reg cken;
  412 + dv_reg ckstat;
  413 + dv_reg systat;
  414 + dv_reg rsvd5[3];
  415 + dv_reg plldiv4;
  416 + dv_reg plldiv5;
  417 + dv_reg plldiv6;
  418 + dv_reg plldiv7;
  419 + dv_reg rsvd6[32];
  420 + dv_reg emucnt0;
  421 + dv_reg emucnt1;
  422 +};
  423 +
  424 +#define davinci_pllc0_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE)
  425 +#define davinci_pllc1_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL1_BASE)
  426 +#define DAVINCI_PLLC_DIV_MASK 0x1f
  427 +
  428 +/*
  429 + * A clock ID is a 32-bit number where bit 16 represents the PLL controller
  430 + * (clear is PLLC0, set is PLLC1) and the low 16 bits represent the divisor,
  431 + * counting from 1. Clock IDs may be passed to clk_get().
  432 + */
  433 +
  434 +/* flags to select PLL controller */
  435 +#define DAVINCI_PLLC0_FLAG (0)
  436 +#define DAVINCI_PLLC1_FLAG (1 << 16)
  437 +
  438 +enum davinci_clk_ids {
  439 + /*
  440 + * Clock IDs for PLL outputs. Each may be switched on/off
  441 + * independently, and each may map to one or more peripherals.
  442 + */
  443 + DAVINCI_PLL0_SYSCLK2 = DAVINCI_PLLC0_FLAG | 2,
  444 + DAVINCI_PLL0_SYSCLK4 = DAVINCI_PLLC0_FLAG | 4,
  445 + DAVINCI_PLL0_SYSCLK6 = DAVINCI_PLLC0_FLAG | 6,
  446 + DAVINCI_PLL1_SYSCLK1 = DAVINCI_PLLC1_FLAG | 1,
  447 + DAVINCI_PLL1_SYSCLK2 = DAVINCI_PLLC1_FLAG | 2,
  448 +
  449 + /* map peripherals to clock IDs */
  450 + DAVINCI_ARM_CLKID = DAVINCI_PLL0_SYSCLK6,
  451 + DAVINCI_DDR_CLKID = DAVINCI_PLL1_SYSCLK1,
  452 + DAVINCI_MDIO_CLKID = DAVINCI_PLL0_SYSCLK4,
  453 + DAVINCI_MMC_CLKID = DAVINCI_PLL0_SYSCLK2,
  454 + DAVINCI_SPI0_CLKID = DAVINCI_PLL0_SYSCLK2,
  455 + DAVINCI_MMCSD_CLKID = DAVINCI_PLL0_SYSCLK2,
  456 +
  457 + /* special clock ID - output of PLL multiplier */
  458 + DAVINCI_PLLM_CLKID = 0x0FF,
  459 +
  460 + /* special clock ID - output of PLL post divisor */
  461 + DAVINCI_PLLC_CLKID = 0x100,
  462 +
  463 + /* special clock ID - PLL bypass */
  464 + DAVINCI_AUXCLK_CLKID = 0x101,
  465 +};
  466 +
  467 +#define DAVINCI_UART2_CLKID (cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \
  468 + : get_async3_src())
  469 +
  470 +#define DAVINCI_SPI1_CLKID (cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \
  471 + : get_async3_src())
  472 +
  473 +int clk_get(enum davinci_clk_ids id);
  474 +
  475 +/* Boot config */
  476 +struct davinci_syscfg_regs {
  477 + dv_reg revid;
  478 + dv_reg rsvd[13];
  479 + dv_reg kick0;
  480 + dv_reg kick1;
  481 + dv_reg rsvd1[52];
  482 + dv_reg mstpri[3];
  483 + dv_reg rsvd2;
  484 + dv_reg pinmux[20];
  485 + dv_reg suspsrc;
  486 + dv_reg chipsig;
  487 + dv_reg chipsig_clr;
  488 + dv_reg cfgchip0;
  489 + dv_reg cfgchip1;
  490 + dv_reg cfgchip2;
  491 + dv_reg cfgchip3;
  492 + dv_reg cfgchip4;
  493 +};
  494 +
  495 +#define davinci_syscfg_regs \
  496 + ((struct davinci_syscfg_regs *)DAVINCI_BOOTCFG_BASE)
  497 +
  498 +#define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
  499 +
  500 +/* Emulation suspend bits */
  501 +#define DAVINCI_SYSCFG_SUSPSRC_EMAC (1 << 5)
  502 +#define DAVINCI_SYSCFG_SUSPSRC_I2C (1 << 16)
  503 +#define DAVINCI_SYSCFG_SUSPSRC_SPI0 (1 << 21)
  504 +#define DAVINCI_SYSCFG_SUSPSRC_SPI1 (1 << 22)
  505 +#define DAVINCI_SYSCFG_SUSPSRC_UART0 (1 << 18)
  506 +#define DAVINCI_SYSCFG_SUSPSRC_UART2 (1 << 20)
  507 +#define DAVINCI_SYSCFG_SUSPSRC_TIMER0 (1 << 27)
  508 +
  509 +struct davinci_syscfg1_regs {
  510 + dv_reg vtpio_ctl;
  511 + dv_reg ddr_slew;
  512 + dv_reg deepsleep;
  513 + dv_reg pupd_ena;
  514 + dv_reg pupd_sel;
  515 + dv_reg rxactive;
  516 + dv_reg pwrdwn;
  517 +};
  518 +
  519 +#define davinci_syscfg1_regs \
  520 + ((struct davinci_syscfg1_regs *)DAVINCI_SYSCFG1_BASE)
  521 +
  522 +#define DDR_SLEW_CMOSEN_BIT 4
  523 +#define DDR_SLEW_DDR_PDENA_BIT 5
  524 +
  525 +#define VTP_POWERDWN (1 << 6)
  526 +#define VTP_LOCK (1 << 7)
  527 +#define VTP_CLKRZ (1 << 13)
  528 +#define VTP_READY (1 << 15)
  529 +#define VTP_IOPWRDWN (1 << 14)
  530 +
  531 +#define DV_SYSCFG_KICK0_UNLOCK 0x83e70b13
  532 +#define DV_SYSCFG_KICK1_UNLOCK 0x95a4f1e0
  533 +
  534 +/* Interrupt controller */
  535 +struct davinci_aintc_regs {
  536 + dv_reg revid;
  537 + dv_reg cr;
  538 + dv_reg dummy0[2];
  539 + dv_reg ger;
  540 + dv_reg dummy1[219];
  541 + dv_reg ecr1;
  542 + dv_reg ecr2;
  543 + dv_reg ecr3;
  544 + dv_reg dummy2[1117];
  545 + dv_reg hier;
  546 +};
  547 +
  548 +#define davinci_aintc_regs ((struct davinci_aintc_regs *)DAVINCI_INTC_BASE)
  549 +
  550 +struct davinci_uart_ctrl_regs {
  551 + dv_reg revid1;
  552 + dv_reg revid2;
  553 + dv_reg pwremu_mgmt;
  554 + dv_reg mdr;
  555 +};
  556 +
  557 +#define DAVINCI_UART_CTRL_BASE 0x28
  558 +#define DAVINCI_UART0_CTRL_ADDR (DAVINCI_UART0_BASE + DAVINCI_UART_CTRL_BASE)
  559 +#define DAVINCI_UART1_CTRL_ADDR (DAVINCI_UART1_BASE + DAVINCI_UART_CTRL_BASE)
  560 +#define DAVINCI_UART2_CTRL_ADDR (DAVINCI_UART2_BASE + DAVINCI_UART_CTRL_BASE)
  561 +
  562 +#define davinci_uart0_ctrl_regs \
  563 + ((struct davinci_uart_ctrl_regs *)DAVINCI_UART0_CTRL_ADDR)
  564 +#define davinci_uart1_ctrl_regs \
  565 + ((struct davinci_uart_ctrl_regs *)DAVINCI_UART1_CTRL_ADDR)
  566 +#define davinci_uart2_ctrl_regs \
  567 + ((struct davinci_uart_ctrl_regs *)DAVINCI_UART2_CTRL_ADDR)
  568 +
  569 +/* UART PWREMU_MGMT definitions */
  570 +#define DAVINCI_UART_PWREMU_MGMT_FREE (1 << 0)
  571 +#define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13)
  572 +#define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14)
  573 +
  574 +static inline int cpu_is_da830(void)
  575 +{
  576 + unsigned int jtag_id = REG(JTAG_ID_REG);
  577 + unsigned short part_no = (jtag_id >> 12) & 0xffff;
  578 +
  579 + return ((part_no == 0xb7df) ? 1 : 0);
  580 +}
  581 +static inline int cpu_is_da850(void)
  582 +{
  583 + unsigned int jtag_id = REG(JTAG_ID_REG);
  584 + unsigned short part_no = (jtag_id >> 12) & 0xffff;
  585 +
  586 + return ((part_no == 0xb7d1) ? 1 : 0);
  587 +}
  588 +
  589 +static inline enum davinci_clk_ids get_async3_src(void)
  590 +{
  591 + return (REG(&davinci_syscfg_regs->cfgchip3) & 0x10) ?
  592 + DAVINCI_PLL1_SYSCLK2 : DAVINCI_PLL0_SYSCLK2;
  593 +}
  594 +
  595 +#endif /* CONFIG_SOC_DA8XX */
  596 +
  597 +#if defined(CONFIG_SOC_DM365)
  598 +#include <asm/arch/aintc_defs.h>
  599 +#include <asm/arch/ddr2_defs.h>
  600 +#include <asm/arch/gpio.h>
  601 +#include <asm/arch/pll_defs.h>
  602 +#include <asm/arch/psc_defs.h>
  603 +#include <asm/arch/syscfg_defs.h>
  604 +#include <asm/arch/timer_defs.h>
  605 +
  606 +#define TMPBUF 0x00017ff8
  607 +#define TMPSTATUS 0x00017ff0
  608 +#define DV_TMPBUF_VAL 0x591b3ed7
  609 +#define FLAG_PORRST 0x00000001
  610 +#define FLAG_WDTRST 0x00000002
  611 +#define FLAG_FLGON 0x00000004
  612 +#define FLAG_FLGOFF 0x00000010
  613 +
  614 +#endif
  615 +
  616 +#endif /* __ASM_ARCH_HARDWARE_H */
arch/arm/mach-davinci/include/mach/i2c_defs.h
Diff comments   View file @ 3d35761
  1 +/*
  2 + * (C) Copyright 2004-2014
  3 + * Texas Instruments, <www.ti.com>
  4 + *
  5 + * Some changes copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
  6 + *
  7 + * SPDX-License-Identifier: GPL-2.0+
  8 + */
  9 +#ifndef _I2C_DEFS_H_
  10 +#define _I2C_DEFS_H_
  11 +
  12 +#ifndef CONFIG_SOC_DA8XX
  13 +#define I2C_BASE 0x01c21000
  14 +#else
  15 +#define I2C_BASE 0x01c22000
  16 +#endif
  17 +
  18 +#endif
arch/arm/mach-davinci/include/mach/pinmux_defs.h
Diff comments   View file @ 3d35761
  1 +/*
  2 + * Pinmux configurations for the DAxxx SoCs
  3 + *
  4 + * Copyright (C) 2011 OMICRON electronics GmbH
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#ifndef __ASM_ARCH_PINMUX_DEFS_H
  10 +#define __ASM_ARCH_PINMUX_DEFS_H
  11 +
  12 +#include <asm/arch/davinci_misc.h>
  13 +#include <config.h>
  14 +
  15 +/* SPI0 pin muxer settings */
  16 +extern const struct pinmux_config spi0_pins_base[3];
  17 +extern const struct pinmux_config spi0_pins_scs0[1];
  18 +extern const struct pinmux_config spi0_pins_ena[1];
  19 +
  20 +/* SPI1 pin muxer settings */
  21 +extern const struct pinmux_config spi1_pins_base[3];
  22 +extern const struct pinmux_config spi1_pins_scs0[1];
  23 +
  24 +/* UART pin muxer settings */
  25 +extern const struct pinmux_config uart0_pins_txrx[2];
  26 +extern const struct pinmux_config uart0_pins_rtscts[2];
  27 +extern const struct pinmux_config uart1_pins_txrx[2];
  28 +extern const struct pinmux_config uart2_pins_txrx[2];
  29 +extern const struct pinmux_config uart2_pins_rtscts[2];
  30 +
  31 +/* EMAC pin muxer settings*/
  32 +extern const struct pinmux_config emac_pins_rmii[8];
  33 +extern const struct pinmux_config emac_pins_rmii_clk_source[1];
  34 +extern const struct pinmux_config emac_pins_mii[15];
  35 +extern const struct pinmux_config emac_pins_mdio[2];
  36 +
  37 +/* I2C pin muxer settings */
  38 +extern const struct pinmux_config i2c0_pins[2];
  39 +extern const struct pinmux_config i2c1_pins[2];
  40 +
  41 +/* EMIFA pin muxer settings */
  42 +extern const struct pinmux_config emifa_pins[40];
  43 +extern const struct pinmux_config emifa_pins_cs0[1];
  44 +extern const struct pinmux_config emifa_pins_cs2[1];
  45 +extern const struct pinmux_config emifa_pins_cs3[1];
  46 +extern const struct pinmux_config emifa_pins_cs4[1];
  47 +extern const struct pinmux_config emifa_pins_nand[12];
  48 +extern const struct pinmux_config emifa_pins_nor[43];
  49 +
  50 +/* USB pin mux setting */
  51 +extern const struct pinmux_config usb_pins[1];
  52 +
  53 +/* MMC pin muxer settings */
  54 +extern const struct pinmux_config mmc0_pins_8bit[10];
  55 +extern const struct pinmux_config mmc0_pins[6];
  56 +
  57 +#endif
arch/arm/mach-davinci/include/mach/pll_defs.h
Diff comments   View file @ 3d35761
  1 +/*
  2 + * Copyright (C) 2011
  3 + * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +#ifndef _DV_PLL_DEFS_H_
  8 +#define _DV_PLL_DEFS_H_
  9 +
  10 +struct dv_pll_regs {
  11 + unsigned int pid; /* 0x00 */
  12 + unsigned char rsvd0[224]; /* 0x04 */
  13 + unsigned int rstype; /* 0xe4 */
  14 + unsigned char rsvd1[24]; /* 0xe8 */
  15 + unsigned int pllctl; /* 0x100 */
  16 + unsigned char rsvd2[4]; /* 0x104 */
  17 + unsigned int secctl; /* 0x108 */
  18 + unsigned int rv; /* 0x10c */
  19 + unsigned int pllm; /* 0x110 */
  20 + unsigned int prediv; /* 0x114 */
  21 + unsigned int plldiv1; /* 0x118 */
  22 + unsigned int plldiv2; /* 0x11c */
  23 + unsigned int plldiv3; /* 0x120 */
  24 + unsigned int oscdiv1; /* 0x124 */
  25 + unsigned int postdiv; /* 0x128 */
  26 + unsigned int bpdiv; /* 0x12c */
  27 + unsigned char rsvd5[8]; /* 0x130 */
  28 + unsigned int pllcmd; /* 0x138 */
  29 + unsigned int pllstat; /* 0x13c */
  30 + unsigned int alnctl; /* 0x140 */
  31 + unsigned int dchange; /* 0x144 */
  32 + unsigned int cken; /* 0x148 */
  33 + unsigned int ckstat; /* 0x14c */
  34 + unsigned int systat; /* 0x150 */
  35 + unsigned char rsvd6[12]; /* 0x154 */
  36 + unsigned int plldiv4; /* 0x160 */
  37 + unsigned int plldiv5; /* 0x164 */
  38 + unsigned int plldiv6; /* 0x168 */
  39 + unsigned int plldiv7; /* 0x16C */
  40 + unsigned int plldiv8; /* 0x170 */
  41 + unsigned int plldiv9; /* 0x174 */
  42 +};
  43 +
  44 +#define PLL_MASTER_LOCK (1 << 4)
  45 +
  46 +#define PLLCTL_CLOCK_MODE_SHIFT 8
  47 +#define PLLCTL_PLLEN (1 << 0)
  48 +#define PLLCTL_PLLPWRDN (1 << 1)
  49 +#define PLLCTL_PLLRST (1 << 3)
  50 +#define PLLCTL_PLLDIS (1 << 4)
  51 +#define PLLCTL_PLLENSRC (1 << 5)
  52 +#define PLLCTL_RES_9 (1 << 8)
  53 +#define PLLCTL_EXTCLKSRC (1 << 9)
  54 +
  55 +#define PLL_DIVEN (1 << 15)
  56 +#define PLL_POSTDEN PLL_DIVEN
  57 +
  58 +#define PLL_SCSCFG3_DIV45PENA (1 << 2)
  59 +#define PLL_SCSCFG3_EMA_CLKSRC (1 << 1)
  60 +
  61 +#define PLL_RSTYPE_POR (1 << 0)
  62 +#define PLL_RSTYPE_XWRST (1 << 1)
  63 +
  64 +#define PLLSECCTL_TINITZ (1 << 16)
  65 +#define PLLSECCTL_TENABLE (1 << 17)
  66 +#define PLLSECCTL_TENABLEDIV (1 << 18)
  67 +#define PLLSECCTL_STOPMODE (1 << 22)
  68 +
  69 +#define PLLCMD_GOSET (1 << 0)
  70 +#define PLLCMD_GOSTAT (1 << 0)
  71 +
  72 +#define PLL0_LOCK 0x07000000
  73 +#define PLL1_LOCK 0x07000000
  74 +
  75 +#define dv_pll0_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL0_BASE)
  76 +#define dv_pll1_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL1_BASE)
  77 +
  78 +#define ARM_PLLDIV (offsetof(struct dv_pll_regs, plldiv2))
  79 +#define DDR_PLLDIV (offsetof(struct dv_pll_regs, plldiv7))
  80 +#define SPI_PLLDIV (offsetof(struct dv_pll_regs, plldiv4))
  81 +
  82 +unsigned int davinci_clk_get(unsigned int div);
  83 +#endif /* _DV_PLL_DEFS_H_ */
arch/arm/mach-davinci/include/mach/psc_defs.h
Diff comments   View file @ 3d35761
  1 +/*
  2 + * Copyright (C) 2011
  3 + * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +#ifndef _DV_PSC_DEFS_H_
  8 +#define _DV_PSC_DEFS_H_
  9 +
  10 +/*
  11 + * Power/Sleep Ctrl Register structure
  12 + * See sprufb3.pdf, Chapter 7
  13 + */
  14 +struct dv_psc_regs {
  15 + unsigned int pid; /* 0x000 */
  16 + unsigned char rsvd0[16]; /* 0x004 */
  17 + unsigned char rsvd1[4]; /* 0x014 */
  18 + unsigned int inteval; /* 0x018 */
  19 + unsigned char rsvd2[36]; /* 0x01C */
  20 + unsigned int merrpr0; /* 0x040 */
  21 + unsigned int merrpr1; /* 0x044 */
  22 + unsigned char rsvd3[8]; /* 0x048 */
  23 + unsigned int merrcr0; /* 0x050 */
  24 + unsigned int merrcr1; /* 0x054 */
  25 + unsigned char rsvd4[8]; /* 0x058 */
  26 + unsigned int perrpr; /* 0x060 */
  27 + unsigned char rsvd5[4]; /* 0x064 */
  28 + unsigned int perrcr; /* 0x068 */
  29 + unsigned char rsvd6[4]; /* 0x06C */
  30 + unsigned int epcpr; /* 0x070 */
  31 + unsigned char rsvd7[4]; /* 0x074 */
  32 + unsigned int epccr; /* 0x078 */
  33 + unsigned char rsvd8[144]; /* 0x07C */
  34 + unsigned char rsvd9[20]; /* 0x10C */
  35 + unsigned int ptcmd; /* 0x120 */
  36 + unsigned char rsvd10[4]; /* 0x124 */
  37 + unsigned int ptstat; /* 0x128 */
  38 + unsigned char rsvd11[212]; /* 0x12C */
  39 + unsigned int pdstat0; /* 0x200 */
  40 + unsigned int pdstat1; /* 0x204 */
  41 + unsigned char rsvd12[248]; /* 0x208 */
  42 + unsigned int pdctl0; /* 0x300 */
  43 + unsigned int pdctl1; /* 0x304 */
  44 + unsigned char rsvd13[536]; /* 0x308 */
  45 + unsigned int mckout0; /* 0x520 */
  46 + unsigned int mckout1; /* 0x524 */
  47 + unsigned char rsvd14[728]; /* 0x528 */
  48 + unsigned int mdstat[52]; /* 0x800 */
  49 + unsigned char rsvd15[304]; /* 0x8D0 */
  50 + unsigned int mdctl[52]; /* 0xA00 */
  51 +};
  52 +
  53 +/* PSC constants */
  54 +#define EMURSTIE_MASK (0x00000200)
  55 +
  56 +#define PD0 (0)
  57 +
  58 +#define PSC_ENABLE (0x3)
  59 +#define PSC_DISABLE (0x2)
  60 +#define PSC_SYNCRESET (0x1)
  61 +#define PSC_SWRSTDISABLE (0x0)
  62 +
  63 +#define PSC_GOSTAT (1 << 0)
  64 +#define PSC_MD_STATE_MSK (0x1f)
  65 +
  66 +#define PSC_CMD_GO (1 << 0)
  67 +
  68 +#define dv_psc_regs ((struct dv_psc_regs *)DAVINCI_PWR_SLEEP_CNTRL_BASE)
  69 +
  70 +#endif /* _DV_PSC_DEFS_H_ */
arch/arm/mach-davinci/include/mach/sdmmc_defs.h
Diff comments   View file @ 3d35761
  1 +/*
  2 + * Davinci MMC Controller Defines - Based on Linux davinci_mmc.c
  3 + *
  4 + * Copyright (C) 2010 Texas Instruments Incorporated
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#ifndef _SDMMC_DEFS_H_
  10 +#define _SDMMC_DEFS_H_
  11 +
  12 +#include <asm/arch/hardware.h>
  13 +
  14 +/* MMC Control Reg fields */
  15 +#define MMCCTL_DATRST (1 << 0)
  16 +#define MMCCTL_CMDRST (1 << 1)
  17 +#define MMCCTL_WIDTH_4_BIT (1 << 2)
  18 +#define MMCCTL_DATEG_DISABLED (0 << 6)
  19 +#define MMCCTL_DATEG_RISING (1 << 6)
  20 +#define MMCCTL_DATEG_FALLING (2 << 6)
  21 +#define MMCCTL_DATEG_BOTH (3 << 6)
  22 +#define MMCCTL_PERMDR_LE (0 << 9)
  23 +#define MMCCTL_PERMDR_BE (1 << 9)
  24 +#define MMCCTL_PERMDX_LE (0 << 10)
  25 +#define MMCCTL_PERMDX_BE (1 << 10)
  26 +
  27 +/* MMC Clock Control Reg fields */
  28 +#define MMCCLK_CLKEN (1 << 8)
  29 +#define MMCCLK_CLKRT_MASK (0xFF << 0)
  30 +
  31 +/* MMC Status Reg0 fields */
  32 +#define MMCST0_DATDNE (1 << 0)
  33 +#define MMCST0_BSYDNE (1 << 1)
  34 +#define MMCST0_RSPDNE (1 << 2)
  35 +#define MMCST0_TOUTRD (1 << 3)
  36 +#define MMCST0_TOUTRS (1 << 4)
  37 +#define MMCST0_CRCWR (1 << 5)
  38 +#define MMCST0_CRCRD (1 << 6)
  39 +#define MMCST0_CRCRS (1 << 7)
  40 +#define MMCST0_DXRDY (1 << 9)
  41 +#define MMCST0_DRRDY (1 << 10)
  42 +#define MMCST0_DATED (1 << 11)
  43 +#define MMCST0_TRNDNE (1 << 12)
  44 +
  45 +#define MMCST0_ERR_MASK (0x00F8)
  46 +
  47 +/* MMC Status Reg1 fields */
  48 +#define MMCST1_BUSY (1 << 0)
  49 +#define MMCST1_CLKSTP (1 << 1)
  50 +#define MMCST1_DXEMP (1 << 2)
  51 +#define MMCST1_DRFUL (1 << 3)
  52 +#define MMCST1_DAT3ST (1 << 4)
  53 +#define MMCST1_FIFOEMP (1 << 5)
  54 +#define MMCST1_FIFOFUL (1 << 6)
  55 +
  56 +/* MMC INT Mask Reg fields */
  57 +#define MMCIM_EDATDNE (1 << 0)
  58 +#define MMCIM_EBSYDNE (1 << 1)
  59 +#define MMCIM_ERSPDNE (1 << 2)
  60 +#define MMCIM_ETOUTRD (1 << 3)
  61 +#define MMCIM_ETOUTRS (1 << 4)
  62 +#define MMCIM_ECRCWR (1 << 5)
  63 +#define MMCIM_ECRCRD (1 << 6)
  64 +#define MMCIM_ECRCRS (1 << 7)
  65 +#define MMCIM_EDXRDY (1 << 9)
  66 +#define MMCIM_EDRRDY (1 << 10)
  67 +#define MMCIM_EDATED (1 << 11)
  68 +#define MMCIM_ETRNDNE (1 << 12)
  69 +
  70 +#define MMCIM_MASKALL (0xFFFFFFFF)
  71 +
  72 +/* MMC Resp Tout Reg fields */
  73 +#define MMCTOR_TOR_MASK (0xFF) /* dont write to reg, | it */
  74 +#define MMCTOR_TOD_20_16_SHIFT (8)
  75 +
  76 +/* MMC Data Read Tout Reg fields */
  77 +#define MMCTOD_TOD_0_15_MASK (0xFFFF)
  78 +
  79 +/* MMC Block len Reg fields */
  80 +#define MMCBLEN_BLEN_MASK (0xFFF)
  81 +
  82 +/* MMC Num Blocks Reg fields */
  83 +#define MMCNBLK_NBLK_MASK (0xFFFF)
  84 +#define MMCNBLK_NBLK_MAX (0xFFFF)
  85 +
  86 +/* MMC Num Blocks Counter Reg fields */
  87 +#define MMCNBLC_NBLC_MASK (0xFFFF)
  88 +
  89 +/* MMC Cmd Reg fields */
  90 +#define MMCCMD_CMD_MASK (0x3F)
  91 +#define MMCCMD_PPLEN (1 << 7)
  92 +#define MMCCMD_BSYEXP (1 << 8)
  93 +#define MMCCMD_RSPFMT_NONE (0 << 9)
  94 +#define MMCCMD_RSPFMT_R1567 (1 << 9)
  95 +#define MMCCMD_RSPFMT_R2 (2 << 9)
  96 +#define MMCCMD_RSPFMT_R3 (3 << 9)
  97 +#define MMCCMD_DTRW (1 << 11)
  98 +#define MMCCMD_STRMTP (1 << 12)
  99 +#define MMCCMD_WDATX (1 << 13)
  100 +#define MMCCMD_INITCK (1 << 14)
  101 +#define MMCCMD_DCLR (1 << 15)
  102 +#define MMCCMD_DMATRIG (1 << 16)
  103 +
  104 +/* FIFO control Reg fields */
  105 +#define MMCFIFOCTL_FIFORST (1 << 0)
  106 +#define MMCFIFOCTL_FIFODIR (1 << 1)
  107 +#define MMCFIFOCTL_FIFOLEV (1 << 2)
  108 +#define MMCFIFOCTL_ACCWD_4 (0 << 3) /* access width of 4 bytes */
  109 +#define MMCFIFOCTL_ACCWD_3 (1 << 3) /* access width of 3 bytes */
  110 +#define MMCFIFOCTL_ACCWD_2 (2 << 3) /* access width of 2 bytes */
  111 +#define MMCFIFOCTL_ACCWD_1 (3 << 3) /* access width of 1 byte */
  112 +
  113 +/* Davinci MMC Register definitions */
  114 +struct davinci_mmc_regs {
  115 + dv_reg mmcctl;
  116 + dv_reg mmcclk;
  117 + dv_reg mmcst0;
  118 + dv_reg mmcst1;
  119 + dv_reg mmcim;
  120 + dv_reg mmctor;
  121 + dv_reg mmctod;
  122 + dv_reg mmcblen;
  123 + dv_reg mmcnblk;
  124 + dv_reg mmcnblc;
  125 + dv_reg mmcdrr;
  126 + dv_reg mmcdxr;
  127 + dv_reg mmccmd;
  128 + dv_reg mmcarghl;
  129 + dv_reg mmcrsp01;
  130 + dv_reg mmcrsp23;
  131 + dv_reg mmcrsp45;
  132 + dv_reg mmcrsp67;
  133 + dv_reg mmcdrsp;
  134 + dv_reg mmcetok;
  135 + dv_reg mmccidx;
  136 + dv_reg mmcckc;
  137 + dv_reg mmctorc;
  138 + dv_reg mmctodc;
  139 + dv_reg mmcblnc;
  140 + dv_reg sdioctl;
  141 + dv_reg sdiost0;
  142 + dv_reg sdioien;
  143 + dv_reg sdioist;
  144 + dv_reg mmcfifoctl;
  145 +};
  146 +
  147 +/* Davinci MMC board definitions */
  148 +struct davinci_mmc {
  149 + struct davinci_mmc_regs *reg_base; /* Register base address */
  150 + uint input_clk; /* Input clock to MMC controller */
  151 + uint host_caps; /* Host capabilities */
  152 + uint voltages; /* Host supported voltages */
  153 + uint version; /* MMC Controller version */
  154 + struct mmc_config cfg;
  155 +};
  156 +
  157 +enum {
  158 + MMC_CTLR_VERSION_1 = 0, /* DM644x and DM355 */
  159 + MMC_CTLR_VERSION_2, /* DA830 */
  160 +};
  161 +
  162 +int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host);
  163 +
  164 +#endif /* _SDMMC_DEFS_H */
arch/arm/mach-davinci/include/mach/syscfg_defs.h
Diff comments   View file @ 3d35761
  1 +/*
  2 + * Copyright (C) 2011
  3 + * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +#ifndef _DV_SYSCFG_DEFS_H_
  8 +#define _DV_SYSCFG_DEFS_H_
  9 +
  10 +#ifndef CONFIG_SOC_DA8XX
  11 +/* System Control Module register structure for DM365 */
  12 +struct dv_sys_module_regs {
  13 + unsigned int pinmux[5]; /* 0x00 */
  14 + unsigned int bootcfg; /* 0x14 */
  15 + unsigned int arm_intmux; /* 0x18 */
  16 + unsigned int edma_evtmux; /* 0x1C */
  17 + unsigned int ddr_slew; /* 0x20 */
  18 + unsigned int clkout; /* 0x24 */
  19 + unsigned int device_id; /* 0x28 */
  20 + unsigned int vdac_config; /* 0x2C */
  21 + unsigned int timer64_ctl; /* 0x30 */
  22 + unsigned int usbbphy_ctl; /* 0x34 */
  23 + unsigned int misc; /* 0x38 */
  24 + unsigned int mstpri[2]; /* 0x3C */
  25 + unsigned int vpss_clkctl; /* 0x44 */
  26 + unsigned int peri_clkctl; /* 0x48 */
  27 + unsigned int deepsleep; /* 0x4C */
  28 + unsigned int dft_enable; /* 0x50 */
  29 + unsigned int debounce[8]; /* 0x54 */
  30 + unsigned int vtpiocr; /* 0x74 */
  31 + unsigned int pupdctl0; /* 0x78 */
  32 + unsigned int pupdctl1; /* 0x7C */
  33 + unsigned int hdimcopbt; /* 0x80 */
  34 + unsigned int pll0_config; /* 0x84 */
  35 + unsigned int pll1_config; /* 0x88 */
  36 +};
  37 +
  38 +#define VPTIO_RDY (1 << 15)
  39 +#define VPTIO_IOPWRDN (1 << 14)
  40 +#define VPTIO_CLRZ (1 << 13)
  41 +#define VPTIO_LOCK (1 << 7)
  42 +#define VPTIO_PWRDN (1 << 6)
  43 +
  44 +#define VPSS_CLK_CTL_VPSS_CLKMD (1 << 7)
  45 +
  46 +#define dv_sys_module_regs \
  47 + ((struct dv_sys_module_regs *)DAVINCI_SYSTEM_MODULE_BASE)
  48 +
  49 +#endif /* !CONFIG_SOC_DA8XX */
  50 +#endif /* _DV_SYSCFG_DEFS_H_ */
arch/arm/mach-davinci/include/mach/timer_defs.h
Diff comments   View file @ 3d35761
  1 +/*
  2 + * Copyright (C) 2011 DENX Software Engineering GmbH
  3 + * Heiko Schocher <hs@denx.de>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +#ifndef _TIMER_DEFS_H_
  8 +#define _TIMER_DEFS_H_
  9 +
  10 +struct davinci_timer {
  11 + u_int32_t pid12;
  12 + u_int32_t emumgt;
  13 + u_int32_t na1;
  14 + u_int32_t na2;
  15 + u_int32_t tim12;
  16 + u_int32_t tim34;
  17 + u_int32_t prd12;
  18 + u_int32_t prd34;
  19 + u_int32_t tcr;
  20 + u_int32_t tgcr;
  21 + u_int32_t wdtcr;
  22 +};
  23 +
  24 +#define DV_TIMER_TCR_ENAMODE_MASK 3
  25 +
  26 +#define DV_TIMER_TCR_ENAMODE12_SHIFT 6
  27 +#define DV_TIMER_TCR_CLKSRC12_SHIFT 8
  28 +#define DV_TIMER_TCR_READRSTMODE12_SHIFT 10
  29 +#define DV_TIMER_TCR_CAPMODE12_SHIFT 11
  30 +#define DV_TIMER_TCR_CAPVTMODE12_SHIFT 12
  31 +#define DV_TIMER_TCR_ENAMODE34_SHIFT 22
  32 +#define DV_TIMER_TCR_CLKSRC34_SHIFT 24
  33 +#define DV_TIMER_TCR_READRSTMODE34_SHIFT 26
  34 +#define DV_TIMER_TCR_CAPMODE34_SHIFT 27
  35 +#define DV_TIMER_TCR_CAPEVTMODE12_SHIFT 28
  36 +
  37 +#define DV_WDT_ENABLE_SYS_RESET 0x00020000
  38 +#define DV_WDT_TRIGGER_SYS_RESET 0x00020002
  39 +
  40 +#ifdef CONFIG_HW_WATCHDOG
  41 +void davinci_hw_watchdog_enable(void);
  42 +void davinci_hw_watchdog_reset(void);
  43 +#endif
  44 +#endif /* _TIMER_DEFS_H_ */