* Patch by Philippe Robin, 09 Mar 2004:

Added ARM Integrator AP, CP and Versatile PB926EJ-S Reference Platform support. * Patch by Masami Komiya, 08 Mar 2004: Don't overwrite server IP address or boot file name when the boot server does not return values * Patch by listmember@orkun.us, 5 Mar 2004: Removed compile time restriction on CFG_I2C_SPEED for DS1338 RTC

* Patch by Philippe Robin, 09 Mar 2004:
Added ARM Integrator AP, CP and Versatile PB926EJ-S Reference Platform support. * Patch by Masami Komiya, 08 Mar 2004: Don't overwrite server IP address or boot file name when the boot server does not return values * Patch by listmember@orkun.us, 5 Mar 2004: Removed compile time restriction on CFG_I2C_SPEED for DS1338 RTC
wdenk
1 parent 4d13cbad1c
Showing 33 changed files with 3640 additions and 23 deletions Side-by-side Diff
CHANGELOG
MAKEALL
Makefile
board/integratorap/Makefile
board/integratorap/config.mk
board/integratorap/flash.c
board/integratorap/integratorap.c
board/integratorap/platform.S
board/integratorap/u-boot.lds
board/integratorcp/Makefile
board/integratorcp/config.mk
board/integratorcp/flash.c
board/integratorcp/integratorcp.c
board/integratorcp/platform.S
board/integratorcp/u-boot.lds
board/versatile/Makefile
board/versatile/config.mk
board/versatile/flash.c
board/versatile/platform.S
board/versatile/u-boot.lds
@@ -2,6 +2,17 @@
 Changes for U-Boot 1.0.2:
 ======================================================================
  
+* Patch by Philippe Robin, 09 Mar 2004:
+  Added ARM Integrator AP, CP and Versatile PB926EJ-S Reference
+  Platform support.
+
+* Patch by Masami Komiya, 08 Mar 2004:
+  Don't overwrite server IP address or boot file name
+  when the boot server does not return values
+
+* Patch by listmember@orkun.us, 5 Mar 2004:
+  Removed compile time restriction on CFG_I2C_SPEED for DS1338 RTC
+
 * Patch by Tolunay Orkun, 5 Mar 2004:
   Fix early board initialization for Cogent CSB272 board
  
@@ -135,9 +135,10 @@
 #########################################################################
  
 LIST_ARM9="	\
-	at91rm9200dk	omap1510inn	omap1610h2	omap1610inn	\
+	at91rm9200dk	integratorcp	integratorap			\
+	omap1510inn	omap1610h2	omap1610inn			\
 	smdk2400	smdk2410	trab				\
-	VCMA9								\
+	VCMA9		versatile					\
 "
  
 #########################################################################
@@ -111,8 +111,9 @@
 .PHONY : $(LIBS)
  
 # Add GCC lib
-PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc
+PLATFORM_LIBS += --no-warn-mismatch -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc
  
+
 # The "tools" are needed early, so put this first
 # Don't include stuff already done in $(LIBS)
 SUBDIRS	= tools \
@@ -926,6 +927,15 @@
  
 SX1_config :		unconfig
 	@./mkconfig $(@:_config=) arm arm925t sx1
+
+integratorcp_config :	unconfig
+	@./mkconfig $(@:_config=) arm arm926ejs integratorcp
+
+integratorap_config :	unconfig
+	@./mkconfig $(@:_config=) arm arm926ejs integratorap
+
+versatile_config :	unconfig
+	@./mkconfig $(@:_config=) arm arm926ejs versatile
  
 omap1510inn_config :	unconfig
 	@./mkconfig $(@:_config=) arm arm925t omap1510inn
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2004
+# ARM Ltd.
+# Philippe Robin, <philippe.robin@arm.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= integratorap.o flash.o
+SOBJS	:= platform.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
+#
+# image should be loaded at 0x01000000 
+#
+
+TEXT_BASE = 0x01000000
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+#define PHYS_FLASH_SECT_SIZE	0x00020000	/* 256 KB sectors (x2) */
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/* Board support for 1 or 2 flash devices */
+#undef FLASH_PORT_WIDTH32
+#define FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#define SWAP(x)			__swab16(x)
+#else
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#define SWAP(x)			__swab32(x)
+#endif
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+
+/* Flash Organization Structure */
+typedef struct OrgDef {
+	unsigned int sector_number;
+	unsigned int sector_size;
+} OrgDef;
+
+
+/* Flash Organizations */
+OrgDef OrgIntel_28F256L18T[] = {
+	{4, 32 * 1024},				/* 4 * 32kBytes sectors */
+	{255, 128 * 1024},			/* 255 * 128kBytes sectors */
+};
+
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+unsigned long flash_init (void);
+static ulong flash_get_size (FPW * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+void inline spin_wheel (void);
+void flash_print_info (flash_info_t * info);
+void flash_unprotect_sectors (FPWV * addr);
+int flash_erase (flash_info_t * info, int s_first, int s_last);
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+			CFG_FLASH_BASE,
+			CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+	OrgDef *pOrgDef;
+
+	pOrgDef = OrgIntel_28F256L18T;
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			if (i > 255) {
+				info->start[i] = base + (i * 0x8000);
+				info->protect[i] = 0;
+			} else {
+				info->start[i] = base +
+						(i * PHYS_FLASH_SECT_SIZE);
+				info->protect[i] = 0;
+			}
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F256L18T:
+		printf ("FLASH 28F256L18T\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW * addr, flash_info_t * info)
+{
+	volatile FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);		/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[1];	/* device ID        */
+	switch (value) {
+
+	case (FPW) (INTEL_ID_28F256L18T):
+		info->flash_id += FLASH_28F256L18T;
+		info->sector_count = 259;
+		info->size = 0x02000000;
+		break;			/* => 32 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+				info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/* unprotects a sector for write and erase
+ * on some intel parts, this unprotects the entire chip, but it
+ * wont hurt to call this additional times per sector...
+ */
+void flash_unprotect_sectors (FPWV * addr)
+{
+#define PD_FINTEL_WSMS_READY_MASK    0x0080
+
+	*addr = (FPW) 0x00500050;	/* clear status register */
+
+	/* this sends the clear lock bit command */
+	*addr = (FPW) 0x00600060;
+	*addr = (FPW) 0x00D000D0;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+				info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+				prot);
+	} else {
+		printf ("\n");
+	}
+
+
+	start = get_timer (0);
+	last = start;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			flash_unprotect_sectors (addr);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			*addr = (FPW) 0x00500050;/* clear status register */
+			*addr = (FPW) 0x00200020;/* erase setup */
+			*addr = (FPW) 0x00D000D0;/* erase confirm */
+
+			while (((status =
+				*addr) & (FPW) 0x00800080) !=
+				(FPW) 0x00800080) {
+					if (get_timer_masked () >
+					CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					/* suspend erase     */
+					*addr = (FPW) 0x00B000B0;
+					/* reset to read mode */
+					*addr = (FPW) 0x00FF00FF;
+					rcode = 1;
+					break;
+				}
+			}
+
+			/* clear status register cmd.   */
+			*addr = (FPW) 0x00500050;
+			*addr = (FPW) 0x00FF00FF;/* resest to read mode */
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	flash_unprotect_sectors (addr);
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_PCI
+#   include <pci.h>
+#endif
+
+void flash__init (void);
+void ether__init (void);
+void peripheral_power_enable (void);
+
+#if defined(CONFIG_SHOW_BOOT_PROGRESS)
+void show_boot_progress(int progress)
+{
+    printf("Boot reached stage %d\n", progress);
+}
+#endif
+
+#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
+
+static inline void delay (unsigned long loops)
+{
+	__asm__ volatile ("1:\n"
+		"subs %0, %1, #1\n"
+		"bne 1b":"=r" (loops):"0" (loops));
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* arch number of Integrator Board */
+	gd->bd->bi_arch_number = 21;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x00000100;
+
+	icache_enable ();
+
+	flash__init ();
+	return 0;
+}
+
+
+int misc_init_r (void)
+{
+#ifdef CONFIG_PCI
+	pci_init();
+#endif
+	setenv("verify", "n");
+	return (0);
+}
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+#ifdef CONFIG_PCI
+
+#ifndef CONFIG_PCI_PNP
+
+static struct pci_config_table pci_integrator_config_table[] = {
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				       PCI_ENET0_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+	{ }
+};
+#endif
+
+// V3 access routines
+#define _V3Write16(o,v) (*(volatile unsigned short *)(PCI_V3_BASE + (unsigned int)(o)) = (unsigned short)(v))
+#define _V3Read16(o)    (*(volatile unsigned short *)(PCI_V3_BASE + (unsigned int)(o)))
+
+#define _V3Write32(o,v) (*(volatile unsigned int *)(PCI_V3_BASE + (unsigned int)(o)) = (unsigned int)(v))
+#define _V3Read32(o)    (*(volatile unsigned int *)(PCI_V3_BASE + (unsigned int)(o)))
+
+// Compute address necessary to access PCI config space for the given
+// bus and device.
+#define PCI_CONFIG_ADDRESS( __bus, __devfn, __offset ) \
+    ({                                                                   		\
+    unsigned int __address, __devicebit;							\
+    unsigned short __mapaddress;								\
+    unsigned int __dev = PCI_DEV(__devfn);	/* FIXME to check!! (slot?) */	\
+											\
+    if (__bus == 0) {									\
+	/* local bus segment so need a type 0 config cycle */				\
+        /* build the PCI configuration "address" with one-hot in A31-A11 */		\
+        __address = PCI_CONFIG_BASE;							\
+        __address |= ((__devfn & 0x07) << 8);						\
+        __address |= __offset & 0xFF;							\
+        __mapaddress = 0x000A;    /* 101=>config cycle, 0=>A1=A0=0 */			\
+        __devicebit = (1 << (__dev + 11));						\
+											\
+        if ((__devicebit & 0xFF000000) != 0) {						\
+            /* high order bits are handled by the MAP register */			\
+            __mapaddress |= (__devicebit >> 16);					\
+        } else {									\
+            /* low order bits handled directly in the address */			\
+            __address |= __devicebit;							\
+        }										\
+    } else {	/* bus !=0 */								\
+        /* not the local bus segment so need a type 1 config cycle */			\
+        /* A31-A24 are don't care (so clear to 0) */					\
+        __mapaddress = 0x000B;    /* 101=>config cycle, 1=>A1&A0 from PCI_CFG */	\
+        __address = PCI_CONFIG_BASE;							\
+        __address |= ((__bus & 0xFF) << 16);  	/* bits 23..16 = bus number 	*/	\
+        __address |= ((__dev & 0x1F) << 11);  	/* bits 15..11 = device number  */	\
+        __address |= ((__devfn & 0x07) << 8);  	/* bits 10..8  = function number*/	\
+        __address |= __offset & 0xFF;  		/* bits  7..0  = register number*/	\
+    }											\
+    _V3Write16(V3_LB_MAP1, __mapaddress);						\
+											\
+    __address;										\
+    })
+
+// _V3OpenConfigWindow - open V3 configuration window
+#define _V3OpenConfigWindow() 							\
+    {										\
+    /* Set up base0 to see all 512Mbytes of memory space (not	     */		\
+    /* prefetchable), this frees up base1 for re-use by configuration*/		\
+    /* memory */								\
+										\
+    _V3Write32 (V3_LB_BASE0, ((INTEGRATOR_PCI_BASE & 0xFFF00000) |		\
+			     0x90 | V3_LB_BASE_M_ENABLE));			\
+    /* Set up base1 to point into configuration space, note that MAP1 */	\
+    /* register is set up by pciMakeConfigAddress(). */				\
+										\
+    _V3Write32 (V3_LB_BASE1, ((CPU_PCI_CNFG_ADRS & 0xFFF00000) |		\
+			     0x40 | V3_LB_BASE_M_ENABLE));			\
+    }
+
+// _V3CloseConfigWindow - close V3 configuration window
+#define _V3CloseConfigWindow()							\
+    {										\
+    /* Reassign base1 for use by prefetchable PCI memory */			\
+    _V3Write32 (V3_LB_BASE1, (((INTEGRATOR_PCI_BASE + 0x10000000) & 0xFFF00000)	\
+					| 0x84 | V3_LB_BASE_M_ENABLE));		\
+    _V3Write16 (V3_LB_MAP1,							\
+	    (((INTEGRATOR_PCI_BASE + 0x10000000) & 0xFFF00000) >> 16) | 0x0006);	\
+										\
+    /* And shrink base0 back to a 256M window (NOTE: MAP0 already correct) */	\
+										\
+    _V3Write32 (V3_LB_BASE0, ((INTEGRATOR_PCI_BASE & 0xFFF00000) |		\
+			     0x80 | V3_LB_BASE_M_ENABLE));			\
+    }
+
+
+static int pci_integrator_read_byte(struct pci_controller *hose, pci_dev_t dev,
+				    int offset, unsigned char *val)
+{
+    _V3OpenConfigWindow();
+    *val = *(volatile unsigned char *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset);
+    _V3CloseConfigWindow();
+
+    return 0;
+}
+
+static int pci_integrator_read__word(struct pci_controller *hose, pci_dev_t dev,
+				     int offset, unsigned short *val)
+{
+    _V3OpenConfigWindow();
+    *val = *(volatile unsigned short *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset);
+    _V3CloseConfigWindow();
+
+    return 0;
+}
+
+static int pci_integrator_read_dword(struct pci_controller *hose, pci_dev_t dev,
+				     int offset, unsigned int *val)
+{
+    _V3OpenConfigWindow();
+    *val = *(volatile unsigned short *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset);
+    *val |= (*(volatile unsigned int *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), (offset+2))) << 16;
+    _V3CloseConfigWindow();
+
+    return 0;
+}
+
+static int pci_integrator_write_byte(struct pci_controller *hose, pci_dev_t dev,
+				     int offset, unsigned char val)
+{
+    _V3OpenConfigWindow();
+    *(volatile unsigned char *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset) = val;
+    _V3CloseConfigWindow();
+
+    return 0;
+}
+
+static int pci_integrator_write_word(struct pci_controller *hose, pci_dev_t dev,
+				     int offset,unsigned short val)
+{
+    _V3OpenConfigWindow();
+    *(volatile unsigned short *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset) = val;
+    _V3CloseConfigWindow();
+
+    return 0;
+}
+
+static int pci_integrator_write_dword(struct pci_controller *hose, pci_dev_t dev,
+				      int offset, unsigned int val)
+{
+    _V3OpenConfigWindow();
+    *(volatile unsigned short *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset) = (val & 0xFFFF);
+    *(volatile unsigned short *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), (offset + 2)) = ((val >> 16) & 0xFFFF);
+    _V3CloseConfigWindow();
+
+    return 0;
+}
+
+/******************************
+ * PCI initialisation
+ ******************************/
+
+struct pci_controller integrator_hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_integrator_config_table,
+#endif
+};
+
+void pci_init_board(void)
+{
+    volatile int i, j;
+    struct pci_controller *hose = &integrator_hose;
+
+    /* setting this register will take the V3 out of reset */
+
+    *(volatile unsigned int *)(INTEGRATOR_SC_PCIENABLE) = 1;
+
+    /* wait a few usecs to settle the device and the PCI bus */
+
+    for (i = 0; i < 100 ; i++)
+	   j = i + 1;
+
+    /* Now write the Base I/O Address Word to V3_BASE + 0x6C */
+
+    *(volatile unsigned short *)(V3_BASE + V3_LB_IO_BASE) = (unsigned short)(V3_BASE >> 16);
+
+    do {
+        *(volatile unsigned char *)(V3_BASE + V3_MAIL_DATA) = 0xAA;
+	*(volatile unsigned char *)(V3_BASE + V3_MAIL_DATA + 4) = 0x55;
+    } while (*(volatile unsigned char *)(V3_BASE + V3_MAIL_DATA) != 0xAA ||
+	     *(volatile unsigned char *)(V3_BASE + V3_MAIL_DATA + 4) != 0x55);
+
+    /* Make sure that V3 register access is not locked, if it is, unlock it */
+
+    if ((*(volatile unsigned short *)(V3_BASE + V3_SYSTEM) & V3_SYSTEM_M_LOCK)
+				== V3_SYSTEM_M_LOCK)
+	*(volatile unsigned short *)(V3_BASE + V3_SYSTEM) = 0xA05F;
+
+    /* Ensure that the slave accesses from PCI are disabled while we */
+    /* setup windows */
+
+    *(volatile unsigned short *)(V3_BASE + V3_PCI_CMD) &=
+				~(V3_COMMAND_M_MEM_EN | V3_COMMAND_M_IO_EN);
+
+    /* Clear RST_OUT to 0; keep the PCI bus in reset until we've finished */
+
+    *(volatile unsigned short *)(V3_BASE + V3_SYSTEM) &= ~V3_SYSTEM_M_RST_OUT;
+
+    /* Make all accesses from PCI space retry until we're ready for them */
+
+    *(volatile unsigned short *)(V3_BASE + V3_PCI_CFG) |= V3_PCI_CFG_M_RETRY_EN;
+
+    /* Set up any V3 PCI Configuration Registers that we absolutely have to */
+    /* LB_CFG controls Local Bus protocol. */
+    /* Enable LocalBus byte strobes for READ accesses too. */
+    /* set bit 7 BE_IMODE and bit 6 BE_OMODE */
+
+    *(volatile unsigned short *)(V3_BASE + V3_LB_CFG) |= 0x0C0;
+
+    /* PCI_CMD controls overall PCI operation. */
+    /* Enable PCI bus master. */
+
+    *(volatile unsigned short *)(V3_BASE + V3_PCI_CMD) |= 0x04;
+
+    /* PCI_MAP0 controls where the PCI to CPU memory window is on Local Bus*/
+
+    *(volatile unsigned int *)(V3_BASE + V3_PCI_MAP0) = (INTEGRATOR_BOOT_ROM_BASE) |
+					(V3_PCI_MAP_M_ADR_SIZE_512M |
+					V3_PCI_MAP_M_REG_EN |
+					V3_PCI_MAP_M_ENABLE);
+
+    /* PCI_BASE0 is the PCI address of the start of the window */
+
+    *(volatile unsigned int *)(V3_BASE + V3_PCI_BASE0) = INTEGRATOR_BOOT_ROM_BASE;
+
+    /* PCI_MAP1 is LOCAL address of the start of the window */
+
+    *(volatile unsigned int *)(V3_BASE + V3_PCI_MAP1) = (INTEGRATOR_HDR0_SDRAM_BASE) |
+			(V3_PCI_MAP_M_ADR_SIZE_1024M | V3_PCI_MAP_M_REG_EN |
+			 V3_PCI_MAP_M_ENABLE);
+
+    /* PCI_BASE1 is the PCI address of the start of the window */
+
+    *(volatile unsigned int *)(V3_BASE + V3_PCI_BASE1) = INTEGRATOR_HDR0_SDRAM_BASE;
+
+    /* Set up the windows from local bus memory into PCI configuration, */
+    /* I/O and Memory. */
+    /* PCI I/O, LB_BASE2 and LB_MAP2 are used exclusively for this. */
+
+    *(volatile unsigned short *)(V3_BASE +V3_LB_BASE2) =
+			((CPU_PCI_IO_ADRS >> 24) << 8) | V3_LB_BASE_M_ENABLE;
+    *(volatile unsigned short *)(V3_BASE + V3_LB_MAP2) = 0;
+
+    /* PCI Configuration, use LB_BASE1/LB_MAP1. */
+
+    /* PCI Memory use LB_BASE0/LB_MAP0 and LB_BASE1/LB_MAP1 */
+    /* Map first 256Mbytes as non-prefetchable via BASE0/MAP0 */
+    /* (INTEGRATOR_PCI_BASE == PCI_MEM_BASE) */
+
+    *(volatile unsigned int *)(V3_BASE + V3_LB_BASE0) =
+			INTEGRATOR_PCI_BASE | (0x80 | V3_LB_BASE_M_ENABLE);
+
+    *(volatile unsigned short *)(V3_BASE + V3_LB_MAP0) =
+			((INTEGRATOR_PCI_BASE >> 20) << 0x4) | 0x0006;
+
+    /* Map second 256 Mbytes as prefetchable via BASE1/MAP1 */
+
+    *(volatile unsigned int *)(V3_BASE + V3_LB_BASE1) =
+			INTEGRATOR_PCI_BASE | (0x84 | V3_LB_BASE_M_ENABLE);
+
+    *(volatile unsigned short *)(V3_BASE + V3_LB_MAP1) =
+			(((INTEGRATOR_PCI_BASE + 0x10000000) >> 20) << 4) | 0x0006;
+
+    /* Allow accesses to PCI Configuration space */
+    /* and set up A1, A0 for type 1 config cycles */
+
+    *(volatile unsigned short *)(V3_BASE + V3_PCI_CFG) =
+			((*(volatile unsigned short *)(V3_BASE + V3_PCI_CFG)) &
+			   ~(V3_PCI_CFG_M_RETRY_EN | V3_PCI_CFG_M_AD_LOW1) ) |
+			   V3_PCI_CFG_M_AD_LOW0;
+
+    /* now we can allow in PCI MEMORY accesses */
+
+    *(volatile unsigned short *)(V3_BASE + V3_PCI_CMD) =
+		(*(volatile unsigned short *)(V3_BASE + V3_PCI_CMD)) | V3_COMMAND_M_MEM_EN;
+
+    /* Set RST_OUT to take the PCI bus is out of reset, PCI devices can */
+    /* initialise and lock the V3 system register so that no one else */
+    /* can play with it */
+
+   *(volatile unsigned short *)(V3_BASE + V3_SYSTEM) =
+		(*(volatile unsigned short *)(V3_BASE + V3_SYSTEM)) | V3_SYSTEM_M_RST_OUT;
+
+   *(volatile unsigned short *)(V3_BASE + V3_SYSTEM) =
+		(*(volatile unsigned short *)(V3_BASE + V3_SYSTEM)) | V3_SYSTEM_M_LOCK;
+
+     /*
+      * Register the hose
+      */
+   hose->first_busno = 0;
+   hose->last_busno = 0xff;
+
+   /* System memory space */
+   pci_set_region(hose->regions + 0,
+		  0x00000000, 0x40000000, 0x01000000,
+		  PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+   /* PCI Memory - config space */
+   pci_set_region(hose->regions + 1,
+		  0x00000000, 0x62000000, 0x01000000,
+		  PCI_REGION_MEM);
+
+   /* PCI V3 regs */
+   pci_set_region(hose->regions + 2,
+		  0x00000000, 0x61000000, 0x00080000,
+		  PCI_REGION_MEM);
+
+   /* PCI I/O space */
+   pci_set_region(hose->regions + 3,
+		  0x00000000, 0x60000000, 0x00010000,
+		  PCI_REGION_IO);
+
+   pci_set_ops(hose,
+	       pci_integrator_read_byte,
+	       pci_integrator_read__word,
+	       pci_integrator_read_dword,
+	       pci_integrator_write_byte,
+	       pci_integrator_write_word,
+	       pci_integrator_write_dword);
+
+   hose->region_count = 4;
+
+   pci_register_hose(hose);
+
+   pciauto_config_init(hose);
+   pciauto_config_device(hose, 0);
+
+   hose->last_busno = pci_hose_scan(hose);
+}
+#endif
+
+/******************************
+ Routine:
+ Description:
+******************************/
+void flash__init (void)
+{
+}
+/*************************************************************
+ Routine:ether__init
+ Description: take the Ethernet controller out of reset and wait
+	  		   for the EEPROM load to complete.
+*************************************************************/
+void ether__init (void)
+{
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+int dram_init (void)
+{
+	return 0;
+}
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2004, ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+.globl platformsetup
+platformsetup:
+
+	/* All done by Integrator's boot monitor! */
+	mov pc, lr
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+	. = ALIGN(4);
+	.text	:
+	{
+	  cpu/arm926ejs/start.o	(.text)
+	  *(.text)
+	}
+	.rodata : { *(.rodata) }
+	. = ALIGN(4);
+	.data : { *(.data) }
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	armboot_end_data = .;
+	. = ALIGN(4);
+	.bss : { *(.bss) }
+	armboot_end = .;
+}
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= integratorcp.o flash.o
+SOBJS	:= platform.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
+#
+# image should be loaded at 0x01000000 
+#
+
+TEXT_BASE = 0x01000000
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+#define PHYS_FLASH_SECT_SIZE	0x00020000	/* 256 KB sectors (x2) */
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/* Board support for 1 or 2 flash devices */
+#undef FLASH_PORT_WIDTH32
+#define FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#define SWAP(x)			__swab16(x)
+#else
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#define SWAP(x)			__swab32(x)
+#endif
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+
+/* Flash Organization Structure */
+typedef struct OrgDef {
+	unsigned int sector_number;
+	unsigned int sector_size;
+} OrgDef;
+
+
+/* Flash Organizations */
+OrgDef OrgIntel_28F256L18T[] = {
+	{4, 32 * 1024},				/* 4 * 32kBytes sectors */
+	{255, 128 * 1024},			/* 255 * 128kBytes sectors */
+};
+
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+unsigned long flash_init (void);
+static ulong flash_get_size (FPW * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+void inline spin_wheel (void);
+void flash_print_info (flash_info_t * info);
+void flash_unprotect_sectors (FPWV * addr);
+int flash_erase (flash_info_t * info, int s_first, int s_last);
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+			CFG_FLASH_BASE,
+			CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+	OrgDef *pOrgDef;
+
+	pOrgDef = OrgIntel_28F256L18T;
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			if (i > 255) {
+				info->start[i] = base + (i * 0x8000);
+				info->protect[i] = 0;
+			} else {
+				info->start[i] = base +
+						(i * PHYS_FLASH_SECT_SIZE);
+				info->protect[i] = 0;
+			}
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F256L18T:
+		printf ("FLASH 28F256L18T\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW * addr, flash_info_t * info)
+{
+	volatile FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);		/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[1];	/* device ID        */
+	switch (value) {
+
+	case (FPW) (INTEL_ID_28F256L18T):
+		info->flash_id += FLASH_28F256L18T;
+		info->sector_count = 259;
+		info->size = 0x02000000;
+		break;			/* => 32 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+				info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/* unprotects a sector for write and erase
+ * on some intel parts, this unprotects the entire chip, but it
+ * wont hurt to call this additional times per sector...
+ */
+void flash_unprotect_sectors (FPWV * addr)
+{
+#define PD_FINTEL_WSMS_READY_MASK    0x0080
+
+	*addr = (FPW) 0x00500050;	/* clear status register */
+
+	/* this sends the clear lock bit command */
+	*addr = (FPW) 0x00600060;
+	*addr = (FPW) 0x00D000D0;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+				info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+				prot);
+	} else {
+		printf ("\n");
+	}
+
+
+	start = get_timer (0);
+	last = start;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			flash_unprotect_sectors (addr);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			*addr = (FPW) 0x00500050;/* clear status register */
+			*addr = (FPW) 0x00200020;/* erase setup */
+			*addr = (FPW) 0x00D000D0;/* erase confirm */
+
+			while (((status =
+				*addr) & (FPW) 0x00800080) !=
+				(FPW) 0x00800080) {
+					if (get_timer_masked () >
+					CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					/* suspend erase     */
+					*addr = (FPW) 0x00B000B0;
+					/* reset to read mode */
+					*addr = (FPW) 0x00FF00FF;
+					rcode = 1;
+					break;
+				}
+			}
+
+			/* clear status register cmd.   */
+			*addr = (FPW) 0x00500050;
+			*addr = (FPW) 0x00FF00FF;/* resest to read mode */
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	flash_unprotect_sectors (addr);
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+void flash__init (void);
+void ether__init (void);
+void peripheral_power_enable (void);
+
+#if defined(CONFIG_SHOW_BOOT_PROGRESS)
+void show_boot_progress(int progress)
+{
+    printf("Boot reached stage %d\n", progress);
+}
+#endif
+
+#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
+
+static inline void delay (unsigned long loops)
+{
+	__asm__ volatile ("1:\n"
+		"subs %0, %1, #1\n"
+		"bne 1b":"=r" (loops):"0" (loops));
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* arch number of Integrator Board */
+	gd->bd->bi_arch_number = 275;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x00000100;
+
+	icache_enable ();
+
+	flash__init ();
+	ether__init ();
+	return 0;
+}
+
+
+int misc_init_r (void)
+{
+	setenv("verify", "n");
+	return (0);
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+void flash__init (void)
+{
+}
+/*************************************************************
+ Routine:ether__init
+ Description: take the Ethernet controller out of reset and wait
+	  		   for the EEPROM load to complete.
+*************************************************************/
+void ether__init (void)
+{
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+int dram_init (void)
+{
+	return 0;
+}
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2003, ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+.globl platformsetup
+platformsetup:
+
+	/* All done by IntegratorCP's boot monitor! */
+	mov pc, lr
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+	. = ALIGN(4);
+	.text	:
+	{
+	  cpu/arm926ejs/start.o	(.text)
+	  *(.text)
+	}
+	.rodata : { *(.rodata) }
+	. = ALIGN(4);
+	.data : { *(.data) }
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	armboot_end_data = .;
+	. = ALIGN(4);
+	.bss : { *(.bss) }
+	armboot_end = .;
+}
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= versatile.o flash.o
+SOBJS	:= platform.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
+#
+# image should be loaded at 0x01000000 
+#
+
+TEXT_BASE = 0x01000000
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+#define PHYS_FLASH_SECT_SIZE	0x00020000	/* 256 KB sectors (x2) */
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/* Board support for 1 or 2 flash devices */
+#undef FLASH_PORT_WIDTH32
+#define FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#define SWAP(x)			__swab16(x)
+#else
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#define SWAP(x)			__swab32(x)
+#endif
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+
+/* Flash Organization Structure */
+typedef struct OrgDef {
+	unsigned int sector_number;
+	unsigned int sector_size;
+} OrgDef;
+
+
+/* Flash Organizations */
+OrgDef OrgIntel_28F256L18T[] = {
+	{4, 32 * 1024},				/* 4 * 32kBytes sectors */
+	{255, 128 * 1024},			/* 255 * 128kBytes sectors */
+};
+
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+unsigned long flash_init (void);
+static ulong flash_get_size (FPW * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+void inline spin_wheel (void);
+void flash_print_info (flash_info_t * info);
+void flash_unprotect_sectors (FPWV * addr);
+int flash_erase (flash_info_t * info, int s_first, int s_last);
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+			CFG_FLASH_BASE,
+			CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+	OrgDef *pOrgDef;
+
+	pOrgDef = OrgIntel_28F256L18T;
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			if (i > 255) {
+				info->start[i] = base + (i * 0x8000);
+				info->protect[i] = 0;
+			} else {
+				info->start[i] = base +
+						(i * PHYS_FLASH_SECT_SIZE);
+				info->protect[i] = 0;
+			}
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F256L18T:
+		printf ("FLASH 28F256L18T\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW * addr, flash_info_t * info)
+{
+	volatile FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);		/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[1];	/* device ID        */
+	switch (value) {
+
+	case (FPW) (INTEL_ID_28F256L18T):
+		info->flash_id += FLASH_28F256L18T;
+		info->sector_count = 259;
+		info->size = 0x02000000;
+		break;			/* => 32 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+				info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/* unprotects a sector for write and erase
+ * on some intel parts, this unprotects the entire chip, but it
+ * wont hurt to call this additional times per sector...
+ */
+void flash_unprotect_sectors (FPWV * addr)
+{
+#define PD_FINTEL_WSMS_READY_MASK    0x0080
+
+	*addr = (FPW) 0x00500050;	/* clear status register */
+
+	/* this sends the clear lock bit command */
+	*addr = (FPW) 0x00600060;
+	*addr = (FPW) 0x00D000D0;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+				info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+				prot);
+	} else {
+		printf ("\n");
+	}
+
+
+	start = get_timer (0);
+	last = start;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			flash_unprotect_sectors (addr);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			*addr = (FPW) 0x00500050;/* clear status register */
+			*addr = (FPW) 0x00200020;/* erase setup */
+			*addr = (FPW) 0x00D000D0;/* erase confirm */
+
+			while (((status =
+				*addr) & (FPW) 0x00800080) !=
+				(FPW) 0x00800080) {
+					if (get_timer_masked () >
+					CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					/* suspend erase     */
+					*addr = (FPW) 0x00B000B0;
+					/* reset to read mode */
+					*addr = (FPW) 0x00FF00FF;
+					rcode = 1;
+					break;
+				}
+			}
+
+			/* clear status register cmd.   */
+			*addr = (FPW) 0x00500050;
+			*addr = (FPW) 0x00FF00FF;/* resest to read mode */
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	flash_unprotect_sectors (addr);
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2003, ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+.globl platformsetup
+platformsetup:
+
+	/* All done by Versatile's boot monitor! */
+	mov pc, lr
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+	. = ALIGN(4);
+	.text	:
+	{
+	  cpu/arm926ejs/start.o	(.text)
+	  *(.text)
+	}
+	.rodata : { *(.rodata) }
+	. = ALIGN(4);
+	.data : { *(.data) }
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	armboot_end_data = .;
+	. = ALIGN(4);
+	.bss : { *(.bss) }
+	armboot_end = .;
+}
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+void flash__init (void);
+void ether__init (void);
+void peripheral_power_enable (void);
+
+#if defined(CONFIG_SHOW_BOOT_PROGRESS)
+void show_boot_progress(int progress)
+{
+    printf("Boot reached stage %d\n", progress);
+}
+#endif
+
+#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
+
+static inline void delay (unsigned long loops)
+{
+	__asm__ volatile ("1:\n"
+		"subs %0, %1, #1\n"
+		"bne 1b":"=r" (loops):"0" (loops));
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+
+	/*
+	 * set clock frequency:
+	 *	VERSATILE_REFCLK is 32KHz
+	 *	VERSATILE_TIMCLK is 1MHz
+	 */
+	*(volatile unsigned int *)(VERSATILE_SCTL_BASE) |=
+	  ((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
+	   (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel));
+
+	/* arch number of Versatile Board */
+	gd->bd->bi_arch_number = 387;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x00000100;
+
+	icache_enable ();
+
+	flash__init ();
+	ether__init ();
+	return 0;
+}
+
+
+int misc_init_r (void)
+{
+	setenv("verify", "n");
+	return (0);
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+void flash__init (void)
+{
+}
+/*************************************************************
+ Routine:ether__init
+ Description: take the Ethernet controller out of reset and wait
+	  		   for the EEPROM load to complete.
+*************************************************************/
+void ether__init (void)
+{
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+int dram_init (void)
+{
+	return 0;
+}
@@ -10,9 +10,12 @@
  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  * Alex Zuepke <azu@sysgo.de>
  *
- * (C) Copyright 2002
+ * (C) Copyright 2002-2004
  * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
  *
+ * (C) Copyright 2004
+ * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  
@@ -41,7 +44,15 @@
 #define TIMER_LOAD_VAL 0xffffffff
  
 /* macro to read the 32 bit timer */
+#ifdef CONFIG_OMAP
 #define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+8))
+#endif
+#ifdef CONFIG_INTEGRATOR
+#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+4))
+#endif
+#ifdef CONFIG_VERSATILE
+#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+4))
+#endif
  
 #ifdef CONFIG_USE_IRQ
 /* enable IRQ interrupts */
  
@@ -182,12 +193,26 @@
 /* nothing really to do with interrupts, just starts up a counter. */
 int interrupt_init (void)
 {
+#ifdef CONFIG_OMAP
 	int32_t val;
  
 	/* Start the decrementer ticking down from 0xffffffff */
 	*((int32_t *) (CFG_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL;
 	val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CFG_PVT << MPUTIM_PTV_BIT);
 	*((int32_t *) (CFG_TIMERBASE + CNTL_TIMER)) = val;
+#endif	/* CONFIG_OMAP */
+#ifdef CONFIG_INTEGRATOR
+	/* Load timer with initial value */
+	*(volatile ulong *)(CFG_TIMERBASE + 0) = TIMER_LOAD_VAL;
+	/* Set timer to be enabled, free-running, no interrupts, 256 divider */
+	*(volatile ulong *)(CFG_TIMERBASE + 8) = 0x8C;
+#endif	/* CONFIG_INTEGRATOR */
+#ifdef CONFIG_VERSATILE
+	*(volatile ulong *)(CFG_TIMERBASE + 0) = CFG_TIMER_RELOAD;	/* TimerLoad */
+	*(volatile ulong *)(CFG_TIMERBASE + 4) = CFG_TIMER_RELOAD;	/* TimerValue */
+	*(volatile ulong *)(CFG_TIMERBASE + 8) = 0x8C;
+	/* *(volatile ulong *)(CFG_TIMERBASE + 8) = CFG_TIMER_CTRL | 0x40;  Periodic */
+#endif	/* CONFIG_VERSATILE */
  
 	/* init the timestamp and lastdec value */
 	reset_timer_masked();
@@ -38,7 +38,8 @@
 	  pcnet.o plb2800_eth.o \
 	  ps2ser.o ps2mult.o pc_keyb.o keyboard.o \
 	  rtl8019.o rtl8139.o \
-	  s3c24x0_i2c.o sed13806.o serial.o serial_max3100.o \
+	  s3c24x0_i2c.o sed13806.o \
+	  serial.o serial_max3100.o serial_pl011.o serial_pl010.o \
 	  smc91111.o smiLynxEM.o status_led.o sym53c8xx.o \
 	  ti_pci1410a.o tigon3.o w83c553f.o omap1510_i2c.o \
 	  usbdcore.o usbdcore_ep0.o usbdcore_omap1510.o usbtty.o
+/*
+ * (C) Copyright 2000
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Simple U-Boot driver for the PrimeCell PL011 UARTs on the IntegratorCP */
+/* Should be fairly simple to make it work with the PL010 as well */
+
+#include <common.h>
+
+#ifdef CFG_PL010_SERIAL
+
+#include "serial_pl011.h"
+
+#define IO_WRITE(addr, val) (*(volatile unsigned int *)(addr) = (val))
+#define IO_READ(addr) (*(volatile unsigned int *)(addr))
+
+/* Integrator AP has two UARTs, we use the first one, at 38400-8-N-1 */
+#define NUM_PORTS 2
+#define CONSOLE_PORT CONFIG_CONS_INDEX
+#define baudRate CONFIG_BAUDRATE
+static volatile unsigned char * const port[NUM_PORTS] = {(void*)(CFG_SERIAL0),
+                                                         (void*)(CFG_SERIAL1)};
+
+
+static void pl010_putc(int portnum, char c);
+static int pl010_getc(int portnum);
+static int pl010_tstc(int portnum);
+
+
+int serial_init (void)
+{
+    unsigned int temp;
+    unsigned int divisor;
+
+    /*
+    ** First, disable everything.
+    */
+    IO_WRITE(port[CONSOLE_PORT] + UART_PL010_CR, 0x0);
+
+    /*
+    ** Set baud rate
+    **
+    */
+    switch (baudRate) {
+    case 9600:
+      divisor = UART_PL010_BAUD_9600;
+      break;
+
+    case 19200:
+      divisor = UART_PL010_BAUD_9600;
+      break;
+
+    case 38400:
+      divisor = UART_PL010_BAUD_38400;
+      break;
+
+    case 57600:
+      divisor = UART_PL010_BAUD_57600;
+      break;
+
+    case 115200:
+      divisor = UART_PL010_BAUD_115200;
+      break;
+
+    default:
+      divisor = UART_PL010_BAUD_38400;
+    }
+ 
+    IO_WRITE(port[CONSOLE_PORT] + UART_PL010_LCRM, ((divisor & 0xf00) >> 8));
+    IO_WRITE(port[CONSOLE_PORT] + UART_PL010_LCRL, (divisor & 0xff));
+
+    /*
+    ** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled.
+    */
+    IO_WRITE(port[CONSOLE_PORT] + UART_PL010_LCRH,
+        (UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN));
+
+    /*
+    ** Finally, enable the UART
+    */
+    IO_WRITE(port[CONSOLE_PORT] + UART_PL010_CR, (UART_PL010_CR_UARTEN));
+
+    return (0);
+}
+
+void
+serial_putc(const char c)
+{
+	if (c == '\n')
+		pl010_putc(CONSOLE_PORT, '\r');
+
+	pl010_putc(CONSOLE_PORT, c);
+}
+
+void
+serial_puts (const char *s)
+{
+	while (*s) {
+		serial_putc (*s++);
+	}
+}
+
+int
+serial_getc(void)
+{
+	return pl010_getc(CONSOLE_PORT);
+}
+
+int
+serial_tstc(void)
+{
+	return pl010_tstc(CONSOLE_PORT);
+}
+
+void
+serial_setbrg (void)
+{
+}
+
+static void pl010_putc(int portnum, char c)
+{
+    /* Wait until there is space in the FIFO */
+    while (IO_READ(port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF);
+    
+    /* Send the character */
+    IO_WRITE(port[portnum] + UART_PL01x_DR, c);
+}
+
+static int pl010_getc(int portnum)
+{
+    unsigned int data;
+
+    /* Wait until there is data in the FIFO */
+    while (IO_READ(port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE);
+    
+    data = IO_READ(port[portnum] + UART_PL01x_DR);
+    
+    /* Check for an error flag */
+    if (data & 0xFFFFFF00)
+    {
+        /* Clear the error */
+        IO_WRITE(port[portnum] + UART_PL01x_ECR, 0xFFFFFFFF);
+        return -1;
+    }
+    
+    return (int)data;
+}
+
+static int pl010_tstc(int portnum)
+{
+    return !(IO_READ(port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE);
+}
+
+#endif
+/*
+ * (C) Copyright 2000
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Simple U-Boot driver for the PrimeCell PL011 UARTs on the IntegratorCP */
+/* Should be fairly simple to make it work with the PL010 as well */
+
+#include <common.h>
+
+#ifdef CFG_PL011_SERIAL
+
+#include "serial_pl011.h"
+
+#define IO_WRITE(addr, val) (*(volatile unsigned int *)(addr) = (val))
+#define IO_READ(addr) (*(volatile unsigned int *)(addr))
+
+/*
+ * IntegratorCP has two UARTs, use the first one, at 38400-8-N-1 
+ * Versatile PB has four UARTs.
+ */
+#define NUM_PORTS 2
+#define CONSOLE_PORT CONFIG_CONS_INDEX
+#define baudRate CONFIG_BAUDRATE
+static volatile unsigned char * const port[NUM_PORTS] = {(void*)(CFG_SERIAL0),
+                                                         (void*)(CFG_SERIAL1)};
+
+
+static void pl011_putc(int portnum, char c);
+static int pl011_getc(int portnum);
+static int pl011_tstc(int portnum);
+
+
+int serial_init (void)
+{
+    unsigned int temp;
+    unsigned int divider;
+    unsigned int remainder;
+    unsigned int fraction;
+
+    /*
+    ** First, disable everything.
+    */
+    IO_WRITE(port[CONSOLE_PORT] + UART_PL011_CR, 0x0);
+
+    /*
+    ** Set baud rate
+    **
+    ** IBRD = UART_CLK / (16 * BAUD_RATE)
+    ** FBRD = ROUND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) / (16 * BAUD_RATE))
+    */
+#ifdef CONFIG_VERSATILE
+    temp      = 16 * baudRate;
+    divider   = 24000000 / temp;
+    remainder = 24000000 % temp;
+    temp      = (8 * remainder) / baudRate;
+    fraction  = (temp >> 1) + (temp & 1);
+#endif
+#ifdef CONFIG_INTEGRATOR
+    temp      = 16 * baudRate;
+    divider   = 14745600 / temp;
+    remainder = 14745600 % temp;
+    temp      = (8 * remainder) / baudRate;
+    fraction  = (temp >> 1) + (temp & 1);
+#endif
+ 
+    IO_WRITE(port[CONSOLE_PORT] + UART_PL011_IBRD, divider);
+    IO_WRITE(port[CONSOLE_PORT] + UART_PL011_FBRD, fraction);
+
+    /*
+    ** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled.
+    */
+    IO_WRITE(port[CONSOLE_PORT] + UART_PL011_LCRH,
+        (UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN));
+
+    /*
+    ** Finally, enable the UART
+    */
+    IO_WRITE(port[CONSOLE_PORT] + UART_PL011_CR,
+        (UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE));
+
+    return (0);
+}
+
+void
+serial_putc(const char c)
+{
+	if (c == '\n')
+		pl011_putc(CONSOLE_PORT, '\r');
+
+	pl011_putc(CONSOLE_PORT, c);
+}
+
+void
+serial_puts (const char *s)
+{
+	while (*s) {
+		serial_putc (*s++);
+	}
+}
+
+int
+serial_getc(void)
+{
+	return pl011_getc(CONSOLE_PORT);
+}
+
+int
+serial_tstc(void)
+{
+	return pl011_tstc(CONSOLE_PORT);
+}
+
+void
+serial_setbrg (void)
+{
+}
+
+static void pl011_putc(int portnum, char c)
+{
+    /* Wait until there is space in the FIFO */
+    while (IO_READ(port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF);
+    
+    /* Send the character */
+    IO_WRITE(port[portnum] + UART_PL01x_DR, c);
+}
+
+static int pl011_getc(int portnum)
+{
+    unsigned int data;
+
+    /* Wait until there is data in the FIFO */
+    while (IO_READ(port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE);
+    
+    data = IO_READ(port[portnum] + UART_PL01x_DR);
+    
+    /* Check for an error flag */
+    if (data & 0xFFFFFF00)
+    {
+        /* Clear the error */
+        IO_WRITE(port[portnum] + UART_PL01x_ECR, 0xFFFFFFFF);
+        return -1;
+    }
+    
+    return (int)data;
+}
+
+static int pl011_tstc(int portnum)
+{
+    return !(IO_READ(port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE);
+}
+
+#endif
+/*
+ * (C) Copyright 2003, 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * ARM PrimeCell UART's (PL010 & PL011) 
+ * ------------------------------------
+ *  
+ *  Definitions common to both PL010 & PL011
+ * 
+ */
+#define UART_PL01x_DR                   0x00	 /*  Data read or written from the interface. */
+#define UART_PL01x_RSR                  0x04	 /*  Receive status register (Read). */
+#define UART_PL01x_ECR                  0x04	 /*  Error clear register (Write). */
+#define UART_PL01x_FR                   0x18	 /*  Flag register (Read only). */
+
+#define UART_PL01x_RSR_OE               0x08
+#define UART_PL01x_RSR_BE               0x04
+#define UART_PL01x_RSR_PE               0x02
+#define UART_PL01x_RSR_FE               0x01
+
+#define UART_PL01x_FR_TXFE              0x80
+#define UART_PL01x_FR_RXFF              0x40
+#define UART_PL01x_FR_TXFF              0x20
+#define UART_PL01x_FR_RXFE              0x10
+#define UART_PL01x_FR_BUSY              0x08
+#define UART_PL01x_FR_TMSK              (UART_PL01x_FR_TXFF + UART_PL01x_FR_BUSY)
+
+/* 
+ *  PL010 definitions
+ * 
+ */
+#define UART_PL010_LCRH                 0x08	 /*  Line control register, high byte. */
+#define UART_PL010_LCRM                 0x0C	 /*  Line control register, middle byte. */
+#define UART_PL010_LCRL                 0x10	 /*  Line control register, low byte. */
+#define UART_PL010_CR                   0x14	 /*  Control register. */
+#define UART_PL010_IIR                  0x1C	 /*  Interrupt indentification register (Read). */
+#define UART_PL010_ICR                  0x1C	 /*  Interrupt clear register (Write). */
+#define UART_PL010_ILPR                 0x20	 /*  IrDA low power counter register. */
+ 
+#define UART_PL010_CR_LPE               (1 << 7)
+#define UART_PL010_CR_RTIE              (1 << 6)
+#define UART_PL010_CR_TIE               (1 << 5)
+#define UART_PL010_CR_RIE               (1 << 4)
+#define UART_PL010_CR_MSIE              (1 << 3)
+#define UART_PL010_CR_IIRLP             (1 << 2)
+#define UART_PL010_CR_SIREN             (1 << 1)
+#define UART_PL010_CR_UARTEN            (1 << 0)
+ 
+#define UART_PL010_LCRH_WLEN_8          (3 << 5)
+#define UART_PL010_LCRH_WLEN_7          (2 << 5)
+#define UART_PL010_LCRH_WLEN_6          (1 << 5)
+#define UART_PL010_LCRH_WLEN_5          (0 << 5)
+#define UART_PL010_LCRH_FEN             (1 << 4)
+#define UART_PL010_LCRH_STP2            (1 << 3)
+#define UART_PL010_LCRH_EPS             (1 << 2)
+#define UART_PL010_LCRH_PEN             (1 << 1)
+#define UART_PL010_LCRH_BRK             (1 << 0)
+
+
+#define UART_PL010_BAUD_460800            1
+#define UART_PL010_BAUD_230400            3
+#define UART_PL010_BAUD_115200            7
+#define UART_PL010_BAUD_57600             15
+#define UART_PL010_BAUD_38400             23
+#define UART_PL010_BAUD_19200             47
+#define UART_PL010_BAUD_14400             63
+#define UART_PL010_BAUD_9600              95
+#define UART_PL010_BAUD_4800              191
+#define UART_PL010_BAUD_2400              383
+#define UART_PL010_BAUD_1200              767
+/* 
+ *  PL011 definitions
+ * 
+ */
+#define UART_PL011_IBRD                 0x24
+#define UART_PL011_FBRD                 0x28
+#define UART_PL011_LCRH                 0x2C
+#define UART_PL011_CR                   0x30
+#define UART_PL011_IMSC                 0x38
+#define UART_PL011_PERIPH_ID0           0xFE0
+ 
+#define UART_PL011_LCRH_SPS             (1 << 7)
+#define UART_PL011_LCRH_WLEN_8          (3 << 5)
+#define UART_PL011_LCRH_WLEN_7          (2 << 5)
+#define UART_PL011_LCRH_WLEN_6          (1 << 5)
+#define UART_PL011_LCRH_WLEN_5          (0 << 5)
+#define UART_PL011_LCRH_FEN             (1 << 4)
+#define UART_PL011_LCRH_STP2            (1 << 3)
+#define UART_PL011_LCRH_EPS             (1 << 2)
+#define UART_PL011_LCRH_PEN             (1 << 1)
+#define UART_PL011_LCRH_BRK             (1 << 0)
+
+#define UART_PL011_CR_CTSEN             (1 << 15)
+#define UART_PL011_CR_RTSEN             (1 << 14)
+#define UART_PL011_CR_OUT2              (1 << 13)
+#define UART_PL011_CR_OUT1              (1 << 12)
+#define UART_PL011_CR_RTS               (1 << 11)
+#define UART_PL011_CR_DTR               (1 << 10)
+#define UART_PL011_CR_RXE               (1 << 9)
+#define UART_PL011_CR_TXE               (1 << 8)
+#define UART_PL011_CR_LPE               (1 << 7)
+#define UART_PL011_CR_IIRLP             (1 << 2)
+#define UART_PL011_CR_SIREN             (1 << 1)
+#define UART_PL011_CR_UARTEN            (1 << 0)
+
+#define UART_PL011_IMSC_OEIM            (1 << 10)
+#define UART_PL011_IMSC_BEIM            (1 << 9)
+#define UART_PL011_IMSC_PEIM            (1 << 8)
+#define UART_PL011_IMSC_FEIM            (1 << 7)
+#define UART_PL011_IMSC_RTIM            (1 << 6)
+#define UART_PL011_IMSC_TXIM            (1 << 5)
+#define UART_PL011_IMSC_RXIM            (1 << 4)
+#define UART_PL011_IMSC_DSRMIM          (1 << 3)
+#define UART_PL011_IMSC_DCDMIM          (1 << 2)
+#define UART_PL011_IMSC_CTSMIM          (1 << 1)
+#define UART_PL011_IMSC_RIMIM           (1 << 0)
@@ -1313,7 +1313,6 @@
 #if SMC_DEBUG > 2
 static void print_packet( byte * buf, int length )
 {
-#if 0
 	int i;
 	int remainder;
 	int lines;
@@ -1345,7 +1344,6 @@
 	}
 	printf("\n");
 #endif
-#endif
 }
 #endif
  
  
  
  
@@ -1423,28 +1421,26 @@
 	}
 	memcpy (bd->bi_enetaddr, v_mac, 6);	/* update global address to match env (allows env changing) */
 	smc_set_mac_addr (v_mac);	/* use old function to update smc default */
+	PRINTK("Using MAC Address %02X:%02X:%02X:%02X:%02X:%02X\n", v_mac[0], v_mac[1],
+                v_mac[2], v_mac[3], v_mac[4], v_mac[5]);
 	return (0);
 }
  
 int get_rom_mac (char *v_rom_mac)
 {
-	int is_rom_present = 0;
-
 #ifdef HARDCODE_MAC	/* used for testing or to supress run time warnings */
 	char hw_mac_addr[] = { 0x02, 0x80, 0xad, 0x20, 0x31, 0xb8 };
  
 	memcpy (v_rom_mac, hw_mac_addr, 6);
 	return (1);
 #else
-	if (is_rom_present) {
-		/* if eeprom contents are valid
-		 *   extract mac address into hw_mac_addr, 8 or 16 bit accesses
-		 *   memcpy (v_rom_mac, hc_mac_addr, 6);
-		 *   return(1);
-		 */
+	int i;
+	SMC_SELECT_BANK (1);
+	for (i=0; i<6; i++)
+	{
+		v_rom_mac[i] = SMC_inb (ADDR0_REG + i);
 	}
-	memset (v_rom_mac, 0, 6);
-	return (0);
+	return (1);
 #endif
 }
 #endif /* CONFIG_DRIVER_SMC91111 */
+/*
+ * (C) Copyright 2003
+ * Texas Instruments.
+ * Kshitij Gupta <kshitij@ti.com>
+ * Configuation settings for the TI OMAP Innovator board.
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ * Configuration for Integrator AP board.
+ *.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM926EJS	1	/* This is an arm926ejs CPU core  */
+#define CONFIG_INTEGRATOR	1	/* in an Integrator board	*/
+#define CONFIG_ARCH_CINTEGRATOR 1	/* Specifically, a CP		*/
+
+
+#define CFG_MEMTEST_START   0x100000
+#define CFG_MEMTEST_END   0x10000000
+#define CFG_HZ	(1000000 / 256)		/* Timer 1 is clocked at 1Mhz, with 256 divider */
+#define CFG_TIMERBASE 0x13000100
+
+#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs  */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r during start up */
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN	(CFG_ENV_SIZE + 128*1024)
+
+/*
+ * PL010 Configuration
+ */
+#define CFG_PL010_SERIAL
+#define CONFIG_CONS_INDEX	0
+#define CONFIG_BAUDRATE         38400
+#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
+#define CFG_SERIAL0		0x16000000
+#define CFG_SERIAL1		0x17000000
+
+//#define CONFIG_COMMANDS	(CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | CFG_CMD_BDI | CFG_CMD_PCI)
+//#define CONFIG_NET_MULTI
+//#define CONFIG_BOOTP_MASK       CONFIG_BOOTP_DEFAULT
+
+#define CONFIG_COMMANDS	(CFG_CMD_IMI | CFG_CMD_BDI | CFG_CMD_MEMORY)
+
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY        2
+#define CONFIG_BOOTARGS         "root=/dev/mtdblock0 mem=32M console=ttyAM0 console=tty" 
+#define CONFIG_BOOTCOMMAND      ""
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP	/* undef to save memory     */
+#define CFG_PROMPT	"Integrator-AP # "	/* Monitor Command Prompt   */
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size  */
+/* Print Buffer Size */
+#define CFG_PBSIZE	(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS	16		/* max number of command args   */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size    */
+
+#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#define CFG_LOAD_ADDR	0x7fc0	/* default load address */
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS    1	/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1            0x00000000	/* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x02000000	/* 32 MB */
+
+#define CFG_FLASH_BASE          0x24000000
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_ENV_IS_NOWHERE
+#define CFG_MAX_FLASH_BANKS	1		/* max number of memory banks */
+#define PHYS_FLASH_SIZE		0x01000000	/* 16MB */
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(20*CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(20*CFG_HZ)	/* Timeout for Flash Write */
+#define CFG_MAX_FLASH_SECT 	128
+#define CFG_ENV_SIZE 		32768
+
+#define PHYS_FLASH_1		(CFG_FLASH_BASE)
+
+/*-----------------------------------------------------------------------
+ * PCI definitions
+ */
+
+//#define CONFIG_PCI			/* include pci support			*/
+#undef CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
+#define DEBUG
+
+#define CONFIG_EEPRO100
+#define CFG_RX_ETH_BUFFER	8       /* use 8 rx buffer on eepro100  */
+
+
+#define INTEGRATOR_BOOT_ROM_BASE	0x20000000
+#define INTEGRATOR_HDR0_SDRAM_BASE      0x80000000
+
+// PCI Base area
+#define INTEGRATOR_PCI_BASE		0x40000000
+#define INTEGRATOR_PCI_SIZE		0x3FFFFFFF
+
+// memory map as seen by the CPU on the local bus
+#define CPU_PCI_IO_ADRS		0x60000000 	// PCI I/O space base
+#define CPU_PCI_IO_SIZE		0x10000	
+
+#define CPU_PCI_CNFG_ADRS	0x61000000	// PCI config space
+#define CPU_PCI_CNFG_SIZE	0x1000000
+
+#define PCI_MEM_BASE            0x40000000   // 512M to xxx
+//  unused 256M from A0000000-AFFFFFFF might be used for I2O ???
+#define INTEGRATOR_PCI_IO_BASE  0x60000000   // 16M to xxx
+//  unused (128-16)M from B1000000-B7FFFFFF
+#define PCI_CONFIG_BASE         0x61000000   // 16M to xxx
+//  unused ((128-16)M - 64K) from XXX
+
+#define PCI_V3_BASE             0x62000000
+
+// V3 PCI bridge controller
+#define V3_BASE			0x62000000    // V360EPC registers
+
+#define PCI_ENET0_IOADDR	(CPU_PCI_IO_ADRS)
+#define PCI_ENET0_MEMADDR	(PCI_MEM_BASE)
+
+
+#define V3_PCI_VENDOR           0x00000000
+#define V3_PCI_DEVICE           0x00000002
+#define V3_PCI_CMD              0x00000004
+#define V3_PCI_STAT             0x00000006
+#define V3_PCI_CC_REV           0x00000008
+#define V3_PCI_HDR_CF           0x0000000C
+#define V3_PCI_IO_BASE          0x00000010
+#define V3_PCI_BASE0            0x00000014
+#define V3_PCI_BASE1            0x00000018
+#define V3_PCI_SUB_VENDOR       0x0000002C
+#define V3_PCI_SUB_ID           0x0000002E
+#define V3_PCI_ROM              0x00000030
+#define V3_PCI_BPARAM           0x0000003C
+#define V3_PCI_MAP0             0x00000040
+#define V3_PCI_MAP1             0x00000044
+#define V3_PCI_INT_STAT         0x00000048
+#define V3_PCI_INT_CFG          0x0000004C
+#define V3_LB_BASE0             0x00000054
+#define V3_LB_BASE1             0x00000058
+#define V3_LB_MAP0              0x0000005E
+#define V3_LB_MAP1              0x00000062
+#define V3_LB_BASE2             0x00000064
+#define V3_LB_MAP2              0x00000066
+#define V3_LB_SIZE              0x00000068
+#define V3_LB_IO_BASE           0x0000006E
+#define V3_FIFO_CFG             0x00000070
+#define V3_FIFO_PRIORITY        0x00000072
+#define V3_FIFO_STAT            0x00000074
+#define V3_LB_ISTAT             0x00000076
+#define V3_LB_IMASK             0x00000077
+#define V3_SYSTEM               0x00000078
+#define V3_LB_CFG               0x0000007A
+#define V3_PCI_CFG              0x0000007C
+#define V3_DMA_PCI_ADR0         0x00000080
+#define V3_DMA_PCI_ADR1         0x00000090
+#define V3_DMA_LOCAL_ADR0       0x00000084
+#define V3_DMA_LOCAL_ADR1       0x00000094
+#define V3_DMA_LENGTH0          0x00000088
+#define V3_DMA_LENGTH1          0x00000098
+#define V3_DMA_CSR0             0x0000008B
+#define V3_DMA_CSR1             0x0000009B
+#define V3_DMA_CTLB_ADR0        0x0000008C
+#define V3_DMA_CTLB_ADR1        0x0000009C
+#define V3_DMA_DELAY            0x000000E0
+#define V3_MAIL_DATA            0x000000C0
+#define V3_PCI_MAIL_IEWR        0x000000D0
+#define V3_PCI_MAIL_IERD        0x000000D2
+#define V3_LB_MAIL_IEWR         0x000000D4
+#define V3_LB_MAIL_IERD         0x000000D6
+#define V3_MAIL_WR_STAT         0x000000D8
+#define V3_MAIL_RD_STAT         0x000000DA
+#define V3_QBA_MAP              0x000000DC
+
+// SYSTEM register bits
+#define V3_SYSTEM_M_RST_OUT             (1 << 15)
+#define V3_SYSTEM_M_LOCK                (1 << 14)
+
+//  PCI_CFG bits
+#define V3_PCI_CFG_M_RETRY_EN           (1 << 10)
+#define V3_PCI_CFG_M_AD_LOW1            (1 << 9)
+#define V3_PCI_CFG_M_AD_LOW0            (1 << 8)
+
+// PCI MAP register bits (PCI -> Local bus)
+#define V3_PCI_MAP_M_MAP_ADR            0xFFF00000
+#define V3_PCI_MAP_M_RD_POST_INH        (1 << 15)
+#define V3_PCI_MAP_M_ROM_SIZE           (1 << 11 | 1 << 10)
+#define V3_PCI_MAP_M_SWAP               (1 << 9 | 1 << 8)
+#define V3_PCI_MAP_M_ADR_SIZE           0x000000F0
+#define V3_PCI_MAP_M_REG_EN             (1 << 1)
+#define V3_PCI_MAP_M_ENABLE             (1 << 0)
+
+// 9 => 512M window size
+#define V3_PCI_MAP_M_ADR_SIZE_512M      0x00000090
+
+// A => 1024M window size
+#define V3_PCI_MAP_M_ADR_SIZE_1024M     0x000000A0
+
+// LB_BASE register bits (Local bus -> PCI)
+#define V3_LB_BASE_M_MAP_ADR            0xFFF00000
+#define V3_LB_BASE_M_SWAP               (1 << 8 | 1 << 9)
+#define V3_LB_BASE_M_ADR_SIZE           0x000000F0
+#define V3_LB_BASE_M_PREFETCH           (1 << 3)
+#define V3_LB_BASE_M_ENABLE             (1 << 0)
+
+// PCI COMMAND REGISTER bits
+#define V3_COMMAND_M_FBB_EN             (1 << 9)
+#define V3_COMMAND_M_SERR_EN            (1 << 8)
+#define V3_COMMAND_M_PAR_EN             (1 << 6)
+#define V3_COMMAND_M_MASTER_EN          (1 << 2)
+#define V3_COMMAND_M_MEM_EN             (1 << 1)
+#define V3_COMMAND_M_IO_EN              (1 << 0)
+
+#define INTEGRATOR_SC_BASE		0x11000000
+#define INTEGRATOR_SC_PCIENABLE_OFFSET	0x18
+#define INTEGRATOR_SC_PCIENABLE \
+			(INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET)
+
+
+#endif							/* __CONFIG_H */
+/*
+ * (C) Copyright 2003
+ * Texas Instruments.
+ * Kshitij Gupta <kshitij@ti.com>
+ * Configuation settings for the TI OMAP Innovator board.
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ * Configuration for Compact Integrator board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM926EJS	1	/* This is an arm926ejs CPU core  */
+#define CONFIG_INTEGRATOR	1	/* in an Integrator board	*/
+#define CONFIG_ARCH_CINTEGRATOR 1	/* Specifically, a CP		*/
+
+
+#define CFG_MEMTEST_START       0x100000
+#define CFG_MEMTEST_END         0x10000000
+#define CFG_HZ                  (1000000 / 256)	/* Timer 1 is clocked at 1Mhz, with 256 divider */
+#define CFG_TIMERBASE           0x13000100
+
+#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs  */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r during start up */
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN	(CFG_ENV_SIZE + 128*1024)
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_SMC91111
+#define CONFIG_SMC_USE_32_BIT
+#define CONFIG_SMC91111_BASE    0xC8000000
+#undef CONFIG_SMC91111_EXT_PHY
+
+/*
+ * NS16550 Configuration
+ */
+#define CFG_PL011_SERIAL
+#define CONFIG_CONS_INDEX	0
+#define CONFIG_BAUDRATE	38400
+#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
+#define CFG_SERIAL0		0x16000000
+#define CFG_SERIAL1		0x17000000
+
+#define CONFIG_COMMANDS	(CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | CFG_CMD_BDI | CFG_CMD_MEMORY)
+#define CONFIG_BOOTP_MASK	CONFIG_BOOTP_DEFAULT
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	2
+#define CONFIG_BOOTARGS	"root=/dev/nfs mem=128M ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0" 
+#define CONFIG_BOOTCOMMAND "bootp ; bootm"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP	/* undef to save memory     */
+#define CFG_PROMPT	"Integrator-CP # "	/* Monitor Command Prompt   */
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size  */
+/* Print Buffer Size */
+#define CFG_PBSIZE	(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS	16		/* max number of command args   */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size    */
+
+#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#define CFG_LOAD_ADDR	0x7fc0	/* default load address */
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS    1	/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1            0x00000000	/* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE       0x02000000	/* 32 MB */
+
+#define CFG_FLASH_BASE          0x24000000
+#define PHYS_FLASH_1		(CFG_FLASH_BASE)
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_ENV_IS_NOWHERE
+#define CFG_MAX_FLASH_BANKS	1		/* max number of memory banks */
+#define PHYS_FLASH_SIZE         0x01000000	/* 16MB */
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(20*CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(20*CFG_HZ)	/* Timeout for Flash Write */
+#define CFG_MAX_FLASH_SECT 128
+#define CFG_ENV_SIZE 32768
+
+#endif							/* __CONFIG_H */
+/*
+ * (C) Copyright 2003
+ * Texas Instruments.
+ * Kshitij Gupta <kshitij@ti.com>
+ * Configuation settings for the TI OMAP Innovator board.
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ * Configuration for Versatile PB.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM926EJS	1	/* This is an arm926ejs CPU core  */
+#define CONFIG_VERSATILE	1	/* in Versatile Platform Board	*/
+#define CONFIG_ARCH_VERSATILE   1	/* Specifically, a Versatile	*/
+
+
+#define CFG_MEMTEST_START       0x100000
+#define CFG_MEMTEST_END         0x10000000
+#define CFG_HZ                  (1000000 / 256)
+#define CFG_TIMERBASE           0x101E2000	/* Timer 0 and 1 base */
+
+#define CFG_TIMER_INTERVAL	10000
+#define CFG_TIMER_RELOAD	(CFG_TIMER_INTERVAL >> 4)	/* Divide by 16 */
+#define CFG_TIMER_CTRL          0x84				/* Enable, Clock / 16 */
+
+/*
+ * control registers
+ */
+#define VERSATILE_SCTL_BASE            0x101E0000	/* System controller */
+
+/*
+ * System controller bit assignment
+ */
+#define VERSATILE_REFCLK	0
+#define VERSATILE_TIMCLK	1
+
+#define VERSATILE_TIMER1_EnSel	15
+#define VERSATILE_TIMER2_EnSel	17
+#define VERSATILE_TIMER3_EnSel	19
+#define VERSATILE_TIMER4_EnSel	21
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs  */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_MISC_INIT_R		1	/* call misc_init_r during start up */
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN	(CFG_ENV_SIZE + 128*1024)
+
+/*
+ * Hardware drivers
+ */
+
+#define CONFIG_DRIVER_SMC91111
+#define CONFIG_SMC_USE_32_BIT
+#define CONFIG_SMC91111_BASE    	0x10010000
+#undef CONFIG_SMC91111_EXT_PHY
+
+/*
+ * NS16550 Configuration
+ */
+#define CFG_PL011_SERIAL
+#define CONFIG_CONS_INDEX	0
+#define CONFIG_BAUDRATE         38400
+#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
+#define CFG_SERIAL0		0x101F1000
+#define CFG_SERIAL1		0x101F2000
+
+#define CONFIG_COMMANDS	(CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | CFG_CMD_BDI | CFG_CMD_MEMORY)
+
+//#define CONFIG_COMMANDS	(CFG_CMD_IMI | CFG_CMD_BDI | CFG_CMD_MEMORY)
+
+#define CONFIG_BOOTP_MASK	CONFIG_BOOTP_DEFAULT
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	2
+#define CONFIG_BOOTARGS	"root=/dev/nfs mem=128M ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0" 
+//#define CONFIG_BOOTCOMMAND "bootp ; bootm"
+
+/*
+ * Static configuration when assigning fixed address
+ */
+//#define CONFIG_NETMASK	255.255.255.0	/* talk on MY local net */
+//#define CONFIG_IPADDR		xx.xx.xx.xx	/* static IP I currently own */
+//#define CONFIG_SERVERIP	xx.xx.xx.xx	/* current IP of my dev pc */
+#define CONFIG_BOOTFILE	    "/tftpboot/uImage" /* file to load */
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP	/* undef to save memory     */
+#define CFG_PROMPT	"Versatile # "	/* Monitor Command Prompt   */
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size  */
+/* Print Buffer Size */
+#define CFG_PBSIZE	(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS	16		/* max number of command args   */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size    */
+
+#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#define CFG_LOAD_ADDR	0x7fc0	/* default load address */
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS    1	/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1            0x00000000	/* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE       0x08000000	/* 128 MB */
+
+#define CFG_FLASH_BASE          0x34000000
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_ENV_IS_NOWHERE
+#define CFG_MAX_FLASH_BANKS	1		/* max number of memory banks */
+#define PHYS_FLASH_SIZE         0x34000000	/* 64MB */
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(20*CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(20*CFG_HZ)	/* Timeout for Flash Write */
+#define CFG_MAX_FLASH_SECT 128
+#define CFG_ENV_SIZE 32768
+
+#define PHYS_FLASH_1		(CFG_FLASH_BASE)
+
+#endif							/* __CONFIG_H */
@@ -117,10 +117,15 @@
  */
 static void BootpCopyNetParams(Bootp_t *bp)
 {
+	IPaddr_t tmp_ip;
+
 	NetCopyIP(&NetOurIP, &bp->bp_yiaddr);
-	NetCopyIP(&NetServerIP, &bp->bp_siaddr);
+	NetCopyIP(&tmp_ip, &bp->bp_siaddr);
+	if (tmp_ip != 0)
+		NetCopyIP(&NetServerIP, &bp->bp_siaddr);
 	memcpy (NetServerEther, ((Ethernet_t *)NetRxPkt)->et_src, 6);
-	copy_filename (BootFile, bp->bp_file, sizeof(BootFile));
+	if (strlen(bp->bp_file) > 0)
+		copy_filename (BootFile, bp->bp_file, sizeof(BootFile));
  
 	debug ("Bootfile: %s\n", BootFile);
  
@@ -323,7 +323,7 @@
 		 * IP addr assigned to us by the BOOTP / RARP server
 		 */
 		NetOurIP = 0;
-		NetServerIP = 0;
+		NetServerIP = getenv_IPaddr ("serverip");
 		break;
 	default:
 		break;
@@ -354,7 +354,7 @@
 		case DHCP:
 			/* Start with a clean slate... */
 			NetOurIP = 0;
-			NetServerIP = 0;
+			NetServerIP = getenv_IPaddr ("serverip");
 			DhcpRequest();		/* Basically same as BOOTP */
 			break;
 #endif /* CFG_CMD_DHCP */
@@ -832,7 +832,8 @@
 			printf("invalid RARP header\n");
 		} else {
 			NetCopyIP(&NetOurIP,    &arp->ar_data[16]);
-			NetCopyIP(&NetServerIP, &arp->ar_data[ 6]);
+			if (NetServerIP == 0)
+				NetCopyIP(&NetServerIP, &arp->ar_data[ 6]);
 			memcpy (NetServerEther, &arp->ar_data[ 0], 6);
  
 			(*packetHandler)(0,0,0,0);
@@ -52,7 +52,7 @@
 # define CFG_I2C_RTC_ADDR	0x68
 #endif
  
-#if CFG_I2C_SPEED > 100000
+#if defined(CONFIG_RTC_DS1307) && (CFG_I2C_SPEED > 100000)
 # error The DS1307 is specified only up to 100kHz!
 #endif
...	...	@@ -2,6 +2,17 @@
2	2	Changes for U-Boot 1.0.2:
3	3	======================================================================
4	4
	5	+* Patch by Philippe Robin, 09 Mar 2004:
	6	+ Added ARM Integrator AP, CP and Versatile PB926EJ-S Reference
	7	+ Platform support.
	8	+
	9	+* Patch by Masami Komiya, 08 Mar 2004:
	10	+ Don't overwrite server IP address or boot file name
	11	+ when the boot server does not return values
	12	+
	13	+* Patch by listmember@orkun.us, 5 Mar 2004:
	14	+ Removed compile time restriction on CFG_I2C_SPEED for DS1338 RTC
	15	+
5	16	* Patch by Tolunay Orkun, 5 Mar 2004:
6	17	Fix early board initialization for Cogent CSB272 board
7	18
...	...	@@ -135,9 +135,10 @@
135	135	#########################################################################
136	136
137	137	LIST_ARM9=" \
138		- at91rm9200dk omap1510inn omap1610h2 omap1610inn \
	138	+ at91rm9200dk integratorcp integratorap \
	139	+ omap1510inn omap1610h2 omap1610inn \
139	140	smdk2400 smdk2410 trab \
140		- VCMA9 \
	141	+ VCMA9 versatile \
141	142	"
142	143
143	144	#########################################################################
...	...	@@ -111,8 +111,9 @@
111	111	.PHONY : $(LIBS)
112	112
113	113	# Add GCC lib
114		-PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc
	114	+PLATFORM_LIBS += --no-warn-mismatch -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc
115	115
	116	+
116	117	# The "tools" are needed early, so put this first
117	118	# Don't include stuff already done in $(LIBS)
118	119	SUBDIRS = tools \
...	...	@@ -926,6 +927,15 @@
926	927
927	928	SX1_config : unconfig
928	929	@./mkconfig $(@:_config=) arm arm925t sx1
	930	+
	931	+integratorcp_config : unconfig
	932	+ @./mkconfig $(@:_config=) arm arm926ejs integratorcp
	933	+
	934	+integratorap_config : unconfig
	935	+ @./mkconfig $(@:_config=) arm arm926ejs integratorap
	936	+
	937	+versatile_config : unconfig
	938	+ @./mkconfig $(@:_config=) arm arm926ejs versatile
929	939
930	940	omap1510inn_config : unconfig
931	941	@./mkconfig $(@:_config=) arm arm925t omap1510inn
	1	+#
	2	+# (C) Copyright 2000-2004
	3	+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+#
	5	+# (C) Copyright 2004
	6	+# ARM Ltd.
	7	+# Philippe Robin, <philippe.robin@arm.com>
	8	+#
	9	+# See file CREDITS for list of people who contributed to this
	10	+# project.
	11	+#
	12	+# This program is free software; you can redistribute it and/or
	13	+# modify it under the terms of the GNU General Public License as
	14	+# published by the Free Software Foundation; either version 2 of
	15	+# the License, or (at your option) any later version.
	16	+#
	17	+# This program is distributed in the hope that it will be useful,
	18	+# but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	+# GNU General Public License for more details.
	21	+#
	22	+# You should have received a copy of the GNU General Public License
	23	+# along with this program; if not, write to the Free Software
	24	+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	+# MA 02111-1307 USA
	26	+#
	27	+
	28	+include $(TOPDIR)/config.mk
	29	+
	30	+LIB = lib$(BOARD).a
	31	+
	32	+OBJS := integratorap.o flash.o
	33	+SOBJS := platform.o
	34	+
	35	+$(LIB): $(OBJS) $(SOBJS)
	36	+ $(AR) crv $@ $^
	37	+
	38	+clean:
	39	+ rm -f $(SOBJS) $(OBJS)
	40	+
	41	+distclean: clean
	42	+ rm -f $(LIB) core *.bak .depend
	43	+
	44	+#########################################################################
	45	+
	46	+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
	47	+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
	48	+
	49	+-include .depend
	50	+
	51	+#########################################################################
	1	+#
	2	+# image should be loaded at 0x01000000
	3	+#
	4	+
	5	+TEXT_BASE = 0x01000000
	1	+/*
	2	+ * (C) Copyright 2001
	3	+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
	4	+ *
	5	+ * (C) Copyright 2001-2004
	6	+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	7	+ *
	8	+ * (C) Copyright 2003
	9	+ * Texas Instruments, <www.ti.com>
	10	+ * Kshitij Gupta <Kshitij@ti.com>
	11	+ *
	12	+ * See file CREDITS for list of people who contributed to this
	13	+ * project.
	14	+ *
	15	+ * This program is free software; you can redistribute it and/or
	16	+ * modify it under the terms of the GNU General Public License as
	17	+ * published by the Free Software Foundation; either version 2 of
	18	+ * the License, or (at your option) any later version.
	19	+ *
	20	+ * This program is distributed in the hope that it will be useful,
	21	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	22	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	23	+ * GNU General Public License for more details.
	24	+ *
	25	+ * You should have received a copy of the GNU General Public License
	26	+ * along with this program; if not, write to the Free Software
	27	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	28	+ * MA 02111-1307 USA
	29	+ */
	30	+
	31	+#include <common.h>
	32	+#include <linux/byteorder/swab.h>
	33	+
	34	+#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */
	35	+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
	36	+
	37	+/* Board support for 1 or 2 flash devices */
	38	+#undef FLASH_PORT_WIDTH32
	39	+#define FLASH_PORT_WIDTH16
	40	+
	41	+#ifdef FLASH_PORT_WIDTH16
	42	+#define FLASH_PORT_WIDTH ushort
	43	+#define FLASH_PORT_WIDTHV vu_short
	44	+#define SWAP(x) __swab16(x)
	45	+#else
	46	+#define FLASH_PORT_WIDTH ulong
	47	+#define FLASH_PORT_WIDTHV vu_long
	48	+#define SWAP(x) __swab32(x)
	49	+#endif
	50	+
	51	+#define FPW FLASH_PORT_WIDTH
	52	+#define FPWV FLASH_PORT_WIDTHV
	53	+
	54	+#define mb() __asm__ __volatile__ ("" : : : "memory")
	55	+
	56	+
	57	+/* Flash Organization Structure */
	58	+typedef struct OrgDef {
	59	+ unsigned int sector_number;
	60	+ unsigned int sector_size;
	61	+} OrgDef;
	62	+
	63	+
	64	+/* Flash Organizations */
	65	+OrgDef OrgIntel_28F256L18T[] = {
	66	+ {4, 32 * 1024}, /* 4 * 32kBytes sectors */
	67	+ {255, 128 * 1024}, /* 255 * 128kBytes sectors */
	68	+};
	69	+
	70	+
	71	+/*-----------------------------------------------------------------------
	72	+ * Functions
	73	+ */
	74	+unsigned long flash_init (void);
	75	+static ulong flash_get_size (FPW * addr, flash_info_t * info);
	76	+static int write_data (flash_info_t * info, ulong dest, FPW data);
	77	+static void flash_get_offsets (ulong base, flash_info_t * info);
	78	+void inline spin_wheel (void);
	79	+void flash_print_info (flash_info_t * info);
	80	+void flash_unprotect_sectors (FPWV * addr);
	81	+int flash_erase (flash_info_t * info, int s_first, int s_last);
	82	+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
	83	+
	84	+/*-----------------------------------------------------------------------
	85	+ */
	86	+
	87	+unsigned long flash_init (void)
	88	+{
	89	+ int i;
	90	+ ulong size = 0;
	91	+ for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
	92	+ switch (i) {
	93	+ case 0:
	94	+ flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
	95	+ flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
	96	+ break;
	97	+ default:
	98	+ panic ("configured too many flash banks!\n");
	99	+ break;
	100	+ }
	101	+ size += flash_info[i].size;
	102	+ }
	103	+
	104	+ /* Protect monitor and environment sectors
	105	+ */
	106	+ flash_protect (FLAG_PROTECT_SET,
	107	+ CFG_FLASH_BASE,
	108	+ CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
	109	+
	110	+ return size;
	111	+}
	112	+
	113	+/*-----------------------------------------------------------------------
	114	+ */
	115	+static void flash_get_offsets (ulong base, flash_info_t * info)
	116	+{
	117	+ int i;
	118	+ OrgDef *pOrgDef;
	119	+
	120	+ pOrgDef = OrgIntel_28F256L18T;
	121	+ if (info->flash_id == FLASH_UNKNOWN) {
	122	+ return;
	123	+ }
	124	+
	125	+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
	126	+ for (i = 0; i < info->sector_count; i++) {
	127	+ if (i > 255) {
	128	+ info->start[i] = base + (i * 0x8000);
	129	+ info->protect[i] = 0;
	130	+ } else {
	131	+ info->start[i] = base +
	132	+ (i * PHYS_FLASH_SECT_SIZE);
	133	+ info->protect[i] = 0;
	134	+ }
	135	+ }
	136	+ }
	137	+}
	138	+
	139	+/*-----------------------------------------------------------------------
	140	+ */
	141	+void flash_print_info (flash_info_t * info)
	142	+{
	143	+ int i;
	144	+
	145	+ if (info->flash_id == FLASH_UNKNOWN) {
	146	+ printf ("missing or unknown FLASH type\n");
	147	+ return;
	148	+ }
	149	+
	150	+ switch (info->flash_id & FLASH_VENDMASK) {
	151	+ case FLASH_MAN_INTEL:
	152	+ printf ("INTEL ");
	153	+ break;
	154	+ default:
	155	+ printf ("Unknown Vendor ");
	156	+ break;
	157	+ }
	158	+
	159	+ switch (info->flash_id & FLASH_TYPEMASK) {
	160	+ case FLASH_28F256L18T:
	161	+ printf ("FLASH 28F256L18T\n");
	162	+ break;
	163	+ default:
	164	+ printf ("Unknown Chip Type\n");
	165	+ break;
	166	+ }
	167	+
	168	+ printf (" Size: %ld MB in %d Sectors\n",
	169	+ info->size >> 20, info->sector_count);
	170	+
	171	+ printf (" Sector Start Addresses:");
	172	+ for (i = 0; i < info->sector_count; ++i) {
	173	+ if ((i % 5) == 0)
	174	+ printf ("\n ");
	175	+ printf (" %08lX%s",
	176	+ info->start[i], info->protect[i] ? " (RO)" : " ");
	177	+ }
	178	+ printf ("\n");
	179	+ return;
	180	+}
	181	+
	182	+/*
	183	+ * The following code cannot be run from FLASH!
	184	+ */
	185	+static ulong flash_get_size (FPW * addr, flash_info_t * info)
	186	+{
	187	+ volatile FPW value;
	188	+
	189	+ /* Write auto select command: read Manufacturer ID */
	190	+ addr[0x5555] = (FPW) 0x00AA00AA;
	191	+ addr[0x2AAA] = (FPW) 0x00550055;
	192	+ addr[0x5555] = (FPW) 0x00900090;
	193	+
	194	+ mb ();
	195	+ value = addr[0];
	196	+
	197	+ switch (value) {
	198	+
	199	+ case (FPW) INTEL_MANUFACT:
	200	+ info->flash_id = FLASH_MAN_INTEL;
	201	+ break;
	202	+
	203	+ default:
	204	+ info->flash_id = FLASH_UNKNOWN;
	205	+ info->sector_count = 0;
	206	+ info->size = 0;
	207	+ addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
	208	+ return (0); /* no or unknown flash */
	209	+ }
	210	+
	211	+ mb ();
	212	+ value = addr[1]; /* device ID */
	213	+ switch (value) {
	214	+
	215	+ case (FPW) (INTEL_ID_28F256L18T):
	216	+ info->flash_id += FLASH_28F256L18T;
	217	+ info->sector_count = 259;
	218	+ info->size = 0x02000000;
	219	+ break; /* => 32 MB */
	220	+
	221	+ default:
	222	+ info->flash_id = FLASH_UNKNOWN;
	223	+ break;
	224	+ }
	225	+
	226	+ if (info->sector_count > CFG_MAX_FLASH_SECT) {
	227	+ printf (" ERROR: sector count %d > max (%d) \n",
	228	+ info->sector_count, CFG_MAX_FLASH_SECT);
	229	+ info->sector_count = CFG_MAX_FLASH_SECT;
	230	+ }
	231	+
	232	+ addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
	233	+
	234	+ return (info->size);
	235	+}
	236	+
	237	+
	238	+/* unprotects a sector for write and erase
	239	+ * on some intel parts, this unprotects the entire chip, but it
	240	+ * wont hurt to call this additional times per sector...
	241	+ */
	242	+void flash_unprotect_sectors (FPWV * addr)
	243	+{
	244	+#define PD_FINTEL_WSMS_READY_MASK 0x0080
	245	+
	246	+ addr = (FPW) 0x00500050; / clear status register */
	247	+
	248	+ /* this sends the clear lock bit command */
	249	+ *addr = (FPW) 0x00600060;
	250	+ *addr = (FPW) 0x00D000D0;
	251	+}
	252	+
	253	+
	254	+/*-----------------------------------------------------------------------
	255	+ */
	256	+
	257	+int flash_erase (flash_info_t * info, int s_first, int s_last)
	258	+{
	259	+ int flag, prot, sect;
	260	+ ulong type, start, last;
	261	+ int rcode = 0;
	262	+
	263	+ if ((s_first < 0) \|\| (s_first > s_last)) {
	264	+ if (info->flash_id == FLASH_UNKNOWN) {
	265	+ printf ("- missing\n");
	266	+ } else {
	267	+ printf ("- no sectors to erase\n");
	268	+ }
	269	+ return 1;
	270	+ }
	271	+
	272	+ type = (info->flash_id & FLASH_VENDMASK);
	273	+ if ((type != FLASH_MAN_INTEL)) {
	274	+ printf ("Can't erase unknown flash type %08lx - aborted\n",
	275	+ info->flash_id);
	276	+ return 1;
	277	+ }
	278	+
	279	+ prot = 0;
	280	+ for (sect = s_first; sect <= s_last; ++sect) {
	281	+ if (info->protect[sect]) {
	282	+ prot++;
	283	+ }
	284	+ }
	285	+
	286	+ if (prot) {
	287	+ printf ("- Warning: %d protected sectors will not be erased!\n",
	288	+ prot);
	289	+ } else {
	290	+ printf ("\n");
	291	+ }
	292	+
	293	+
	294	+ start = get_timer (0);
	295	+ last = start;
	296	+
	297	+ /* Disable interrupts which might cause a timeout here */
	298	+ flag = disable_interrupts ();
	299	+
	300	+ /* Start erase on unprotected sectors */
	301	+ for (sect = s_first; sect <= s_last; sect++) {
	302	+ if (info->protect[sect] == 0) { /* not protected */
	303	+ FPWV addr = (FPWV ) (info->start[sect]);
	304	+ FPW status;
	305	+
	306	+ printf ("Erasing sector %2d ... ", sect);
	307	+
	308	+ flash_unprotect_sectors (addr);
	309	+
	310	+ /* arm simple, non interrupt dependent timer */
	311	+ reset_timer_masked ();
	312	+
	313	+ addr = (FPW) 0x00500050;/ clear status register */
	314	+ addr = (FPW) 0x00200020;/ erase setup */
	315	+ addr = (FPW) 0x00D000D0;/ erase confirm */
	316	+
	317	+ while (((status =
	318	+ *addr) & (FPW) 0x00800080) !=
	319	+ (FPW) 0x00800080) {
	320	+ if (get_timer_masked () >
	321	+ CFG_FLASH_ERASE_TOUT) {
	322	+ printf ("Timeout\n");
	323	+ /* suspend erase */
	324	+ *addr = (FPW) 0x00B000B0;
	325	+ /* reset to read mode */
	326	+ *addr = (FPW) 0x00FF00FF;
	327	+ rcode = 1;
	328	+ break;
	329	+ }
	330	+ }
	331	+
	332	+ /* clear status register cmd. */
	333	+ *addr = (FPW) 0x00500050;
	334	+ addr = (FPW) 0x00FF00FF;/ resest to read mode */
	335	+ printf (" done\n");
	336	+ }
	337	+ }
	338	+ return rcode;
	339	+}
	340	+
	341	+/*-----------------------------------------------------------------------
	342	+ * Copy memory to flash, returns:
	343	+ * 0 - OK
	344	+ * 1 - write timeout
	345	+ * 2 - Flash not erased
	346	+ * 4 - Flash not identified
	347	+ */
	348	+
	349	+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
	350	+{
	351	+ ulong cp, wp;
	352	+ FPW data;
	353	+ int count, i, l, rc, port_width;
	354	+
	355	+ if (info->flash_id == FLASH_UNKNOWN) {
	356	+ return 4;
	357	+ }
	358	+/* get lower word aligned address */
	359	+#ifdef FLASH_PORT_WIDTH16
	360	+ wp = (addr & ~1);
	361	+ port_width = 2;
	362	+#else
	363	+ wp = (addr & ~3);
	364	+ port_width = 4;
	365	+#endif
	366	+
	367	+ /*
	368	+ * handle unaligned start bytes
	369	+ */
	370	+ if ((l = addr - wp) != 0) {
	371	+ data = 0;
	372	+ for (i = 0, cp = wp; i < l; ++i, ++cp) {
	373	+ data = (data << 8) \| ((uchar ) cp);
	374	+ }
	375	+ for (; i < port_width && cnt > 0; ++i) {
	376	+ data = (data << 8) \| *src++;
	377	+ --cnt;
	378	+ ++cp;
	379	+ }
	380	+ for (; cnt == 0 && i < port_width; ++i, ++cp) {
	381	+ data = (data << 8) \| ((uchar ) cp);
	382	+ }
	383	+
	384	+ if ((rc = write_data (info, wp, SWAP (data))) != 0) {
	385	+ return (rc);
	386	+ }
	387	+ wp += port_width;
	388	+ }
	389	+
	390	+ /*
	391	+ * handle word aligned part
	392	+ */
	393	+ count = 0;
	394	+ while (cnt >= port_width) {
	395	+ data = 0;
	396	+ for (i = 0; i < port_width; ++i) {
	397	+ data = (data << 8) \| *src++;
	398	+ }
	399	+ if ((rc = write_data (info, wp, SWAP (data))) != 0) {
	400	+ return (rc);
	401	+ }
	402	+ wp += port_width;
	403	+ cnt -= port_width;
	404	+ if (count++ > 0x800) {
	405	+ spin_wheel ();
	406	+ count = 0;
	407	+ }
	408	+ }
	409	+
	410	+ if (cnt == 0) {
	411	+ return (0);
	412	+ }
	413	+
	414	+ /*
	415	+ * handle unaligned tail bytes
	416	+ */
	417	+ data = 0;
	418	+ for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
	419	+ data = (data << 8) \| *src++;
	420	+ --cnt;
	421	+ }
	422	+ for (; i < port_width; ++i, ++cp) {
	423	+ data = (data << 8) \| ((uchar ) cp);
	424	+ }
	425	+
	426	+ return (write_data (info, wp, SWAP (data)));
	427	+}
	428	+
	429	+/*-----------------------------------------------------------------------
	430	+ * Write a word or halfword to Flash, returns:
	431	+ * 0 - OK
	432	+ * 1 - write timeout
	433	+ * 2 - Flash not erased
	434	+ */
	435	+static int write_data (flash_info_t * info, ulong dest, FPW data)
	436	+{
	437	+ FPWV addr = (FPWV ) dest;
	438	+ ulong status;
	439	+ int flag;
	440	+
	441	+ /* Check if Flash is (sufficiently) erased */
	442	+ if ((*addr & data) != data) {
	443	+ printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
	444	+ return (2);
	445	+ }
	446	+ flash_unprotect_sectors (addr);
	447	+ /* Disable interrupts which might cause a timeout here */
	448	+ flag = disable_interrupts ();
	449	+ addr = (FPW) 0x00400040; / write setup */
	450	+ *addr = data;
	451	+
	452	+ /* arm simple, non interrupt dependent timer */
	453	+ reset_timer_masked ();
	454	+
	455	+ /* wait while polling the status register */
	456	+ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
	457	+ if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
	458	+ addr = (FPW) 0x00FF00FF; / restore read mode */
	459	+ return (1);
	460	+ }
	461	+ }
	462	+ addr = (FPW) 0x00FF00FF; / restore read mode */
	463	+ return (0);
	464	+}
	465	+
	466	+void inline spin_wheel (void)
	467	+{
	468	+ static int p = 0;
	469	+ static char w[] = "\\/-";
	470	+
	471	+ printf ("\010%c", w[p]);
	472	+ (++p == 3) ? (p = 0) : 0;
	473	+}
	1	+/*
	2	+ * (C) Copyright 2002
	3	+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	4	+ * Marius Groeger <mgroeger@sysgo.de>
	5	+ *
	6	+ * (C) Copyright 2002
	7	+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
	8	+ *
	9	+ * (C) Copyright 2003
	10	+ * Texas Instruments, <www.ti.com>
	11	+ * Kshitij Gupta <Kshitij@ti.com>
	12	+ *
	13	+ * (C) Copyright 2004
	14	+ * ARM Ltd.
	15	+ * Philippe Robin, <philippe.robin@arm.com>
	16	+ *
	17	+ * See file CREDITS for list of people who contributed to this
	18	+ * project.
	19	+ *
	20	+ * This program is free software; you can redistribute it and/or
	21	+ * modify it under the terms of the GNU General Public License as
	22	+ * published by the Free Software Foundation; either version 2 of
	23	+ * the License, or (at your option) any later version.
	24	+ *
	25	+ * This program is distributed in the hope that it will be useful,
	26	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	27	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	28	+ * GNU General Public License for more details.
	29	+ *
	30	+ * You should have received a copy of the GNU General Public License
	31	+ * along with this program; if not, write to the Free Software
	32	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	33	+ * MA 02111-1307 USA
	34	+ */
	35	+
	36	+#include <common.h>
	37	+
	38	+#ifdef CONFIG_PCI
	39	+# include <pci.h>
	40	+#endif
	41	+
	42	+void flash__init (void);
	43	+void ether__init (void);
	44	+void peripheral_power_enable (void);
	45	+
	46	+#if defined(CONFIG_SHOW_BOOT_PROGRESS)
	47	+void show_boot_progress(int progress)
	48	+{
	49	+ printf("Boot reached stage %d\n", progress);
	50	+}
	51	+#endif
	52	+
	53	+#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
	54	+
	55	+static inline void delay (unsigned long loops)
	56	+{
	57	+ __asm__ volatile ("1:\n"
	58	+ "subs %0, %1, #1\n"
	59	+ "bne 1b":"=r" (loops):"0" (loops));
	60	+}
	61	+
	62	+/*
	63	+ * Miscellaneous platform dependent initialisations
	64	+ */
	65	+
	66	+int board_init (void)
	67	+{
	68	+ DECLARE_GLOBAL_DATA_PTR;
	69	+
	70	+ /* arch number of Integrator Board */
	71	+ gd->bd->bi_arch_number = 21;
	72	+
	73	+ /* adress of boot parameters */
	74	+ gd->bd->bi_boot_params = 0x00000100;
	75	+
	76	+ icache_enable ();
	77	+
	78	+ flash__init ();
	79	+ return 0;
	80	+}
	81	+
	82	+
	83	+int misc_init_r (void)
	84	+{
	85	+#ifdef CONFIG_PCI
	86	+ pci_init();
	87	+#endif
	88	+ setenv("verify", "n");
	89	+ return (0);
	90	+}
	91	+
	92	+/*
	93	+ * Initialize PCI Devices, report devices found.
	94	+ */
	95	+#ifdef CONFIG_PCI
	96	+
	97	+#ifndef CONFIG_PCI_PNP
	98	+
	99	+static struct pci_config_table pci_integrator_config_table[] = {
	100	+ { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
	101	+ pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
	102	+ PCI_ENET0_MEMADDR,
	103	+ PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER }},
	104	+ { }
	105	+};
	106	+#endif
	107	+
	108	+// V3 access routines
	109	+#define _V3Write16(o,v) ((volatile unsigned short )(PCI_V3_BASE + (unsigned int)(o)) = (unsigned short)(v))
	110	+#define _V3Read16(o) ((volatile unsigned short )(PCI_V3_BASE + (unsigned int)(o)))
	111	+
	112	+#define _V3Write32(o,v) ((volatile unsigned int )(PCI_V3_BASE + (unsigned int)(o)) = (unsigned int)(v))
	113	+#define _V3Read32(o) ((volatile unsigned int )(PCI_V3_BASE + (unsigned int)(o)))
	114	+
	115	+// Compute address necessary to access PCI config space for the given
	116	+// bus and device.
	117	+#define PCI_CONFIG_ADDRESS( __bus, __devfn, __offset ) \
	118	+ ({ \
	119	+ unsigned int __address, __devicebit; \
	120	+ unsigned short __mapaddress; \
	121	+ unsigned int __dev = PCI_DEV(__devfn); /* FIXME to check!! (slot?) */ \
	122	+ \
	123	+ if (__bus == 0) { \
	124	+ /* local bus segment so need a type 0 config cycle */ \
	125	+ /* build the PCI configuration "address" with one-hot in A31-A11 */ \
	126	+ __address = PCI_CONFIG_BASE; \
	127	+ __address \|= ((__devfn & 0x07) << 8); \
	128	+ __address \|= __offset & 0xFF; \
	129	+ __mapaddress = 0x000A; /* 101=>config cycle, 0=>A1=A0=0 */ \
	130	+ __devicebit = (1 << (__dev + 11)); \
	131	+ \
	132	+ if ((__devicebit & 0xFF000000) != 0) { \
	133	+ /* high order bits are handled by the MAP register */ \
	134	+ __mapaddress \|= (__devicebit >> 16); \
	135	+ } else { \
	136	+ /* low order bits handled directly in the address */ \
	137	+ __address \|= __devicebit; \
	138	+ } \
	139	+ } else { /* bus !=0 */ \
	140	+ /* not the local bus segment so need a type 1 config cycle */ \
	141	+ /* A31-A24 are don't care (so clear to 0) */ \
	142	+ __mapaddress = 0x000B; /* 101=>config cycle, 1=>A1&A0 from PCI_CFG */ \
	143	+ __address = PCI_CONFIG_BASE; \
	144	+ __address \|= ((__bus & 0xFF) << 16); /* bits 23..16 = bus number */ \
	145	+ __address \|= ((__dev & 0x1F) << 11); /* bits 15..11 = device number */ \
	146	+ __address \|= ((__devfn & 0x07) << 8); /* bits 10..8 = function number*/ \
	147	+ __address \|= __offset & 0xFF; /* bits 7..0 = register number*/ \
	148	+ } \
	149	+ _V3Write16(V3_LB_MAP1, __mapaddress); \
	150	+ \
	151	+ __address; \
	152	+ })
	153	+
	154	+// _V3OpenConfigWindow - open V3 configuration window
	155	+#define _V3OpenConfigWindow() \
	156	+ { \
	157	+ /* Set up base0 to see all 512Mbytes of memory space (not */ \
	158	+ /* prefetchable), this frees up base1 for re-use by configuration*/ \
	159	+ /* memory */ \
	160	+ \
	161	+ _V3Write32 (V3_LB_BASE0, ((INTEGRATOR_PCI_BASE & 0xFFF00000) \| \
	162	+ 0x90 \| V3_LB_BASE_M_ENABLE)); \
	163	+ /* Set up base1 to point into configuration space, note that MAP1 */ \
	164	+ /* register is set up by pciMakeConfigAddress(). */ \
	165	+ \
	166	+ _V3Write32 (V3_LB_BASE1, ((CPU_PCI_CNFG_ADRS & 0xFFF00000) \| \
	167	+ 0x40 \| V3_LB_BASE_M_ENABLE)); \
	168	+ }
	169	+
	170	+// _V3CloseConfigWindow - close V3 configuration window
	171	+#define _V3CloseConfigWindow() \
	172	+ { \
	173	+ /* Reassign base1 for use by prefetchable PCI memory */ \
	174	+ _V3Write32 (V3_LB_BASE1, (((INTEGRATOR_PCI_BASE + 0x10000000) & 0xFFF00000) \
	175	+ \| 0x84 \| V3_LB_BASE_M_ENABLE)); \
	176	+ _V3Write16 (V3_LB_MAP1, \
	177	+ (((INTEGRATOR_PCI_BASE + 0x10000000) & 0xFFF00000) >> 16) \| 0x0006); \
	178	+ \
	179	+ /* And shrink base0 back to a 256M window (NOTE: MAP0 already correct) */ \
	180	+ \
	181	+ _V3Write32 (V3_LB_BASE0, ((INTEGRATOR_PCI_BASE & 0xFFF00000) \| \
	182	+ 0x80 \| V3_LB_BASE_M_ENABLE)); \
	183	+ }
	184	+
	185	+
	186	+static int pci_integrator_read_byte(struct pci_controller *hose, pci_dev_t dev,
	187	+ int offset, unsigned char *val)
	188	+{
	189	+ _V3OpenConfigWindow();
	190	+ val = (volatile unsigned char *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset);
	191	+ _V3CloseConfigWindow();
	192	+
	193	+ return 0;
	194	+}
	195	+
	196	+static int pci_integrator_read__word(struct pci_controller *hose, pci_dev_t dev,
	197	+ int offset, unsigned short *val)
	198	+{
	199	+ _V3OpenConfigWindow();
	200	+ val = (volatile unsigned short *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset);
	201	+ _V3CloseConfigWindow();
	202	+
	203	+ return 0;
	204	+}
	205	+
	206	+static int pci_integrator_read_dword(struct pci_controller *hose, pci_dev_t dev,
	207	+ int offset, unsigned int *val)
	208	+{
	209	+ _V3OpenConfigWindow();
	210	+ val = (volatile unsigned short *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset);
	211	+ val \|= ((volatile unsigned int *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), (offset+2))) << 16;
	212	+ _V3CloseConfigWindow();
	213	+
	214	+ return 0;
	215	+}
	216	+
	217	+static int pci_integrator_write_byte(struct pci_controller *hose, pci_dev_t dev,
	218	+ int offset, unsigned char val)
	219	+{
	220	+ _V3OpenConfigWindow();
	221	+ (volatile unsigned char )PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset) = val;
	222	+ _V3CloseConfigWindow();
	223	+
	224	+ return 0;
	225	+}
	226	+
	227	+static int pci_integrator_write_word(struct pci_controller *hose, pci_dev_t dev,
	228	+ int offset,unsigned short val)
	229	+{
	230	+ _V3OpenConfigWindow();
	231	+ (volatile unsigned short )PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset) = val;
	232	+ _V3CloseConfigWindow();
	233	+
	234	+ return 0;
	235	+}
	236	+
	237	+static int pci_integrator_write_dword(struct pci_controller *hose, pci_dev_t dev,
	238	+ int offset, unsigned int val)
	239	+{
	240	+ _V3OpenConfigWindow();
	241	+ (volatile unsigned short )PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset) = (val & 0xFFFF);
	242	+ (volatile unsigned short )PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), (offset + 2)) = ((val >> 16) & 0xFFFF);
	243	+ _V3CloseConfigWindow();
	244	+
	245	+ return 0;
	246	+}
	247	+
	248	+/******************************
	249	+ * PCI initialisation
	250	+ ******************************/
	251	+
	252	+struct pci_controller integrator_hose = {
	253	+#ifndef CONFIG_PCI_PNP
	254	+ config_table: pci_integrator_config_table,
	255	+#endif
	256	+};
	257	+
	258	+void pci_init_board(void)
	259	+{
	260	+ volatile int i, j;
	261	+ struct pci_controller *hose = &integrator_hose;
	262	+
	263	+ /* setting this register will take the V3 out of reset */
	264	+
	265	+ (volatile unsigned int )(INTEGRATOR_SC_PCIENABLE) = 1;
	266	+
	267	+ /* wait a few usecs to settle the device and the PCI bus */
	268	+
	269	+ for (i = 0; i < 100 ; i++)
	270	+ j = i + 1;
	271	+
	272	+ /* Now write the Base I/O Address Word to V3_BASE + 0x6C */
	273	+
	274	+ (volatile unsigned short )(V3_BASE + V3_LB_IO_BASE) = (unsigned short)(V3_BASE >> 16);
	275	+
	276	+ do {
	277	+ (volatile unsigned char )(V3_BASE + V3_MAIL_DATA) = 0xAA;
	278	+ (volatile unsigned char )(V3_BASE + V3_MAIL_DATA + 4) = 0x55;
	279	+ } while ((volatile unsigned char )(V3_BASE + V3_MAIL_DATA) != 0xAA \|\|
	280	+ (volatile unsigned char )(V3_BASE + V3_MAIL_DATA + 4) != 0x55);
	281	+
	282	+ /* Make sure that V3 register access is not locked, if it is, unlock it */
	283	+
	284	+ if (((volatile unsigned short )(V3_BASE + V3_SYSTEM) & V3_SYSTEM_M_LOCK)
	285	+ == V3_SYSTEM_M_LOCK)
	286	+ (volatile unsigned short )(V3_BASE + V3_SYSTEM) = 0xA05F;
	287	+
	288	+ /* Ensure that the slave accesses from PCI are disabled while we */
	289	+ /* setup windows */
	290	+
	291	+ (volatile unsigned short )(V3_BASE + V3_PCI_CMD) &=
	292	+ ~(V3_COMMAND_M_MEM_EN \| V3_COMMAND_M_IO_EN);
	293	+
	294	+ /* Clear RST_OUT to 0; keep the PCI bus in reset until we've finished */
	295	+
	296	+ (volatile unsigned short )(V3_BASE + V3_SYSTEM) &= ~V3_SYSTEM_M_RST_OUT;
	297	+
	298	+ /* Make all accesses from PCI space retry until we're ready for them */
	299	+
	300	+ (volatile unsigned short )(V3_BASE + V3_PCI_CFG) \|= V3_PCI_CFG_M_RETRY_EN;
	301	+
	302	+ /* Set up any V3 PCI Configuration Registers that we absolutely have to */
	303	+ /* LB_CFG controls Local Bus protocol. */
	304	+ /* Enable LocalBus byte strobes for READ accesses too. */
	305	+ /* set bit 7 BE_IMODE and bit 6 BE_OMODE */
	306	+
	307	+ (volatile unsigned short )(V3_BASE + V3_LB_CFG) \|= 0x0C0;
	308	+
	309	+ /* PCI_CMD controls overall PCI operation. */
	310	+ /* Enable PCI bus master. */
	311	+
	312	+ (volatile unsigned short )(V3_BASE + V3_PCI_CMD) \|= 0x04;
	313	+
	314	+ /* PCI_MAP0 controls where the PCI to CPU memory window is on Local Bus*/
	315	+
	316	+ (volatile unsigned int )(V3_BASE + V3_PCI_MAP0) = (INTEGRATOR_BOOT_ROM_BASE) \|
	317	+ (V3_PCI_MAP_M_ADR_SIZE_512M \|
	318	+ V3_PCI_MAP_M_REG_EN \|
	319	+ V3_PCI_MAP_M_ENABLE);
	320	+
	321	+ /* PCI_BASE0 is the PCI address of the start of the window */
	322	+
	323	+ (volatile unsigned int )(V3_BASE + V3_PCI_BASE0) = INTEGRATOR_BOOT_ROM_BASE;
	324	+
	325	+ /* PCI_MAP1 is LOCAL address of the start of the window */
	326	+
	327	+ (volatile unsigned int )(V3_BASE + V3_PCI_MAP1) = (INTEGRATOR_HDR0_SDRAM_BASE) \|
	328	+ (V3_PCI_MAP_M_ADR_SIZE_1024M \| V3_PCI_MAP_M_REG_EN \|
	329	+ V3_PCI_MAP_M_ENABLE);
	330	+
	331	+ /* PCI_BASE1 is the PCI address of the start of the window */
	332	+
	333	+ (volatile unsigned int )(V3_BASE + V3_PCI_BASE1) = INTEGRATOR_HDR0_SDRAM_BASE;
	334	+
	335	+ /* Set up the windows from local bus memory into PCI configuration, */
	336	+ /* I/O and Memory. */
	337	+ /* PCI I/O, LB_BASE2 and LB_MAP2 are used exclusively for this. */
	338	+
	339	+ (volatile unsigned short )(V3_BASE +V3_LB_BASE2) =
	340	+ ((CPU_PCI_IO_ADRS >> 24) << 8) \| V3_LB_BASE_M_ENABLE;
	341	+ (volatile unsigned short )(V3_BASE + V3_LB_MAP2) = 0;
	342	+
	343	+ /* PCI Configuration, use LB_BASE1/LB_MAP1. */
	344	+
	345	+ /* PCI Memory use LB_BASE0/LB_MAP0 and LB_BASE1/LB_MAP1 */
	346	+ /* Map first 256Mbytes as non-prefetchable via BASE0/MAP0 */
	347	+ /* (INTEGRATOR_PCI_BASE == PCI_MEM_BASE) */
	348	+
	349	+ (volatile unsigned int )(V3_BASE + V3_LB_BASE0) =
	350	+ INTEGRATOR_PCI_BASE \| (0x80 \| V3_LB_BASE_M_ENABLE);
	351	+
	352	+ (volatile unsigned short )(V3_BASE + V3_LB_MAP0) =
	353	+ ((INTEGRATOR_PCI_BASE >> 20) << 0x4) \| 0x0006;
	354	+
	355	+ /* Map second 256 Mbytes as prefetchable via BASE1/MAP1 */
	356	+
	357	+ (volatile unsigned int )(V3_BASE + V3_LB_BASE1) =
	358	+ INTEGRATOR_PCI_BASE \| (0x84 \| V3_LB_BASE_M_ENABLE);
	359	+
	360	+ (volatile unsigned short )(V3_BASE + V3_LB_MAP1) =
	361	+ (((INTEGRATOR_PCI_BASE + 0x10000000) >> 20) << 4) \| 0x0006;
	362	+
	363	+ /* Allow accesses to PCI Configuration space */
	364	+ /* and set up A1, A0 for type 1 config cycles */
	365	+
	366	+ (volatile unsigned short )(V3_BASE + V3_PCI_CFG) =
	367	+ (((volatile unsigned short )(V3_BASE + V3_PCI_CFG)) &
	368	+ ~(V3_PCI_CFG_M_RETRY_EN \| V3_PCI_CFG_M_AD_LOW1) ) \|
	369	+ V3_PCI_CFG_M_AD_LOW0;
	370	+
	371	+ /* now we can allow in PCI MEMORY accesses */
	372	+
	373	+ (volatile unsigned short )(V3_BASE + V3_PCI_CMD) =
	374	+ ((volatile unsigned short )(V3_BASE + V3_PCI_CMD)) \| V3_COMMAND_M_MEM_EN;
	375	+
	376	+ /* Set RST_OUT to take the PCI bus is out of reset, PCI devices can */
	377	+ /* initialise and lock the V3 system register so that no one else */
	378	+ /* can play with it */
	379	+
	380	+ (volatile unsigned short )(V3_BASE + V3_SYSTEM) =
	381	+ ((volatile unsigned short )(V3_BASE + V3_SYSTEM)) \| V3_SYSTEM_M_RST_OUT;
	382	+
	383	+ (volatile unsigned short )(V3_BASE + V3_SYSTEM) =
	384	+ ((volatile unsigned short )(V3_BASE + V3_SYSTEM)) \| V3_SYSTEM_M_LOCK;
	385	+
	386	+ /*
	387	+ * Register the hose
	388	+ */
	389	+ hose->first_busno = 0;
	390	+ hose->last_busno = 0xff;
	391	+
	392	+ /* System memory space */
	393	+ pci_set_region(hose->regions + 0,
	394	+ 0x00000000, 0x40000000, 0x01000000,
	395	+ PCI_REGION_MEM \| PCI_REGION_MEMORY);
	396	+
	397	+ /* PCI Memory - config space */
	398	+ pci_set_region(hose->regions + 1,
	399	+ 0x00000000, 0x62000000, 0x01000000,
	400	+ PCI_REGION_MEM);
	401	+
	402	+ /* PCI V3 regs */
	403	+ pci_set_region(hose->regions + 2,
	404	+ 0x00000000, 0x61000000, 0x00080000,
	405	+ PCI_REGION_MEM);
	406	+
	407	+ /* PCI I/O space */
	408	+ pci_set_region(hose->regions + 3,
	409	+ 0x00000000, 0x60000000, 0x00010000,
	410	+ PCI_REGION_IO);
	411	+
	412	+ pci_set_ops(hose,
	413	+ pci_integrator_read_byte,
	414	+ pci_integrator_read__word,
	415	+ pci_integrator_read_dword,
	416	+ pci_integrator_write_byte,
	417	+ pci_integrator_write_word,
	418	+ pci_integrator_write_dword);
	419	+
	420	+ hose->region_count = 4;
	421	+
	422	+ pci_register_hose(hose);
	423	+
	424	+ pciauto_config_init(hose);
	425	+ pciauto_config_device(hose, 0);
	426	+
	427	+ hose->last_busno = pci_hose_scan(hose);
	428	+}
	429	+#endif
	430	+
	431	+/******************************
	432	+ Routine:
	433	+ Description:
	434	+******************************/
	435	+void flash__init (void)
	436	+{
	437	+}
	438	+/*************************************************************
	439	+ Routine:ether__init
	440	+ Description: take the Ethernet controller out of reset and wait
	441	+ for the EEPROM load to complete.
	442	+*************************************************************/
	443	+void ether__init (void)
	444	+{
	445	+}
	446	+
	447	+/******************************
	448	+ Routine:
	449	+ Description:
	450	+******************************/
	451	+int dram_init (void)
	452	+{
	453	+ return 0;
	454	+}
	1	+/*
	2	+ * Board specific setup info
	3	+ *
	4	+ * (C) Copyright 2004, ARM Ltd.
	5	+ * Philippe Robin, <philippe.robin@arm.com>
	6	+ *
	7	+ * See file CREDITS for list of people who contributed to this
	8	+ * project.
	9	+ *
	10	+ * This program is free software; you can redistribute it and/or
	11	+ * modify it under the terms of the GNU General Public License as
	12	+ * published by the Free Software Foundation; either version 2 of
	13	+ * the License, or (at your option) any later version.
	14	+ *
	15	+ * This program is distributed in the hope that it will be useful,
	16	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	+ * GNU General Public License for more details.
	19	+ *
	20	+ * You should have received a copy of the GNU General Public License
	21	+ * along with this program; if not, write to the Free Software
	22	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	+ * MA 02111-1307 USA
	24	+ */
	25	+
	26	+#include <config.h>
	27	+#include <version.h>
	28	+
	29	+.globl platformsetup
	30	+platformsetup:
	31	+
	32	+ /* All done by Integrator's boot monitor! */
	33	+ mov pc, lr
	1	+/*
	2	+ * (C) Copyright 2002
	3	+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
	4	+ *
	5	+ * See file CREDITS for list of people who contributed to this
	6	+ * project.
	7	+ *
	8	+ * This program is free software; you can redistribute it and/or
	9	+ * modify it under the terms of the GNU General Public License as
	10	+ * published by the Free Software Foundation; either version 2 of
	11	+ * the License, or (at your option) any later version.
	12	+ *
	13	+ * This program is distributed in the hope that it will be useful,
	14	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+ * GNU General Public License for more details.
	17	+ *
	18	+ * You should have received a copy of the GNU General Public License
	19	+ * along with this program; if not, write to the Free Software
	20	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+ * MA 02111-1307 USA
	22	+ */
	23	+
	24	+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
	25	+OUTPUT_ARCH(arm)
	26	+ENTRY(_start)
	27	+SECTIONS
	28	+{
	29	+ . = 0x00000000;
	30	+ . = ALIGN(4);
	31	+ .text :
	32	+ {
	33	+ cpu/arm926ejs/start.o (.text)
	34	+ *(.text)
	35	+ }
	36	+ .rodata : { *(.rodata) }
	37	+ . = ALIGN(4);
	38	+ .data : { *(.data) }
	39	+ . = ALIGN(4);
	40	+ .got : { *(.got) }
	41	+
	42	+ __u_boot_cmd_start = .;
	43	+ .u_boot_cmd : { *(.u_boot_cmd) }
	44	+ __u_boot_cmd_end = .;
	45	+
	46	+ armboot_end_data = .;
	47	+ . = ALIGN(4);
	48	+ .bss : { *(.bss) }
	49	+ armboot_end = .;
	50	+}
	1	+/*
	2	+ * Board specific setup info
	3	+ *
	4	+ * (C) Copyright 2003, ARM Ltd.
	5	+ * Philippe Robin, <philippe.robin@arm.com>
	6	+ *
	7	+ * See file CREDITS for list of people who contributed to this
	8	+ * project.
	9	+ *
	10	+ * This program is free software; you can redistribute it and/or
	11	+ * modify it under the terms of the GNU General Public License as
	12	+ * published by the Free Software Foundation; either version 2 of
	13	+ * the License, or (at your option) any later version.
	14	+ *
	15	+ * This program is distributed in the hope that it will be useful,
	16	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	+ * GNU General Public License for more details.
	19	+ *
	20	+ * You should have received a copy of the GNU General Public License
	21	+ * along with this program; if not, write to the Free Software
	22	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	+ * MA 02111-1307 USA
	24	+ */
	25	+
	26	+#include <config.h>
	27	+#include <version.h>
	28	+
	29	+.globl platformsetup
	30	+platformsetup:
	31	+
	32	+ /* All done by IntegratorCP's boot monitor! */
	33	+ mov pc, lr