Commit 3d5bbbc47190071a69fca817647ed3ec13a36d81

Authored by Bin Meng
Committed by Simon Glass
1 parent 99a309f323

x86: Set CONFIG_NR_DRAM_BANKS to 8 and move it to x86-common.h

Some x86 boards set CONFIG_NR_DRAM_BANKS to 1, which causes incorrect
DRAM size printed when booting from coreboot, like this:

	CPU: x86, vendor Intel, device 663h
	DRAM:  636 KiB
	Using default environment

Change it to 8 which should be enough for both coreboot and bare
cases, and move it to x86-common.h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

Showing 6 changed files with 1 additions and 9 deletions Side-by-side Diff

include/configs/crownbay.h
... ... @@ -17,8 +17,6 @@
17 17 #define CONFIG_BOARD_EARLY_INIT_F
18 18 #define CONFIG_ARCH_MISC_INIT
19 19  
20   -#define CONFIG_NR_DRAM_BANKS 1
21   -
22 20 #define CONFIG_X86_SERIAL
23 21 #define CONFIG_SMSC_LPC47M
24 22  
include/configs/galileo.h
... ... @@ -16,8 +16,6 @@
16 16 #define CONFIG_SYS_MONITOR_LEN (1 << 20)
17 17 #define CONFIG_BOARD_EARLY_INIT_F
18 18  
19   -#define CONFIG_NR_DRAM_BANKS 1
20   -
21 19 #define CONFIG_X86_SERIAL
22 20  
23 21 /* ns16550 UART is memory-mapped in Quark SoC */
include/configs/minnowmax.h
... ... @@ -16,8 +16,6 @@
16 16 #define CONFIG_SYS_MONITOR_LEN (1 << 20)
17 17 #define CONFIG_BOARD_EARLY_INIT_F
18 18  
19   -#define CONFIG_NR_DRAM_BANKS 1
20   -
21 19 #define CONFIG_X86_SERIAL
22 20 #define CONFIG_SMSC_LPC47M
23 21  
include/configs/qemu-x86.h
... ... @@ -15,8 +15,6 @@
15 15  
16 16 #define CONFIG_SYS_MONITOR_LEN (1 << 20)
17 17  
18   -#define CONFIG_NR_DRAM_BANKS 1
19   -
20 18 #define CONFIG_X86_SERIAL
21 19  
22 20 #define CONFIG_PCI_MEM_BUS 0xc0000000
include/configs/x86-chromebook.h
... ... @@ -14,7 +14,6 @@
14 14 #define CONFIG_BOARD_EARLY_INIT_F
15 15 #define CONFIG_MISC_INIT_R
16 16  
17   -#define CONFIG_NR_DRAM_BANKS 8
18 17 #define CONFIG_X86_MRC_ADDR 0xfffa0000
19 18 #define CONFIG_CACHE_MRC_SIZE_KB 512
20 19  
include/configs/x86-common.h
... ... @@ -21,6 +21,7 @@
21 21 #define CONFIG_DISPLAY_BOARDINFO_LATE
22 22 #define CONFIG_DISPLAY_CPUINFO
23 23 #define CONFIG_LAST_STAGE_INIT
  24 +#define CONFIG_NR_DRAM_BANKS 8
24 25  
25 26 #define CONFIG_LMB
26 27 #define CONFIG_OF_LIBFDT