Commit 3e38691e8f7aa0d9b498d76c7279ddec6e4946f3
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* Patch by Arun Dharankar, 4 Apr 2003:
Add IDMA example code (tested on 8260 only) * Add support for Purple Board (MIPS64 5Kc) * Add support for MIPS64 5Kc CPUs * Fix missing setting of "loadaddr" and "bootfile" on ARM and MIPS * Patch by Denis Peter, 04 Apr 2003: - update MIP405-4 board * Patches by Denis Peter, 03 April 2003: - fix PCI IRQs on MPL boards - fix two more un-relocated pointer problems * Fix behaviour of "run" command: - print error message iv variable does not exist - terminate processing of arguments in case of error * Patches by Peter Figuli, 10 Mar 2003 - Add support for BTUART on PXA platform - Add support for WEP EP250 (PXA) board * Fix flash problems on INCA-IP; add tool to allow bruning images to flash using a BDI2000 * Implement fix for I2C Edge Conditions problem for all boards that use the bit-banging driver (common/soft_i2c.c) * Add patches by Robert Schwebel, 31 Mar 2003: - csb226 board: bring in sync with innokom/memsetup.S - csb226 board: fix MDREFR handling - misc doc fixes / extensions - innokom board: cleanup, MDREFR fix in memsetup.S, config update - add BOOT_PROGRESS to armlinux.c
Showing 52 changed files with 2061 additions and 448 deletions Side-by-side Diff
- CHANGELOG
- CREDITS
- MAINTAINERS
- MAKEALL
- Makefile
- README
- board/csb226/memsetup.S
- board/innokom/flash.c
- board/innokom/innokom.c
- board/innokom/memsetup.S
- board/mpl/common/pci.c
- board/mpl/mip405/mip405.c
- board/svm_sc8xx/ppcboot.lds
- board/svm_sc8xx/ppcboot.lds.debug
- board/wepep250/Makefile
- board/wepep250/config.mk
- board/wepep250/flash.c
- board/wepep250/intel.h
- board/wepep250/memsetup.S
- board/wepep250/u-boot.lds
- board/wepep250/wepep250.c
- common/cmd_date.c
- common/hush.c
- common/main.c
- cpu/mips/cache.S
- cpu/mips/cpu.c
- cpu/mips/serial.c
- cpu/mips/start.S
- cpu/xscale/serial.c
- doc/I2C_Edge_Conditions
- doc/README.INCA-IP
- doc/README.idma2intr
- doc/README.sched
- drivers/ct69000.c
- examples/Makefile
- examples/mem_to_mem_idma2intr.c
- examples/ppc_longjmp.S
- examples/ppc_setjmp.S
- examples/sched.c
- include/asm-mips/inca-ip.h
- include/cmd_net.h
- include/configs/MIP405.h
- include/configs/PIP405.h
- include/configs/incaip.h
- include/configs/innokom.h
- include/configs/wepep250.h
- lib_arm/board.c
- lib_mips/board.c
- net/bootp.c
- net/eth.c
- tools/Makefile
- tools/inca-swap-bytes.c
CHANGELOG
... | ... | @@ -2,12 +2,42 @@ |
2 | 2 | Changes since U-Boot 0.2.2: |
3 | 3 | ====================================================================== |
4 | 4 | |
5 | +* Patch by Arun Dharankar, 4 Apr 2003: | |
6 | + Add IDMA example code (tested on 8260 only) | |
7 | + | |
8 | +* Add support for Purple Board (MIPS64 5Kc) | |
9 | + | |
10 | +* Add support for MIPS64 5Kc CPUs | |
11 | + | |
12 | +* Fix missing setting of "loadaddr" and "bootfile" on ARM and MIPS | |
13 | + | |
14 | +* Patch by Denis Peter, 04 Apr 2003: | |
15 | + - update MIP405-4 board | |
16 | + | |
5 | 17 | * Patch by Stefan Roese, 4 Apr 2003: |
6 | 18 | - U-Boot version environment variable "ver" added |
7 | 19 | (CONFIG_VERSION_VARIABLE). |
8 | 20 | - Changed PPC405GPr version from A to B. |
9 | 21 | - Changed CPCI405 to use CTS instead of DSR on PPC405 UART1. |
10 | 22 | |
23 | +* Patches by Denis Peter, 03 April 2003: | |
24 | + - fix PCI IRQs on MPL boards | |
25 | + - fix two more un-relocated pointer problems | |
26 | + | |
27 | +* Fix behaviour of "run" command: | |
28 | + - print error message iv variable does not exist | |
29 | + - terminate processing of arguments in case of error | |
30 | + | |
31 | +* Patches by Peter Figuli, 10 Mar 2003 | |
32 | + - Add support for BTUART on PXA platform | |
33 | + - Add support for WEP EP250 (PXA) board | |
34 | + | |
35 | +* Fix flash problems on INCA-IP; add tool to allow bruning images to | |
36 | + flash using a BDI2000 | |
37 | + | |
38 | +* Implement fix for I2C Edge Conditions problem for all boards that | |
39 | + use the bit-banging driver (common/soft_i2c.c) | |
40 | + | |
11 | 41 | * Patch by Martin Winistoerfer, 23 Mar 2003 |
12 | 42 | - Add port to MPC555/556 microcontrollers |
13 | 43 | - Add support for cmi customer board with |
... | ... | @@ -22,6 +52,11 @@ |
22 | 52 | * Add patches by Robert Schwebel, 31 Mar 2003: |
23 | 53 | - add ctrl-c support for kermit download |
24 | 54 | - align bdinfo output on ARM |
55 | + - csb226 board: bring in sync with innokom/memsetup.S | |
56 | + - csb226 board: fix MDREFR handling | |
57 | + - misc doc fixes / extensions | |
58 | + - innokom board: cleanup, MDREFR fix in memsetup.S, config update | |
59 | + - add BOOT_PROGRESS to armlinux.c | |
25 | 60 | |
26 | 61 | * Add CPU ID, version, and clock speed for INCA-IP |
27 | 62 |
CREDITS
... | ... | @@ -104,6 +104,10 @@ |
104 | 104 | D: Support for Interphase 4539 T1/E1/J1 PMC, PN62, CCM, SCM boards |
105 | 105 | W: www.denx.de |
106 | 106 | |
107 | +N: Peter Figuli | |
108 | +E: peposh@etc.sk | |
109 | +D: Support for WEP EP250 (PXA) board | |
110 | + | |
107 | 111 | N: Thomas Frieden |
108 | 112 | E: ThomasF@hyperion-entertainment.com |
109 | 113 | D: Support for AmigaOne |
MAINTAINERS
... | ... | @@ -241,6 +241,10 @@ |
241 | 241 | # Board CPU # |
242 | 242 | ######################################################################### |
243 | 243 | |
244 | +Peter Figuli <peposh@etc.sk> | |
245 | + | |
246 | + wepep250 xscale | |
247 | + | |
244 | 248 | Marius Grรถger <mag@sysgo.de> |
245 | 249 | |
246 | 250 | impa7 ARM720T (EP7211) |
... | ... | @@ -296,6 +300,7 @@ |
296 | 300 | Wolfgang Denk <wd@denx.de> |
297 | 301 | |
298 | 302 | incaip MIPS32 4Kc |
303 | + purple MIPS64 5Kc | |
299 | 304 | |
300 | 305 | ######################################################################### |
301 | 306 | # End of MAINTAINERS list # |
MAKEALL
... | ... | @@ -112,7 +112,7 @@ |
112 | 112 | ## Xscale Systems |
113 | 113 | ######################################################################### |
114 | 114 | |
115 | -LIST_xscale="cradle csb226 innokom lubbock" | |
115 | +LIST_xscale="cradle csb226 innokom lubbock wepep250" | |
116 | 116 | |
117 | 117 | |
118 | 118 | LIST_arm="${LIST_SA} ${LIST_ARM7} ${LIST_ARM9} ${LIST_xscale}" |
... | ... | @@ -123,7 +123,9 @@ |
123 | 123 | |
124 | 124 | LIST_mips4kc="incaip" |
125 | 125 | |
126 | -LIST_mips="${LIST_mips4kc}" | |
126 | +LIST_mips5kc="purple" | |
127 | + | |
128 | +LIST_mips="${LIST_mips4kc} ${LIST_mips5kc}" | |
127 | 129 | |
128 | 130 | |
129 | 131 | #----- for now, just run PPC by default ----- |
Makefile
... | ... | @@ -629,7 +629,6 @@ |
629 | 629 | ELPPC_config: unconfig |
630 | 630 | @./mkconfig $(@:_config=) ppc 74xx_7xx elppc eltec |
631 | 631 | |
632 | - | |
633 | 632 | #======================================================================== |
634 | 633 | # ARM |
635 | 634 | #======================================================================== |
... | ... | @@ -699,6 +698,9 @@ |
699 | 698 | lubbock_config : unconfig |
700 | 699 | @./mkconfig $(@:_config=) arm xscale lubbock |
701 | 700 | |
701 | +wepep250_config : unconfig | |
702 | + @./mkconfig $(@:_config=) arm xscale wepep250 | |
703 | + | |
702 | 704 | #======================================================================== |
703 | 705 | # i386 |
704 | 706 | #======================================================================== |
705 | 707 | |
... | ... | @@ -718,7 +720,11 @@ |
718 | 720 | incaip_config : unconfig |
719 | 721 | @./mkconfig $(@:_config=) mips mips incaip |
720 | 722 | |
723 | +purple_config : unconfig | |
724 | + @./mkconfig $(@:_config=) mips mips purple | |
721 | 725 | |
726 | +######################################################################### | |
727 | +######################################################################### | |
722 | 728 | |
723 | 729 | clean: |
724 | 730 | find . -type f \ |
... | ... | @@ -726,7 +732,8 @@ |
726 | 732 | -o -name '*.o' -o -name '*.a' \) -print \ |
727 | 733 | | xargs rm -f |
728 | 734 | rm -f examples/hello_world examples/timer \ |
729 | - examples/eepro100_eeprom examples/sched | |
735 | + examples/eepro100_eeprom examples/sched \ | |
736 | + examples/mem_to_mem_idma2intr | |
730 | 737 | rm -f tools/img2srec tools/mkimage tools/envcrc tools/gen_eth_addr |
731 | 738 | rm -f tools/easylogo/easylogo tools/bmp_logo |
732 | 739 | rm -f tools/gdb/astest tools/gdb/gdbcont tools/gdb/gdbsend |
... | ... | @@ -741,7 +748,7 @@ |
741 | 748 | rm -fr *.*~ |
742 | 749 | rm -f u-boot u-boot.bin u-boot.elf u-boot.srec u-boot.map System.map |
743 | 750 | rm -f tools/crc32.c tools/environment.c tools/env/crc32.c |
744 | - rm -f cpu/mpc824x/bedbug_603e.c | |
751 | + rm -f tools/inca-swap-bytes cpu/mpc824x/bedbug_603e.c | |
745 | 752 | rm -f include/asm/arch include/asm |
746 | 753 | |
747 | 754 | mrproper \ |
README
... | ... | @@ -1462,7 +1462,7 @@ |
1462 | 1462 | |
1463 | 1463 | These settings describe a second storage area used to hold |
1464 | 1464 | a redundand copy of the environment data, so that there is |
1465 | - a valid backup copy in case there is a power failur during | |
1465 | + a valid backup copy in case there is a power failure during | |
1466 | 1466 | a "saveenv" operation. |
1467 | 1467 | |
1468 | 1468 | BE CAREFUL! Any changes to the flash layout, and some changes to the |
board/csb226/memsetup.S
... | ... | @@ -38,7 +38,10 @@ |
38 | 38 | sub pc,pc,#4 |
39 | 39 | .endm |
40 | 40 | |
41 | +_TEXT_BASE: | |
42 | + .word TEXT_BASE | |
41 | 43 | |
44 | + | |
42 | 45 | /* |
43 | 46 | * Memory setup |
44 | 47 | */ |
45 | 48 | |
46 | 49 | |
47 | 50 | |
48 | 51 | |
49 | 52 | |
... | ... | @@ -222,25 +225,30 @@ |
222 | 225 | /* Step 2c: Write FLYCNFG FIXME: what's that??? */ |
223 | 226 | /* ---------------------------------------------------------------- */ |
224 | 227 | |
228 | + /* test if we run from flash or RAM - RAM/BDI: don't setup RAM */ | |
229 | + adr r3, mem_init /* r0 <- current position of code */ | |
230 | + ldr r2, =mem_init | |
231 | + cmp r3, r2 /* skip init if in place */ | |
232 | + beq initirqs | |
225 | 233 | |
234 | + | |
226 | 235 | /* ---------------------------------------------------------------- */ |
227 | 236 | /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ |
228 | 237 | /* ---------------------------------------------------------------- */ |
229 | 238 | |
230 | 239 | /* Before accessing MDREFR we need a valid DRI field, so we set */ |
231 | - /* this to power on defaults + DIR field. */ | |
240 | + /* this to power on defaults + DRI field. */ | |
232 | 241 | |
233 | - ldr r4, =0x03ca4fff | |
242 | + ldr r3, =CFG_MDREFR_VAL | |
243 | + ldr r2, =0xFFF | |
244 | + and r3, r3, r2 | |
245 | + ldr r4, =0x03ca4000 | |
246 | + orr r4, r4, r3 | |
247 | + | |
234 | 248 | str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ |
235 | 249 | ldr r4, [r1, #MDREFR_OFFSET] |
236 | 250 | |
237 | - ldr r4, =0x03ca4030 | |
238 | - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ | |
239 | - ldr r4, [r1, #MDREFR_OFFSET] | |
240 | 251 | |
241 | - /* Note: preserve the mdrefr value in r4 */ | |
242 | - | |
243 | - | |
244 | 252 | /* ---------------------------------------------------------------- */ |
245 | 253 | /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */ |
246 | 254 | /* ---------------------------------------------------------------- */ |
247 | 255 | |
248 | 256 | |
249 | 257 | |
... | ... | @@ -258,18 +266,16 @@ |
258 | 266 | /* Step 4: Initialize SDRAM */ |
259 | 267 | /* ---------------------------------------------------------------- */ |
260 | 268 | |
261 | - /* Step 4a: assert MDREFR:K1RUN and MDREFR:K2RUN and configure */ | |
269 | + /* Step 4a: assert MDREFR:K?RUN and configure */ | |
262 | 270 | /* MDREFR:K1DB2 and MDREFR:K2DB2 as desired. */ |
263 | 271 | |
264 | - orr r4, r4, #(MDREFR_K1RUN|MDREFR_K0RUN) | |
272 | + ldr r4, =CFG_MDREFR_VAL | |
273 | + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ | |
274 | + ldr r4, [r1, #MDREFR_OFFSET] | |
265 | 275 | |
266 | - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ | |
267 | - ldr r4, [r1, #MDREFR_OFFSET] | |
268 | - | |
269 | - | |
270 | 276 | /* Step 4b: de-assert MDREFR:SLFRSH. */ |
271 | 277 | |
272 | - bic r4, r4, #(MDREFR_SLFRSH) | |
278 | + bic r4, r4, #(MDREFR_SLFRSH) | |
273 | 279 | |
274 | 280 | str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ |
275 | 281 | ldr r4, [r1, #MDREFR_OFFSET] |
board/innokom/flash.c
... | ... | @@ -10,7 +10,8 @@ |
10 | 10 | * Robert Schwebel, Pengutronix, <r.schwebel@pengutronix.de> |
11 | 11 | * |
12 | 12 | * (C) Copyright 2002 |
13 | - * Kai-Uwe Bloem, GDS, <kai-uwe.bloem@auerswald.de> | |
13 | + * Auerswald GmbH & Co KG, Germany | |
14 | + * Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de> | |
14 | 15 | * |
15 | 16 | * See file CREDITS for list of people who contributed to this |
16 | 17 | * project. |
board/innokom/innokom.c
... | ... | @@ -48,7 +48,7 @@ |
48 | 48 | icr = ICR; ICR &= ~(ICR_SCLE | ICR_IUE); |
49 | 49 | |
50 | 50 | /* set gpio pin low _before_ we change direction to output */ |
51 | - GPCR(70) = GPIO_bit(70); | |
51 | + GPCR(70) = GPIO_bit(70); | |
52 | 52 | |
53 | 53 | /* now toggle between output=low and high-impedance */ |
54 | 54 | for (i = 0; i < 20; i++) { |
55 | 55 | |
56 | 56 | |
... | ... | @@ -100,13 +100,8 @@ |
100 | 100 | /* memory and cpu-speed are setup before relocation */ |
101 | 101 | /* so we do _nothing_ here */ |
102 | 102 | |
103 | - /* arch number of Innokom board */ | |
104 | 103 | gd->bd->bi_arch_number = MACH_TYPE_INNOKOM; |
105 | - | |
106 | - /* adress of boot parameters */ | |
107 | 104 | gd->bd->bi_boot_params = 0xa0000100; |
108 | - | |
109 | - /* baud rate */ | |
110 | 105 | gd->bd->bi_baudrate = CONFIG_BAUDRATE; |
111 | 106 | |
112 | 107 | return 0; |
board/innokom/memsetup.S
... | ... | @@ -237,19 +237,18 @@ |
237 | 237 | /* ---------------------------------------------------------------- */ |
238 | 238 | |
239 | 239 | /* Before accessing MDREFR we need a valid DRI field, so we set */ |
240 | - /* this to power on defaults + DIR field. */ | |
240 | + /* this to power on defaults + DRI field. */ | |
241 | 241 | |
242 | - ldr r4, =0x03ca4fff | |
242 | + ldr r3, =CFG_MDREFR_VAL | |
243 | + ldr r2, =0xFFF | |
244 | + and r3, r3, r2 | |
245 | + ldr r4, =0x03ca4000 | |
246 | + orr r4, r4, r3 | |
247 | + | |
243 | 248 | str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ |
244 | 249 | ldr r4, [r1, #MDREFR_OFFSET] |
245 | 250 | |
246 | - ldr r4, =0x03ca4030 | |
247 | - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ | |
248 | - ldr r4, [r1, #MDREFR_OFFSET] | |
249 | 251 | |
250 | - /* Note: preserve the mdrefr value in r4 */ | |
251 | - | |
252 | - | |
253 | 252 | /* ---------------------------------------------------------------- */ |
254 | 253 | /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */ |
255 | 254 | /* ---------------------------------------------------------------- */ |
256 | 255 | |
257 | 256 | |
258 | 257 | |
... | ... | @@ -267,18 +266,16 @@ |
267 | 266 | /* Step 4: Initialize SDRAM */ |
268 | 267 | /* ---------------------------------------------------------------- */ |
269 | 268 | |
270 | - /* Step 4a: assert MDREFR:K1RUN and MDREFR:K2RUN and configure */ | |
269 | + /* Step 4a: assert MDREFR:K?RUN and configure */ | |
271 | 270 | /* MDREFR:K1DB2 and MDREFR:K2DB2 as desired. */ |
272 | 271 | |
273 | - orr r4, r4, #(MDREFR_K1RUN|MDREFR_K0RUN) | |
272 | + ldr r4, =CFG_MDREFR_VAL | |
273 | + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ | |
274 | + ldr r4, [r1, #MDREFR_OFFSET] | |
274 | 275 | |
275 | - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ | |
276 | - ldr r4, [r1, #MDREFR_OFFSET] | |
277 | - | |
278 | - | |
279 | 276 | /* Step 4b: de-assert MDREFR:SLFRSH. */ |
280 | 277 | |
281 | - bic r4, r4, #(MDREFR_SLFRSH) | |
278 | + bic r4, r4, #(MDREFR_SLFRSH) | |
282 | 279 | |
283 | 280 | str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ |
284 | 281 | ldr r4, [r1, #MDREFR_OFFSET] |
board/mpl/common/pci.c
... | ... | @@ -65,21 +65,22 @@ |
65 | 65 | static void pci_pip405_fixup_irq(struct pci_controller *hose, pci_dev_t dev) |
66 | 66 | { |
67 | 67 | unsigned char int_line = 0xff; |
68 | + unsigned char pin; | |
68 | 69 | /* |
69 | 70 | * Write pci interrupt line register |
70 | 71 | */ |
71 | 72 | if(PCI_DEV(dev)==0) /* Device0 = PPC405 -> skip */ |
72 | 73 | return; |
73 | - if(PCI_FUNC(dev)==0) | |
74 | - { | |
75 | - /* assuming all function 0 are using their INTA# Pin*/ | |
76 | - int_line=PCI_IRQ_VECTOR(dev); | |
77 | - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line); | |
74 | + pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin); | |
75 | + if ((pin == 0) || (pin > 4)) | |
76 | + return; | |
77 | + | |
78 | + int_line = ((PCI_DEV(dev) + (pin-1) + 10) % 4) + 28; | |
79 | + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line); | |
78 | 80 | #ifdef DEBUG |
79 | - printf("Fixup IRQ: dev %d (%x) int line %d 0x%x\n", | |
80 | - PCI_DEV(dev),dev,int_line,int_line); | |
81 | + printf("Fixup IRQ: dev %d (%x) int line %d 0x%x\n", | |
82 | + PCI_DEV(dev),dev,int_line,int_line); | |
81 | 83 | #endif |
82 | - } | |
83 | 84 | } |
84 | 85 | |
85 | 86 | extern void pci_405gp_init(struct pci_controller *hose); |
86 | 87 | |
... | ... | @@ -90,11 +91,34 @@ |
90 | 91 | fixup_irq: pci_pip405_fixup_irq, |
91 | 92 | }; |
92 | 93 | |
94 | + | |
95 | +static void reloc_pci_cfg_table(struct pci_config_table *table) | |
96 | +{ | |
97 | + DECLARE_GLOBAL_DATA_PTR; | |
98 | + unsigned long addr; | |
99 | + | |
100 | + for (; table && table->vendor; table++) { | |
101 | + addr = (ulong) (table->config_device) + gd->reloc_off; | |
102 | +#ifdef DEBUG | |
103 | + printf ("device \"%d\": 0x%08lx => 0x%08lx\n", | |
104 | + table->device, (ulong) (table->config_device), addr); | |
105 | +#endif | |
106 | + table->config_device = | |
107 | + (void (*)(struct pci_controller* hose, pci_dev_t dev, | |
108 | + struct pci_config_table *))addr; | |
109 | + table->priv[0]+=gd->reloc_off; | |
110 | + } | |
111 | +} | |
112 | + | |
93 | 113 | void pci_init_board(void) |
94 | 114 | { |
95 | 115 | /*we want the ptrs to RAM not flash (ie don't use init list)*/ |
96 | 116 | hose.fixup_irq = pci_pip405_fixup_irq; |
97 | 117 | hose.config_table = pci_pip405_config_table; |
118 | + reloc_pci_cfg_table(hose.config_table); | |
119 | +#ifdef DEBUG | |
120 | + printf("Init PCI: fixup_irq=%p config_table=%p hose=%p\n",pci_pip405_fixup_irq,pci_pip405_config_table,hose); | |
121 | +#endif | |
98 | 122 | pci_405gp_init(&hose); |
99 | 123 | } |
100 | 124 |
board/mpl/mip405/mip405.c
... | ... | @@ -128,6 +128,15 @@ |
128 | 128 | 2, /* Address Mode = 2 */ |
129 | 129 | 4, /* size value */ |
130 | 130 | 1}, /* ECC enabled */ |
131 | + { 0x03, /* Rev A, 128MByte -4 Board */ | |
132 | + 3, /* Case Latenty = 3 */ | |
133 | + 3, /* trp 20ns / 7.5 ns datain[27] */ | |
134 | + 3, /* trcd 20ns /7.5 ns (datain[29]) */ | |
135 | + 6, /* tras 44ns /7.5 ns (datain[30]) */ | |
136 | + 4, /* tcpt 44 - 20ns = 24ns */ | |
137 | + 3, /* Address Mode = 3 */ | |
138 | + 5, /* size value */ | |
139 | + 1}, /* ECC enabled */ | |
131 | 140 | { 0xff, /* terminator */ |
132 | 141 | 0xff, |
133 | 142 | 0xff, |
134 | 143 | |
... | ... | @@ -616,7 +625,13 @@ |
616 | 625 | |
617 | 626 | int last_stage_init (void) |
618 | 627 | { |
628 | + /* write correct LED configuration */ | |
619 | 629 | if (miiphy_write (0x1, 0x14, 0x2402) != 0) { |
630 | + printf ("Error writing to the PHY\n"); | |
631 | + } | |
632 | + /* since LED/CFG2 is not connected on the -2, | |
633 | + * write to correct capability information */ | |
634 | + if (miiphy_write (0x1, 0x4, 0x01E1) != 0) { | |
620 | 635 | printf ("Error writing to the PHY\n"); |
621 | 636 | } |
622 | 637 | print_mip405_rev (); |
board/svm_sc8xx/ppcboot.lds
1 | -/* | |
2 | - * (C) Copyright 2000 | |
3 | - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | - * | |
5 | - * See file CREDITS for list of people who contributed to this | |
6 | - * project. | |
7 | - * | |
8 | - * This program is free software; you can redistribute it and/or | |
9 | - * modify it under the terms of the GNU General Public License as | |
10 | - * published by the Free Software Foundation; either version 2 of | |
11 | - * the License, or (at your option) any later version. | |
12 | - * | |
13 | - * This program is distributed in the hope that it will be useful, | |
14 | - * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | - * GNU General Public License for more details. | |
17 | - * | |
18 | - * You should have received a copy of the GNU General Public License | |
19 | - * along with this program; if not, write to the Free Software | |
20 | - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | - * MA 02111-1307 USA | |
22 | - */ | |
23 | - | |
24 | -OUTPUT_ARCH(powerpc) | |
25 | -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); | |
26 | -/* Do we need any of these for elf? | |
27 | - __DYNAMIC = 0; */ | |
28 | -SECTIONS | |
29 | -{ | |
30 | - /* Read-only sections, merged into text segment: */ | |
31 | - . = + SIZEOF_HEADERS; | |
32 | - .interp : { *(.interp) } | |
33 | - .hash : { *(.hash) } | |
34 | - .dynsym : { *(.dynsym) } | |
35 | - .dynstr : { *(.dynstr) } | |
36 | - .rel.text : { *(.rel.text) } | |
37 | - .rela.text : { *(.rela.text) } | |
38 | - .rel.data : { *(.rel.data) } | |
39 | - .rela.data : { *(.rela.data) } | |
40 | - .rel.rodata : { *(.rel.rodata) } | |
41 | - .rela.rodata : { *(.rela.rodata) } | |
42 | - .rel.got : { *(.rel.got) } | |
43 | - .rela.got : { *(.rela.got) } | |
44 | - .rel.ctors : { *(.rel.ctors) } | |
45 | - .rela.ctors : { *(.rela.ctors) } | |
46 | - .rel.dtors : { *(.rel.dtors) } | |
47 | - .rela.dtors : { *(.rela.dtors) } | |
48 | - .rel.bss : { *(.rel.bss) } | |
49 | - .rela.bss : { *(.rela.bss) } | |
50 | - .rel.plt : { *(.rel.plt) } | |
51 | - .rela.plt : { *(.rela.plt) } | |
52 | - .init : { *(.init) } | |
53 | - .plt : { *(.plt) } | |
54 | - .text : | |
55 | - { | |
56 | - /* WARNING - the following is hand-optimized to fit within */ | |
57 | - /* the sector layout of our flash chips! XXX FIXME XXX */ | |
58 | - | |
59 | - cpu/mpc8xx/start.o (.text) | |
60 | - common/dlmalloc.o (.text) | |
61 | - ppc/ppcstring.o (.text) | |
62 | - ppc/vsprintf.o (.text) | |
63 | - ppc/crc32.o (.text) | |
64 | - ppc/zlib.o (.text) | |
65 | - | |
66 | - . = env_offset; | |
67 | - common/environment.o(.text) | |
68 | - | |
69 | - *(.text) | |
70 | - *(.fixup) | |
71 | - *(.got1) | |
72 | - } | |
73 | - _etext = .; | |
74 | - PROVIDE (etext = .); | |
75 | - .rodata : | |
76 | - { | |
77 | - *(.rodata) | |
78 | - *(.rodata1) | |
79 | - } | |
80 | - .fini : { *(.fini) } =0 | |
81 | - .ctors : { *(.ctors) } | |
82 | - .dtors : { *(.dtors) } | |
83 | - | |
84 | - /* Read-write section, merged into data segment: */ | |
85 | - . = (. + 0x00FF) & 0xFFFFFF00; | |
86 | - _erotext = .; | |
87 | - PROVIDE (erotext = .); | |
88 | - .reloc : | |
89 | - { | |
90 | - *(.got) | |
91 | - _GOT2_TABLE_ = .; | |
92 | - *(.got2) | |
93 | - _FIXUP_TABLE_ = .; | |
94 | - *(.fixup) | |
95 | - } | |
96 | - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; | |
97 | - __fixup_entries = (. - _FIXUP_TABLE_)>>2; | |
98 | - | |
99 | - .data : | |
100 | - { | |
101 | - *(.data) | |
102 | - *(.data1) | |
103 | - *(.sdata) | |
104 | - *(.sdata2) | |
105 | - *(.dynamic) | |
106 | - CONSTRUCTORS | |
107 | - } | |
108 | - _edata = .; | |
109 | - PROVIDE (edata = .); | |
110 | - | |
111 | - __start___ex_table = .; | |
112 | - __ex_table : { *(__ex_table) } | |
113 | - __stop___ex_table = .; | |
114 | - | |
115 | - . = ALIGN(256); | |
116 | - __init_begin = .; | |
117 | - .text.init : { *(.text.init) } | |
118 | - .data.init : { *(.data.init) } | |
119 | - . = ALIGN(256); | |
120 | - __init_end = .; | |
121 | - | |
122 | - __bss_start = .; | |
123 | - .bss : | |
124 | - { | |
125 | - *(.sbss) *(.scommon) | |
126 | - *(.dynbss) | |
127 | - *(.bss) | |
128 | - *(COMMON) | |
129 | - } | |
130 | - _end = . ; | |
131 | - PROVIDE (end = .); | |
132 | -} |
board/svm_sc8xx/ppcboot.lds.debug
1 | -/* | |
2 | - * (C) Copyright 2000 | |
3 | - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | - * | |
5 | - * See file CREDITS for list of people who contributed to this | |
6 | - * project. | |
7 | - * | |
8 | - * This program is free software; you can redistribute it and/or | |
9 | - * modify it under the terms of the GNU General Public License as | |
10 | - * published by the Free Software Foundation; either version 2 of | |
11 | - * the License, or (at your option) any later version. | |
12 | - * | |
13 | - * This program is distributed in the hope that it will be useful, | |
14 | - * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | - * GNU General Public License for more details. | |
17 | - * | |
18 | - * You should have received a copy of the GNU General Public License | |
19 | - * along with this program; if not, write to the Free Software | |
20 | - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | - * MA 02111-1307 USA | |
22 | - */ | |
23 | - | |
24 | -OUTPUT_ARCH(powerpc) | |
25 | -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); | |
26 | -/* Do we need any of these for elf? | |
27 | - __DYNAMIC = 0; */ | |
28 | -SECTIONS | |
29 | -{ | |
30 | - /* Read-only sections, merged into text segment: */ | |
31 | - . = + SIZEOF_HEADERS; | |
32 | - .interp : { *(.interp) } | |
33 | - .hash : { *(.hash) } | |
34 | - .dynsym : { *(.dynsym) } | |
35 | - .dynstr : { *(.dynstr) } | |
36 | - .rel.text : { *(.rel.text) } | |
37 | - .rela.text : { *(.rela.text) } | |
38 | - .rel.data : { *(.rel.data) } | |
39 | - .rela.data : { *(.rela.data) } | |
40 | - .rel.rodata : { *(.rel.rodata) } | |
41 | - .rela.rodata : { *(.rela.rodata) } | |
42 | - .rel.got : { *(.rel.got) } | |
43 | - .rela.got : { *(.rela.got) } | |
44 | - .rel.ctors : { *(.rel.ctors) } | |
45 | - .rela.ctors : { *(.rela.ctors) } | |
46 | - .rel.dtors : { *(.rel.dtors) } | |
47 | - .rela.dtors : { *(.rela.dtors) } | |
48 | - .rel.bss : { *(.rel.bss) } | |
49 | - .rela.bss : { *(.rela.bss) } | |
50 | - .rel.plt : { *(.rel.plt) } | |
51 | - .rela.plt : { *(.rela.plt) } | |
52 | - .init : { *(.init) } | |
53 | - .plt : { *(.plt) } | |
54 | - .text : | |
55 | - { | |
56 | - /* WARNING - the following is hand-optimized to fit within */ | |
57 | - /* the sector layout of our flash chips! XXX FIXME XXX */ | |
58 | - | |
59 | - cpu/mpc8xx/start.o (.text) | |
60 | - common/dlmalloc.o (.text) | |
61 | - ppc/vsprintf.o (.text) | |
62 | - ppc/crc32.o (.text) | |
63 | - | |
64 | - . = env_offset; | |
65 | - common/environment.o(.text) | |
66 | - | |
67 | - *(.text) | |
68 | - *(.fixup) | |
69 | - *(.got1) | |
70 | - } | |
71 | - _etext = .; | |
72 | - PROVIDE (etext = .); | |
73 | - .rodata : | |
74 | - { | |
75 | - *(.rodata) | |
76 | - *(.rodata1) | |
77 | - } | |
78 | - .fini : { *(.fini) } =0 | |
79 | - .ctors : { *(.ctors) } | |
80 | - .dtors : { *(.dtors) } | |
81 | - | |
82 | - /* Read-write section, merged into data segment: */ | |
83 | - . = (. + 0x0FFF) & 0xFFFFF000; | |
84 | - _erotext = .; | |
85 | - PROVIDE (erotext = .); | |
86 | - .reloc : | |
87 | - { | |
88 | - *(.got) | |
89 | - _GOT2_TABLE_ = .; | |
90 | - *(.got2) | |
91 | - _FIXUP_TABLE_ = .; | |
92 | - *(.fixup) | |
93 | - } | |
94 | - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; | |
95 | - __fixup_entries = (. - _FIXUP_TABLE_)>>2; | |
96 | - | |
97 | - .data : | |
98 | - { | |
99 | - *(.data) | |
100 | - *(.data1) | |
101 | - *(.sdata) | |
102 | - *(.sdata2) | |
103 | - *(.dynamic) | |
104 | - CONSTRUCTORS | |
105 | - } | |
106 | - _edata = .; | |
107 | - PROVIDE (edata = .); | |
108 | - | |
109 | - __start___ex_table = .; | |
110 | - __ex_table : { *(__ex_table) } | |
111 | - __stop___ex_table = .; | |
112 | - | |
113 | - . = ALIGN(4096); | |
114 | - __init_begin = .; | |
115 | - .text.init : { *(.text.init) } | |
116 | - .data.init : { *(.data.init) } | |
117 | - . = ALIGN(4096); | |
118 | - __init_end = .; | |
119 | - | |
120 | - __bss_start = .; | |
121 | - .bss : | |
122 | - { | |
123 | - *(.sbss) *(.scommon) | |
124 | - *(.dynbss) | |
125 | - *(.bss) | |
126 | - *(COMMON) | |
127 | - } | |
128 | - _end = . ; | |
129 | - PROVIDE (end = .); | |
130 | -} |
board/wepep250/Makefile
1 | +# | |
2 | +# (C) Copyright 2000, 2002 | |
3 | +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | +# | |
5 | +# See file CREDITS for list of people who contributed to this | |
6 | +# project. | |
7 | +# | |
8 | +# This program is free software; you can redistribute it and/or | |
9 | +# modify it under the terms of the GNU General Public License as | |
10 | +# published by the Free Software Foundation; either version 2 of | |
11 | +# the License, or (at your option) any later version. | |
12 | +# | |
13 | +# This program is distributed in the hope that it will be useful, | |
14 | +# but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | +# GNU General Public License for more details. | |
17 | +# | |
18 | +# You should have received a copy of the GNU General Public License | |
19 | +# along with this program; if not, write to the Free Software | |
20 | +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | +# MA 02111-1307 USA | |
22 | +# | |
23 | + | |
24 | +include $(TOPDIR)/config.mk | |
25 | + | |
26 | +LIB = lib$(BOARD).a | |
27 | + | |
28 | +OBJS := wepep250.o flash.o | |
29 | +SOBJS := memsetup.o | |
30 | + | |
31 | +$(LIB): $(OBJS) $(SOBJS) | |
32 | + $(AR) crv $@ $^ | |
33 | + | |
34 | +clean: | |
35 | + rm -f $(SOBJS) $(OBJS) | |
36 | + | |
37 | +distclean: clean | |
38 | + rm -f $(LIB) core *.bak .depend | |
39 | + | |
40 | +######################################################################### | |
41 | + | |
42 | +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) | |
43 | + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ | |
44 | + | |
45 | +-include .depend | |
46 | + | |
47 | +######################################################################### |
board/wepep250/config.mk
1 | +# | |
2 | +# This is config used for compilation of WEP EP250 sources | |
3 | +# | |
4 | +# You might change location of U-Boot in memory by setting right TEXT_BASE. | |
5 | +# This allows for example having one copy located at the end of ram and stored | |
6 | +# in flash device and later on while developing use other location to test | |
7 | +# the code in RAM device only. | |
8 | +# | |
9 | + | |
10 | +TEXT_BASE = 0xa1fe0000 | |
11 | +#TEXT_BASE = 0xa1001000 |
board/wepep250/flash.c
1 | +/* | |
2 | + * Copyright (C) 2003 ETC s.r.o. | |
3 | + * | |
4 | + * This code was inspired by Marius Groeger and Kyle Harris code | |
5 | + * available in other board ports for U-Boot | |
6 | + * | |
7 | + * See file CREDITS for list of people who contributed to this | |
8 | + * project. | |
9 | + * | |
10 | + * This program is free software; you can redistribute it and/or | |
11 | + * modify it under the terms of the GNU General Public License as | |
12 | + * published by the Free Software Foundation; either version 2 of | |
13 | + * the License, or (at your option) any later version. | |
14 | + * | |
15 | + * This program is distributed in the hope that it will be useful, | |
16 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | + * GNU General Public License for more details. | |
19 | + * | |
20 | + * You should have received a copy of the GNU General Public License | |
21 | + * along with this program; if not, write to the Free Software | |
22 | + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | + * MA 02111-1307 USA | |
24 | + * | |
25 | + * Written by Peter Figuli <peposh@etc.sk>, 2003. | |
26 | + * | |
27 | + */ | |
28 | + | |
29 | +#include <common.h> | |
30 | +#include "intel.h" | |
31 | + | |
32 | + | |
33 | +/* | |
34 | + * This code should handle CFI FLASH memory device. This code is very | |
35 | + * minimalistic approach without many essential error handling code as well. | |
36 | + * Because U-Boot actually is missing smart handling of FLASH device, | |
37 | + * we just set flash_id to anything else to FLASH_UNKNOW, so common code | |
38 | + * can call us without any restrictions. | |
39 | + * TODO: Add CFI Query, to be able to determine FLASH device. | |
40 | + * TODO: Add error handling code | |
41 | + * NOTE: This code was tested with BUS_WIDTH 4 and ITERLEAVE 2 only, but | |
42 | + * hopefully may work with other configurations. | |
43 | + */ | |
44 | + | |
45 | +#if ( WEP_FLASH_BUS_WIDTH == 1 ) | |
46 | +# define FLASH_BUS vu_char | |
47 | +# if ( WEP_FLASH_INTERLEAVE == 1 ) | |
48 | +# define FLASH_CMD( x ) x | |
49 | +# else | |
50 | +# error "With 8bit bus only one chip is allowed" | |
51 | +# endif | |
52 | + | |
53 | + | |
54 | +#elif ( WEP_FLASH_BUS_WIDTH == 2 ) | |
55 | +# define FLASH_BUS vu_short | |
56 | +# if ( WEP_FLASH_INTERLEAVE == 1 ) | |
57 | +# define FLASH_CMD( x ) x | |
58 | +# elif ( WEP_FLASH_INTERLEAVE == 2 ) | |
59 | +# define FLASH_CMD( x ) (( x << 8 )| x ) | |
60 | +# else | |
61 | +# error "With 16bit bus only 1 or 2 chip(s) are allowed" | |
62 | +# endif | |
63 | + | |
64 | + | |
65 | +#elif ( WEP_FLASH_BUS_WIDTH == 4 ) | |
66 | +# define FLASH_BUS vu_long | |
67 | +# if ( WEP_FLASH_INTERLEAVE == 1 ) | |
68 | +# define FLASH_CMD( x ) x | |
69 | +# elif ( WEP_FLASH_INTERLEAVE == 2 ) | |
70 | +# define FLASH_CMD( x ) (( x << 16 )| x ) | |
71 | +# elif ( WEP_FLASH_INTERLEAVE == 4 ) | |
72 | +# define FLASH_CMD( x ) (( x << 24 )|( x << 16 ) ( x << 8 )| x ) | |
73 | +# else | |
74 | +# error "With 32bit bus only 1,2 or 4 chip(s) are allowed" | |
75 | +# endif | |
76 | + | |
77 | +#else | |
78 | +# error "Flash bus width might be 1,2,4 for 8,16,32 bit configuration" | |
79 | +#endif | |
80 | + | |
81 | + | |
82 | +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; | |
83 | + | |
84 | +static FLASH_BUS flash_status_reg (void) | |
85 | +{ | |
86 | + | |
87 | + FLASH_BUS *addr = (FLASH_BUS *) 0; | |
88 | + | |
89 | + *addr = FLASH_CMD (CFI_INTEL_CMD_READ_STATUS_REGISTER); | |
90 | + | |
91 | + return *addr; | |
92 | +} | |
93 | + | |
94 | +static int flash_ready (ulong timeout) | |
95 | +{ | |
96 | + int ok = 1; | |
97 | + | |
98 | + reset_timer_masked (); | |
99 | + while ((flash_status_reg () & FLASH_CMD (CFI_INTEL_SR_READY)) != | |
100 | + FLASH_CMD (CFI_INTEL_SR_READY)) { | |
101 | + if (get_timer_masked () > timeout && timeout != 0) { | |
102 | + ok = 0; | |
103 | + break; | |
104 | + } | |
105 | + } | |
106 | + return ok; | |
107 | +} | |
108 | + | |
109 | +#if ( CFG_MAX_FLASH_BANKS != 1 ) | |
110 | +# error "WEP platform has only one flash bank!" | |
111 | +#endif | |
112 | + | |
113 | + | |
114 | +ulong flash_init (void) | |
115 | +{ | |
116 | + int i; | |
117 | + FLASH_BUS address = WEP_FLASH_BASE; | |
118 | + | |
119 | + flash_info[0].size = WEP_FLASH_BANK_SIZE; | |
120 | + flash_info[0].sector_count = CFG_MAX_FLASH_SECT; | |
121 | + flash_info[0].flash_id = INTEL_MANUFACT; | |
122 | + memset (flash_info[0].protect, 0, CFG_MAX_FLASH_SECT); | |
123 | + | |
124 | + for (i = 0; i < CFG_MAX_FLASH_SECT; i++) { | |
125 | + flash_info[0].start[i] = address; | |
126 | +#ifdef WEP_FLASH_UNLOCK | |
127 | + /* Some devices are hw locked after start. */ | |
128 | + *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_LOCK_SETUP); | |
129 | + *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_UNLOCK_BLOCK); | |
130 | + flash_ready (0); | |
131 | + *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY); | |
132 | +#endif | |
133 | + address += WEP_FLASH_SECT_SIZE; | |
134 | + } | |
135 | + | |
136 | + flash_protect (FLAG_PROTECT_SET, | |
137 | + CFG_FLASH_BASE, | |
138 | + CFG_FLASH_BASE + _armboot_end_data - _armboot_start, | |
139 | + &flash_info[0]); | |
140 | + | |
141 | + flash_protect (FLAG_PROTECT_SET, | |
142 | + CFG_ENV_ADDR, | |
143 | + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); | |
144 | + | |
145 | + return WEP_FLASH_BANK_SIZE; | |
146 | +} | |
147 | + | |
148 | +void flash_print_info (flash_info_t * info) | |
149 | +{ | |
150 | + int i; | |
151 | + | |
152 | + printf (" Intel vendor\n"); | |
153 | + printf (" Size: %ld MB in %d Sectors\n", | |
154 | + info->size >> 20, info->sector_count); | |
155 | + | |
156 | + printf (" Sector Start Addresses:"); | |
157 | + for (i = 0; i < info->sector_count; i++) { | |
158 | + if (!(i % 5)) { | |
159 | + printf ("\n"); | |
160 | + } | |
161 | + | |
162 | + printf (" %08lX%s", info->start[i], | |
163 | + info->protect[i] ? " (RO)" : " "); | |
164 | + } | |
165 | + printf ("\n"); | |
166 | +} | |
167 | + | |
168 | + | |
169 | +int flash_erase (flash_info_t * info, int s_first, int s_last) | |
170 | +{ | |
171 | + int flag, non_protected = 0, sector; | |
172 | + int rc = ERR_OK; | |
173 | + | |
174 | + FLASH_BUS *address; | |
175 | + | |
176 | + for (sector = s_first; sector <= s_last; sector++) { | |
177 | + if (!info->protect[sector]) { | |
178 | + non_protected++; | |
179 | + } | |
180 | + } | |
181 | + | |
182 | + if (!non_protected) { | |
183 | + return ERR_PROTECTED; | |
184 | + } | |
185 | + | |
186 | + /* | |
187 | + * Disable interrupts which might cause a timeout | |
188 | + * here. Remember that our exception vectors are | |
189 | + * at address 0 in the flash, and we don't want a | |
190 | + * (ticker) exception to happen while the flash | |
191 | + * chip is in programming mode. | |
192 | + */ | |
193 | + flag = disable_interrupts (); | |
194 | + | |
195 | + | |
196 | + /* Start erase on unprotected sectors */ | |
197 | + for (sector = s_first; sector <= s_last && !ctrlc (); sector++) { | |
198 | + if (info->protect[sector]) { | |
199 | + printf ("Protected sector %2d skipping...\n", sector); | |
200 | + continue; | |
201 | + } else { | |
202 | + printf ("Erasing sector %2d ... ", sector); | |
203 | + } | |
204 | + | |
205 | + address = (FLASH_BUS *) (info->start[sector]); | |
206 | + | |
207 | + *address = FLASH_CMD (CFI_INTEL_CMD_BLOCK_ERASE); | |
208 | + *address = FLASH_CMD (CFI_INTEL_CMD_CONFIRM); | |
209 | + if (flash_ready (CFG_FLASH_ERASE_TOUT)) { | |
210 | + *address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER); | |
211 | + printf ("ok.\n"); | |
212 | + } else { | |
213 | + *address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND); | |
214 | + rc = ERR_TIMOUT; | |
215 | + printf ("timeout! Aborting...\n"); | |
216 | + break; | |
217 | + } | |
218 | + *address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY); | |
219 | + } | |
220 | + if (ctrlc ()) | |
221 | + printf ("User Interrupt!\n"); | |
222 | + | |
223 | + /* allow flash to settle - wait 10 ms */ | |
224 | + udelay_masked (10000); | |
225 | + if (flag) { | |
226 | + enable_interrupts (); | |
227 | + } | |
228 | + | |
229 | + return rc; | |
230 | +} | |
231 | + | |
232 | +static int write_data (flash_info_t * info, ulong dest, FLASH_BUS data) | |
233 | +{ | |
234 | + FLASH_BUS *address = (FLASH_BUS *) dest; | |
235 | + int rc = ERR_OK; | |
236 | + int flag; | |
237 | + | |
238 | + /* Check if Flash is (sufficiently) erased */ | |
239 | + if ((*address & data) != data) { | |
240 | + return ERR_NOT_ERASED; | |
241 | + } | |
242 | + | |
243 | + /* | |
244 | + * Disable interrupts which might cause a timeout | |
245 | + * here. Remember that our exception vectors are | |
246 | + * at address 0 in the flash, and we don't want a | |
247 | + * (ticker) exception to happen while the flash | |
248 | + * chip is in programming mode. | |
249 | + */ | |
250 | + | |
251 | + flag = disable_interrupts (); | |
252 | + | |
253 | + *address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER); | |
254 | + *address = FLASH_CMD (CFI_INTEL_CMD_PROGRAM1); | |
255 | + *address = data; | |
256 | + | |
257 | + if (!flash_ready (CFG_FLASH_WRITE_TOUT)) { | |
258 | + *address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND); | |
259 | + rc = ERR_TIMOUT; | |
260 | + printf ("timeout! Aborting...\n"); | |
261 | + } | |
262 | + | |
263 | + *address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY); | |
264 | + if (flag) { | |
265 | + enable_interrupts (); | |
266 | + } | |
267 | + | |
268 | + return rc; | |
269 | +} | |
270 | + | |
271 | +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) | |
272 | +{ | |
273 | + ulong read_addr, write_addr; | |
274 | + FLASH_BUS data; | |
275 | + int i, result = ERR_OK; | |
276 | + | |
277 | + | |
278 | + read_addr = addr & ~(sizeof (FLASH_BUS) - 1); | |
279 | + write_addr = read_addr; | |
280 | + if (read_addr != addr) { | |
281 | + data = 0; | |
282 | + for (i = 0; i < sizeof (FLASH_BUS); i++) { | |
283 | + if (read_addr < addr || cnt == 0) { | |
284 | + data |= *((uchar *) read_addr) << i * 8; | |
285 | + } else { | |
286 | + data |= (*src++) << i * 8; | |
287 | + cnt--; | |
288 | + } | |
289 | + read_addr++; | |
290 | + } | |
291 | + if ((result = write_data (info, write_addr, data)) != ERR_OK) { | |
292 | + return result; | |
293 | + } | |
294 | + write_addr += sizeof (FLASH_BUS); | |
295 | + } | |
296 | + for (; cnt >= sizeof (FLASH_BUS); cnt -= sizeof (FLASH_BUS)) { | |
297 | + if ((result = write_data (info, write_addr, | |
298 | + *((FLASH_BUS *) src))) != ERR_OK) { | |
299 | + return result; | |
300 | + } | |
301 | + write_addr += sizeof (FLASH_BUS); | |
302 | + src += sizeof (FLASH_BUS); | |
303 | + } | |
304 | + if (cnt > 0) { | |
305 | + read_addr = write_addr; | |
306 | + data = 0; | |
307 | + for (i = 0; i < sizeof (FLASH_BUS); i++) { | |
308 | + if (cnt > 0) { | |
309 | + data |= (*src++) << i * 8; | |
310 | + cnt--; | |
311 | + } else { | |
312 | + data |= *((uchar *) read_addr) << i * 8; | |
313 | + } | |
314 | + read_addr++; | |
315 | + } | |
316 | + if ((result = write_data (info, write_addr, data)) != 0) { | |
317 | + return result; | |
318 | + } | |
319 | + } | |
320 | + return ERR_OK; | |
321 | +} |
board/wepep250/intel.h
1 | +/* | |
2 | + * Copyright (C) 2002 ETC s.r.o. | |
3 | + * All rights reserved. | |
4 | + * | |
5 | + * Redistribution and use in source and binary forms, with or without | |
6 | + * modification, are permitted provided that the following conditions | |
7 | + * are met: | |
8 | + * 1. Redistributions of source code must retain the above copyright | |
9 | + * notice, this list of conditions and the following disclaimer. | |
10 | + * 2. Redistributions in binary form must reproduce the above copyright | |
11 | + * notice, this list of conditions and the following disclaimer in the | |
12 | + * documentation and/or other materials provided with the distribution. | |
13 | + * 3. Neither the name of the ETC s.r.o. nor the names of its contributors | |
14 | + * may be used to endorse or promote products derived from this software | |
15 | + * without specific prior written permission. | |
16 | + * | |
17 | + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
18 | + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
19 | + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
20 | + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE | |
21 | + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
22 | + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
23 | + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER | |
24 | + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | |
25 | + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
26 | + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
27 | + * | |
28 | + * Written by Marcel Telka <marcel@telka.sk>, 2002. | |
29 | + * | |
30 | + * Documentation: | |
31 | + * [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A, | |
32 | + * 28F320J3A (x8/x16)", April 2002, Order Number: 290667-011 | |
33 | + * [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18, | |
34 | + * 28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005 | |
35 | + * | |
36 | + * This file is taken from OpenWinCE project hosted by SourceForge.net | |
37 | + * | |
38 | + */ | |
39 | + | |
40 | +#ifndef FLASH_INTEL_H | |
41 | +#define FLASH_INTEL_H | |
42 | + | |
43 | +#include <common.h> | |
44 | + | |
45 | +/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */ | |
46 | + | |
47 | +#define CFI_INTEL_CMD_READ_ARRAY 0xFF /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ | |
48 | +#define CFI_INTEL_CMD_READ_IDENTIFIER 0x90 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ | |
49 | +#define CFI_INTEL_CMD_READ_QUERY 0x98 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ | |
50 | +#define CFI_INTEL_CMD_READ_STATUS_REGISTER 0x70 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ | |
51 | +#define CFI_INTEL_CMD_CLEAR_STATUS_REGISTER 0x50 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ | |
52 | +#define CFI_INTEL_CMD_PROGRAM1 0x40 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ | |
53 | +#define CFI_INTEL_CMD_PROGRAM2 0x10 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ | |
54 | +#define CFI_INTEL_CMD_WRITE_TO_BUFFER 0xE8 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ | |
55 | +#define CFI_INTEL_CMD_CONFIRM 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ | |
56 | +#define CFI_INTEL_CMD_BLOCK_ERASE 0x20 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ | |
57 | +#define CFI_INTEL_CMD_SUSPEND 0xB0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ | |
58 | +#define CFI_INTEL_CMD_RESUME 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ | |
59 | +#define CFI_INTEL_CMD_LOCK_SETUP 0x60 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ | |
60 | +#define CFI_INTEL_CMD_LOCK_BLOCK 0x01 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ | |
61 | +#define CFI_INTEL_CMD_UNLOCK_BLOCK 0xD0 /* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */ | |
62 | +#define CFI_INTEL_CMD_LOCK_DOWN_BLOCK 0x2F /* 28FxxxK3, 28FxxxK18 */ | |
63 | + | |
64 | +/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */ | |
65 | + | |
66 | +#define CFI_INTEL_SR_READY 1 << 7 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ | |
67 | +#define CFI_INTEL_SR_ERASE_SUSPEND 1 << 6 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ | |
68 | +#define CFI_INTEL_SR_ERASE_ERROR 1 << 5 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ | |
69 | +#define CFI_INTEL_SR_PROGRAM_ERROR 1 << 4 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ | |
70 | +#define CFI_INTEL_SR_VPEN_ERROR 1 << 3 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ | |
71 | +#define CFI_INTEL_SR_PROGRAM_SUSPEND 1 << 2 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ | |
72 | +#define CFI_INTEL_SR_BLOCK_LOCKED 1 << 1 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ | |
73 | +#define CFI_INTEL_SR_BEFP 1 << 0 /* 28FxxxK3, 28FxxxK18 */ | |
74 | + | |
75 | +/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */ | |
76 | + | |
77 | +#define CFI_CHIP_INTEL_28F320J3A 0x0016 | |
78 | +#define CFI_CHIPN_INTEL_28F320J3A "28F320J3A" | |
79 | +#define CFI_CHIP_INTEL_28F640J3A 0x0017 | |
80 | +#define CFI_CHIPN_INTEL_28F640J3A "28F640J3A" | |
81 | +#define CFI_CHIP_INTEL_28F128J3A 0x0018 | |
82 | +#define CFI_CHIPN_INTEL_28F128J3A "28F128J3A" | |
83 | + | |
84 | +/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */ | |
85 | + | |
86 | +#define CFI_CHIP_INTEL_28F640K3 0x8801 | |
87 | +#define CFI_CHIPN_INTEL_28F640K3 "28F640K3" | |
88 | +#define CFI_CHIP_INTEL_28F128K3 0x8802 | |
89 | +#define CFI_CHIPN_INTEL_28F128K3 "28F128K3" | |
90 | +#define CFI_CHIP_INTEL_28F256K3 0x8803 | |
91 | +#define CFI_CHIPN_INTEL_28F256K3 "28F256K3" | |
92 | +#define CFI_CHIP_INTEL_28F640K18 0x8805 | |
93 | +#define CFI_CHIPN_INTEL_28F640K18 "28F640K18" | |
94 | +#define CFI_CHIP_INTEL_28F128K18 0x8806 | |
95 | +#define CFI_CHIPN_INTEL_28F128K18 "28F128K18" | |
96 | +#define CFI_CHIP_INTEL_28F256K18 0x8807 | |
97 | +#define CFI_CHIPN_INTEL_28F256K18 "28F256K18" | |
98 | + | |
99 | +#endif /* FLASH_INTEL_H */ |
board/wepep250/memsetup.S
1 | +/* | |
2 | + * Copyright (C) 2001, 2002 ETC s.r.o. | |
3 | + * | |
4 | + * This program is free software; you can redistribute it and/or | |
5 | + * modify it under the terms of the GNU General Public License | |
6 | + * as published by the Free Software Foundation; either version 2 | |
7 | + * of the License, or (at your option) any later version. | |
8 | + * | |
9 | + * This program is distributed in the hope that it will be useful, | |
10 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | + * GNU General Public License for more details. | |
13 | + * | |
14 | + * You should have received a copy of the GNU General Public License | |
15 | + * along with this program; if not, write to the Free Software | |
16 | + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA | |
17 | + * 02111-1307, USA. | |
18 | + * | |
19 | + * Written by Marcel Telka <marcel@telka.sk>, 2001, 2002. | |
20 | + * Changes for U-Boot Peter Figuli <peposh@etc.sk>, 2003. | |
21 | + * | |
22 | + * This file is taken from OpenWinCE project hosted by SourceForge.net | |
23 | + * | |
24 | + * Documentation: | |
25 | + * [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors | |
26 | + * Developer's Manual", February 2002, Order Number: 278522-001 | |
27 | + * [2] Samsung Electronics, "8Mx16 SDRAM 54CSP K4S281633D-RL/N/P", | |
28 | + * Revision 1.0, February 2002 | |
29 | + * [3] Samsung Electronics, "16Mx16 SDRAM 54CSP K4S561633C-RL(N)", | |
30 | + * Revision 1.0, February 2002 | |
31 | + * | |
32 | +*/ | |
33 | + | |
34 | +#include <config.h> | |
35 | +#include <version.h> | |
36 | +#include <asm/arch/pxa-regs.h> | |
37 | + | |
38 | +.globl memsetup | |
39 | +memsetup: | |
40 | + | |
41 | + mov r10, lr | |
42 | + | |
43 | +/* setup memory - see 6.12 in [1] | |
44 | + * Step 1 - wait 200 us | |
45 | + */ | |
46 | + mov r0,#0x2700 /* wait 200 us @ 99.5 MHz */ | |
47 | +1: subs r0, r0, #1 | |
48 | + bne 1b | |
49 | +/* TODO: complete step 1 for Synchronous Static memory*/ | |
50 | + | |
51 | + ldr r0, =0x48000000 /* MC_BASE */ | |
52 | + | |
53 | + | |
54 | + | |
55 | +/* step 1.a - setup MSCx | |
56 | + */ | |
57 | + ldr r1, =0x000012B3 /* MSC0_RRR0(1) | MSC0_RDN0(2) | MSC0_RDF0(11) | MSC0_RT0(3) */ | |
58 | + str r1, [r0, #0x8] /* MSC0_OFFSET */ | |
59 | + | |
60 | +/* step 1.c - clear MDREFR:K1FREE, set MDREFR:DRI | |
61 | + * see AUTO REFRESH chapter in section D. in [2] and in [3] | |
62 | + * DRI = (64ms / 4096) * 99.53MHz / 32 = 48 for K4S281633 | |
63 | + * DRI = (64ms / 8192) * 99.52MHz / 32 = 24 for K4S561633 | |
64 | + * TODO: complete for Synchronous Static memory | |
65 | + */ | |
66 | + ldr r1, [r0, #4] /* MDREFR_OFFSET */ | |
67 | + ldr r2, =0x01000FFF /* MDREFR_K1FREE | MDREFR_DRI_MASK */ | |
68 | + bic r1, r1, r2 | |
69 | +#if defined( WEP_SDRAM_K4S281633 ) | |
70 | + orr r1, r1, #48 /* MDREFR_DRI(48) */ | |
71 | +#elif defined( WEP_SDRAM_K4S561633 ) | |
72 | + orr r1, r1, #24 /* MDREFR_DRI(24) */ | |
73 | +#else | |
74 | +#error SDRAM chip is not defined | |
75 | +#endif | |
76 | + | |
77 | + str r1, [r0, #4] /* MDREFR_OFFSET */ | |
78 | + | |
79 | +/* Step 2 - only for Synchronous Static memory (TODO) | |
80 | + * | |
81 | + * Step 3 - same as step 4 | |
82 | + * | |
83 | + * Step 4 | |
84 | + * | |
85 | + * Step 4.a - set MDREFR:K1RUN, clear MDREFR:K1DB2 | |
86 | + */ | |
87 | + orr r1, r1, #0x00010000 /* MDREFR_K1RUN */ | |
88 | + bic r1, r1, #0x00020000 /* MDREFR_K1DB2 */ | |
89 | + str r1, [r0, #4] /* MDREFR_OFFSET */ | |
90 | + | |
91 | +/* Step 4.b - clear MDREFR:SLFRSH */ | |
92 | + bic r1, r1, #0x00400000 /* MDREFR_SLFRSH */ | |
93 | + str r1, [r0, #4] /* MDREFR_OFFSET */ | |
94 | + | |
95 | +/* Step 4.c - set MDREFR:E1PIN */ | |
96 | + orr r1, r1, #0x00008000 /* MDREFR_E1PIN */ | |
97 | + str r1, [r0, #4] /* MDREFR_OFFSET */ | |
98 | + | |
99 | +/* Step 4.d - automatically done | |
100 | + * | |
101 | + * Steps 4.e and 4.f - configure SDRAM | |
102 | + */ | |
103 | +#if defined( WEP_SDRAM_K4S281633 ) | |
104 | + ldr r1, =0x00000AA8 /* MDCNFG_DTC0(2) | MDCNFG_DLATCH0 | MDCNFG_DCAC0(1) | MDCNFG_DRAC0(1) | MDCNFG_DNB0 */ | |
105 | +#elif defined( WEP_SDRAM_K4S561633 ) | |
106 | + ldr r1, =0x00000AC8 /* MDCNFG_DTC0(2) | MDCNFG_DLATCH0 | MDCNFG_DCAC0(1) | MDCNFG_DRAC0(2) | MDCNFG_DNB0 */ | |
107 | +#else | |
108 | +#error SDRAM chip is not defined | |
109 | +#endif | |
110 | + str r1, [r0, #0] /* MDCNFG_OFFSET */ | |
111 | + | |
112 | +/* Step 5 - wait at least 200 us for SDRAM | |
113 | + * see section B. in [2] | |
114 | + */ | |
115 | + mov r2,#0x2700 /* wait 200 us @ 99.5 MHz */ | |
116 | +1: subs r2, r2, #1 | |
117 | + bne 1b | |
118 | + | |
119 | +/* Step 6 - after reset dcache is disabled, so automatically done | |
120 | + * | |
121 | + * Step 7 - eight refresh cycles | |
122 | + */ | |
123 | + mov r2, #0xA0000000 | |
124 | + ldr r3, [r2] | |
125 | + ldr r3, [r2] | |
126 | + ldr r3, [r2] | |
127 | + ldr r3, [r2] | |
128 | + ldr r3, [r2] | |
129 | + ldr r3, [r2] | |
130 | + ldr r3, [r2] | |
131 | + ldr r3, [r2] | |
132 | + | |
133 | +/* Step 8 - we don't need dcache now | |
134 | + * | |
135 | + * Step 9 - enable SDRAM partition 0 | |
136 | + */ | |
137 | + orr r1, r1, #1 /* MDCNFG_DE0 */ | |
138 | + str r1, [r0, #0] /* MDCNFG_OFFSET */ | |
139 | + | |
140 | +/* Step 10 - write MDMRS */ | |
141 | + mov r1, #0 | |
142 | + str r1, [r0, #0x40] /* MDMRS_OFFSET */ | |
143 | + | |
144 | +/* Step 11 - optional (TODO) */ | |
145 | + | |
146 | + mov pc,r10 |
board/wepep250/u-boot.lds
1 | +/* | |
2 | + * (C) Copyright 2000 | |
3 | + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | + * | |
5 | + * See file CREDITS for list of people who contributed to this | |
6 | + * project. | |
7 | + * | |
8 | + * This program is free software; you can redistribute it and/or | |
9 | + * modify it under the terms of the GNU General Public License as | |
10 | + * published by the Free Software Foundation; either version 2 of | |
11 | + * the License, or (at your option) any later version. | |
12 | + * | |
13 | + * This program is distributed in the hope that it will be useful, | |
14 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | + * GNU General Public License for more details. | |
17 | + * | |
18 | + * You should have received a copy of the GNU General Public License | |
19 | + * along with this program; if not, write to the Free Software | |
20 | + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | + * MA 02111-1307 USA | |
22 | + */ | |
23 | + | |
24 | +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") | |
25 | +OUTPUT_ARCH(arm) | |
26 | +ENTRY(_start) | |
27 | +SECTIONS | |
28 | +{ | |
29 | + . = 0x00000000; | |
30 | + | |
31 | + . = ALIGN(4); | |
32 | + .text : | |
33 | + { | |
34 | + cpu/xscale/start.o (.text) | |
35 | + *(.text) | |
36 | + } | |
37 | + | |
38 | + . = ALIGN(4); | |
39 | + .rodata : { *(.rodata) } | |
40 | + | |
41 | + . = ALIGN(4); | |
42 | + .data : { *(.data) } | |
43 | + | |
44 | + . = ALIGN(4); | |
45 | + .got : { *(.got) } | |
46 | + | |
47 | + armboot_end_data = .; | |
48 | + | |
49 | + . = ALIGN(4); | |
50 | + bss_start = .; | |
51 | + .bss : { *(.bss) } | |
52 | + bss_end = .; | |
53 | + | |
54 | + armboot_end = .; | |
55 | +} |
board/wepep250/wepep250.c
1 | +/* | |
2 | + * Copyright (C) 2003 ETC s.r.o. | |
3 | + * | |
4 | + * This program is free software; you can redistribute it and/or | |
5 | + * modify it under the terms of the GNU General Public License as | |
6 | + * published by the Free Software Foundation; either version 2 of | |
7 | + * the License, or (at your option) any later version. | |
8 | + * | |
9 | + * This program is distributed in the hope that it will be useful, | |
10 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | + * GNU General Public License for more details. | |
13 | + * | |
14 | + * You should have received a copy of the GNU General Public License | |
15 | + * along with this program; if not, write to the Free Software | |
16 | + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
17 | + * MA 02111-1307 USA | |
18 | + * | |
19 | + * Written by Peter Figuli <peposh@etc.sk>, 2003. | |
20 | + * | |
21 | + */ | |
22 | + | |
23 | +#include <common.h> | |
24 | +#include <asm/arch/pxa-regs.h> | |
25 | + | |
26 | +int board_init( void ){ | |
27 | + DECLARE_GLOBAL_DATA_PTR; | |
28 | + | |
29 | + gd->bd->bi_arch_number = 288; | |
30 | + gd->bd->bi_boot_params = 0xa0000000; | |
31 | +/* | |
32 | + * Setup GPIO stuff to get serial working | |
33 | + */ | |
34 | +#if defined( CONFIG_FFUART ) | |
35 | + GPDR1 = 0x80; | |
36 | + GAFR1_L = 0x8010; | |
37 | +#elif defined( CONFIG_BTUART ) | |
38 | + GPDR1 = 0x800; | |
39 | + GAFR1_L = 0x900000; | |
40 | +#endif | |
41 | + PSSR = 0x20; | |
42 | + | |
43 | +/* | |
44 | + * Following code is just bug workaround, remove it if not neccessary | |
45 | + */ | |
46 | + | |
47 | + /* cpu/xscale/cpu.c do not set armboot_real_end that is used for | |
48 | + malloc pool.*/ | |
49 | + if( _armboot_real_end == 0xbadc0de ){ | |
50 | + _armboot_real_end = _armboot_end; | |
51 | + } | |
52 | + return 0; | |
53 | +} | |
54 | + | |
55 | +int dram_init( void ){ | |
56 | + DECLARE_GLOBAL_DATA_PTR; | |
57 | + | |
58 | +#if ( CONFIG_NR_DRAM_BANKS > 0 ) | |
59 | + gd->bd->bi_dram[0].start = WEP_SDRAM_1; | |
60 | + gd->bd->bi_dram[0].size = WEP_SDRAM_1_SIZE; | |
61 | +#endif | |
62 | +#if ( CONFIG_NR_DRAM_BANKS > 1 ) | |
63 | + gd->bd->bi_dram[1].start = WEP_SDRAM_2; | |
64 | + gd->bd->bi_dram[1].size = WEP_SDRAM_2_SIZE; | |
65 | +#endif | |
66 | +#if ( CONFIG_NR_DRAM_BANKS > 2 ) | |
67 | + gd->bd->bi_dram[2].start = WEP_SDRAM_3; | |
68 | + gd->bd->bi_dram[2].size = WEP_SDRAM_3_SIZE; | |
69 | +#endif | |
70 | +#if ( CONFIG_NR_DRAM_BANKS > 3 ) | |
71 | + gd->bd->bi_dram[3].start = WEP_SDRAM_4; | |
72 | + gd->bd->bi_dram[3].size = WEP_SDRAM_4_SIZE; | |
73 | +#endif | |
74 | + | |
75 | + return 0; | |
76 | +} |
common/cmd_date.c
... | ... | @@ -34,10 +34,13 @@ |
34 | 34 | "Sun", "Mon", "Tues", "Wednes", "Thurs", "Fri", "Satur", |
35 | 35 | }; |
36 | 36 | |
37 | +#define RELOC(a) ((typeof(a))((unsigned long)(a) + gd->reloc_off)) | |
38 | + | |
37 | 39 | int mk_date (char *, struct rtc_time *); |
38 | 40 | |
39 | 41 | int do_date (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
40 | 42 | { |
43 | + DECLARE_GLOBAL_DATA_PTR; | |
41 | 44 | struct rtc_time tm; |
42 | 45 | int rcode = 0; |
43 | 46 | |
... | ... | @@ -64,7 +67,7 @@ |
64 | 67 | printf ("Date: %4d-%02d-%02d (%sday) Time: %2d:%02d:%02d\n", |
65 | 68 | tm.tm_year, tm.tm_mon, tm.tm_mday, |
66 | 69 | (tm.tm_wday<0 || tm.tm_wday>6) ? |
67 | - "unknown " : weekdays[tm.tm_wday], | |
70 | + "unknown " : RELOC(weekdays[tm.tm_wday]), | |
68 | 71 | tm.tm_hour, tm.tm_min, tm.tm_sec); |
69 | 72 | |
70 | 73 | return 0; |
common/hush.c
... | ... | @@ -2357,34 +2357,35 @@ |
2357 | 2357 | * should handle if, then, elif, else, fi, for, while, until, do, done. |
2358 | 2358 | * case, function, and select are obnoxious, save those for later. |
2359 | 2359 | */ |
2360 | +struct reserved_combo { | |
2361 | + char *literal; | |
2362 | + int code; | |
2363 | + long flag; | |
2364 | +}; | |
2365 | +/* Mostly a list of accepted follow-up reserved words. | |
2366 | + * FLAG_END means we are done with the sequence, and are ready | |
2367 | + * to turn the compound list into a command. | |
2368 | + * FLAG_START means the word must start a new compound list. | |
2369 | + */ | |
2370 | +static struct reserved_combo reserved_list[] = { | |
2371 | + { "if", RES_IF, FLAG_THEN | FLAG_START }, | |
2372 | + { "then", RES_THEN, FLAG_ELIF | FLAG_ELSE | FLAG_FI }, | |
2373 | + { "elif", RES_ELIF, FLAG_THEN }, | |
2374 | + { "else", RES_ELSE, FLAG_FI }, | |
2375 | + { "fi", RES_FI, FLAG_END }, | |
2376 | + { "for", RES_FOR, FLAG_IN | FLAG_START }, | |
2377 | + { "while", RES_WHILE, FLAG_DO | FLAG_START }, | |
2378 | + { "until", RES_UNTIL, FLAG_DO | FLAG_START }, | |
2379 | + { "in", RES_IN, FLAG_DO }, | |
2380 | + { "do", RES_DO, FLAG_DONE }, | |
2381 | + { "done", RES_DONE, FLAG_END } | |
2382 | +}; | |
2383 | +#define NRES (sizeof(reserved_list)/sizeof(struct reserved_combo)) | |
2384 | + | |
2360 | 2385 | int reserved_word(o_string *dest, struct p_context *ctx) |
2361 | 2386 | { |
2362 | - struct reserved_combo { | |
2363 | - char *literal; | |
2364 | - int code; | |
2365 | - long flag; | |
2366 | - }; | |
2367 | - /* Mostly a list of accepted follow-up reserved words. | |
2368 | - * FLAG_END means we are done with the sequence, and are ready | |
2369 | - * to turn the compound list into a command. | |
2370 | - * FLAG_START means the word must start a new compound list. | |
2371 | - */ | |
2372 | - static struct reserved_combo reserved_list[] = { | |
2373 | - { "if", RES_IF, FLAG_THEN | FLAG_START }, | |
2374 | - { "then", RES_THEN, FLAG_ELIF | FLAG_ELSE | FLAG_FI }, | |
2375 | - { "elif", RES_ELIF, FLAG_THEN }, | |
2376 | - { "else", RES_ELSE, FLAG_FI }, | |
2377 | - { "fi", RES_FI, FLAG_END }, | |
2378 | - { "for", RES_FOR, FLAG_IN | FLAG_START }, | |
2379 | - { "while", RES_WHILE, FLAG_DO | FLAG_START }, | |
2380 | - { "until", RES_UNTIL, FLAG_DO | FLAG_START }, | |
2381 | - { "in", RES_IN, FLAG_DO }, | |
2382 | - { "do", RES_DO, FLAG_DONE }, | |
2383 | - { "done", RES_DONE, FLAG_END } | |
2384 | - }; | |
2385 | 2387 | struct reserved_combo *r; |
2386 | 2388 | for (r=reserved_list; |
2387 | -#define NRES sizeof(reserved_list)/sizeof(struct reserved_combo) | |
2388 | 2389 | r<reserved_list+NRES; r++) { |
2389 | 2390 | if (strcmp(dest->data, r->literal) == 0) { |
2390 | 2391 | debug_printf("found reserved word %s, code %d\n",r->literal,r->code); |
... | ... | @@ -3169,6 +3170,18 @@ |
3169 | 3170 | } |
3170 | 3171 | |
3171 | 3172 | #ifdef __U_BOOT__ |
3173 | +static void u_boot_hush_reloc(void) | |
3174 | +{ | |
3175 | + DECLARE_GLOBAL_DATA_PTR; | |
3176 | + unsigned long addr; | |
3177 | + struct reserved_combo *r; | |
3178 | + | |
3179 | + for (r=reserved_list; r<reserved_list+NRES; r++) { | |
3180 | + addr = (ulong) (r->literal) + gd->reloc_off; | |
3181 | + r->literal = (char *)addr; | |
3182 | + } | |
3183 | +} | |
3184 | + | |
3172 | 3185 | int u_boot_hush_start(void) |
3173 | 3186 | { |
3174 | 3187 | top_vars = malloc(sizeof(struct variables)); |
... | ... | @@ -3177,6 +3190,7 @@ |
3177 | 3190 | top_vars->next = 0; |
3178 | 3191 | top_vars->flg_export = 0; |
3179 | 3192 | top_vars->flg_read_only = 1; |
3193 | + u_boot_hush_reloc(); | |
3180 | 3194 | return 0; |
3181 | 3195 | } |
3182 | 3196 |
common/main.c
... | ... | @@ -862,7 +862,6 @@ |
862 | 862 | int do_run (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) |
863 | 863 | { |
864 | 864 | int i; |
865 | - int rcode = 1; | |
866 | 865 | |
867 | 866 | if (argc < 2) { |
868 | 867 | printf ("Usage:\n%s\n", cmdtp->usage); |
869 | 868 | |
870 | 869 | |
871 | 870 | |
872 | 871 | |
... | ... | @@ -870,14 +869,22 @@ |
870 | 869 | } |
871 | 870 | |
872 | 871 | for (i=1; i<argc; ++i) { |
872 | + char *arg; | |
873 | + | |
874 | + if ((arg = getenv (argv[i])) == NULL) { | |
875 | + printf ("## Error: \"%s\" not defined\n", argv[i]); | |
876 | + return 1; | |
877 | + } | |
873 | 878 | #ifndef CFG_HUSH_PARSER |
874 | - if (run_command (getenv (argv[i]), flag) != -1) ++rcode; | |
879 | + if (run_command (arg, flag) == -1) | |
880 | + return 1; | |
875 | 881 | #else |
876 | - if (parse_string_outer(getenv (argv[i]), | |
877 | - FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP) == 0) ++rcode; | |
882 | + if (parse_string_outer(arg, | |
883 | + FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP) == 0) | |
884 | + return 1; | |
878 | 885 | #endif |
879 | 886 | } |
880 | - return ((rcode == i) ? 0 : 1); | |
887 | + return 0; | |
881 | 888 | } |
882 | -#endif | |
889 | +#endif /* CFG_CMD_RUN */ |
cpu/mips/cache.S
... | ... | @@ -253,9 +253,9 @@ |
253 | 253 | .globl mips_cache_lock |
254 | 254 | .ent mips_cache_lock |
255 | 255 | mips_cache_lock: |
256 | - li a1, K0BASE - CFG_DCACHE_SIZE | |
256 | + li a1, K0BASE - CFG_DCACHE_SIZE/2 | |
257 | 257 | addu a0, a1 |
258 | - li a2, CFG_DCACHE_SIZE | |
258 | + li a2, CFG_DCACHE_SIZE/2 | |
259 | 259 | li a3, CFG_CACHELINE_SIZE |
260 | 260 | move a1, a2 |
261 | 261 | icacheop(a0,a1,a2,a3,0x1d) |
cpu/mips/cpu.c
... | ... | @@ -27,8 +27,12 @@ |
27 | 27 | |
28 | 28 | int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
29 | 29 | { |
30 | -#ifdef CONFIG_INCA_IP | |
30 | +#if defined(CONFIG_INCA_IP) | |
31 | 31 | *INCA_IP_WDT_RST_REQ = 0x3f; |
32 | +#elif defined(CONFIG_PURPLE) | |
33 | + void (*f)(void) = (void *) 0xbfc00000; | |
34 | + | |
35 | + f(); | |
32 | 36 | #endif |
33 | 37 | fprintf(stderr, "*** reset failed ***\n"); |
34 | 38 | return 0; |
cpu/mips/serial.c
... | ... | @@ -2,10 +2,49 @@ |
2 | 2 | * (INCA) ASC UART support |
3 | 3 | */ |
4 | 4 | |
5 | +#include <config.h> | |
6 | + | |
7 | +#ifdef CONFIG_PURPLE | |
8 | +#define serial_init asc_serial_init | |
9 | +#define serial_putc asc_serial_putc | |
10 | +#define serial_puts asc_serial_puts | |
11 | +#define serial_getc asc_serial_getc | |
12 | +#define serial_tstc asc_serial_tstc | |
13 | +#define serial_setbrg asc_serial_setbrg | |
14 | +#endif | |
15 | + | |
5 | 16 | #include <common.h> |
6 | 17 | #include <asm/inca-ip.h> |
7 | 18 | #include "serial.h" |
8 | 19 | |
20 | +#ifdef CONFIG_PURPLE | |
21 | + | |
22 | +#undef ASC_FIFO_PRESENT | |
23 | +#define TOUT_LOOP 100000 | |
24 | + | |
25 | +/* Set base address for second FPI interrupt control register bank */ | |
26 | +#define SFPI_INTCON_BASEADDR 0xBF0F0000 | |
27 | + | |
28 | +/* Register offset from base address */ | |
29 | +#define FBS_ISR 0x00000000 /* Interrupt status register */ | |
30 | +#define FBS_IMR 0x00000008 /* Interrupt mask register */ | |
31 | +#define FBS_IDIS 0x00000010 /* Interrupt disable register */ | |
32 | + | |
33 | +/* Interrupt status register bits */ | |
34 | +#define FBS_ISR_AT 0x00000040 /* ASC transmit interrupt */ | |
35 | +#define FBS_ISR_AR 0x00000020 /* ASC receive interrupt */ | |
36 | +#define FBS_ISR_AE 0x00000010 /* ASC error interrupt */ | |
37 | +#define FBS_ISR_AB 0x00000008 /* ASC transmit buffer interrupt */ | |
38 | +#define FBS_ISR_AS 0x00000004 /* ASC start of autobaud detection interrupt */ | |
39 | +#define FBS_ISR_AF 0x00000002 /* ASC end of autobaud detection interrupt */ | |
40 | + | |
41 | +#else | |
42 | + | |
43 | +#define ASC_FIFO_PRESENT | |
44 | + | |
45 | +#endif | |
46 | + | |
47 | + | |
9 | 48 | #define SET_BIT(reg, mask) reg |= (mask) |
10 | 49 | #define CLEAR_BIT(reg, mask) reg &= (~mask) |
11 | 50 | #define CLEAR_BITS(reg, mask) CLEAR_BIT(reg, mask) |
12 | 51 | |
... | ... | @@ -32,8 +71,10 @@ |
32 | 71 | |
33 | 72 | int serial_init (void) |
34 | 73 | { |
74 | +#ifdef CONFIG_INCA_IP | |
35 | 75 | /* we have to set PMU.EN13 bit to enable an ASC device*/ |
36 | 76 | INCAASC_PMU_ENABLE(13); |
77 | +#endif | |
37 | 78 | |
38 | 79 | /* and we have to set CLC register*/ |
39 | 80 | CLEAR_BIT(pAsc->asc_clc, ASCCLC_DISS); |
... | ... | @@ -45,6 +86,7 @@ |
45 | 86 | /* select input port */ |
46 | 87 | pAsc->asc_pisel = (CONSOLE_TTY & 0x1); |
47 | 88 | |
89 | +#ifdef ASC_FIFO_PRESENT | |
48 | 90 | /* TXFIFO's filling level */ |
49 | 91 | SET_BITFIELD(pAsc->asc_txfcon, ASCTXFCON_TXFITLMASK, |
50 | 92 | ASCTXFCON_TXFITLOFF, INCAASC_TXFIFO_FL); |
51 | 93 | |
52 | 94 | |
53 | 95 | |
54 | 96 | |
... | ... | @@ -56,20 +98,25 @@ |
56 | 98 | ASCRXFCON_RXFITLOFF, INCAASC_RXFIFO_FL); |
57 | 99 | /* enable RXFIFO */ |
58 | 100 | SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXFEN); |
101 | +#endif | |
59 | 102 | |
60 | 103 | /* enable error signals */ |
61 | 104 | SET_BIT(pAsc->asc_con, ASCCON_FEN); |
62 | 105 | SET_BIT(pAsc->asc_con, ASCCON_OEN); |
63 | 106 | |
107 | +#ifdef CONFIG_INCA_IP | |
64 | 108 | /* acknowledge ASC interrupts */ |
65 | 109 | ASC_INTERRUPTS_CLEAR(INCAASC_IRQ_LINE_ALL); |
66 | 110 | |
67 | 111 | /* disable ASC interrupts */ |
68 | 112 | ASC_INTERRUPTS_DISABLE(INCAASC_IRQ_LINE_ALL); |
113 | +#endif | |
69 | 114 | |
115 | +#ifdef ASC_FIFO_PRESENT | |
70 | 116 | /* set FIFOs into the transparent mode */ |
71 | 117 | SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXTMEN); |
72 | 118 | SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXTMEN); |
119 | +#endif | |
73 | 120 | |
74 | 121 | /* set baud rate */ |
75 | 122 | serial_setbrg(); |
76 | 123 | |
... | ... | @@ -85,7 +132,11 @@ |
85 | 132 | ulong uiReloadValue, fdv; |
86 | 133 | ulong f_ASC; |
87 | 134 | |
135 | +#ifdef CONFIG_INCA_IP | |
88 | 136 | f_ASC = incaip_get_fpiclk(); |
137 | +#else | |
138 | + f_ASC = ASC_CLOCK_RATE; | |
139 | +#endif | |
89 | 140 | |
90 | 141 | #ifndef INCAASC_USE_FDV |
91 | 142 | fdv = 2; |
92 | 143 | |
93 | 144 | |
... | ... | @@ -210,10 +261,15 @@ |
210 | 261 | |
211 | 262 | void serial_putc (const char c) |
212 | 263 | { |
264 | +#ifdef ASC_FIFO_PRESENT | |
213 | 265 | uint txFl = 0; |
266 | +#else | |
267 | + uint timeout = 0; | |
268 | +#endif | |
214 | 269 | |
215 | 270 | if (c == '\n') serial_putc ('\r'); |
216 | 271 | |
272 | +#ifdef ASC_FIFO_PRESENT | |
217 | 273 | /* check do we have a free space in the TX FIFO */ |
218 | 274 | /* get current filling level */ |
219 | 275 | do |
220 | 276 | |
221 | 277 | |
... | ... | @@ -221,8 +277,25 @@ |
221 | 277 | txFl = ( pAsc->asc_fstat & ASCFSTAT_TXFFLMASK ) >> ASCFSTAT_TXFFLOFF; |
222 | 278 | } |
223 | 279 | while ( txFl == INCAASC_TXFIFO_FULL ); |
280 | +#else | |
224 | 281 | |
282 | + while(!(*(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) & | |
283 | + FBS_ISR_AB)) | |
284 | + { | |
285 | + if (timeout++ > TOUT_LOOP) | |
286 | + { | |
287 | + break; | |
288 | + } | |
289 | + } | |
290 | +#endif | |
291 | + | |
225 | 292 | pAsc->asc_tbuf = c; /* write char to Transmit Buffer Register */ |
293 | + | |
294 | +#ifndef ASC_FIFO_PRESENT | |
295 | + *(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) = FBS_ISR_AB | | |
296 | + FBS_ISR_AT; | |
297 | +#endif | |
298 | + | |
226 | 299 | /* check for errors */ |
227 | 300 | if ( pAsc->asc_con & ASCCON_OE ) |
228 | 301 | { |
... | ... | @@ -251,6 +324,10 @@ |
251 | 324 | |
252 | 325 | c = (char)(pAsc->asc_rbuf & symbol_mask); |
253 | 326 | |
327 | +#ifndef ASC_FIFO_PRESENT | |
328 | + *(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) = FBS_ISR_AR; | |
329 | +#endif | |
330 | + | |
254 | 331 | return c; |
255 | 332 | } |
256 | 333 | |
257 | 334 | |
... | ... | @@ -258,10 +335,19 @@ |
258 | 335 | { |
259 | 336 | int res = 1; |
260 | 337 | |
338 | +#ifdef ASC_FIFO_PRESENT | |
261 | 339 | if ( (pAsc->asc_fstat & ASCFSTAT_RXFFLMASK) == 0 ) |
262 | 340 | { |
263 | 341 | res = 0; |
264 | 342 | } |
343 | +#else | |
344 | + if (!(*(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) & | |
345 | + FBS_ISR_AR)) | |
346 | + | |
347 | + { | |
348 | + res = 0; | |
349 | + } | |
350 | +#endif | |
265 | 351 | else if ( pAsc->asc_con & ASCCON_FE ) |
266 | 352 | { |
267 | 353 | SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRFE); |
cpu/mips/start.S
... | ... | @@ -42,9 +42,12 @@ |
42 | 42 | _start: |
43 | 43 | RVECENT(reset,0) /* U-boot entry point */ |
44 | 44 | RVECENT(reset,1) /* software reboot */ |
45 | -#ifdef CONFIG_INCA_IP | |
46 | - .word 0x000020C4 /* EBU init code, fetched during booting */ | |
47 | - .word 0x00000000 /* phase of the flash */ | |
45 | +#if defined(CONFIG_INCA_IP) | |
46 | + .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */ | |
47 | + .word 0x00000000 /* phase of the flash */ | |
48 | +#elif defined(CONFIG_PURPLE) | |
49 | + .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */ | |
50 | + .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */ | |
48 | 51 | #else |
49 | 52 | RVECENT(romReserved,2) |
50 | 53 | #endif |
... | ... | @@ -178,6 +181,30 @@ |
178 | 181 | * 128 * 8 == 1024 == 0x400 |
179 | 182 | * so this is address R_VEC+0x400 == 0xbfc00400 |
180 | 183 | */ |
184 | +#ifdef CONFIG_PURPLE | |
185 | +/* 0xbfc00400 */ | |
186 | + .word 0xdc870000 | |
187 | + .word 0xfca70000 | |
188 | + .word 0x20840008 | |
189 | + .word 0x20a50008 | |
190 | + .word 0x20c6ffff | |
191 | + .word 0x14c0fffa | |
192 | + .word 0x00000000 | |
193 | + .word 0x03e00008 | |
194 | + .word 0x00000000 | |
195 | + .word 0x00000000 | |
196 | +/* 0xbfc00428 */ | |
197 | + .word 0xdc870000 | |
198 | + .word 0xfca70000 | |
199 | + .word 0x20840008 | |
200 | + .word 0x20a50008 | |
201 | + .word 0x20c6ffff | |
202 | + .word 0x14c0fffa | |
203 | + .word 0x00000000 | |
204 | + .word 0x03e00008 | |
205 | + .word 0x00000000 | |
206 | + .word 0x00000000 | |
207 | +#endif /* CONFIG_PURPLE */ | |
181 | 208 | .align 4 |
182 | 209 | reset: |
183 | 210 | |
184 | 211 | |
... | ... | @@ -283,12 +310,17 @@ |
283 | 310 | * t1 = target address |
284 | 311 | * t2 = source end address |
285 | 312 | */ |
313 | + /* On the purple board we copy the code earlier in a special way | |
314 | + * in order to solve flash problems | |
315 | + */ | |
316 | +#ifndef CONFIG_PURPLE | |
286 | 317 | 1: |
287 | 318 | lw t3, 0(t0) |
288 | 319 | sw t3, 0(t1) |
289 | 320 | addu t0, 4 |
290 | 321 | ble t0, t2, 1b |
291 | 322 | addu t1, 4 /* delay slot */ |
323 | +#endif | |
292 | 324 | |
293 | 325 | /* If caches were enabled, we would have to flush them here. |
294 | 326 | */ |
cpu/xscale/serial.c
... | ... | @@ -67,7 +67,21 @@ |
67 | 67 | |
68 | 68 | FFIER = IER_UUE; /* Enable FFUART */ |
69 | 69 | |
70 | -#elif CONFIG_STUART | |
70 | +#elif defined(CONFIG_BTUART) | |
71 | + CKEN |= CKEN7_BTUART; | |
72 | + | |
73 | + BTIER = 0; | |
74 | + BTFCR = 0; | |
75 | + | |
76 | + /* set baud rate */ | |
77 | + BTLCR = LCR_DLAB; | |
78 | + BTDLL = quot & 0xff; | |
79 | + BTDLH = quot >> 8; | |
80 | + BTLCR = LCR_WLS0 | LCR_WLS1; | |
81 | + | |
82 | + BTIER = IER_UUE; /* Enable BFUART */ | |
83 | + | |
84 | +#elif defined(CONFIG_STUART) | |
71 | 85 | #error "Bad: not implemented yet!" |
72 | 86 | #else |
73 | 87 | #error "Bad: you didn't configured serial ..." |
... | ... | @@ -98,7 +112,10 @@ |
98 | 112 | while ((FFLSR & LSR_TEMT) == 0); |
99 | 113 | |
100 | 114 | FFTHR = c; |
101 | -#elif CONFIG_STUART | |
115 | +#elif defined(CONFIG_BTUART) | |
116 | + while ((BTLSR & LSR_TEMT ) == 0 ); | |
117 | + BTTHR = c; | |
118 | +#elif defined(CONFIG_STUART) | |
102 | 119 | #endif |
103 | 120 | |
104 | 121 | /* If \n, also do \r */ |
... | ... | @@ -115,7 +132,9 @@ |
115 | 132 | { |
116 | 133 | #ifdef CONFIG_FFUART |
117 | 134 | return FFLSR & LSR_DR; |
118 | -#elif CONFIG_STUART | |
135 | +#elif defined(CONFIG_BTUART) | |
136 | + return BTLSR & LSR_DR; | |
137 | +#elif defined(CONFIG_STUART) | |
119 | 138 | #endif |
120 | 139 | } |
121 | 140 | |
... | ... | @@ -130,7 +149,11 @@ |
130 | 149 | while (!(FFLSR & LSR_DR)); |
131 | 150 | |
132 | 151 | return (char) FFRBR & 0xff; |
133 | -#elif CONFIG_STUART | |
152 | +#elif defined(CONFIG_BTUART) | |
153 | + while (!(BTLSR & LSR_DR)); | |
154 | + | |
155 | + return (char) BTRBR & 0xff; | |
156 | +#elif defined(CONFIG_STUART) | |
134 | 157 | #endif |
135 | 158 | } |
136 | 159 |
doc/I2C_Edge_Conditions
... | ... | @@ -31,8 +31,13 @@ |
31 | 31 | !!!THIS IS AN UNDOCUMENTED I2C BUS BUG, NOT A IBM 4xx BUG!!! |
32 | 32 | |
33 | 33 | This reset edge condition could possibly be present in every I2C |
34 | -controller and device available. We should probably have a bus reset | |
35 | -function for all our target CPUs. | |
34 | +controller and device available. For boards where a I2C bus reset | |
35 | +function can be implemented a i2c_init_board() function should be | |
36 | +provided and enabled by #define'ing CFG_I2C_INIT_BOARD in your | |
37 | +board's config file. Note that this is NOT necessary when using the | |
38 | +bit-banging I2C driver (common/soft_i2c.c) as this already includes | |
39 | +the I2C bus reset sequence. | |
40 | + | |
36 | 41 | |
37 | 42 | Many thanks to Bill Hunter for finding this serious BUG. |
38 | 43 | email to: <williamhunter@attbi.com> |
doc/README.INCA-IP
1 | + | |
2 | +Flash programming on the INCA-IP board is complicated because of the | |
3 | +EBU swapping unit. A BDI2000 can be used for flash programming only | |
4 | +if the EBU swapping unit is enabled; otherwise it will not detect the | |
5 | +flash memory. But the EBU swapping unit is disadbled after reset, so | |
6 | +if you program some code to flash with the swapping unit on, it will | |
7 | +not be runnable with the swapping unit off. | |
8 | + | |
9 | +The consequence is that you have to write a pre-swapped image to | |
10 | +flash using the BDI2000. A simple host-side tool "inca-swap-bytes" is | |
11 | +provided in the "tools/" directory. Use it as follows: | |
12 | + | |
13 | + bash$ ./inca-swap-bytes <u-boot.bin >u-boot.bin.swp | |
14 | + | |
15 | +Note that the current BDI config file _disables_ the EBU swapping | |
16 | +unit for the flash bank 0. To enable it, (this is required for the | |
17 | +BDI flash commands to work) uncomment the following line in the | |
18 | +config file: | |
19 | + | |
20 | + ;WM32 0xb8000260 0x404161ff ; Swapping unit enabled | |
21 | + | |
22 | +and comment out | |
23 | + | |
24 | + WM32 0xb8000260 0x004161ff ; Swapping unit disabled | |
25 | + | |
26 | +Alternatively, you can use "mm 0xb8000260 <value>" commands to | |
27 | +enable/disable the swapping unit manually. | |
28 | + | |
29 | +Just for reference, here is the complete sequence of actions we took | |
30 | +to install a U-Boot image into flash. | |
31 | + | |
32 | + 1. ./inca-swap-bytes <u-boot.bin >u-boot.bin.swp | |
33 | + | |
34 | + 2. From BDI: | |
35 | + | |
36 | + mm 0xb8000260 0x404161ff | |
37 | + erase 0xb0000000 | |
38 | + erase 0xb0010000 | |
39 | + prog 0xb0000000 /tftpboot/INCA/u-boot.bin.swp bin | |
40 | + mm 0xb8000260 0x004161ff | |
41 | + go 0xb0000000 | |
42 | + | |
43 | + | |
44 | +(C) 2003 Wolfgang Denk |
doc/README.idma2intr
1 | +(C) 2003 Arun Dharankar <ADharankar@ATTBI.Com> | |
2 | + | |
3 | +Attached is an IDMA example code for MPC8260/PPCBoot. I had tried to | |
4 | +search around and could not find any for implementing IDMA, so | |
5 | +implemented one. Its not coded in the best way, but works. | |
6 | + | |
7 | +Also, I was able to test the IDMA specific code under Linux also | |
8 | +(with modifications). My requirement was to implement it for | |
9 | +CompactFlash implemented in memory mode, and it works for it under | |
10 | +PPCBoot and Linux. |
doc/README.sched
1 | +Notes on the scheduler in sched.c: | |
2 | +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
3 | + | |
4 | + 'sched.c' provides an very simplistic multi-threading scheduler. | |
5 | + See the example, function 'sched(...)', in the same file for its | |
6 | + API usage. | |
7 | + | |
8 | + Until an exhaustive testing can be done, the implementation cannot | |
9 | + qualify as that of production quality. It works with the example | |
10 | + in 'sched.c', it may or may not work in other cases. | |
11 | + | |
12 | + | |
13 | +Limitations: | |
14 | +~~~~~~~~~~~~ | |
15 | + | |
16 | + - There are NO primitives for thread synchronization (locking, | |
17 | + notify etc). | |
18 | + | |
19 | + - Only the GPRs and FPRs context is saved during a thread context | |
20 | + switch. Other registers on the PowerPC processor (60x, 7xx, 7xxx | |
21 | + etc) are NOT saved. | |
22 | + | |
23 | + - The scheduler is NOT transparent to the user. The user | |
24 | + applications must invoke thread_yield() to allow other threads to | |
25 | + scheduler. | |
26 | + | |
27 | + - There are NO priorities, and the scheduling policy is round-robin | |
28 | + based. | |
29 | + | |
30 | + - There are NO capabilities to collect thread CPU usage, scheduler | |
31 | + stats, thread status etc. | |
32 | + | |
33 | + - The semantics are somewhat based on those of pthreads, but NOT | |
34 | + the same. | |
35 | + | |
36 | + - Only seven threads are allowed. These can be easily increased by | |
37 | + changing "#define MAX_THREADS" depending on the available memory. | |
38 | + | |
39 | + - The stack size of each thread is 8KBytes. This can be easily | |
40 | + increased depending on the requirement and the available memory, | |
41 | + by increasing "#define STK_SIZE". | |
42 | + | |
43 | + - Only one master/parent thread is allowed, and it cannot be | |
44 | + stopped or deleted. Any given thread is NOT allowed to stop or | |
45 | + delete itself. | |
46 | + | |
47 | + - There NOT enough safety checks as are probably in the other | |
48 | + threads implementations. | |
49 | + | |
50 | + - There is no parent-child relationship between threads. Only one | |
51 | + thread may thread_join, preferably the master/parent thread. | |
52 | + | |
53 | +(C) 2003 Arun Dharankar <ADharankar@ATTBI.Com> |
drivers/ct69000.c
... | ... | @@ -830,6 +830,7 @@ |
830 | 830 | unsigned int m, n, vld, pd, PD, fref, xr_cb; |
831 | 831 | unsigned int fvcomin, fvcomax, pclckmin, pclckmax, pclk; |
832 | 832 | unsigned int pfreq, fvco, new_pixclock; |
833 | + unsigned int D,nback,mback; | |
833 | 834 | |
834 | 835 | fref = VIDEO_FREF; |
835 | 836 | pd = 1; |
... | ... | @@ -850,10 +851,19 @@ |
850 | 851 | PD++; |
851 | 852 | } |
852 | 853 | /* fvco is exactly pd * pixelclock and higher than the ninmal VCO frequency */ |
853 | - vld = (param->vld_set > param->vld_not_set) ? | |
854 | - param->vld_not_set : param->vld_set; | |
855 | - /* start with lower VLD (higher VLD is NOT yet implemented */ | |
856 | - FindBestPQFittingMN (fvco / vld, fref, param->mn_min, param->mn_max, &m, &n); /* rds = 1 */ | |
854 | + /* first try */ | |
855 | + vld = param->vld_set; | |
856 | + D=FindBestPQFittingMN (fvco / vld, fref, param->mn_min, param->mn_max, &m, &n); /* rds = 1 */ | |
857 | + mback=m; | |
858 | + nback=n; | |
859 | + /* second try */ | |
860 | + vld = param->vld_not_set; | |
861 | + if(D<FindBestPQFittingMN (fvco / vld, fref, param->mn_min, param->mn_max, &m, &n)) { /* rds = 1 */ | |
862 | + /* first try was better */ | |
863 | + m=mback; | |
864 | + n=nback; | |
865 | + vld = param->vld_set; | |
866 | + } | |
857 | 867 | m += param->mn_diff; |
858 | 868 | n += param->mn_diff; |
859 | 869 | PRINTF ("VCO %d, pd %d, m %d n %d vld %d \n", fvco, pd, m, n, vld); |
examples/Makefile
... | ... | @@ -33,7 +33,7 @@ |
33 | 33 | BIN += sched.bin |
34 | 34 | endif |
35 | 35 | |
36 | -ifeq ($(CPU),mips) | |
36 | +ifeq ($(ARCH),mips) | |
37 | 37 | SREC = |
38 | 38 | BIN = |
39 | 39 | endif |
... | ... | @@ -42,6 +42,12 @@ |
42 | 42 | ifeq ($(CPU),mpc8xx) |
43 | 43 | SREC += timer.srec |
44 | 44 | BIN += timer.bin |
45 | +endif | |
46 | + | |
47 | +# The following example is 8260 specific... | |
48 | +ifeq ($(CPU),mpc8260) | |
49 | +SREC += mem_to_mem_idma2intr.srec | |
50 | +BIN += mem_to_mem_idma2intr.bin | |
45 | 51 | endif |
46 | 52 | |
47 | 53 | # Utility for resetting i82559 EEPROM |
examples/mem_to_mem_idma2intr.c
1 | +/* The dpalloc function used and implemented in this file was derieved | |
2 | + * from PPCBoot/U-Boot file "cpu/mpc8260/commproc.c". | |
3 | + */ | |
4 | + | |
5 | +/* Author: Arun Dharankar <ADharankar@ATTBI.Com> | |
6 | + * This example is meant to only demonstrate how the IDMA could be used. | |
7 | + */ | |
8 | + | |
9 | +/* | |
10 | + * This file is based on "arch/ppc/8260_io/commproc.c" - here is it's | |
11 | + * copyright notice: | |
12 | + * | |
13 | + * General Purpose functions for the global management of the | |
14 | + * 8260 Communication Processor Module. | |
15 | + * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) | |
16 | + * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com) | |
17 | + * 2.3.99 Updates | |
18 | + * | |
19 | + * In addition to the individual control of the communication | |
20 | + * channels, there are a few functions that globally affect the | |
21 | + * communication processor. | |
22 | + * | |
23 | + * Buffer descriptors must be allocated from the dual ported memory | |
24 | + * space. The allocator for that is here. When the communication | |
25 | + * process is reset, we reclaim the memory available. There is | |
26 | + * currently no deallocator for this memory. | |
27 | + */ | |
28 | + | |
29 | + | |
30 | + | |
31 | +#include <common.h> | |
32 | +#include <syscall.h> | |
33 | + | |
34 | +#define STANDALONE | |
35 | + | |
36 | +#ifndef STANDALONE /* Linked into/Part of PPCBoot */ | |
37 | +#include <command.h> | |
38 | +#include <watchdog.h> | |
39 | +#else /* Standalone app of PPCBoot */ | |
40 | +#include <syscall.h> | |
41 | +#define printf mon_printf | |
42 | +#define tstc mon_tstc | |
43 | +#define getc mon_getc | |
44 | +#define putc mon_putc | |
45 | +#define udelay mon_udelay | |
46 | +#define malloc mon_malloc | |
47 | +#define WATCHDOG_RESET() { \ | |
48 | + *(ushort *)(CFG_IMMR + 0x1000E) = 0x556c; \ | |
49 | + *(ushort *)(CFG_IMMR + 0x1000E) = 0xaa39; \ | |
50 | + } | |
51 | +#endif /* STANDALONE */ | |
52 | + | |
53 | +static int debug = 1; | |
54 | + | |
55 | +#define DEBUG(fmt, args...) { \ | |
56 | + if(debug != 0) { \ | |
57 | + printf("[%s %d %s]: ",__FILE__,__LINE__,__FUNCTION__); \ | |
58 | + printf(fmt, ##args); \ | |
59 | + } \ | |
60 | +} | |
61 | + | |
62 | +#define CPM_CR_IDMA1_SBLOCK (0x14) | |
63 | +#define CPM_CR_IDMA2_SBLOCK (0x15) | |
64 | +#define CPM_CR_IDMA3_SBLOCK (0x16) | |
65 | +#define CPM_CR_IDMA4_SBLOCK (0x17) | |
66 | +#define CPM_CR_IDMA1_PAGE (0x07) | |
67 | +#define CPM_CR_IDMA2_PAGE (0x08) | |
68 | +#define CPM_CR_IDMA3_PAGE (0x09) | |
69 | +#define CPM_CR_IDMA4_PAGE (0x0a) | |
70 | +#define PROFF_IDMA1_BASE ((uint)0x87fe) | |
71 | +#define PROFF_IDMA2_BASE ((uint)0x88fe) | |
72 | +#define PROFF_IDMA3_BASE ((uint)0x89fe) | |
73 | +#define PROFF_IDMA4_BASE ((uint)0x8afe) | |
74 | + | |
75 | +#define CPM_CR_INIT_TRX ((ushort)0x0000) | |
76 | +#define CPM_CR_FLG ((ushort)0x0001) | |
77 | + | |
78 | +#define mk_cr_cmd(PG, SBC, MCN, OP) \ | |
79 | + ((PG << 26) | (SBC << 21) | (MCN << 6) | OP) | |
80 | + | |
81 | + | |
82 | +#pragma pack(1) | |
83 | +typedef struct ibdbits { | |
84 | + unsigned b_valid:1; | |
85 | + unsigned b_resv1:1; | |
86 | + unsigned b_wrap:1; | |
87 | + unsigned b_interrupt:1; | |
88 | + unsigned b_last:1; | |
89 | + unsigned b_resv2:1; | |
90 | + unsigned b_cm:1; | |
91 | + unsigned b_resv3:2; | |
92 | + unsigned b_sdn:1; | |
93 | + unsigned b_ddn:1; | |
94 | + unsigned b_dgbl:1; | |
95 | + unsigned b_dbo:2; | |
96 | + unsigned b_resv4:1; | |
97 | + unsigned b_ddtb:1; | |
98 | + unsigned b_resv5:2; | |
99 | + unsigned b_sgbl:1; | |
100 | + unsigned b_sbo:2; | |
101 | + unsigned b_resv6:1; | |
102 | + unsigned b_sdtb:1; | |
103 | + unsigned b_resv7:9; | |
104 | +} ibdbits_t; | |
105 | + | |
106 | +#pragma pack(1) | |
107 | +typedef union ibdbitsu { | |
108 | + ibdbits_t b; | |
109 | + uint i; | |
110 | +} ibdbitsu_t; | |
111 | + | |
112 | +#pragma pack(1) | |
113 | +typedef struct idma_buf_desc { | |
114 | + ibdbitsu_t ibd_bits; /* Status and Control */ | |
115 | + uint ibd_datlen; /* Data length in buffer */ | |
116 | + uint ibd_sbuf; /* Source buffer addr in host mem */ | |
117 | + uint ibd_dbuf; /* Destination buffer addr in host mem */ | |
118 | +} ibd_t; | |
119 | + | |
120 | + | |
121 | +#pragma pack(1) | |
122 | +typedef struct dcmbits { | |
123 | + unsigned b_fb:1; | |
124 | + unsigned b_lp:1; | |
125 | + unsigned b_resv1:3; | |
126 | + unsigned b_tc2:1; | |
127 | + unsigned b_resv2:1; | |
128 | + unsigned b_wrap:3; | |
129 | + unsigned b_sinc:1; | |
130 | + unsigned b_dinc:1; | |
131 | + unsigned b_erm:1; | |
132 | + unsigned b_dt:1; | |
133 | + unsigned b_sd:2; | |
134 | +} dcmbits_t; | |
135 | + | |
136 | +#pragma pack(1) | |
137 | +typedef union dcmbitsu { | |
138 | + dcmbits_t b; | |
139 | + ushort i; | |
140 | +} dcmbitsu_t; | |
141 | + | |
142 | +#pragma pack(1) | |
143 | +typedef struct pram_idma { | |
144 | + ushort pi_ibase; | |
145 | + dcmbitsu_t pi_dcmbits; | |
146 | + ushort pi_ibdptr; | |
147 | + ushort pi_dprbuf; | |
148 | + ushort pi_bufinv; /* internal to CPM */ | |
149 | + ushort pi_ssmax; | |
150 | + ushort pi_dprinptr; /* internal to CPM */ | |
151 | + ushort pi_sts; | |
152 | + ushort pi_dproutptr; /* internal to CPM */ | |
153 | + ushort pi_seob; | |
154 | + ushort pi_deob; | |
155 | + ushort pi_dts; | |
156 | + ushort pi_retadd; | |
157 | + ushort pi_resv1; /* internal to CPM */ | |
158 | + uint pi_bdcnt; | |
159 | + uint pi_sptr; | |
160 | + uint pi_dptr; | |
161 | + uint pi_istate; | |
162 | +} pram_idma_t; | |
163 | + | |
164 | + | |
165 | +volatile immap_t *immap = (immap_t *) CFG_IMMR; | |
166 | +volatile ibd_t *bdf; | |
167 | +volatile pram_idma_t *piptr; | |
168 | + | |
169 | +volatile int dmadone; | |
170 | +volatile int *dmadonep = &dmadone; | |
171 | +void dmadone_handler (void *); | |
172 | + | |
173 | +int idma_init (void); | |
174 | +void idma_start (int, int, int, uint, uint, int); | |
175 | +uint dpalloc (uint, uint); | |
176 | + | |
177 | + | |
178 | +uint dpinit_done = 0; | |
179 | + | |
180 | + | |
181 | +#ifdef STANDALONE | |
182 | +int ctrlc (void) | |
183 | +{ | |
184 | + if (mon_tstc()) { | |
185 | + switch (mon_getc ()) { | |
186 | + case 0x03: /* ^C - Control C */ | |
187 | + return 1; | |
188 | + default: | |
189 | + break; | |
190 | + } | |
191 | + } | |
192 | + return 0; | |
193 | +} | |
194 | +void * memset(void * s,int c,size_t count) | |
195 | +{ | |
196 | + char *xs = (char *) s; | |
197 | + while (count--) | |
198 | + *xs++ = c; | |
199 | + return s; | |
200 | +} | |
201 | +int memcmp(const void * cs,const void * ct,size_t count) | |
202 | +{ | |
203 | + const unsigned char *su1, *su2; | |
204 | + int res = 0; | |
205 | + for( su1 = cs, su2 = ct; 0 < count; ++su1, ++su2, count--) | |
206 | + if ((res = *su1 - *su2) != 0) | |
207 | + break; | |
208 | + return res; | |
209 | +} | |
210 | +#endif /* STANDALONE */ | |
211 | + | |
212 | +#ifdef STANDALONE | |
213 | +int mem_to_mem_idma2intr (bd_t * bd, int argc, char *argv[]) | |
214 | +#else | |
215 | +int do_idma (bd_t * bd, int argc, char *argv[]) | |
216 | +#endif /* STANDALONE */ | |
217 | +{ | |
218 | + int i; | |
219 | + | |
220 | + dpinit_done = 0; | |
221 | + | |
222 | + idma_init (); | |
223 | + | |
224 | + DEBUG ("Installing dma handler\n"); | |
225 | + mon_install_hdlr (7, dmadone_handler, (void *) bdf); | |
226 | + | |
227 | + memset ((void *) 0x100000, 'a', 512); | |
228 | + memset ((void *) 0x200000, 'b', 512); | |
229 | + | |
230 | + for (i = 0; i < 32; i++) { | |
231 | + printf ("Startin IDMA, iteration=%d\n", i); | |
232 | + idma_start (1, 1, 512, 0x100000, 0x200000, 3); | |
233 | + } | |
234 | + | |
235 | + DEBUG ("Uninstalling dma handler\n"); | |
236 | + mon_free_hdlr (7); | |
237 | + | |
238 | + return 0; | |
239 | +} | |
240 | + | |
241 | +void | |
242 | +idma_start (int sinc, int dinc, int sz, uint sbuf, uint dbuf, int ttype) | |
243 | +{ | |
244 | + /* ttype is for M-M, M-P, P-M or P-P: not used for now */ | |
245 | + | |
246 | + piptr->pi_istate = 0; /* manual says: clear it before every START_IDMA */ | |
247 | + piptr->pi_dcmbits.b.b_resv1 = 0; | |
248 | + | |
249 | + if (sinc == 1) | |
250 | + piptr->pi_dcmbits.b.b_sinc = 1; | |
251 | + else | |
252 | + piptr->pi_dcmbits.b.b_sinc = 0; | |
253 | + | |
254 | + if (dinc == 1) | |
255 | + piptr->pi_dcmbits.b.b_dinc = 1; | |
256 | + else | |
257 | + piptr->pi_dcmbits.b.b_dinc = 0; | |
258 | + | |
259 | + piptr->pi_dcmbits.b.b_erm = 0; | |
260 | + piptr->pi_dcmbits.b.b_sd = 0x00; /* M-M */ | |
261 | + | |
262 | + bdf->ibd_sbuf = sbuf; | |
263 | + bdf->ibd_dbuf = dbuf; | |
264 | + bdf->ibd_bits.b.b_cm = 0; | |
265 | + bdf->ibd_bits.b.b_interrupt = 1; | |
266 | + bdf->ibd_bits.b.b_wrap = 1; | |
267 | + bdf->ibd_bits.b.b_last = 1; | |
268 | + bdf->ibd_bits.b.b_sdn = 0; | |
269 | + bdf->ibd_bits.b.b_ddn = 0; | |
270 | + bdf->ibd_bits.b.b_dgbl = 0; | |
271 | + bdf->ibd_bits.b.b_ddtb = 0; | |
272 | + bdf->ibd_bits.b.b_sgbl = 0; | |
273 | + bdf->ibd_bits.b.b_sdtb = 0; | |
274 | + bdf->ibd_bits.b.b_dbo = 1; | |
275 | + bdf->ibd_bits.b.b_sbo = 1; | |
276 | + bdf->ibd_bits.b.b_valid = 1; | |
277 | + bdf->ibd_datlen = 512; | |
278 | + | |
279 | + *dmadonep = 0; | |
280 | + | |
281 | + immap->im_sdma.sdma_idmr2 = (uchar) 0xf; | |
282 | + | |
283 | + immap->im_cpm.cp_cpcr = mk_cr_cmd (CPM_CR_IDMA2_PAGE, | |
284 | + CPM_CR_IDMA2_SBLOCK, 0x0, | |
285 | + 0x9) | 0x00010000; | |
286 | + | |
287 | + while (*dmadonep != 1) { | |
288 | + if (ctrlc ()) { | |
289 | + DEBUG ("\nInterrupted waiting for DMA interrupt.\n"); | |
290 | + goto done; | |
291 | + } | |
292 | + printf ("Waiting for DMA interrupt (dmadone=%d b_valid = %d)...\n", | |
293 | + dmadone, bdf->ibd_bits.b.b_valid); | |
294 | + udelay (1000000); | |
295 | + } | |
296 | + printf ("DMA complete notification received!\n"); | |
297 | + | |
298 | + done: | |
299 | + DEBUG ("memcmp(0x%08x, 0x%08x, 512) = %d\n", | |
300 | + sbuf, dbuf, memcmp ((void *) sbuf, (void *) dbuf, 512)); | |
301 | + | |
302 | + return; | |
303 | +} | |
304 | + | |
305 | +#define MAX_INT_BUFSZ 64 | |
306 | +#define DCM_WRAP 0 /* MUST be consistant with MAX_INT_BUFSZ */ | |
307 | + | |
308 | +int idma_init (void) | |
309 | +{ | |
310 | + uint memaddr; | |
311 | + | |
312 | + immap->im_cpm.cp_rccr &= ~0x00F3FFFF; | |
313 | + immap->im_cpm.cp_rccr |= 0x00A00A00; | |
314 | + | |
315 | + memaddr = dpalloc (sizeof (pram_idma_t), 64); | |
316 | + | |
317 | + *(volatile ushort *) &immap->im_dprambase[PROFF_IDMA2_BASE] = memaddr; | |
318 | + piptr = (volatile pram_idma_t *) ((uint) (immap) + memaddr); | |
319 | + | |
320 | + piptr->pi_resv1 = 0; /* manual says: clear it */ | |
321 | + piptr->pi_dcmbits.b.b_fb = 0; | |
322 | + piptr->pi_dcmbits.b.b_lp = 1; | |
323 | + piptr->pi_dcmbits.b.b_erm = 0; | |
324 | + piptr->pi_dcmbits.b.b_dt = 0; | |
325 | + | |
326 | + memaddr = (uint) dpalloc (sizeof (ibd_t), 64); | |
327 | + piptr->pi_ibase = piptr->pi_ibdptr = (volatile short) memaddr; | |
328 | + bdf = (volatile ibd_t *) ((uint) (immap) + memaddr); | |
329 | + bdf->ibd_bits.b.b_valid = 0; | |
330 | + | |
331 | + memaddr = (uint) dpalloc (64, 64); | |
332 | + piptr->pi_dprbuf = (volatile ushort) memaddr; | |
333 | + piptr->pi_dcmbits.b.b_wrap = 4; | |
334 | + piptr->pi_ssmax = 32; | |
335 | + | |
336 | + piptr->pi_sts = piptr->pi_ssmax; | |
337 | + piptr->pi_dts = piptr->pi_ssmax; | |
338 | + | |
339 | + return 1; | |
340 | +} | |
341 | + | |
342 | +void dmadone_handler (void *arg) | |
343 | +{ | |
344 | + immap->im_sdma.sdma_idmr2 = (uchar) 0x0; | |
345 | + | |
346 | + *dmadonep = 1; | |
347 | + | |
348 | + return; | |
349 | +} | |
350 | + | |
351 | + | |
352 | +static uint dpbase = 0; | |
353 | + | |
354 | +uint dpalloc (uint size, uint align) | |
355 | +{ | |
356 | + DECLARE_GLOBAL_DATA_PTR; | |
357 | + | |
358 | + volatile immap_t *immr = (immap_t *) CFG_IMMR; | |
359 | + uint retloc; | |
360 | + uint align_mask, off; | |
361 | + uint savebase; | |
362 | + | |
363 | + /* Pointer to initial global data area */ | |
364 | + | |
365 | + if (dpinit_done == 0) { | |
366 | + dpbase = gd->dp_alloc_base; | |
367 | + dpinit_done = 1; | |
368 | + } | |
369 | + | |
370 | + align_mask = align - 1; | |
371 | + savebase = dpbase; | |
372 | + | |
373 | + if ((off = (dpbase & align_mask)) != 0) | |
374 | + dpbase += (align - off); | |
375 | + | |
376 | + if ((off = size & align_mask) != 0) | |
377 | + size += align - off; | |
378 | + | |
379 | + if ((dpbase + size) >= gd->dp_alloc_top) { | |
380 | + dpbase = savebase; | |
381 | + printf ("dpalloc: ran out of dual port ram!"); | |
382 | + return 0; | |
383 | + } | |
384 | + | |
385 | + retloc = dpbase; | |
386 | + dpbase += size; | |
387 | + | |
388 | + memset ((void *) &immr->im_dprambase[retloc], 0, size); | |
389 | + | |
390 | + return (retloc); | |
391 | +} |
examples/ppc_longjmp.S
examples/ppc_setjmp.S
examples/sched.c
... | ... | @@ -3,12 +3,12 @@ |
3 | 3 | * modify it under the terms of the GNU General Public License as |
4 | 4 | * published by the Free Software Foundation; either version 2 of |
5 | 5 | * the License, or (at your option) any later version. |
6 | - * | |
6 | + * | |
7 | 7 | * This program is distributed in the hope that it will be useful, |
8 | 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
9 | 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
10 | 10 | * GNU General Public License for more details. |
11 | - * | |
11 | + * | |
12 | 12 | * You should have received a copy of the GNU General Public License |
13 | 13 | * along with this program; if not, write to the Free Software |
14 | 14 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
... | ... | @@ -17,7 +17,6 @@ |
17 | 17 | |
18 | 18 | #include <common.h> |
19 | 19 | #include <syscall.h> |
20 | -#include <setjmp.h> | |
21 | 20 | |
22 | 21 | /* |
23 | 22 | * Author: Arun Dharankar <ADharankar@ATTBI.Com> |
... | ... | @@ -54,6 +53,13 @@ |
54 | 53 | #define RC_FAILURE (-1) |
55 | 54 | #define RC_SUCCESS (0) |
56 | 55 | |
56 | +typedef vu_char *jmp_ctx; | |
57 | +unsigned long setctxsp (vu_char *sp); | |
58 | +int ppc_setjmp(jmp_ctx env); | |
59 | +void ppc_longjmp(jmp_ctx env, int val); | |
60 | +#define setjmp ppc_setjmp | |
61 | +#define longjmp ppc_longjmp | |
62 | + | |
57 | 63 | struct lthread { |
58 | 64 | int state; |
59 | 65 | int retval; |
... | ... | @@ -68,13 +74,13 @@ |
68 | 74 | |
69 | 75 | static uchar dbg = 0; |
70 | 76 | |
71 | -#define DEBUG(fmt, args...) { \ | |
72 | - if(dbg != 0) { \ | |
73 | - mon_printf("[%s %d %s]: ", __FILE__, __LINE__, __FUNCTION__); \ | |
74 | - mon_printf(fmt, ##args); \ | |
75 | - mon_printf("\n"); \ | |
76 | - } \ | |
77 | - } | |
77 | +#define PDEBUG(fmt, args...) { \ | |
78 | + if(dbg != 0) { \ | |
79 | + mon_printf("[%s %d %s]: ",__FILE__,__LINE__,__FUNCTION__);\ | |
80 | + mon_printf(fmt, ##args); \ | |
81 | + mon_printf("\n"); \ | |
82 | + } \ | |
83 | +} | |
78 | 84 | |
79 | 85 | static int testthread (void *); |
80 | 86 | static void sched_init (void); |
81 | 87 | |
82 | 88 | |
... | ... | @@ -83,14 +89,15 @@ |
83 | 89 | static void thread_yield (void); |
84 | 90 | static int thread_delete (int id); |
85 | 91 | static int thread_join (int *ret); |
86 | -#if 0 /* not used yet */ | |
92 | + | |
93 | +#if 0 /* not used yet */ | |
87 | 94 | static int thread_stop (int id); |
88 | -#endif /* not used yet */ | |
95 | +#endif /* not used yet */ | |
89 | 96 | |
90 | 97 | /* An example of schedular test */ |
91 | 98 | |
92 | 99 | #define NUMTHREADS 7 |
93 | -int sched (bd_t *bd, int ac, char *av[]) | |
100 | +int sched (bd_t * bd, int ac, char *av[]) | |
94 | 101 | { |
95 | 102 | int i, j; |
96 | 103 | int tid[NUMTHREADS]; |
97 | 104 | |
... | ... | @@ -102,11 +109,10 @@ |
102 | 109 | names[i] = i; |
103 | 110 | j = thread_create (testthread, (void *) &names[i]); |
104 | 111 | if (j == RC_FAILURE) |
105 | - mon_printf ("schedtest: Failed to create thread %d\n", | |
106 | - i); | |
112 | + mon_printf ("schedtest: Failed to create thread %d\n", i); | |
107 | 113 | if (j > 0) { |
108 | 114 | mon_printf ("schedtest: Created thread with id %d, name %d\n", |
109 | - j, i); | |
115 | + j, i); | |
110 | 116 | tid[i] = j; |
111 | 117 | } |
112 | 118 | } |
... | ... | @@ -125,8 +131,7 @@ |
125 | 131 | if (mon_tstc () && mon_getc () == 0x3) { |
126 | 132 | mon_printf ("schedtest: Aborting threads...\n"); |
127 | 133 | for (i = 0; i < NUMTHREADS; i++) { |
128 | - mon_printf ("schedtest: Deleting thread %d\n", | |
129 | - tid[i]); | |
134 | + mon_printf ("schedtest: Deleting thread %d\n", tid[i]); | |
130 | 135 | thread_delete (tid[i]); |
131 | 136 | } |
132 | 137 | return RC_SUCCESS; |
133 | 138 | |
... | ... | @@ -135,11 +140,10 @@ |
135 | 140 | i = thread_join (&j); |
136 | 141 | if (i == RC_FAILURE) { |
137 | 142 | mon_printf ("schedtest: No threads pending, " |
138 | - "exiting schedular test\n"); | |
143 | + "exiting schedular test\n"); | |
139 | 144 | return RC_SUCCESS; |
140 | 145 | } |
141 | - mon_printf ("schedtest: thread is %d returned %d\n", i, | |
142 | - j); | |
146 | + mon_printf ("schedtest: thread is %d returned %d\n", i, j); | |
143 | 147 | thread_yield (); |
144 | 148 | } |
145 | 149 | |
146 | 150 | |
... | ... | @@ -151,14 +155,14 @@ |
151 | 155 | int i; |
152 | 156 | |
153 | 157 | mon_printf ("testthread: Begin executing thread, myname %d, &i=0x%08x\n", |
154 | - *(int *) name, &i); | |
158 | + *(int *) name, &i); | |
155 | 159 | |
156 | 160 | mon_printf ("Thread %02d, i=%d\n", *(int *) name); |
157 | 161 | |
158 | 162 | for (i = 0; i < 0xffff * (*(int *) name + 1); i++) { |
159 | 163 | if (mon_tstc () && mon_getc () == 0x3) { |
160 | 164 | mon_printf ("testthread: myname %d terminating.\n", |
161 | - *(int *) name); | |
165 | + *(int *) name); | |
162 | 166 | return *(int *) name + 1; |
163 | 167 | } |
164 | 168 | |
... | ... | @@ -167,7 +171,7 @@ |
167 | 171 | } |
168 | 172 | |
169 | 173 | mon_printf ("testthread: returning %d, i=0x%x\n", |
170 | - *(int *) name + 1, i); | |
174 | + *(int *) name + 1, i); | |
171 | 175 | |
172 | 176 | return *(int *) name + 1; |
173 | 177 | } |
... | ... | @@ -182,8 +186,8 @@ |
182 | 186 | |
183 | 187 | current_tid = MASTER_THREAD; |
184 | 188 | lthreads[current_tid].state = STATE_RUNNABLE; |
185 | - DEBUG ("sched_init: master context = 0x%08x", | |
186 | - lthreads[current_tid].context); | |
189 | + PDEBUG ("sched_init: master context = 0x%08x", | |
190 | + lthreads[current_tid].context); | |
187 | 191 | return; |
188 | 192 | } |
189 | 193 | |
190 | 194 | |
191 | 195 | |
192 | 196 | |
... | ... | @@ -191,19 +195,19 @@ |
191 | 195 | { |
192 | 196 | static int i; |
193 | 197 | |
194 | - DEBUG ("thread_yield: current tid=%d", current_tid); | |
198 | + PDEBUG ("thread_yield: current tid=%d", current_tid); | |
195 | 199 | |
196 | 200 | #define SWITCH(new) \ |
197 | 201 | if(lthreads[new].state == STATE_RUNNABLE) { \ |
198 | - DEBUG("thread_yield: %d match, ctx=0x%08x", \ | |
202 | + PDEBUG("thread_yield: %d match, ctx=0x%08x", \ | |
199 | 203 | new, lthreads[current_tid].context); \ |
200 | 204 | if(setjmp(lthreads[current_tid].context) == 0) { \ |
201 | 205 | current_tid = new; \ |
202 | - DEBUG("thread_yield: tid %d returns 0", \ | |
206 | + PDEBUG("thread_yield: tid %d returns 0", \ | |
203 | 207 | new); \ |
204 | 208 | longjmp(lthreads[new].context, 1); \ |
205 | 209 | } else { \ |
206 | - DEBUG("thread_yield: tid %d returns 1", \ | |
210 | + PDEBUG("thread_yield: tid %d returns 1", \ | |
207 | 211 | new); \ |
208 | 212 | return; \ |
209 | 213 | } \ |
... | ... | @@ -219,7 +223,7 @@ |
219 | 223 | } |
220 | 224 | } |
221 | 225 | |
222 | - DEBUG ("thread_yield: returning from thread_yield"); | |
226 | + PDEBUG ("thread_yield: returning from thread_yield"); | |
223 | 227 | return; |
224 | 228 | } |
225 | 229 | |
226 | 230 | |
... | ... | @@ -232,12 +236,12 @@ |
232 | 236 | lthreads[i].state = STATE_STOPPED; |
233 | 237 | lthreads[i].func = func; |
234 | 238 | lthreads[i].arg = arg; |
235 | - DEBUG ("thread_create: returns new tid %d", i); | |
239 | + PDEBUG ("thread_create: returns new tid %d", i); | |
236 | 240 | return i; |
237 | 241 | } |
238 | 242 | } |
239 | 243 | |
240 | - DEBUG ("thread_create: returns failure"); | |
244 | + PDEBUG ("thread_create: returns failure"); | |
241 | 245 | return RC_FAILURE; |
242 | 246 | } |
243 | 247 | |
244 | 248 | |
245 | 249 | |
... | ... | @@ -255,13 +259,13 @@ |
255 | 259 | |
256 | 260 | static void thread_launcher (void) |
257 | 261 | { |
258 | - DEBUG ("thread_launcher: invoking func=0x%08x", | |
262 | + PDEBUG ("thread_launcher: invoking func=0x%08x", | |
259 | 263 | lthreads[current_tid].func); |
260 | 264 | |
261 | 265 | lthreads[current_tid].retval = |
262 | - lthreads[current_tid].func(lthreads[current_tid].arg); | |
266 | + lthreads[current_tid].func (lthreads[current_tid].arg); | |
263 | 267 | |
264 | - DEBUG ("thread_launcher: tid %d terminated", current_tid); | |
268 | + PDEBUG ("thread_launcher: tid %d terminated", current_tid); | |
265 | 269 | |
266 | 270 | lthreads[current_tid].state = STATE_TERMINATED; |
267 | 271 | thread_yield (); |
... | ... | @@ -272,7 +276,7 @@ |
272 | 276 | |
273 | 277 | static int thread_start (int id) |
274 | 278 | { |
275 | - DEBUG ("thread_start: id=%d", id); | |
279 | + PDEBUG ("thread_start: id=%d", id); | |
276 | 280 | if (id <= MASTER_THREAD || id > MAX_THREADS) { |
277 | 281 | return RC_FAILURE; |
278 | 282 | } |
279 | 283 | |
280 | 284 | |
... | ... | @@ -283,17 +287,17 @@ |
283 | 287 | if (setjmp (lthreads[current_tid].context) == 0) { |
284 | 288 | lthreads[id].state = STATE_RUNNABLE; |
285 | 289 | current_tid = id; |
286 | - DEBUG ("thread_start: to be stack=0%08x", lthreads[id].stack); | |
290 | + PDEBUG ("thread_start: to be stack=0%08x", lthreads[id].stack); | |
287 | 291 | setctxsp (<hreads[id].stack[STK_SIZE]); |
288 | 292 | thread_launcher (); |
289 | 293 | } |
290 | 294 | |
291 | - DEBUG ("thread_start: Thread id=%d started, parent returns", id); | |
295 | + PDEBUG ("thread_start: Thread id=%d started, parent returns", id); | |
292 | 296 | |
293 | 297 | return RC_SUCCESS; |
294 | 298 | } |
295 | 299 | |
296 | -#if 0 /* not used so far */ | |
300 | +#if 0 /* not used so far */ | |
297 | 301 | static int thread_stop (int id) |
298 | 302 | { |
299 | 303 | if (id <= MASTER_THREAD || id >= MAX_THREADS) |
300 | 304 | |
301 | 305 | |
302 | 306 | |
303 | 307 | |
304 | 308 | |
305 | 309 | |
306 | 310 | |
307 | 311 | |
308 | 312 | |
... | ... | @@ -305,46 +309,46 @@ |
305 | 309 | lthreads[id].state = STATE_STOPPED; |
306 | 310 | return RC_SUCCESS; |
307 | 311 | } |
308 | -#endif /* not used so far */ | |
312 | +#endif /* not used so far */ | |
309 | 313 | |
310 | 314 | static int thread_join (int *ret) |
311 | 315 | { |
312 | 316 | int i, j = 0; |
313 | 317 | |
314 | - DEBUG ("thread_join: *ret = %d", *ret); | |
318 | + PDEBUG ("thread_join: *ret = %d", *ret); | |
315 | 319 | |
316 | 320 | if (!(*ret == -1 || *ret > MASTER_THREAD || *ret < MAX_THREADS)) { |
317 | - DEBUG ("thread_join: invalid tid %d", *ret); | |
321 | + PDEBUG ("thread_join: invalid tid %d", *ret); | |
318 | 322 | return RC_FAILURE; |
319 | 323 | } |
320 | 324 | |
321 | 325 | if (*ret == -1) { |
322 | - DEBUG ("Checking for tid = -1"); | |
326 | + PDEBUG ("Checking for tid = -1"); | |
323 | 327 | while (1) { |
324 | - /* DEBUG("thread_join: start while-loopn"); */ | |
328 | + /* PDEBUG("thread_join: start while-loopn"); */ | |
325 | 329 | j = 0; |
326 | 330 | for (i = MASTER_THREAD + 1; i < MAX_THREADS; i++) { |
327 | 331 | if (lthreads[i].state == STATE_TERMINATED) { |
328 | 332 | *ret = lthreads[i].retval; |
329 | 333 | lthreads[i].state = STATE_EMPTY; |
330 | - /* DEBUG("thread_join: returning retval %d of tid %d", | |
331 | - ret, i); */ | |
334 | + /* PDEBUG("thread_join: returning retval %d of tid %d", | |
335 | + ret, i); */ | |
332 | 336 | return RC_SUCCESS; |
333 | 337 | } |
334 | 338 | |
335 | 339 | if (lthreads[i].state != STATE_EMPTY) { |
336 | - DEBUG ("thread_join: %d used slots tid %d state=%d", | |
337 | - j, i, lthreads[i].state); | |
340 | + PDEBUG ("thread_join: %d used slots tid %d state=%d", | |
341 | + j, i, lthreads[i].state); | |
338 | 342 | j++; |
339 | 343 | } |
340 | 344 | } |
341 | 345 | if (j == 0) { |
342 | - DEBUG ("thread_join: all slots empty!"); | |
346 | + PDEBUG ("thread_join: all slots empty!"); | |
343 | 347 | return RC_FAILURE; |
344 | 348 | } |
345 | - /* DEBUG("thread_join: yielding"); */ | |
349 | + /* PDEBUG("thread_join: yielding"); */ | |
346 | 350 | thread_yield (); |
347 | - /* DEBUG("thread_join: back from yield"); */ | |
351 | + /* PDEBUG("thread_join: back from yield"); */ | |
348 | 352 | } |
349 | 353 | } |
350 | 354 | |
351 | 355 | |
... | ... | @@ -352,11 +356,11 @@ |
352 | 356 | i = *ret; |
353 | 357 | *ret = lthreads[*ret].retval; |
354 | 358 | lthreads[*ret].state = STATE_EMPTY; |
355 | - DEBUG ("thread_join: returing %d for tid %d", *ret, i); | |
359 | + PDEBUG ("thread_join: returing %d for tid %d", *ret, i); | |
356 | 360 | return RC_SUCCESS; |
357 | 361 | } |
358 | 362 | |
359 | - DEBUG ("thread_join: thread %d is not terminated!", *ret); | |
363 | + PDEBUG ("thread_join: thread %d is not terminated!", *ret); | |
360 | 364 | return RC_FAILURE; |
361 | 365 | } |
include/asm-mips/inca-ip.h
... | ... | @@ -894,7 +894,12 @@ |
894 | 894 | /* Module : EBU register address and bits */ |
895 | 895 | /***********************************************************************/ |
896 | 896 | |
897 | +#if defined(CONFIG_INCA_IP) | |
897 | 898 | #define INCA_IP_EBU (0xB8000200) |
899 | +#elif defined(CONFIG_PURPLE) | |
900 | +#define INCA_IP_EBU (0xB800D800) | |
901 | +#endif | |
902 | + | |
898 | 903 | /***********************************************************************/ |
899 | 904 | |
900 | 905 | |
901 | 906 | |
... | ... | @@ -1490,7 +1495,12 @@ |
1490 | 1495 | /* Module : ASC register address and bits */ |
1491 | 1496 | /***********************************************************************/ |
1492 | 1497 | |
1498 | +#if defined(CONFIG_INCA_IP) | |
1493 | 1499 | #define INCA_IP_ASC (0xB8000400) |
1500 | +#elif defined(CONFIG_PURPLE) | |
1501 | +#define INCA_IP_ASC (0xBE500000) | |
1502 | +#endif | |
1503 | + | |
1494 | 1504 | /***********************************************************************/ |
1495 | 1505 | |
1496 | 1506 |
include/cmd_net.h
... | ... | @@ -56,7 +56,7 @@ |
56 | 56 | #define CMD_TBL_DHCP MK_CMD_TBL_ENTRY( \ |
57 | 57 | "dhcp", 4, 3, 1, do_dhcp, \ |
58 | 58 | "dhcp - invoke DHCP client to obtain IP/boot params\n", \ |
59 | - "\n" \ | |
59 | + "[loadAddress] [bootfilename]\n" \ | |
60 | 60 | ), |
61 | 61 | |
62 | 62 | int do_dhcp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); |
include/configs/MIP405.h
... | ... | @@ -109,7 +109,7 @@ |
109 | 109 | #define CONFIG_BOOT_RETRY_TIME -10 /* feature is avaiable but not enabled */ |
110 | 110 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ |
111 | 111 | |
112 | -#define CONFIG_BOOTCOMMAND "diskboot 200000 0:1; bootm" /* autoboot command */ | |
112 | +#define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */ | |
113 | 113 | #define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */ |
114 | 114 | |
115 | 115 | #define CONFIG_IPADDR 10.0.0.100 |
... | ... | @@ -162,7 +162,7 @@ |
162 | 162 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ |
163 | 163 | 57600, 115200, 230400, 460800, 921600 } |
164 | 164 | |
165 | -#define CFG_LOAD_ADDR 0x200000 /* default load address */ | |
165 | +#define CFG_LOAD_ADDR 0x400000 /* default load address */ | |
166 | 166 | #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
167 | 167 | |
168 | 168 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
include/configs/PIP405.h
... | ... | @@ -113,7 +113,7 @@ |
113 | 113 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ |
114 | 114 | |
115 | 115 | |
116 | -#define CONFIG_BOOTCOMMAND "diskboot 200000 0:1; bootm" /* autoboot command */ | |
116 | +#define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */ | |
117 | 117 | #define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */ |
118 | 118 | |
119 | 119 | #define CONFIG_IPADDR 10.0.0.100 |
... | ... | @@ -166,7 +166,7 @@ |
166 | 166 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ |
167 | 167 | 57600, 115200, 230400, 460800, 921600 } |
168 | 168 | |
169 | -#define CFG_LOAD_ADDR 0x200000 /* default load address */ | |
169 | +#define CFG_LOAD_ADDR 0x400000 /* default load address */ | |
170 | 170 | #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
171 | 171 | |
172 | 172 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
include/configs/incaip.h
... | ... | @@ -34,18 +34,60 @@ |
34 | 34 | /* allowed values: 100000000 and 150000000 */ |
35 | 35 | #define CPU_CLOCK_RATE 150000000 /* 150 MHz clock for the MIPS core */ |
36 | 36 | |
37 | -#define CONFIG_BAUDRATE 115200 | |
37 | +#if CPU_CLOCK_RATE == 100000000 | |
38 | +#define INFINEON_EBU_BOOTCFG 0x20C4 /* CMULT = 4 for 100 MHz */ | |
39 | +#else | |
40 | +#define INFINEON_EBU_BOOTCFG 0x40C4 /* CMULT = 8 for 150 MHz */ | |
41 | +#endif | |
38 | 42 | |
39 | -#define CFG_SDRAM_BASE 0x80000000 | |
40 | 43 | |
41 | -#define CFG_MALLOC_LEN 128*1024 | |
44 | +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
42 | 45 | |
43 | -#define CFG_BOOTPARAMS_LEN 128*1024 | |
46 | +#define CONFIG_BAUDRATE 115200 | |
44 | 47 | |
45 | 48 | /* valid baudrates */ |
46 | 49 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
47 | 50 | |
48 | -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_ELF) | |
51 | +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ | |
52 | + | |
53 | +#define CONFIG_PREBOOT "echo;" \ | |
54 | + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ | |
55 | + "echo" | |
56 | + | |
57 | +#undef CONFIG_BOOTARGS | |
58 | + | |
59 | +#define CONFIG_EXTRA_ENV_SETTINGS \ | |
60 | + "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
61 | + "nfsroot=$(serverip):$(rootpath)\0" \ | |
62 | + "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
63 | + "addip=setenv bootargs $(bootargs) " \ | |
64 | + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ | |
65 | + ":$(hostname):$(netdev):off\0" \ | |
66 | + "addmisc=setenv bootargs $(bootargs) " \ | |
67 | + "console=ttyS0,$(baudrate) " \ | |
68 | + "ethaddr=$(ethaddr) " \ | |
69 | + "panic=1\0" \ | |
70 | + "flash_nfs=run nfsargs addip addmisc;" \ | |
71 | + "bootm $(kernel_addr)\0" \ | |
72 | + "flash_self=run ramargs addip addmisc;" \ | |
73 | + "bootm $(kernel_addr) $(ramdisk_addr)\0" \ | |
74 | + "net_nfs=tftp 80500000 $(bootfile);" \ | |
75 | + "run nfsargs addip addmisc;bootm\0" \ | |
76 | + "rootpath=/opt/eldk/mips_4KC\0" \ | |
77 | + "bootfile=/tftpboot/INCA/uImage\0" \ | |
78 | + "kernel_addr=B0040000\0" \ | |
79 | + "ramdisk_addr=B0100000\0" \ | |
80 | + "u-boot=/tftpboot/INCA/u-boot.bin\0" \ | |
81 | + "load=tftp 80500000 $(u-boot)\0" \ | |
82 | + "update=protect off 1:0-2;era 1:0-2;" \ | |
83 | + "cp.b 80500000 B0000000 $(filesize)\0" \ | |
84 | + "" | |
85 | +#define CONFIG_BOOTCOMMAND "run flash_self" | |
86 | + | |
87 | +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ | |
88 | + CFG_CMD_ASKENV | \ | |
89 | + CFG_CMD_DHCP | \ | |
90 | + CFG_CMD_ELF ) | |
49 | 91 | #include <cmd_confdefs.h> |
50 | 92 | |
51 | 93 | /* |
52 | 94 | |
53 | 95 | |
... | ... | @@ -55,12 +97,19 @@ |
55 | 97 | #define CFG_PROMPT "INCA-IP # " /* Monitor Command Prompt */ |
56 | 98 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
57 | 99 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
58 | -#define CFG_HZ (CPU_CLOCK_RATE/2) | |
59 | 100 | #define CFG_MAXARGS 16 /* max number of command args*/ |
60 | 101 | |
102 | +#define CFG_MALLOC_LEN 128*1024 | |
103 | + | |
104 | +#define CFG_BOOTPARAMS_LEN 128*1024 | |
105 | + | |
106 | +#define CFG_HZ (CPU_CLOCK_RATE/2) | |
107 | + | |
108 | +#define CFG_SDRAM_BASE 0x80000000 | |
109 | + | |
61 | 110 | #define CFG_LOAD_ADDR 0x80100000 /* default load address */ |
62 | 111 | |
63 | -#define CFG_MEMTEST_START 0x80200000 | |
112 | +#define CFG_MEMTEST_START 0x80100000 | |
64 | 113 | #define CFG_MEMTEST_END 0x80800000 |
65 | 114 | |
66 | 115 | /*----------------------------------------------------------------------- |
include/configs/innokom.h
... | ... | @@ -62,7 +62,8 @@ |
62 | 62 | #define CONFIG_BAUDRATE 19200 |
63 | 63 | #define CONFIG_MISC_INIT_R 1 /* we have a misc_init_r() function */ |
64 | 64 | |
65 | -#define CONFIG_COMMANDS (CONFIG_CMD_DFL|CFG_CMD_I2C|CFG_CMD_EEPROM|CFG_CMD_NET|CFG_CMD_JFFS2|CFG_CMD_DHCP) | |
65 | +#define CONFIG_COMMANDS (CFG_CMD_BDI|CFG_CMD_LOADB|CFG_CMD_IMI|CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_NET|CFG_CMD_ENV|CFG_CMD_RUN|CFG_CMD_ASKENV|CFG_CMD_ECHO|CFG_CMD_I2C|CFG_CMD_DHCP) | |
66 | +/* CONFIG_CMD_DFL|CFG_CMD_I2C|CFG_CMD_EEPROM|CFG_CMD_NET|CFG_CMD_JFFS2|CFG_CMD_DHCP) */ | |
66 | 67 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
67 | 68 | #include <cmd_confdefs.h> |
68 | 69 | |
... | ... | @@ -78,11 +79,6 @@ |
78 | 79 | |
79 | 80 | #define CONFIG_CMDLINE_TAG 1 |
80 | 81 | |
81 | -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
82 | -#define CONFIG_KGDB_BAUDRATE 19200 /* speed to run kgdb serial port */ | |
83 | -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
84 | -#endif | |
85 | - | |
86 | 82 | /* |
87 | 83 | * Miscellaneous configurable options |
88 | 84 | */ |
... | ... | @@ -186,7 +182,7 @@ |
186 | 182 | |
187 | 183 | |
188 | 184 | /* |
189 | - * GPIO settings; see BDI2000 config file for details | |
185 | + * GPIO settings | |
190 | 186 | * |
191 | 187 | * GP15 == nCS1 is 1 |
192 | 188 | * GP24 == SFRM is 1 |
... | ... | @@ -391,7 +387,7 @@ |
391 | 387 | * [32:26] 0 - reserved |
392 | 388 | * [25] 0 - K2FREE: not free running |
393 | 389 | * [24] 0 - K1FREE: not free running |
394 | - * [23] 0 - K0FREE: not free running | |
390 | + * [23] 1 - K0FREE: not free running | |
395 | 391 | * [22] 0 - SLFRSH: self refresh disabled |
396 | 392 | * [21] 0 - reserved |
397 | 393 | * [20] 0 - APD: no auto power down |
398 | 394 | |
... | ... | @@ -401,11 +397,11 @@ |
401 | 397 | * [16] 1 - K1RUN: enable SDCLK1 |
402 | 398 | * [15] 1 - E1PIN: SDRAM clock enable |
403 | 399 | * [14] 1 - K0DB2: SDCLK0 is MemClk |
404 | - * [13] 1 - K0RUN: disable SDCLK0 | |
400 | + * [13] 0 - K0RUN: disable SDCLK0 | |
405 | 401 | * [12] 1 - E0PIN: disable SDCKE0 |
406 | 402 | * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24 |
407 | 403 | */ |
408 | -#define CFG_MDREFR_VAL 0x0001F018 | |
404 | +#define CFG_MDREFR_VAL 0x0081D018 | |
409 | 405 | |
410 | 406 | /* MDMRS: Mode Register Set Configuration Register |
411 | 407 | * |
include/configs/wepep250.h
1 | +/* | |
2 | + * Copyright (C) 2003 ETC s.r.o. | |
3 | + * | |
4 | + * This program is free software; you can redistribute it and/or | |
5 | + * modify it under the terms of the GNU General Public License as | |
6 | + * published by the Free Software Foundation; either version 2 of | |
7 | + * the License, or (at your option) any later version. | |
8 | + * | |
9 | + * This program is distributed in the hope that it will be useful, | |
10 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | + * GNU General Public License for more details. | |
13 | + * | |
14 | + * You should have received a copy of the GNU General Public License | |
15 | + * along with this program; if not, write to the Free Software | |
16 | + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
17 | + * MA 02111-1307 USA | |
18 | + * | |
19 | + * Written by Peter Figuli <peposh@etc.sk>, 2003. | |
20 | + * | |
21 | + */ | |
22 | + | |
23 | +#ifndef __CONFIG_H | |
24 | +#define __CONFIG_H | |
25 | + | |
26 | +#define CONFIG_PXA250 1 /* this is an PXA250 CPU */ | |
27 | +#define CONFIG_WEPEP250 1 /* config for wepep250 board */ | |
28 | +#undef CONFIG_USE_IRQ /* don't need use IRQ/FIQ */ | |
29 | + | |
30 | + | |
31 | +/* | |
32 | + * Select serial console configuration | |
33 | + */ | |
34 | +#define CONFIG_BTUART 1 /* BTUART is default on WEP dev board */ | |
35 | +#define CONFIG_BAUDRATE 115200 | |
36 | + | |
37 | + | |
38 | +/* | |
39 | + * Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if | |
40 | + * neccessary in include/cmd_confdefs.h file. (Un)comment for getting | |
41 | + * functionality or size of u-boot code. | |
42 | + */ | |
43 | +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | |
44 | + & ~CFG_CMD_NET \ | |
45 | + & ~CFG_CMD_LOADS \ | |
46 | + & ~CFG_CMD_CONSOLE \ | |
47 | + & ~CFG_CMD_AUTOSCRIPT \ | |
48 | +/* | CFG_CMD_JFFS2 */ \ | |
49 | + ) | |
50 | +#include <cmd_confdefs.h> | |
51 | + | |
52 | +/* | |
53 | + * Boot options. Setting delay to -1 stops autostart count down. | |
54 | + * NOTE: Sending parameters to kernel depends on kernel version and | |
55 | + * 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept | |
56 | + * parameters at all! Do not get confused by them so. | |
57 | + */ | |
58 | +#define CONFIG_BOOTDELAY -1 | |
59 | +#define CONFIG_BOOTARGS "root=/dev/mtdblock2 mem=32m console=ttyS01,115200n8" | |
60 | +#define CONFIG_BOOTCOMMAND "bootm 40000" | |
61 | + | |
62 | + | |
63 | +/* | |
64 | + * General options for u-boot. Modify to save memory foot print | |
65 | + */ | |
66 | +#define CFG_LONGHELP /* undef saves memory */ | |
67 | +#define CFG_PROMPT "WEP> " /* prompt string */ | |
68 | +#define CFG_CBSIZE 256 /* console I/O buffer */ | |
69 | +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer size */ | |
70 | +#define CFG_MAXARGS 16 /* max command args */ | |
71 | +#define CFG_BARGSIZE CFG_CBSIZE /* boot args buf size */ | |
72 | + | |
73 | +#define CFG_MEMTEST_START 0xa0400000 /* memtest test area */ | |
74 | +#define CFG_MEMTEST_END 0xa0800000 | |
75 | + | |
76 | +#undef CFG_CLKS_IN_HZ /* use HZ for freq. display */ | |
77 | + | |
78 | +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ | |
79 | +#define CFG_CPUSPEED 0x141 /* core clock - register value */ | |
80 | + | |
81 | +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
82 | + | |
83 | +/* | |
84 | + * Definitions related to passing arguments to kernel. | |
85 | + */ | |
86 | +#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */ | |
87 | +#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */ | |
88 | +#undef CONFIG_INITRD_TAG /* do not send initrd params */ | |
89 | +#undef CONFIG_VFD /* do not send framebuffer setup */ | |
90 | + | |
91 | + | |
92 | +/* | |
93 | + * Malloc pool need to host env + 128 Kb reserve for other allocations. | |
94 | + */ | |
95 | +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + (128<<10) ) | |
96 | + | |
97 | +#define CONFIG_STACKSIZE (120<<10) /* stack size */ | |
98 | + | |
99 | +#ifdef CONFIG_USE_IRQ | |
100 | +#define CONFIG_STACKSIZE_IRQ (4<<10) /* IRQ stack */ | |
101 | +#define CONFIG_STACKSIZE_FIQ (4<<10) /* FIQ stack */ | |
102 | +#endif | |
103 | + | |
104 | +/* | |
105 | + * SDRAM Memory Map | |
106 | + */ | |
107 | +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */ | |
108 | +#define WEP_SDRAM_1 0xa0000000 /* SDRAM bank #1 */ | |
109 | +#define WEP_SDRAM_1_SIZE 0x02000000 /* 32 MB ( 2 chip ) */ | |
110 | +#define WEP_SDRAM_2 0xa2000000 /* SDRAM bank #2 */ | |
111 | +#define WEP_SDRAM_2_SIZE 0x00000000 /* 0 MB */ | |
112 | +#define WEP_SDRAM_3 0xa8000000 /* SDRAM bank #3 */ | |
113 | +#define WEP_SDRAM_3_SIZE 0x00000000 /* 0 MB */ | |
114 | +#define WEP_SDRAM_4 0xac000000 /* SDRAM bank #4 */ | |
115 | +#define WEP_SDRAM_4_SIZE 0x00000000 /* 0 MB */ | |
116 | + | |
117 | +#define CFG_DRAM_BASE 0xa0000000 | |
118 | +#define CFG_DRAM_SIZE 0x02000000 | |
119 | + | |
120 | +/* Uncomment used SDRAM chip */ | |
121 | +#define WEP_SDRAM_K4S281633 | |
122 | +/*#define WEP_SDRAM_K4S561633*/ | |
123 | + | |
124 | + | |
125 | +/* | |
126 | + * Configuration for FLASH memory | |
127 | + */ | |
128 | +#define CFG_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/ | |
129 | +#define CFG_MAX_FLASH_SECT 128 /* number of sector in FLASH bank */ | |
130 | +#define WEP_FLASH_BUS_WIDTH 4 /* we use 32 bit FLASH memory... */ | |
131 | +#define WEP_FLASH_INTERLEAVE 2 /* ... made of 2 chips */ | |
132 | +#define WEP_FLASH_BANK_SIZE 0x2000000 /* size of one flash bank*/ | |
133 | +#define WEP_FLASH_SECT_SIZE 0x0040000 /* size of erase sector */ | |
134 | +#define WEP_FLASH_BASE 0x0000000 /* location of flash memory */ | |
135 | +#define WEP_FLASH_UNLOCK 1 /* perform hw unlock first */ | |
136 | + | |
137 | + | |
138 | +/* This should be defined if CFI FLASH device is present. Actually benefit | |
139 | + is not so clear to me. In other words we can provide more informations | |
140 | + to user, but this expects more complex flash handling we do not provide | |
141 | + now.*/ | |
142 | +#undef CFG_FLASH_CFI | |
143 | + | |
144 | +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* timeout for Erase operation */ | |
145 | +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* timeout for Write operation */ | |
146 | + | |
147 | +#define CFG_FLASH_BASE WEP_FLASH_BASE | |
148 | + | |
149 | +/* | |
150 | + * This is setting for JFFS2 support in u-boot. | |
151 | + * Right now there is no gain for user, but later on booting kernel might be | |
152 | + * possible. Consider using XIP kernel running from flash to save RAM | |
153 | + * footprint. | |
154 | + * NOTE: Enable CFG_CMD_JFFS2 for JFFS2 support. | |
155 | + */ | |
156 | +#define CFG_JFFS2_FIRST_BANK 0 | |
157 | +#define CFG_JFFS2_FIRST_SECTOR 5 | |
158 | +#define CFG_JFFS2_NUM_BANKS 1 | |
159 | + | |
160 | +/* | |
161 | + * Environment setup. Definitions of monitor location and size with | |
162 | + * definition of environment setup ends up in 2 possibilities. | |
163 | + * 1. Embeded environment - in u-boot code is space for environment | |
164 | + * 2. Environment is read from predefined sector of flash | |
165 | + * Right now we support 2. possiblity, but expecting no env placed | |
166 | + * on mentioned address right now. This also needs to provide whole | |
167 | + * sector for it - for us 256Kb is really waste of memory. U-boot uses | |
168 | + * default env. and until kernel parameters could be sent to kernel | |
169 | + * env. has no sense to us. | |
170 | + */ | |
171 | + | |
172 | +#define CFG_MONITOR_BASE PHYS_FLASH_1 | |
173 | +#define CFG_MONITOR_LEN 0x20000 /* 128kb ( 1 flash sector ) */ | |
174 | +#define CFG_ENV_IS_IN_FLASH 1 | |
175 | +#define CFG_ENV_ADDR 0x20000 /* absolute address for now */ | |
176 | +#define CFG_ENV_SIZE 0x2000 | |
177 | + | |
178 | +#undef CONFIG_ENV_OVERWRITE /* env is not writable now */ | |
179 | + | |
180 | +/* | |
181 | + * Well this has to be defined, but on the other hand it is used differently | |
182 | + * one may expect. For instance loadb command do not cares :-) | |
183 | + * So advice is - do not relay on this... | |
184 | + */ | |
185 | +#define CFG_LOAD_ADDR 0x40000 | |
186 | + | |
187 | +#endif /* __CONFIG_H */ |
lib_arm/board.c
... | ... | @@ -190,6 +190,7 @@ |
190 | 190 | gd_t gd_data; |
191 | 191 | bd_t bd_data; |
192 | 192 | init_fnc_t **init_fnc_ptr; |
193 | + char *s; | |
193 | 194 | #if defined(CONFIG_VFD) |
194 | 195 | unsigned long addr; |
195 | 196 | #endif |
... | ... | @@ -273,6 +274,16 @@ |
273 | 274 | #ifdef CONFIG_DRIVER_CS8900 |
274 | 275 | cs8900_get_enetaddr (gd->bd->bi_enetaddr); |
275 | 276 | #endif |
277 | + | |
278 | + /* Initialize from environment */ | |
279 | + if ((s = getenv ("loadaddr")) != NULL) { | |
280 | + load_addr = simple_strtoul (s, NULL, 16); | |
281 | + } | |
282 | +#if (CONFIG_COMMANDS & CFG_CMD_NET) | |
283 | + if ((s = getenv ("bootfile")) != NULL) { | |
284 | + copy_filename (BootFile, s, sizeof (BootFile)); | |
285 | + } | |
286 | +#endif /* CFG_CMD_NET */ | |
276 | 287 | |
277 | 288 | #ifdef BOARD_POST_INIT |
278 | 289 | board_post_init (); |
lib_mips/board.c
... | ... | @@ -177,6 +177,9 @@ |
177 | 177 | bd_t *bd; |
178 | 178 | init_fnc_t **init_fnc_ptr; |
179 | 179 | ulong addr, addr_sp, len = CFG_MONITOR_LEN; |
180 | +#ifdef CONFIG_PURPLE | |
181 | + void copy_code (ulong); | |
182 | +#endif | |
180 | 183 | |
181 | 184 | /* Pointer is writable since we allocated a register for it. |
182 | 185 | */ |
... | ... | @@ -271,6 +274,14 @@ |
271 | 274 | bd->bi_baudrate = gd->baudrate; /* Console Baudrate */ |
272 | 275 | |
273 | 276 | memcpy (id, gd, sizeof (gd_t)); |
277 | + | |
278 | + /* On the purple board we copy the code in a special way | |
279 | + * in order to solve flash problems | |
280 | + */ | |
281 | +#ifdef CONFIG_PURPLE | |
282 | + copy_code(addr); | |
283 | +#endif | |
284 | + | |
274 | 285 | relocate_code (addr_sp, id, addr); |
275 | 286 | |
276 | 287 | /* NOTREACHED - relocate_code() does not return */ |
... | ... | @@ -382,6 +393,21 @@ |
382 | 393 | /* Initialize the console (after the relocation and devices init) */ |
383 | 394 | console_init_r (); |
384 | 395 | /** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** **/ |
396 | + | |
397 | + /* Initialize from environment */ | |
398 | + if ((s = getenv ("loadaddr")) != NULL) { | |
399 | + load_addr = simple_strtoul (s, NULL, 16); | |
400 | + } | |
401 | +#if (CONFIG_COMMANDS & CFG_CMD_NET) | |
402 | + if ((s = getenv ("bootfile")) != NULL) { | |
403 | + copy_filename (BootFile, s, sizeof (BootFile)); | |
404 | + } | |
405 | +#endif /* CFG_CMD_NET */ | |
406 | + | |
407 | +#if defined(CONFIG_MISC_INIT_R) | |
408 | + /* miscellaneous platform dependent initialisations */ | |
409 | + misc_init_r (); | |
410 | +#endif | |
385 | 411 | |
386 | 412 | #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) |
387 | 413 | puts ("Net: "); |
net/bootp.c
... | ... | @@ -59,7 +59,8 @@ |
59 | 59 | static void DhcpHandler(uchar * pkt, unsigned dest, unsigned src, unsigned len); |
60 | 60 | |
61 | 61 | /* For Debug */ |
62 | -char *dhcpmsg2str(int type) | |
62 | +#if 0 | |
63 | +static char *dhcpmsg2str(int type) | |
63 | 64 | { |
64 | 65 | switch (type) { |
65 | 66 | case 1: return "DHCPDISCOVER"; break; |
... | ... | @@ -72,6 +73,7 @@ |
72 | 73 | default: return "UNKNOWN/INVALID MSG TYPE"; break; |
73 | 74 | } |
74 | 75 | } |
76 | +#endif | |
75 | 77 | |
76 | 78 | #if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_VENDOREX) |
77 | 79 | extern u8 *dhcp_vendorex_prep (u8 *e); /*rtn new e after add own opts. */ |
... | ... | @@ -112,7 +114,7 @@ |
112 | 114 | /* |
113 | 115 | * Copy parameters of interest from BOOTP_REPLY/DHCP_OFFER packet |
114 | 116 | */ |
115 | -void BootpCopyNetParams(Bootp_t *bp) | |
117 | +static void BootpCopyNetParams(Bootp_t *bp) | |
116 | 118 | { |
117 | 119 | NetCopyIP(&NetOurIP, &bp->bp_yiaddr); |
118 | 120 | NetCopyIP(&NetServerIP, &bp->bp_siaddr); |
119 | 121 | |
... | ... | @@ -675,9 +677,9 @@ |
675 | 677 | } |
676 | 678 | |
677 | 679 | #if (CONFIG_COMMANDS & CFG_CMD_DHCP) |
678 | -void DhcpOptionsProcess(char *popt) | |
680 | +static void DhcpOptionsProcess(uchar *popt) | |
679 | 681 | { |
680 | - char *end = popt + BOOTP_HDR_SIZE; | |
682 | + uchar *end = popt + BOOTP_HDR_SIZE; | |
681 | 683 | int oplen, size; |
682 | 684 | |
683 | 685 | while ( popt < end && *popt != 0xff ) { |
... | ... | @@ -747,7 +749,7 @@ |
747 | 749 | return -1; |
748 | 750 | } |
749 | 751 | |
750 | -void DhcpSendRequestPkt(Bootp_t *bp_offer) | |
752 | +static void DhcpSendRequestPkt(Bootp_t *bp_offer) | |
751 | 753 | { |
752 | 754 | volatile uchar *pkt, *iphdr; |
753 | 755 | Bootp_t *bp; |
net/eth.c
... | ... | @@ -40,6 +40,7 @@ |
40 | 40 | extern int fec_initialize(bd_t*); |
41 | 41 | extern int scc_initialize(bd_t*); |
42 | 42 | extern int inca_switch_initialize(bd_t*); |
43 | +extern int plb2800_eth_initialize(bd_t*); | |
43 | 44 | |
44 | 45 | static struct eth_device *eth_devices, *eth_current; |
45 | 46 | |
... | ... | @@ -98,6 +99,9 @@ |
98 | 99 | |
99 | 100 | #ifdef CONFIG_INCA_IP_SWITCH |
100 | 101 | inca_switch_initialize(bis); |
102 | +#endif | |
103 | +#ifdef CONFIG_PLB2800_ETHER | |
104 | + plb2800_eth_initialize(bis); | |
101 | 105 | #endif |
102 | 106 | #ifdef CONFIG_EEPRO100 |
103 | 107 | eepro100_initialize(bis); |
tools/Makefile
... | ... | @@ -25,6 +25,11 @@ |
25 | 25 | |
26 | 26 | OBJS = environment.o img2srec.o mkimage.o crc32.o envcrc.o gen_eth_addr.o bmp_logo.o |
27 | 27 | |
28 | +ifeq ($(ARCH),mips) | |
29 | +BINS += inca-swap-bytes$(SFX) | |
30 | +OBJS += inca-swap-bytes.o | |
31 | +endif | |
32 | + | |
28 | 33 | LOGO_H = $(TOPDIR)/include/bmp_logo.h |
29 | 34 | |
30 | 35 | ifeq ($(LOGO_BMP),) |
... | ... | @@ -133,6 +138,10 @@ |
133 | 138 | $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^ |
134 | 139 | $(STRIP) $@ |
135 | 140 | |
141 | +inca-swap-bytes$(SFX): inca-swap-bytes.o | |
142 | + $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^ | |
143 | + $(STRIP) $@ | |
144 | + | |
136 | 145 | envcrc.o: envcrc.c |
137 | 146 | $(CC) -g $(CFLAGS) -c $< |
138 | 147 | |
... | ... | @@ -143,6 +152,9 @@ |
143 | 152 | $(CC) -g $(CFLAGS) -c $< |
144 | 153 | |
145 | 154 | gen_eth_addr.o: gen_eth_addr.c |
155 | + $(CC) -g $(CFLAGS) -c $< | |
156 | + | |
157 | +inca-swap-bytes.o: inca-swap-bytes.c | |
146 | 158 | $(CC) -g $(CFLAGS) -c $< |
147 | 159 | |
148 | 160 | subdirs: |
tools/inca-swap-bytes.c
1 | +#include <stdio.h> | |
2 | +#include <stdlib.h> | |
3 | +#include <string.h> | |
4 | +#include <unistd.h> | |
5 | + | |
6 | +#ifndef BUFSIZ | |
7 | +# define BUFSIZ 4096 | |
8 | +#endif | |
9 | + | |
10 | +#undef BUFSIZ | |
11 | +# define BUFSIZ 64 | |
12 | +int main (void) | |
13 | +{ | |
14 | + short ibuff[BUFSIZ], obuff[BUFSIZ]; | |
15 | + int rc, i, len; | |
16 | + | |
17 | + while ((rc = read (0, ibuff, sizeof (ibuff))) > 0) { | |
18 | + memset (obuff, 0, sizeof (obuff)); | |
19 | + for (i = 0; i < (rc + 1) / 2; i++) { | |
20 | + obuff[i] = ibuff[i ^ 1]; | |
21 | + } | |
22 | + | |
23 | + len = (rc + 1) & ~1; | |
24 | + | |
25 | + if (write (1, obuff, len) != len) { | |
26 | + perror ("read error"); | |
27 | + return (EXIT_FAILURE); | |
28 | + } | |
29 | + | |
30 | + memset (ibuff, 0, sizeof (ibuff)); | |
31 | + } | |
32 | + | |
33 | + if (rc < 0) { | |
34 | + perror ("read error"); | |
35 | + return (EXIT_FAILURE); | |
36 | + } | |
37 | + return (EXIT_SUCCESS); | |
38 | +} |