Eric Lee / smarc-uboot

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Commit 3eace37e5098c7f020a45a3672c062cd4ea199a0

Authored by Simon Glass
Committed by Tom Rini
1 parent 6bacc73621
Exists in smarc_8mq_lf_v2020.04 and in 17 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

arm: freescale: Rename initdram() to fsl_initdram() 

This function name shadows a global name but is in fact different. This
is very confusing. Rename it to help with the following refactoring.

Signed-off-by: Simon Glass <sjg@chromium.org>

Showing 13 changed files with 24 additions and 12 deletions Side-by-side Diff

arch/arm/cpu/armv8/fsl-layerscape/cpu.c
Diff comments   View file @ 3eace37
... ... @@ -5,6 +5,7 @@
5 5 */
6 6  
7 7 #include <common.h>
  8 +#include <fsl_ddr_sdram.h>
8 9 #include <asm/io.h>
9 10 #include <linux/errno.h>
10 11 #include <asm/system.h>
... ... @@ -876,7 +877,7 @@
876 877  
877 878 __weak int dram_init(void)
878 879 {
879   - initdram();
  880 + fsl_initdram();
880 881 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
881 882 /* This will break-before-make MMU for DDR */
882 883 update_early_mmu_table();
board/freescale/ls1021aqds/ddr.c
Diff comments   View file @ 3eace37
... ... @@ -164,7 +164,7 @@
164 164 }
165 165 #endif
166 166  
167   -int initdram(void)
  167 +int fsl_initdram(void)
168 168 {
169 169 phys_size_t dram_size;
170 170  
board/freescale/ls1021aqds/ls1021aqds.c
Diff comments   View file @ 3eace37
... ... @@ -162,7 +162,7 @@
162 162 * before accessing DDR SPD.
163 163 */
164 164 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
165   - return initdram();
  165 + return fsl_initdram();
166 166 }
167 167  
168 168 #ifdef CONFIG_FSL_ESDHC
board/freescale/ls1043aqds/ddr.c
Diff comments   View file @ 3eace37
... ... @@ -108,7 +108,7 @@
108 108 #endif
109 109 }
110 110  
111   -int initdram(void)
  111 +int fsl_initdram(void)
112 112 {
113 113 phys_size_t dram_size;
114 114  
board/freescale/ls1043aqds/ls1043aqds.c
Diff comments   View file @ 3eace37
... ... @@ -7,6 +7,7 @@
7 7 #include <common.h>
8 8 #include <i2c.h>
9 9 #include <fdt_support.h>
  10 +#include <fsl_ddr_sdram.h>
10 11 #include <asm/io.h>
11 12 #include <asm/arch/clock.h>
12 13 #include <asm/arch/fsl_serdes.h>
... ... @@ -153,7 +154,7 @@
153 154 * before accessing DDR SPD.
154 155 */
155 156 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
156   - initdram();
  157 + fsl_initdram();
157 158 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
158 159 /* This will break-before-make MMU for DDR */
159 160 update_early_mmu_table();
board/freescale/ls1043ardb/ddr.c
Diff comments   View file @ 3eace37
... ... @@ -170,7 +170,7 @@
170 170 }
171 171 #endif
172 172  
173   -int initdram(void)
  173 +int fsl_initdram(void)
174 174 {
175 175 phys_size_t dram_size;
176 176  
board/freescale/ls1046aqds/ddr.c
Diff comments   View file @ 3eace37
... ... @@ -92,7 +92,7 @@
92 92 popts->cpo_sample = 0x70;
93 93 }
94 94  
95   -int initdram(void)
  95 +int fsl_initdram(void)
96 96 {
97 97 phys_size_t dram_size;
98 98  
board/freescale/ls1046aqds/ls1046aqds.c
Diff comments   View file @ 3eace37
... ... @@ -7,6 +7,7 @@
7 7 #include <common.h>
8 8 #include <i2c.h>
9 9 #include <fdt_support.h>
  10 +#include <fsl_ddr_sdram.h>
10 11 #include <asm/io.h>
11 12 #include <asm/arch/clock.h>
12 13 #include <asm/arch/fsl_serdes.h>
... ... @@ -149,7 +150,7 @@
149 150 * before accessing DDR SPD.
150 151 */
151 152 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
152   - initdram();
  153 + fsl_initdram();
153 154 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
154 155 /* This will break-before-make MMU for DDR */
155 156 update_early_mmu_table();
board/freescale/ls1046ardb/ddr.c
Diff comments   View file @ 3eace37
... ... @@ -96,7 +96,7 @@
96 96 popts->cpo_sample = 0x70;
97 97 }
98 98  
99   -int initdram(void)
  99 +int fsl_initdram(void)
100 100 {
101 101 phys_size_t dram_size;
102 102  
board/freescale/ls2080a/ddr.c
Diff comments   View file @ 3eace37
... ... @@ -158,7 +158,8 @@
158 158 return 0;
159 159 }
160 160 #endif
161   -int initdram(void)
  161 +
  162 +int fsl_initdram(void)
162 163 {
163 164 puts("Initializing DDR....");
164 165  
board/freescale/ls2080aqds/ddr.c
Diff comments   View file @ 3eace37
... ... @@ -155,7 +155,7 @@
155 155 }
156 156 }
157 157  
158   -int initdram(void)
  158 +int fsl_initdram(void)
159 159 {
160 160 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
161 161 gd->ram_size = fsl_ddr_sdram_size();
board/freescale/ls2080ardb/ddr.c
Diff comments   View file @ 3eace37
... ... @@ -158,7 +158,7 @@
158 158 }
159 159 }
160 160  
161   -int initdram(void)
  161 +int fsl_initdram(void)
162 162 {
163 163 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
164 164 gd->ram_size = fsl_ddr_sdram_size();
include/fsl_ddr_sdram.h
Diff comments   View file @ 3eace37
... ... @@ -477,5 +477,13 @@
477 477 int max_freq;
478 478 fsl_ddr_cfg_regs_t *ddr_settings;
479 479 } fixed_ddr_parm_t;
  480 +
  481 +/**
  482 + * fsl_initdram() - Set up the SDRAM
  483 + *
  484 + * @return 0 if OK, -ve on error
  485 + */
  486 +int fsl_initdram(void);
  487 +
480 488 #endif