Commit 3ef2412de6680c751abd39047cadff7e052a0f51
Committed by
York Sun
York Sun
1 parent
e5d08b4d60
Exists in
v2017.01-smarct4x
and in
31 other branches
drivers/crypto/fsl: fix snooping for write transactions
HW coherency won't work properly for CAAM write transactions if AWCACHE is left to default (POR) value - 4'b0001. It has to be programmed to 4'b0010. For platforms that have HW coherency support: -PPC-based: the update has no effect; CAAM coherency already works due to the IOMMU (PAMU) driver setting the correct memory coherency attributes -ARM-based: the update fixes cache coherency issues, since IOMMU (SMMU) driver is not programmed to behave similar to PAMU Fixes: b9eebfade974c ("fsl_sec: Add hardware accelerated SHA256 and SHA1") Signed-off-by: Horia Geantă <horia.geanta@freescale.com> Reviewed-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com> Acked-by: Ruchika Gupta<ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Showing 2 changed files with 8 additions and 4 deletions Side-by-side Diff
drivers/crypto/fsl/jr.c
| ... | ... | @@ -468,14 +468,16 @@ |
| 468 | 468 | |
| 469 | 469 | int sec_init(void) |
| 470 | 470 | { |
| 471 | - int ret = 0; | |
| 472 | - | |
| 473 | -#ifdef CONFIG_PHYS_64BIT | |
| 474 | 471 | ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; |
| 475 | 472 | uint32_t mcr = sec_in32(&sec->mcfgr); |
| 473 | + int ret = 0; | |
| 476 | 474 | |
| 477 | - sec_out32(&sec->mcfgr, mcr | 1 << MCFGR_PS_SHIFT); | |
| 475 | + mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT); | |
| 476 | +#ifdef CONFIG_PHYS_64BIT | |
| 477 | + mcr |= (1 << MCFGR_PS_SHIFT); | |
| 478 | 478 | #endif |
| 479 | + sec_out32(&sec->mcfgr, mcr); | |
| 480 | + | |
| 479 | 481 | ret = jr_init(); |
| 480 | 482 | if (ret < 0) { |
| 481 | 483 | printf("SEC initialization failed\n"); |
drivers/crypto/fsl/jr.h
| ... | ... | @@ -21,6 +21,8 @@ |
| 21 | 21 | #define MCFGR_SWRST ((uint32_t)(1)<<31) /* Software Reset */ |
| 22 | 22 | #define MCFGR_DMA_RST ((uint32_t)(1)<<28) /* DMA Reset */ |
| 23 | 23 | #define MCFGR_PS_SHIFT 16 |
| 24 | +#define MCFGR_AWCACHE_SHIFT 8 | |
| 25 | +#define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT) | |
| 24 | 26 | #define JR_INTMASK 0x00000001 |
| 25 | 27 | #define JRCR_RESET 0x01 |
| 26 | 28 | #define JRINT_ERR_HALT_INPROGRESS 0x4 |