mx6sabreauto: Make Ethernet functional again

Since commit ce412b79e7255770 ("drivers: net: phy: atheros: add separate config for AR8031") Ethernet does not work on mx6sabreauto. This commit correctly assigns ar8031_config() as the configuration function for AR8031 in the same way as done in the Linux kernel. However, on mx6sabreauto design we need some additional configurations, such as enabling the 125 MHz AR8031 output and setting the TX clock delay that need to be done in the board file. This is the equivalent fix from commit 4b6035da482c ("mx6sabresd: Make Ethernet functional again"). Reported-by: Miquel RAYNAL <miquel.raynal@free-electrons.com> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>

mx6sabreauto: Make Ethernet functional again
Since commit ce412b79e7255770 ("drivers: net: phy: atheros: add separate config for AR8031") Ethernet does not work on mx6sabreauto. This commit correctly assigns ar8031_config() as the configuration function for AR8031 in the same way as done in the Linux kernel. However, on mx6sabreauto design we need some additional configurations, such as enabling the 125 MHz AR8031 output and setting the TX clock delay that need to be done in the board file. This is the equivalent fix from commit 4b6035da482c ("mx6sabresd: Make Ethernet functional again"). Reported-by: Miquel RAYNAL <miquel.raynal@free-electrons.com> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Fabio Estevam · Stefano Babic
1 parent bc104a7066
Showing 1 changed file with 33 additions and 0 deletions Side-by-side Diff
board/freescale/mx6sabreauto/mx6sabreauto.c
@@ -433,6 +433,39 @@
 	return (get_cpu_rev() & ~(0xF << 8)) | rev;
 }
  
+static int ar8031_phy_fixup(struct phy_device *phydev)
+{
+	unsigned short val;
+
+	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+	val &= 0xffe3;
+	val |= 0x18;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+	/* introduce tx clock delay */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+	val |= 0x0100;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	ar8031_phy_fixup(phydev);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
 #if defined(CONFIG_VIDEO_IPUV3)
 static void disable_lvds(struct display_info_t const *dev)
 {
...	...	@@ -433,6 +433,39 @@
433	433	return (get_cpu_rev() & ~(0xF << 8)) \| rev;
434	434	}
435	435
	436	+static int ar8031_phy_fixup(struct phy_device *phydev)
	437	+{
	438	+ unsigned short val;
	439	+
	440	+ /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
	441	+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
	442	+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
	443	+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
	444	+
	445	+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
	446	+ val &= 0xffe3;
	447	+ val \|= 0x18;
	448	+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
	449	+
	450	+ /* introduce tx clock delay */
	451	+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
	452	+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
	453	+ val \|= 0x0100;
	454	+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
	455	+
	456	+ return 0;
	457	+}
	458	+
	459	+int board_phy_config(struct phy_device *phydev)
	460	+{
	461	+ ar8031_phy_fixup(phydev);
	462	+
	463	+ if (phydev->drv->config)
	464	+ phydev->drv->config(phydev);
	465	+
	466	+ return 0;
	467	+}
	468	+
436	469	#if defined(CONFIG_VIDEO_IPUV3)
437	470	static void disable_lvds(struct display_info_t const *dev)
438	471	{