Merge branch 'master' of git://git.denx.de/u-boot-arm

Tom Rini
2 parents 622da1c36a b939689c7b
Showing 8 changed files Side-by-side Diff
arch/arm/cpu/armv7/cache_v7.c
arch/arm/include/asm/armv7.h
arch/arm/include/asm/bitops.h
arch/arm/include/asm/macro.h
arch/arm/include/asm/system.h
arch/arm/lib/cache-cp15.c
drivers/serial/arm_dcc.c
include/configs/zynq-common.h
@@ -68,7 +68,7 @@
 		}
 	}
 	/* DSB to make sure the operation is complete */
-	CP15DSB;
+	DSB;
 }
  
 static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
@@ -96,7 +96,7 @@
 		}
 	}
 	/* DSB to make sure the operation is complete */
-	CP15DSB;
+	DSB;
 }
  
 static void v7_maint_dcache_level_setway(u32 level, u32 operation)
@@ -215,7 +215,7 @@
 	}
  
 	/* DSB to make sure the operation is complete */
-	CP15DSB;
+	DSB;
 }
  
 /* Invalidate TLB */
  
@@ -228,9 +228,9 @@
 	/* Invalidate entire instruction TLB */
 	asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0));
 	/* Full system DSB - make sure that the invalidation is complete */
-	CP15DSB;
+	DSB;
 	/* Full system ISB - make sure the instruction stream sees it */
-	CP15ISB;
+	ISB;
 }
  
 void invalidate_dcache_all(void)
  
@@ -343,10 +343,10 @@
 	asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
  
 	/* Full system DSB - make sure that the invalidation is complete */
-	CP15DSB;
+	DSB;
  
 	/* ISB - make sure the instruction stream sees it */
-	CP15ISB;
+	ISB;
 }
 #else
 void invalidate_icache_all(void)
@@ -70,6 +70,16 @@
 #define CP15DSB	asm volatile ("mcr     p15, 0, %0, c7, c10, 4" : : "r" (0))
 #define CP15DMB	asm volatile ("mcr     p15, 0, %0, c7, c10, 5" : : "r" (0))
  
+#ifdef __ARM_ARCH_7A__
+#define ISB	asm volatile ("isb" : : : "memory")
+#define DSB	asm volatile ("dsb" : : : "memory")
+#define DMB	asm volatile ("dmb" : : : "memory")
+#else
+#define ISB	CP15ISB
+#define DSB	CP15DSB
+#define DMB	CP15DMB
+#endif
+
 /*
  * Workaround for ARM errata # 798870
  * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
@@ -95,9 +95,6 @@
 	return (old & mask) != 0;
 }
  
-extern int find_first_zero_bit(void * addr, unsigned size);
-extern int find_next_zero_bit(void * addr, int size, int offset);
-
 /*
  * This routine doesn't need to be atomic.
  */
@@ -129,6 +126,43 @@
 	return k;
 }
  
+static inline int find_next_zero_bit(void *addr, int size, int offset)
+{
+	unsigned long *p = ((unsigned long *)addr) + (offset >> 5);
+	unsigned long result = offset & ~31UL;
+	unsigned long tmp;
+
+	if (offset >= size)
+		return size;
+	size -= result;
+	offset &= 31UL;
+	if (offset) {
+		tmp = *(p++);
+		tmp |= ~0UL >> (32-offset);
+		if (size < 32)
+			goto found_first;
+		if (~tmp)
+			goto found_middle;
+		size -= 32;
+		result += 32;
+	}
+	while (size & ~31UL) {
+		tmp = *(p++);
+		if (~tmp)
+			goto found_middle;
+		result += 32;
+		size -= 32;
+	}
+	if (!size)
+		return result;
+	tmp = *p;
+
+found_first:
+	tmp |= ~0UL >> size;
+found_middle:
+	return result + ffz(tmp);
+}
+
 /*
  * hweightN: returns the hamming weight (i.e. the number
  * of bits set) of a N-bit word
@@ -137,6 +171,9 @@
 #define hweight32(x) generic_hweight32(x)
 #define hweight16(x) generic_hweight16(x)
 #define hweight8(x) generic_hweight8(x)
+
+#define find_first_zero_bit(addr, size) \
+	find_next_zero_bit((addr), (size), 0)
  
 #define ext2_set_bit			test_and_set_bit
 #define ext2_clear_bit			test_and_clear_bit
@@ -143,6 +143,9 @@
 	mov	\xreg1, #0x33ff
 	msr	cptr_el2, \xreg1	/* Disable coprocessor traps to EL2 */
  
+	/* Initialize Generic Timers */
+	msr	cntvoff_el2, xzr
+
 	/* Initialize SCTLR_EL2
 	 *
 	 * setting RES1 bits (29,28,23,22,18,16,11,5,4) to 1
@@ -196,19 +196,56 @@
 	isb();
 }
  
+#ifdef CONFIG_ARMV7
+/* Short-Descriptor Translation Table Level 1 Bits */
+#define TTB_SECT_NS_MASK	(1 << 19)
+#define TTB_SECT_NG_MASK	(1 << 17)
+#define TTB_SECT_S_MASK		(1 << 16)
+/* Note: TTB AP bits are set elsewhere */
+#define TTB_SECT_TEX(x)		((x & 0x7) << 12)
+#define TTB_SECT_DOMAIN(x)	((x & 0xf) << 5)
+#define TTB_SECT_XN_MASK	(1 << 4)
+#define TTB_SECT_C_MASK		(1 << 3)
+#define TTB_SECT_B_MASK		(1 << 2)
+#define TTB_SECT			(2 << 0)
+
 /* options available for data cache on each page */
 enum dcache_option {
+	DCACHE_OFF = TTB_SECT_S_MASK | TTB_SECT_DOMAIN(0) |
+					TTB_SECT_XN_MASK | TTB_SECT,
+	DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK,
+	DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK,
+	DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1),
+};
+#else
+/* options available for data cache on each page */
+enum dcache_option {
 	DCACHE_OFF = 0x12,
 	DCACHE_WRITETHROUGH = 0x1a,
 	DCACHE_WRITEBACK = 0x1e,
 	DCACHE_WRITEALLOC = 0x16,
 };
+#endif
  
 /* Size of an MMU section */
 enum {
 	MMU_SECTION_SHIFT	= 20,
 	MMU_SECTION_SIZE	= 1 << MMU_SECTION_SHIFT,
 };
+
+#ifdef CONFIG_ARMV7
+/* TTBR0 bits */
+#define TTBR0_BASE_ADDR_MASK	0xFFFFC000
+#define TTBR0_RGN_NC			(0 << 3)
+#define TTBR0_RGN_WBWA			(1 << 3)
+#define TTBR0_RGN_WT			(2 << 3)
+#define TTBR0_RGN_WB			(3 << 3)
+/* TTBR0[6] is IRGN[0] and TTBR[0] is IRGN[1] */
+#define TTBR0_IRGN_NC			(0 << 0 | 0 << 6)
+#define TTBR0_IRGN_WBWA			(0 << 0 | 1 << 6)
+#define TTBR0_IRGN_WT			(1 << 0 | 0 << 6)
+#define TTBR0_IRGN_WB			(1 << 0 | 1 << 6)
+#endif
  
 /**
  * Change the cache settings for a region.
@@ -96,9 +96,23 @@
 		dram_bank_mmu_setup(i);
 	}
  
+#ifdef CONFIG_ARMV7
+	/* Set TTBR0 */
+	reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK;
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+	reg |= TTBR0_RGN_WT | TTBR0_IRGN_WT;
+#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
+	reg |= TTBR0_RGN_WBWA | TTBR0_IRGN_WBWA;
+#else
+	reg |= TTBR0_RGN_WB | TTBR0_IRGN_WB;
+#endif
+	asm volatile("mcr p15, 0, %0, c2, c0, 0"
+		     : : "r" (reg) : "memory");
+#else
 	/* Copy the page table address to cp15 */
 	asm volatile("mcr p15, 0, %0, c2, c0, 0"
 		     : : "r" (gd->arch.tlb_addr) : "memory");
+#endif
 	/* Set the access control to all-supervisor */
 	asm volatile("mcr p15, 0, %0, c3, c0, 0"
 		     : : "r" (~0));
@@ -29,9 +29,9 @@
 #include <common.h>
 #include <serial.h>
  
-#if defined(CONFIG_CPU_V6)
+#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V7)
 /*
- * ARMV6
+ * ARMV6 & ARMV7
  */
 #define DCC_RBIT	(1 << 30)
 #define DCC_WBIT	(1 << 29)
@@ -34,7 +34,6 @@
 /* DCC driver */
 #if defined(CONFIG_ZYNQ_DCC)
 # define CONFIG_ARM_DCC
-# define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */
 #else
 # define CONFIG_ZYNQ_SERIAL
 #endif
...	...	@@ -68,7 +68,7 @@
68	68	}
69	69	}
70	70	/* DSB to make sure the operation is complete */
71		- CP15DSB;
	71	+ DSB;
72	72	}
73	73
74	74	static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
...	...	@@ -96,7 +96,7 @@
96	96	}
97	97	}
98	98	/* DSB to make sure the operation is complete */
99		- CP15DSB;
	99	+ DSB;
100	100	}
101	101
102	102	static void v7_maint_dcache_level_setway(u32 level, u32 operation)
...	...	@@ -215,7 +215,7 @@
215	215	}
216	216
217	217	/* DSB to make sure the operation is complete */
218		- CP15DSB;
	218	+ DSB;
219	219	}
220	220
221	221	/* Invalidate TLB */
222	222
...	...	@@ -228,9 +228,9 @@
228	228	/* Invalidate entire instruction TLB */
229	229	asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0));
230	230	/* Full system DSB - make sure that the invalidation is complete */
231		- CP15DSB;
	231	+ DSB;
232	232	/* Full system ISB - make sure the instruction stream sees it */
233		- CP15ISB;
	233	+ ISB;
234	234	}
235	235
236	236	void invalidate_dcache_all(void)
237	237
...	...	@@ -343,10 +343,10 @@
343	343	asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
344	344
345	345	/* Full system DSB - make sure that the invalidation is complete */
346		- CP15DSB;
	346	+ DSB;
347	347
348	348	/* ISB - make sure the instruction stream sees it */
349		- CP15ISB;
	349	+ ISB;
350	350	}
351	351	#else
352	352	void invalidate_icache_all(void)
...	...	@@ -70,6 +70,16 @@
70	70	#define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0))
71	71	#define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0))
72	72
	73	+#ifdef __ARM_ARCH_7A__
	74	+#define ISB asm volatile ("isb" : : : "memory")
	75	+#define DSB asm volatile ("dsb" : : : "memory")
	76	+#define DMB asm volatile ("dmb" : : : "memory")
	77	+#else
	78	+#define ISB CP15ISB
	79	+#define DSB CP15DSB
	80	+#define DMB CP15DMB
	81	+#endif
	82	+
73	83	/*
74	84	* Workaround for ARM errata # 798870
75	85	* Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
...	...	@@ -95,9 +95,6 @@
95	95	return (old & mask) != 0;
96	96	}
97	97
98		-extern int find_first_zero_bit(void * addr, unsigned size);
99		-extern int find_next_zero_bit(void * addr, int size, int offset);
100		-
101	98	/*
102	99	* This routine doesn't need to be atomic.
103	100	*/
...	...	@@ -129,6 +126,43 @@
129	126	return k;
130	127	}
131	128
	129	+static inline int find_next_zero_bit(void *addr, int size, int offset)
	130	+{
	131	+ unsigned long p = ((unsigned long )addr) + (offset >> 5);
	132	+ unsigned long result = offset & ~31UL;
	133	+ unsigned long tmp;
	134	+
	135	+ if (offset >= size)
	136	+ return size;
	137	+ size -= result;
	138	+ offset &= 31UL;
	139	+ if (offset) {
	140	+ tmp = *(p++);
	141	+ tmp \|= ~0UL >> (32-offset);
	142	+ if (size < 32)
	143	+ goto found_first;
	144	+ if (~tmp)
	145	+ goto found_middle;
	146	+ size -= 32;
	147	+ result += 32;
	148	+ }
	149	+ while (size & ~31UL) {
	150	+ tmp = *(p++);
	151	+ if (~tmp)
	152	+ goto found_middle;
	153	+ result += 32;
	154	+ size -= 32;
	155	+ }
	156	+ if (!size)
	157	+ return result;
	158	+ tmp = *p;
	159	+
	160	+found_first:
	161	+ tmp \|= ~0UL >> size;
	162	+found_middle:
	163	+ return result + ffz(tmp);
	164	+}
	165	+
132	166	/*
133	167	* hweightN: returns the hamming weight (i.e. the number
134	168	* of bits set) of a N-bit word
...	...	@@ -137,6 +171,9 @@
137	171	#define hweight32(x) generic_hweight32(x)
138	172	#define hweight16(x) generic_hweight16(x)
139	173	#define hweight8(x) generic_hweight8(x)
	174	+
	175	+#define find_first_zero_bit(addr, size) \
	176	+ find_next_zero_bit((addr), (size), 0)
140	177
141	178	#define ext2_set_bit test_and_set_bit
142	179	#define ext2_clear_bit test_and_clear_bit
...	...	@@ -143,6 +143,9 @@
143	143	mov \xreg1, #0x33ff
144	144	msr cptr_el2, \xreg1 /* Disable coprocessor traps to EL2 */
145	145
	146	+ /* Initialize Generic Timers */
	147	+ msr cntvoff_el2, xzr
	148	+
146	149	/* Initialize SCTLR_EL2
147	150	*
148	151	* setting RES1 bits (29,28,23,22,18,16,11,5,4) to 1
...	...	@@ -196,19 +196,56 @@
196	196	isb();
197	197	}
198	198
	199	+#ifdef CONFIG_ARMV7
	200	+/* Short-Descriptor Translation Table Level 1 Bits */
	201	+#define TTB_SECT_NS_MASK (1 << 19)
	202	+#define TTB_SECT_NG_MASK (1 << 17)
	203	+#define TTB_SECT_S_MASK (1 << 16)
	204	+/* Note: TTB AP bits are set elsewhere */
	205	+#define TTB_SECT_TEX(x) ((x & 0x7) << 12)
	206	+#define TTB_SECT_DOMAIN(x) ((x & 0xf) << 5)
	207	+#define TTB_SECT_XN_MASK (1 << 4)
	208	+#define TTB_SECT_C_MASK (1 << 3)
	209	+#define TTB_SECT_B_MASK (1 << 2)
	210	+#define TTB_SECT (2 << 0)
	211	+
199	212	/* options available for data cache on each page */
200	213	enum dcache_option {
	214	+ DCACHE_OFF = TTB_SECT_S_MASK \| TTB_SECT_DOMAIN(0) \|
	215	+ TTB_SECT_XN_MASK \| TTB_SECT,
	216	+ DCACHE_WRITETHROUGH = DCACHE_OFF \| TTB_SECT_C_MASK,
	217	+ DCACHE_WRITEBACK = DCACHE_WRITETHROUGH \| TTB_SECT_B_MASK,
	218	+ DCACHE_WRITEALLOC = DCACHE_WRITEBACK \| TTB_SECT_TEX(1),
	219	+};
	220	+#else
	221	+/* options available for data cache on each page */
	222	+enum dcache_option {
201	223	DCACHE_OFF = 0x12,
202	224	DCACHE_WRITETHROUGH = 0x1a,
203	225	DCACHE_WRITEBACK = 0x1e,
204	226	DCACHE_WRITEALLOC = 0x16,
205	227	};
	228	+#endif
206	229
207	230	/* Size of an MMU section */
208	231	enum {
209	232	MMU_SECTION_SHIFT = 20,
210	233	MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT,
211	234	};
	235	+
	236	+#ifdef CONFIG_ARMV7
	237	+/* TTBR0 bits */
	238	+#define TTBR0_BASE_ADDR_MASK 0xFFFFC000
	239	+#define TTBR0_RGN_NC (0 << 3)
	240	+#define TTBR0_RGN_WBWA (1 << 3)
	241	+#define TTBR0_RGN_WT (2 << 3)
	242	+#define TTBR0_RGN_WB (3 << 3)
	243	+/* TTBR0[6] is IRGN[0] and TTBR[0] is IRGN[1] */
	244	+#define TTBR0_IRGN_NC (0 << 0 \| 0 << 6)
	245	+#define TTBR0_IRGN_WBWA (0 << 0 \| 1 << 6)
	246	+#define TTBR0_IRGN_WT (1 << 0 \| 0 << 6)
	247	+#define TTBR0_IRGN_WB (1 << 0 \| 1 << 6)
	248	+#endif
212	249
213	250	/**
214	251	* Change the cache settings for a region.
...	...	@@ -96,9 +96,23 @@
96	96	dram_bank_mmu_setup(i);
97	97	}
98	98
	99	+#ifdef CONFIG_ARMV7
	100	+ /* Set TTBR0 */
	101	+ reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK;
	102	+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
	103	+ reg \|= TTBR0_RGN_WT \| TTBR0_IRGN_WT;
	104	+#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
	105	+ reg \|= TTBR0_RGN_WBWA \| TTBR0_IRGN_WBWA;
	106	+#else
	107	+ reg \|= TTBR0_RGN_WB \| TTBR0_IRGN_WB;
	108	+#endif
	109	+ asm volatile("mcr p15, 0, %0, c2, c0, 0"
	110	+ : : "r" (reg) : "memory");
	111	+#else
99	112	/* Copy the page table address to cp15 */
100	113	asm volatile("mcr p15, 0, %0, c2, c0, 0"
101	114	: : "r" (gd->arch.tlb_addr) : "memory");
	115	+#endif
102	116	/* Set the access control to all-supervisor */
103	117	asm volatile("mcr p15, 0, %0, c3, c0, 0"
104	118	: : "r" (~0));
...	...	@@ -29,9 +29,9 @@
29	29	#include <common.h>
30	30	#include <serial.h>
31	31
32		-#if defined(CONFIG_CPU_V6)
	32	+#if defined(CONFIG_CPU_V6) \|\| defined(CONFIG_CPU_V7)
33	33	/*
34		- * ARMV6
	34	+ * ARMV6 & ARMV7
35	35	*/
36	36	#define DCC_RBIT (1 << 30)
37	37	#define DCC_WBIT (1 << 29)
...	...	@@ -34,7 +34,6 @@
34	34	/* DCC driver */
35	35	#if defined(CONFIG_ZYNQ_DCC)
36	36	# define CONFIG_ARM_DCC
37		-# define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */
38	37	#else
39	38	# define CONFIG_ZYNQ_SERIAL
40	39	#endif