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Commit 3f353ceccbbb25315cf7591f59f8dbd853b657e4

Authored by Albert ARIBAUD \\(3ADEV\\)
Committed by Stefano Babic
1 parent b9a1609915
Exists in v2017.01-smarct4x and in 30 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

vf610: refactor DDRMC code 

The VF610 DDRMC driver code contains settings which are
board-specific. Move these out to boards so that new boards
can define their own without having to modify the driver.

Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>

Showing 5 changed files with 314 additions and 225 deletions Side-by-side Diff

arch/arm/imx-common/ddrmc-vf610.c
Diff comments   View file @ 3f353ce
... ... @@ -12,9 +12,9 @@
12 12 #include <asm/arch/iomux-vf610.h>
13 13 #include <asm/arch/ddrmc-vf610.h>
14 14  
15   -void ddrmc_setup_iomux(void)
  15 +void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count)
16 16 {
17   - static const iomux_v3_cfg_t ddr_pads[] = {
  17 + static const iomux_v3_cfg_t default_pads[] = {
18 18 VF610_PAD_DDR_A15__DDR_A_15,
19 19 VF610_PAD_DDR_A14__DDR_A_14,
20 20 VF610_PAD_DDR_A13__DDR_A_13,
21 21  
22 22  
23 23  
24 24  
25 25  
26 26  
27 27  
28 28  
29 29  
30 30  
31 31  
32 32  
33 33  
... ... @@ -65,76 +65,54 @@
65 65 VF610_PAD_DDR_RESETB,
66 66 };
67 67  
68   - imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
  68 + if ((pads == NULL) || (pads_count == 0)) {
  69 + pads = default_pads;
  70 + pads_count = ARRAY_SIZE(default_pads);
  71 + }
  72 +
  73 + imx_iomux_v3_setup_multiple_pads(pads, pads_count);
69 74 }
70 75  
71   -void ddrmc_phy_init(void)
72   -{
73   - struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
  76 +static struct ddrmc_phy_setting default_phy_settings[] = {
  77 + { DDRMC_PHY_DQ_TIMING, 0 },
  78 + { DDRMC_PHY_DQ_TIMING, 16 },
  79 + { DDRMC_PHY_DQ_TIMING, 32 },
74 80  
75   - writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[0]);
76   - writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[16]);
77   - writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[32]);
  81 + { DDRMC_PHY_DQS_TIMING, 1 },
  82 + { DDRMC_PHY_DQS_TIMING, 17 },
78 83  
79   - writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[1]);
80   - writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[17]);
  84 + { DDRMC_PHY_CTRL, 2 },
  85 + { DDRMC_PHY_CTRL, 18 },
  86 + { DDRMC_PHY_CTRL, 34 },
81 87  
82   - writel(DDRMC_PHY_CTRL, &ddrmr->phy[2]);
83   - writel(DDRMC_PHY_CTRL, &ddrmr->phy[18]);
84   - writel(DDRMC_PHY_CTRL, &ddrmr->phy[34]);
  88 + { DDRMC_PHY_MASTER_CTRL, 3 },
  89 + { DDRMC_PHY_MASTER_CTRL, 19 },
  90 + { DDRMC_PHY_MASTER_CTRL, 35 },
85 91  
86   - writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[3]);
87   - writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[19]);
88   - writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[35]);
  92 + { DDRMC_PHY_SLAVE_CTRL, 4 },
  93 + { DDRMC_PHY_SLAVE_CTRL, 20 },
  94 + { DDRMC_PHY_SLAVE_CTRL, 36 },
89 95  
90   - writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[4]);
91   - writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[20]);
92   - writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[36]);
93   -
94 96 /* LPDDR2 only parameter */
95   - writel(DDRMC_PHY_OFF, &ddrmr->phy[49]);
  97 + { DDRMC_PHY_OFF, 49 },
96 98  
97   - writel(DDRMC_PHY50_DDR3_MODE |
98   - DDRMC_PHY50_EN_SW_HALF_CYCLE, &ddrmr->phy[50]);
  99 + { DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, 50 },
99 100  
100 101 /* Processor Pad ODT settings */
101   - writel(DDRMC_PHY_PROC_PAD_ODT, &ddrmr->phy[52]);
102   -}
  102 + { DDRMC_PHY_PROC_PAD_ODT, 52 },
103 103  
104   -static void ddrmc_ctrl_lvl_init(struct ddrmc_lvl_info *lvl)
105   -{
106   - struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
107   - u32 cr102 = 0, cr105 = 0, cr106 = 0, cr110 = 0;
  104 + /* end marker */
  105 + { 0, -1 }
  106 +};
108 107  
109   - if (lvl->wrlvl_reg_en) {
110   - writel(DDRMC_CR97_WRLVL_EN, &ddrmr->cr[97]);
111   - writel(DDRMC_CR98_WRLVL_DL_0(lvl->wrlvl_dl_0), &ddrmr->cr[98]);
112   - writel(DDRMC_CR99_WRLVL_DL_1(lvl->wrlvl_dl_1), &ddrmr->cr[99]);
113   - }
114   -
115   - if (lvl->rdlvl_reg_en) {
116   - cr102 |= DDRMC_CR102_RDLVL_REG_EN;
117   - cr105 |= DDRMC_CR105_RDLVL_DL_0(lvl->rdlvl_dl_0);
118   - cr110 |= DDRMC_CR110_RDLVL_DL_1(lvl->rdlvl_dl_1);
119   - }
120   -
121   - if (lvl->rdlvl_gt_reg_en) {
122   - cr102 |= DDRMC_CR102_RDLVL_GT_REGEN;
123   - cr106 |= DDRMC_CR106_RDLVL_GTDL_0(lvl->rdlvl_gt_dl_0);
124   - cr110 |= DDRMC_CR110_RDLVL_GTDL_1(lvl->rdlvl_gt_dl_1);
125   - }
126   -
127   - writel(cr102, &ddrmr->cr[102]);
128   - writel(cr105, &ddrmr->cr[105]);
129   - writel(cr106, &ddrmr->cr[106]);
130   - writel(cr110, &ddrmr->cr[110]);
131   -}
132   -
133 108 void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
134   - struct ddrmc_lvl_info *lvl,
135   - int col_diff, int row_diff)
  109 + struct ddrmc_cr_setting *board_cr_settings,
  110 + struct ddrmc_phy_setting *board_phy_settings,
  111 + int col_diff, int row_diff)
136 112 {
137 113 struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
  114 + struct ddrmc_cr_setting *cr_setting;
  115 + struct ddrmc_phy_setting *phy_setting;
138 116  
139 117 writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]);
140 118 writel(DDRMC_CR02_DRAM_TINIT(timings->tinit), &ddrmr->cr[2]);
... ... @@ -144,7 +122,9 @@
144 122 writel(DDRMC_CR12_WRLAT(timings->wrlat) |
145 123 DDRMC_CR12_CASLAT_LIN(timings->caslat_lin), &ddrmr->cr[12]);
146 124 writel(DDRMC_CR13_TRC(timings->trc) | DDRMC_CR13_TRRD(timings->trrd) |
147   - DDRMC_CR13_TCCD(timings->tccd), &ddrmr->cr[13]);
  125 + DDRMC_CR13_TCCD(timings->tccd) |
  126 + DDRMC_CR13_TBST_INT_INTERVAL(timings->tbst_int_interval),
  127 + &ddrmr->cr[13]);
148 128 writel(DDRMC_CR14_TFAW(timings->tfaw) | DDRMC_CR14_TRP(timings->trp) |
149 129 DDRMC_CR14_TWTR(timings->twtr) |
150 130 DDRMC_CR14_TRAS_MIN(timings->tras_min), &ddrmr->cr[14]);
151 131  
152 132  
... ... @@ -156,18 +136,19 @@
156 136 DDRMC_CR18_TCKE(timings->tcke), &ddrmr->cr[18]);
157 137  
158 138 writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]);
159   - writel(DDRMC_CR21_TRCD_INT(timings->trcd_int) |
160   - DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]);
  139 + writel(DDRMC_CR21_TRCD_INT(timings->trcd_int) | DDRMC_CR21_CCMAP_EN |
  140 + DDRMC_CR21_TRAS_LOCKOUT(timings->tras_lockout),
  141 + &ddrmr->cr[21]);
161 142  
162 143 writel(DDRMC_CR22_TDAL(timings->tdal), &ddrmr->cr[22]);
163   - writel(DDRMC_CR23_BSTLEN(3) |
  144 + writel(DDRMC_CR23_BSTLEN(timings->bstlen) |
164 145 DDRMC_CR23_TDLL(timings->tdll), &ddrmr->cr[23]);
165 146 writel(DDRMC_CR24_TRP_AB(timings->trp_ab), &ddrmr->cr[24]);
166 147  
167 148 writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]);
168 149 writel(DDRMC_CR26_TREF(timings->tref) |
169 150 DDRMC_CR26_TRFC(timings->trfc), &ddrmr->cr[26]);
170   - writel(DDRMC_CR28_TREF_INT(0), &ddrmr->cr[28]);
  151 + writel(DDRMC_CR28_TREF_INT(timings->tref_int), &ddrmr->cr[28]);
171 152 writel(DDRMC_CR29_TPDEX(timings->tpdex), &ddrmr->cr[29]);
172 153  
173 154 writel(DDRMC_CR30_TXPDLL(timings->txpdll), &ddrmr->cr[30]);
... ... @@ -177,7 +158,7 @@
177 158 writel(DDRMC_CR34_CKSRX(timings->cksrx) |
178 159 DDRMC_CR34_CKSRE(timings->cksre), &ddrmr->cr[34]);
179 160  
180   - writel(DDRMC_CR38_FREQ_CHG_EN(0), &ddrmr->cr[38]);
  161 + writel(DDRMC_CR38_FREQ_CHG_EN(timings->freq_chg_en), &ddrmr->cr[38]);
181 162 writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) |
182 163 DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]);
183 164  
184 165  
... ... @@ -191,13 +172,14 @@
191 172 writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]);
192 173  
193 174 writel(DDRMC_CR70_REF_PER_ZQ(timings->ref_per_zq), &ddrmr->cr[70]);
194   - writel(DDRMC_CR72_ZQCS_ROTATE(0), &ddrmr->cr[72]);
  175 + writel(DDRMC_CR72_ZQCS_ROTATE(timings->zqcs_rotate), &ddrmr->cr[72]);
195 176  
196 177 writel(DDRMC_CR73_APREBIT(timings->aprebit) |
197 178 DDRMC_CR73_COL_DIFF(col_diff) |
198 179 DDRMC_CR73_ROW_DIFF(row_diff), &ddrmr->cr[73]);
199 180 writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN |
200   - DDRMC_CR74_CMD_AGE_CNT(64) | DDRMC_CR74_AGE_CNT(64),
  181 + DDRMC_CR74_CMD_AGE_CNT(timings->cmd_age_cnt) |
  182 + DDRMC_CR74_AGE_CNT(timings->age_cnt),
201 183 &ddrmr->cr[74]);
202 184 writel(DDRMC_CR75_RW_PG_EN | DDRMC_CR75_RW_EN | DDRMC_CR75_PRI_EN |
203 185 DDRMC_CR75_PLEN, &ddrmr->cr[75]);
204 186  
... ... @@ -205,13 +187,15 @@
205 187 DDRMC_CR76_W2R_SPLT_EN, &ddrmr->cr[76]);
206 188 writel(DDRMC_CR77_CS_MAP | DDRMC_CR77_DI_RD_INTLEAVE |
207 189 DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]);
208   - writel(DDRMC_CR78_Q_FULLNESS(7) |
  190 + writel(DDRMC_CR78_Q_FULLNESS(timings->q_fullness) |
209 191 DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]);
210 192 writel(DDRMC_CR79_CTLUPD_AREF(0), &ddrmr->cr[79]);
211 193  
212 194 writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]);
213 195  
214   - writel(DDRMC_CR87_ODT_WR_MAPCS0, &ddrmr->cr[87]);
  196 + writel(DDRMC_CR87_ODT_RD_MAPCS0(timings->odt_rd_mapcs0) |
  197 + DDRMC_CR87_ODT_WR_MAPCS0(timings->odt_wr_mapcs0),
  198 + &ddrmr->cr[87]);
215 199 writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]);
216 200 writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]);
217 201  
218 202  
219 203  
220 204  
... ... @@ -219,58 +203,33 @@
219 203 writel(DDRMC_CR96_WLMRD(timings->wlmrd) |
220 204 DDRMC_CR96_WLDQSEN(timings->wldqsen), &ddrmr->cr[96]);
221 205  
222   - if (lvl != NULL)
223   - ddrmc_ctrl_lvl_init(lvl);
  206 + /* execute custom CR setting sequence (may be NULL) */
  207 + cr_setting = board_cr_settings;
  208 + if (cr_setting != NULL)
  209 + while (cr_setting->cr_rnum >= 0) {
  210 + writel(cr_setting->setting,
  211 + &ddrmr->cr[cr_setting->cr_rnum]);
  212 + cr_setting++;
  213 + }
224 214  
225   - writel(DDRMC_CR117_AXI0_W_PRI(0) |
226   - DDRMC_CR117_AXI0_R_PRI(0), &ddrmr->cr[117]);
227   - writel(DDRMC_CR118_AXI1_W_PRI(1) |
228   - DDRMC_CR118_AXI1_R_PRI(1), &ddrmr->cr[118]);
  215 + /* perform default PHY settings (may be overriden by custom settings */
  216 + phy_setting = default_phy_settings;
  217 + while (phy_setting->phy_rnum >= 0) {
  218 + writel(phy_setting->setting,
  219 + &ddrmr->phy[phy_setting->phy_rnum]);
  220 + phy_setting++;
  221 + }
229 222  
230   - writel(DDRMC_CR120_AXI0_PRI1_RPRI(2) |
231   - DDRMC_CR120_AXI0_PRI0_RPRI(2), &ddrmr->cr[120]);
232   - writel(DDRMC_CR121_AXI0_PRI3_RPRI(2) |
233   - DDRMC_CR121_AXI0_PRI2_RPRI(2), &ddrmr->cr[121]);
234   - writel(DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
235   - DDRMC_CR122_AXI0_PRIRLX(100), &ddrmr->cr[122]);
236   - writel(DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
237   - DDRMC_CR123_AXI1_PRI2_RPRI(1), &ddrmr->cr[123]);
238   - writel(DDRMC_CR124_AXI1_PRIRLX(100), &ddrmr->cr[124]);
  223 + /* execute custom PHY setting sequence (may be NULL) */
  224 + phy_setting = board_phy_settings;
  225 + if (phy_setting != NULL)
  226 + while (phy_setting->phy_rnum >= 0) {
  227 + writel(phy_setting->setting,
  228 + &ddrmr->phy[phy_setting->phy_rnum]);
  229 + phy_setting++;
  230 + }
239 231  
240   - writel(DDRMC_CR126_PHY_RDLAT(8), &ddrmr->cr[126]);
241   - writel(DDRMC_CR132_WRLAT_ADJ(5) |
242   - DDRMC_CR132_RDLAT_ADJ(6), &ddrmr->cr[132]);
243   - writel(DDRMC_CR137_PHYCTL_DL(2), &ddrmr->cr[137]);
244   - writel(DDRMC_CR138_PHY_WRLV_MXDL(256) |
245   - DDRMC_CR138_PHYDRAM_CK_EN(1), &ddrmr->cr[138]);
246   - writel(DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
247   - DDRMC_CR139_PHY_WRLV_DLL(3) |
248   - DDRMC_CR139_PHY_WRLV_EN(3), &ddrmr->cr[139]);
249   - writel(DDRMC_CR140_PHY_WRLV_WW(64), &ddrmr->cr[140]);
250   - writel(DDRMC_CR143_RDLV_GAT_MXDL(1536) |
251   - DDRMC_CR143_RDLV_MXDL(128), &ddrmr->cr[143]);
252   - writel(DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) |
253   - DDRMC_CR144_PHY_RDLV_DLL(3) |
254   - DDRMC_CR144_PHY_RDLV_EN(3), &ddrmr->cr[144]);
255   - writel(DDRMC_CR145_PHY_RDLV_RR(64), &ddrmr->cr[145]);
256   - writel(DDRMC_CR146_PHY_RDLVL_RESP(64), &ddrmr->cr[146]);
257   - writel(DDRMC_CR147_RDLV_RESP_MASK(983040), &ddrmr->cr[147]);
258   - writel(DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), &ddrmr->cr[148]);
259   - writel(DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) |
260   - DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), &ddrmr->cr[151]);
261   -
262   - writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
263   - DDRMC_CR154_PAD_ZQ_MODE(1) |
264   - DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
265   - DDRMC_CR154_PAD_ZQ_HW_FOR(1), &ddrmr->cr[154]);
266   - writel(DDRMC_CR155_PAD_ODT_BYTE1(2) |
267   - DDRMC_CR155_PAD_ODT_BYTE0(2), &ddrmr->cr[155]);
268   - writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]);
269   - writel(DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
270   - DDRMC_CR161_TODTH_WR(2), &ddrmr->cr[161]);
271   -
272   - ddrmc_phy_init();
273   -
  232 + /* all inits done, start the DDR controller */
274 233 writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]);
275 234  
276 235 while (!(readl(&ddrmr->cr[80]) && 0x100))
arch/arm/include/asm/arch-vf610/ddrmc-vf610.h
Diff comments   View file @ 3f353ce
... ... @@ -11,18 +11,6 @@
11 11 #ifndef __ASM_ARCH_VF610_DDRMC_H
12 12 #define __ASM_ARCH_VF610_DDRMC_H
13 13  
14   -struct ddrmc_lvl_info {
15   - u16 wrlvl_reg_en;
16   - u16 wrlvl_dl_0;
17   - u16 wrlvl_dl_1;
18   - u16 rdlvl_gt_reg_en;
19   - u16 rdlvl_gt_dl_0;
20   - u16 rdlvl_gt_dl_1;
21   - u16 rdlvl_reg_en;
22   - u16 rdlvl_dl_0;
23   - u16 rdlvl_dl_1;
24   -};
25   -
26 14 struct ddr3_jedec_timings {
27 15 u8 tinit;
28 16 u32 trst_pwron;
... ... @@ -32,6 +20,7 @@
32 20 u8 trc;
33 21 u8 trrd;
34 22 u8 tccd;
  23 + u8 tbst_int_interval;
35 24 u8 tfaw;
36 25 u8 trp;
37 26 u8 twtr;
38 27  
39 28  
40 29  
41 30  
42 31  
43 32  
44 33  
... ... @@ -43,31 +32,52 @@
43 32 u8 tckesr;
44 33 u8 tcke;
45 34 u8 trcd_int;
  35 + u8 tras_lockout;
46 36 u8 tdal;
  37 + u8 bstlen;
47 38 u16 tdll;
48 39 u8 trp_ab;
49 40 u16 tref;
50 41 u8 trfc;
  42 + u16 tref_int;
51 43 u8 tpdex;
52 44 u8 txpdll;
53 45 u8 txsnr;
54 46 u16 txsr;
55 47 u8 cksrx;
56 48 u8 cksre;
  49 + u8 freq_chg_en;
57 50 u16 zqcl;
58 51 u16 zqinit;
59 52 u8 zqcs;
60 53 u8 ref_per_zq;
  54 + u8 zqcs_rotate;
61 55 u8 aprebit;
  56 + u8 cmd_age_cnt;
  57 + u8 age_cnt;
  58 + u8 q_fullness;
  59 + u8 odt_rd_mapcs0;
  60 + u8 odt_wr_mapcs0;
62 61 u8 wlmrd;
63 62 u8 wldqsen;
64 63 };
65 64  
66   -void ddrmc_setup_iomux(void);
  65 +struct ddrmc_cr_setting {
  66 + u32 setting;
  67 + int cr_rnum; /* CR register ; -1 for last entry */
  68 +};
  69 +
  70 +struct ddrmc_phy_setting {
  71 + u32 setting;
  72 + int phy_rnum; /* PHY register ; -1 for last entry */
  73 +};
  74 +
  75 +void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count);
67 76 void ddrmc_phy_init(void);
68 77 void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
69   - struct ddrmc_lvl_info *lvl,
70   - int col_diff, int row_diff);
  78 + struct ddrmc_cr_setting *board_cr_settings,
  79 + struct ddrmc_phy_setting *board_phy_settings,
  80 + int col_diff, int row_diff);
71 81  
72 82 #endif
arch/arm/include/asm/arch-vf610/imx-regs.h
Diff comments   View file @ 3f353ce
... ... @@ -148,7 +148,7 @@
148 148 #define DDRMC_CR18_TCKE(v) ((v) & 0x7)
149 149 #define DDRMC_CR20_AP_EN (1 << 24)
150 150 #define DDRMC_CR21_TRCD_INT(v) (((v) & 0xff) << 16)
151   -#define DDRMC_CR21_TRAS_LOCKOUT (1 << 8)
  151 +#define DDRMC_CR21_TRAS_LOCKOUT(v) ((v) << 8)
152 152 #define DDRMC_CR21_CCMAP_EN 1
153 153 #define DDRMC_CR22_TDAL(v) (((v) & 0x3f) << 16)
154 154 #define DDRMC_CR23_BSTLEN(v) (((v) & 0x7) << 24)
... ... @@ -200,8 +200,8 @@
200 200 #define DDRMC_CR78_BUR_ON_FLY_BIT(v) ((v) & 0xf)
201 201 #define DDRMC_CR79_CTLUPD_AREF(v) (((v) & 0x1) << 24)
202 202 #define DDRMC_CR82_INT_MASK 0x10000000
203   -#define DDRMC_CR87_ODT_WR_MAPCS0 (1 << 24)
204   -#define DDRMC_CR87_ODT_RD_MAPCS0 (1 << 16)
  203 +#define DDRMC_CR87_ODT_WR_MAPCS0(v) ((v) << 24)
  204 +#define DDRMC_CR87_ODT_RD_MAPCS0(v) ((v) << 16)
205 205 #define DDRMC_CR88_TODTL_CMD(v) (((v) & 0x1f) << 16)
206 206 #define DDRMC_CR89_AODT_RWSMCS(v) ((v) & 0xf)
207 207 #define DDRMC_CR91_R2W_SMCSDL(v) (((v) & 0x7) << 16)
board/freescale/vf610twr/vf610twr.c
Diff comments   View file @ 3f353ce
... ... @@ -28,63 +28,117 @@
28 28 #define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
29 29 PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
30 30  
  31 +static struct ddrmc_cr_setting vf610twr_cr_settings[] = {
  32 + /* levelling */
  33 + { DDRMC_CR97_WRLVL_EN, 97 },
  34 + { DDRMC_CR98_WRLVL_DL_0(0), 98 },
  35 + { DDRMC_CR99_WRLVL_DL_1(0), 99 },
  36 + { DDRMC_CR102_RDLVL_REG_EN | DDRMC_CR102_RDLVL_GT_REGEN, 102 },
  37 + { DDRMC_CR105_RDLVL_DL_0(0), 105 },
  38 + { DDRMC_CR106_RDLVL_GTDL_0(4), 106 },
  39 + { DDRMC_CR110_RDLVL_DL_1(0) | DDRMC_CR110_RDLVL_GTDL_1(4), 110 },
  40 + /* AXI */
  41 + { DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 },
  42 + { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
  43 + { DDRMC_CR120_AXI0_PRI1_RPRI(2) |
  44 + DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 },
  45 + { DDRMC_CR121_AXI0_PRI3_RPRI(2) |
  46 + DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 },
  47 + { DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
  48 + DDRMC_CR122_AXI0_PRIRLX(100), 122 },
  49 + { DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
  50 + DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 },
  51 + { DDRMC_CR124_AXI1_PRIRLX(100), 124 },
  52 + { DDRMC_CR126_PHY_RDLAT(8), 126 },
  53 + { DDRMC_CR132_WRLAT_ADJ(5) |
  54 + DDRMC_CR132_RDLAT_ADJ(6), 132 },
  55 + { DDRMC_CR137_PHYCTL_DL(2), 137 },
  56 + { DDRMC_CR138_PHY_WRLV_MXDL(256) |
  57 + DDRMC_CR138_PHYDRAM_CK_EN(1), 138 },
  58 + { DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
  59 + DDRMC_CR139_PHY_WRLV_DLL(3) |
  60 + DDRMC_CR139_PHY_WRLV_EN(3), 139 },
  61 + { DDRMC_CR140_PHY_WRLV_WW(64), 140 },
  62 + { DDRMC_CR143_RDLV_GAT_MXDL(1536) |
  63 + DDRMC_CR143_RDLV_MXDL(128), 143 },
  64 + { DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) |
  65 + DDRMC_CR144_PHY_RDLV_DLL(3) |
  66 + DDRMC_CR144_PHY_RDLV_EN(3), 144 },
  67 + { DDRMC_CR145_PHY_RDLV_RR(64), 145 },
  68 + { DDRMC_CR146_PHY_RDLVL_RESP(64), 146 },
  69 + { DDRMC_CR147_RDLV_RESP_MASK(983040), 147 },
  70 + { DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), 148 },
  71 + { DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) |
  72 + DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), 151 },
  73 +
  74 + { DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
  75 + DDRMC_CR154_PAD_ZQ_MODE(1) |
  76 + DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
  77 + DDRMC_CR154_PAD_ZQ_HW_FOR(1), 154 },
  78 + { DDRMC_CR155_PAD_ODT_BYTE1(1) | DDRMC_CR155_PAD_ODT_BYTE0(1), 155 },
  79 + { DDRMC_CR158_TWR(6), 158 },
  80 + { DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
  81 + DDRMC_CR161_TODTH_WR(2), 161 },
  82 + /* end marker */
  83 + { 0, -1 }
  84 +};
  85 +
31 86 int dram_init(void)
32 87 {
33   - struct ddrmc_lvl_info lvl = {
34   - .wrlvl_reg_en = 1,
35   - .wrlvl_dl_0 = 0,
36   - .wrlvl_dl_1 = 0,
37   - .rdlvl_gt_reg_en = 1,
38   - .rdlvl_gt_dl_0 = 4,
39   - .rdlvl_gt_dl_1 = 4,
40   - .rdlvl_reg_en = 1,
41   - .rdlvl_dl_0 = 0,
42   - .rdlvl_dl_1 = 0,
43   - };
44   -
45 88 static const struct ddr3_jedec_timings timings = {
46   - .tinit = 5,
47   - .trst_pwron = 80000,
48   - .cke_inactive = 200000,
49   - .wrlat = 5,
50   - .caslat_lin = 12,
51   - .trc = 21,
52   - .trrd = 4,
53   - .tccd = 4,
54   - .tfaw = 20,
55   - .trp = 6,
56   - .twtr = 4,
57   - .tras_min = 15,
58   - .tmrd = 4,
59   - .trtp = 4,
60   - .tras_max = 28080,
61   - .tmod = 12,
62   - .tckesr = 4,
63   - .tcke = 3,
64   - .trcd_int = 6,
65   - .tdal = 12,
66   - .tdll = 512,
67   - .trp_ab = 6,
68   - .tref = 3120,
69   - .trfc = 44,
70   - .tpdex = 3,
71   - .txpdll = 10,
72   - .txsnr = 48,
73   - .txsr = 468,
74   - .cksrx = 5,
75   - .cksre = 5,
76   - .zqcl = 256,
77   - .zqinit = 512,
78   - .zqcs = 64,
79   - .ref_per_zq = 64,
80   - .aprebit = 10,
81   - .wlmrd = 40,
82   - .wldqsen = 25,
  89 + .tinit = 5,
  90 + .trst_pwron = 80000,
  91 + .cke_inactive = 200000,
  92 + .wrlat = 5,
  93 + .caslat_lin = 12,
  94 + .trc = 21,
  95 + .trrd = 4,
  96 + .tccd = 4,
  97 + .tbst_int_interval = 0,
  98 + .tfaw = 20,
  99 + .trp = 6,
  100 + .twtr = 4,
  101 + .tras_min = 15,
  102 + .tmrd = 4,
  103 + .trtp = 4,
  104 + .tras_max = 28080,
  105 + .tmod = 12,
  106 + .tckesr = 4,
  107 + .tcke = 3,
  108 + .trcd_int = 6,
  109 + .tras_lockout = 0,
  110 + .tdal = 12,
  111 + .bstlen = 0,
  112 + .tdll = 512,
  113 + .trp_ab = 6,
  114 + .tref = 3120,
  115 + .trfc = 44,
  116 + .tref_int = 0,
  117 + .tpdex = 3,
  118 + .txpdll = 10,
  119 + .txsnr = 48,
  120 + .txsr = 468,
  121 + .cksrx = 5,
  122 + .cksre = 5,
  123 + .freq_chg_en = 0,
  124 + .zqcl = 256,
  125 + .zqinit = 512,
  126 + .zqcs = 64,
  127 + .ref_per_zq = 64,
  128 + .zqcs_rotate = 0,
  129 + .aprebit = 10,
  130 + .cmd_age_cnt = 64,
  131 + .age_cnt = 64,
  132 + .q_fullness = 7,
  133 + .odt_rd_mapcs0 = 0,
  134 + .odt_wr_mapcs0 = 1,
  135 + .wlmrd = 40,
  136 + .wldqsen = 25,
83 137 };
84 138  
85   - ddrmc_setup_iomux();
  139 + ddrmc_setup_iomux(NULL, 0);
86 140  
87   - ddrmc_ctrl_init_ddr3(&timings, &lvl, 1, 3);
  141 + ddrmc_ctrl_init_ddr3(&timings, vf610twr_cr_settings, NULL, 1, 3);
88 142 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
89 143  
90 144 return 0;
board/toradex/colibri_vf/colibri_vf.c
Diff comments   View file @ 3f353ce
... ... @@ -35,6 +35,61 @@
35 35  
36 36 #define USB_PEN_GPIO 83
37 37  
  38 +static struct ddrmc_cr_setting colibri_vf_cr_settings[] = {
  39 + /* levelling */
  40 + { DDRMC_CR97_WRLVL_EN, 97 },
  41 + { DDRMC_CR98_WRLVL_DL_0(0), 98 },
  42 + { DDRMC_CR99_WRLVL_DL_1(0), 99 },
  43 + { DDRMC_CR102_RDLVL_REG_EN | DDRMC_CR102_RDLVL_GT_REGEN, 102 },
  44 + { DDRMC_CR105_RDLVL_DL_0(0), 105 },
  45 + { DDRMC_CR106_RDLVL_GTDL_0(4), 106 },
  46 + { DDRMC_CR110_RDLVL_DL_1(0) | DDRMC_CR110_RDLVL_GTDL_1(4), 110 },
  47 + /* AXI */
  48 + { DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 },
  49 + { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
  50 + { DDRMC_CR120_AXI0_PRI1_RPRI(2) |
  51 + DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 },
  52 + { DDRMC_CR121_AXI0_PRI3_RPRI(2) |
  53 + DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 },
  54 + { DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
  55 + DDRMC_CR122_AXI0_PRIRLX(100), 122 },
  56 + { DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
  57 + DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 },
  58 + { DDRMC_CR124_AXI1_PRIRLX(100), 124 },
  59 + { DDRMC_CR126_PHY_RDLAT(8), 126 },
  60 + { DDRMC_CR132_WRLAT_ADJ(5) |
  61 + DDRMC_CR132_RDLAT_ADJ(6), 132 },
  62 + { DDRMC_CR137_PHYCTL_DL(2), 137 },
  63 + { DDRMC_CR138_PHY_WRLV_MXDL(256) |
  64 + DDRMC_CR138_PHYDRAM_CK_EN(1), 138 },
  65 + { DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
  66 + DDRMC_CR139_PHY_WRLV_DLL(3) |
  67 + DDRMC_CR139_PHY_WRLV_EN(3), 139 },
  68 + { DDRMC_CR140_PHY_WRLV_WW(64), 140 },
  69 + { DDRMC_CR143_RDLV_GAT_MXDL(1536) |
  70 + DDRMC_CR143_RDLV_MXDL(128), 143 },
  71 + { DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) |
  72 + DDRMC_CR144_PHY_RDLV_DLL(3) |
  73 + DDRMC_CR144_PHY_RDLV_EN(3), 144 },
  74 + { DDRMC_CR145_PHY_RDLV_RR(64), 145 },
  75 + { DDRMC_CR146_PHY_RDLVL_RESP(64), 146 },
  76 + { DDRMC_CR147_RDLV_RESP_MASK(983040), 147 },
  77 + { DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), 148 },
  78 + { DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) |
  79 + DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), 151 },
  80 +
  81 + { DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
  82 + DDRMC_CR154_PAD_ZQ_MODE(1) |
  83 + DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
  84 + DDRMC_CR154_PAD_ZQ_HW_FOR(1), 154 },
  85 + { DDRMC_CR155_PAD_ODT_BYTE1(1) | DDRMC_CR155_PAD_ODT_BYTE0(1), 155 },
  86 + { DDRMC_CR158_TWR(6), 158 },
  87 + { DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
  88 + DDRMC_CR161_TODTH_WR(2), 161 },
  89 + /* end marker */
  90 + { 0, -1 }
  91 +};
  92 +
38 93 static const iomux_v3_cfg_t usb_pads[] = {
39 94 VF610_PAD_PTD4__GPIO_83,
40 95 };
41 96  
42 97  
... ... @@ -42,48 +97,59 @@
42 97 int dram_init(void)
43 98 {
44 99 static const struct ddr3_jedec_timings timings = {
45   - .tinit = 5,
46   - .trst_pwron = 80000,
47   - .cke_inactive = 200000,
48   - .wrlat = 5,
49   - .caslat_lin = 12,
50   - .trc = 21,
51   - .trrd = 4,
52   - .tccd = 4,
53   - .tfaw = 20,
54   - .trp = 6,
55   - .twtr = 4,
56   - .tras_min = 15,
57   - .tmrd = 4,
58   - .trtp = 4,
59   - .tras_max = 28080,
60   - .tmod = 12,
61   - .tckesr = 4,
62   - .tcke = 3,
63   - .trcd_int = 6,
64   - .tdal = 12,
65   - .tdll = 512,
66   - .trp_ab = 6,
67   - .tref = 3120,
68   - .trfc = 64,
69   - .tpdex = 3,
70   - .txpdll = 10,
71   - .txsnr = 48,
72   - .txsr = 468,
73   - .cksrx = 5,
74   - .cksre = 5,
75   - .zqcl = 256,
76   - .zqinit = 512,
77   - .zqcs = 64,
78   - .ref_per_zq = 64,
79   - .aprebit = 10,
80   - .wlmrd = 40,
81   - .wldqsen = 25,
  100 + .tinit = 5,
  101 + .trst_pwron = 80000,
  102 + .cke_inactive = 200000,
  103 + .wrlat = 5,
  104 + .caslat_lin = 12,
  105 + .trc = 21,
  106 + .trrd = 4,
  107 + .tccd = 4,
  108 + .tbst_int_interval = 0,
  109 + .tfaw = 20,
  110 + .trp = 6,
  111 + .twtr = 4,
  112 + .tras_min = 15,
  113 + .tmrd = 4,
  114 + .trtp = 4,
  115 + .tras_max = 28080,
  116 + .tmod = 12,
  117 + .tckesr = 4,
  118 + .tcke = 3,
  119 + .trcd_int = 6,
  120 + .tras_lockout = 0,
  121 + .tdal = 12,
  122 + .bstlen = 0,
  123 + .tdll = 512,
  124 + .trp_ab = 6,
  125 + .tref = 3120,
  126 + .trfc = 64,
  127 + .tref_int = 0,
  128 + .tpdex = 3,
  129 + .txpdll = 10,
  130 + .txsnr = 48,
  131 + .txsr = 468,
  132 + .cksrx = 5,
  133 + .cksre = 5,
  134 + .freq_chg_en = 0,
  135 + .zqcl = 256,
  136 + .zqinit = 512,
  137 + .zqcs = 64,
  138 + .ref_per_zq = 64,
  139 + .zqcs_rotate = 0,
  140 + .aprebit = 10,
  141 + .cmd_age_cnt = 64,
  142 + .age_cnt = 64,
  143 + .q_fullness = 7,
  144 + .odt_rd_mapcs0 = 0,
  145 + .odt_wr_mapcs0 = 1,
  146 + .wlmrd = 40,
  147 + .wldqsen = 25,
82 148 };
83 149  
84   - ddrmc_setup_iomux();
  150 + ddrmc_setup_iomux(NULL, 0);
85 151  
86   - ddrmc_ctrl_init_ddr3(&timings, NULL, 1, 2);
  152 + ddrmc_ctrl_init_ddr3(&timings, colibri_vf_cr_settings, NULL, 1, 2);
87 153 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
88 154  
89 155 return 0;