Merge branch 'master' of /home/wd/git/u-boot/custodians

* 'master' of /home/wd/git/u-boot/custodians: i2c:designware Turn off the ctrl when setting the speed i2c: Add support for designware i2c controller sh: i2c: Add support I2C controller of SH7734

Merge branch 'master' of /home/wd/git/u-boot/custodians
* 'master' of /home/wd/git/u-boot/custodians: i2c:designware Turn off the ctrl when setting the speed i2c: Add support for designware i2c controller sh: i2c: Add support I2C controller of SH7734
Wolfgang Denk
2 parents 0cdf37ba09 04a9cb8c59
Showing 7 changed files Side-by-side Diff
arch/arm/include/asm/arch-spear/spr_i2c.h
drivers/i2c/Makefile
drivers/i2c/designware_i2c.c
drivers/i2c/designware_i2c.h
drivers/i2c/sh_sh7734_i2c.c
drivers/i2c/spr_i2c.c
include/configs/spear-common.h
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __SPR_I2C_H_
-#define __SPR_I2C_H_
-
-struct i2c_regs {
-	u32 ic_con;
-	u32 ic_tar;
-	u32 ic_sar;
-	u32 ic_hs_maddr;
-	u32 ic_cmd_data;
-	u32 ic_ss_scl_hcnt;
-	u32 ic_ss_scl_lcnt;
-	u32 ic_fs_scl_hcnt;
-	u32 ic_fs_scl_lcnt;
-	u32 ic_hs_scl_hcnt;
-	u32 ic_hs_scl_lcnt;
-	u32 ic_intr_stat;
-	u32 ic_intr_mask;
-	u32 ic_raw_intr_stat;
-	u32 ic_rx_tl;
-	u32 ic_tx_tl;
-	u32 ic_clr_intr;
-	u32 ic_clr_rx_under;
-	u32 ic_clr_rx_over;
-	u32 ic_clr_tx_over;
-	u32 ic_clr_rd_req;
-	u32 ic_clr_tx_abrt;
-	u32 ic_clr_rx_done;
-	u32 ic_clr_activity;
-	u32 ic_clr_stop_det;
-	u32 ic_clr_start_det;
-	u32 ic_clr_gen_call;
-	u32 ic_enable;
-	u32 ic_status;
-	u32 ic_txflr;
-	u32 ix_rxflr;
-	u32 reserved_1;
-	u32 ic_tx_abrt_source;
-};
-
-#define IC_CLK			166
-#define NANO_TO_MICRO		1000
-
-/* High and low times in different speed modes (in ns) */
-#define MIN_SS_SCL_HIGHTIME	4000
-#define MIN_SS_SCL_LOWTIME	5000
-#define MIN_FS_SCL_HIGHTIME	800
-#define MIN_FS_SCL_LOWTIME	1700
-#define MIN_HS_SCL_HIGHTIME	60
-#define MIN_HS_SCL_LOWTIME	160
-
-/* Worst case timeout for 1 byte is kept as 2ms */
-#define I2C_BYTE_TO		(CONFIG_SYS_HZ/500)
-#define I2C_STOPDET_TO		(CONFIG_SYS_HZ/500)
-#define I2C_BYTE_TO_BB		(I2C_BYTE_TO * 16)
-
-/* i2c control register definitions */
-#define IC_CON_SD		0x0040
-#define IC_CON_RE		0x0020
-#define IC_CON_10BITADDRMASTER	0x0010
-#define IC_CON_10BITADDR_SLAVE	0x0008
-#define IC_CON_SPD_MSK		0x0006
-#define IC_CON_SPD_SS		0x0002
-#define IC_CON_SPD_FS		0x0004
-#define IC_CON_SPD_HS		0x0006
-#define IC_CON_MM		0x0001
-
-/* i2c target address register definitions */
-#define TAR_ADDR		0x0050
-
-/* i2c slave address register definitions */
-#define IC_SLAVE_ADDR		0x0002
-
-/* i2c data buffer and command register definitions */
-#define IC_CMD			0x0100
-
-/* i2c interrupt status register definitions */
-#define IC_GEN_CALL		0x0800
-#define IC_START_DET		0x0400
-#define IC_STOP_DET		0x0200
-#define IC_ACTIVITY		0x0100
-#define IC_RX_DONE		0x0080
-#define IC_TX_ABRT		0x0040
-#define IC_RD_REQ		0x0020
-#define IC_TX_EMPTY		0x0010
-#define IC_TX_OVER		0x0008
-#define IC_RX_FULL		0x0004
-#define IC_RX_OVER 		0x0002
-#define IC_RX_UNDER		0x0001
-
-/* fifo threshold register definitions */
-#define IC_TL0			0x00
-#define IC_TL1			0x01
-#define IC_TL2			0x02
-#define IC_TL3			0x03
-#define IC_TL4			0x04
-#define IC_TL5			0x05
-#define IC_TL6			0x06
-#define IC_TL7			0x07
-#define IC_RX_TL		IC_TL0
-#define IC_TX_TL		IC_TL0
-
-/* i2c enable register definitions */
-#define IC_ENABLE_0B		0x0001
-
-/* i2c status register  definitions */
-#define IC_STATUS_SA		0x0040
-#define IC_STATUS_MA		0x0020
-#define IC_STATUS_RFF		0x0010
-#define IC_STATUS_RFNE		0x0008
-#define IC_STATUS_TFE		0x0004
-#define IC_STATUS_TFNF		0x0002
-#define IC_STATUS_ACT		0x0001
-
-/* Speed Selection */
-#define IC_SPEED_MODE_STANDARD	1
-#define IC_SPEED_MODE_FAST	2
-#define IC_SPEED_MODE_MAX	3
-
-#define I2C_MAX_SPEED		3400000
-#define I2C_FAST_SPEED		400000
-#define I2C_STANDARD_SPEED	100000
-
-#endif /* __SPR_I2C_H_ */
@@ -27,6 +27,7 @@
  
 COBJS-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o
 COBJS-$(CONFIG_DRIVER_DAVINCI_I2C) += davinci_i2c.o
+COBJS-$(CONFIG_DW_I2C) += designware_i2c.o
 COBJS-$(CONFIG_FSL_I2C) += fsl_i2c.o
 COBJS-$(CONFIG_I2C_MVTWSI) += mvtwsi.o
 COBJS-$(CONFIG_I2C_MV) += mv_i2c.o
  
@@ -40,11 +41,11 @@
 COBJS-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o
 COBJS-$(CONFIG_S3C44B0_I2C) += s3c44b0_i2c.o
 COBJS-$(CONFIG_SOFT_I2C) += soft_i2c.o
-COBJS-$(CONFIG_SPEAR_I2C) += spr_i2c.o
 COBJS-$(CONFIG_TEGRA_I2C) += tegra_i2c.o
 COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
 COBJS-$(CONFIG_U8500_I2C) += u8500_i2c.o
 COBJS-$(CONFIG_SH_I2C) += sh_i2c.o
+COBJS-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
  
 COBJS	:= $(COBJS-y)
 SRCS	:= $(COBJS:.o=.c)
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include "designware_i2c.h"
+
+static struct i2c_regs *const i2c_regs_p =
+    (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
+
+/*
+ * set_speed - Set the i2c speed mode (standard, high, fast)
+ * @i2c_spd:	required i2c speed mode
+ *
+ * Set the i2c speed mode (standard, high, fast)
+ */
+static void set_speed(int i2c_spd)
+{
+	unsigned int cntl;
+	unsigned int hcnt, lcnt;
+	unsigned int high, low;
+	unsigned int enbl;
+
+	/* to set speed cltr must be disabled */
+	enbl = readl(&i2c_regs_p->ic_enable);
+	enbl &= ~IC_ENABLE_0B;
+	writel(enbl, &i2c_regs_p->ic_enable);
+
+
+	cntl = (readl(&i2c_regs_p->ic_con) & (~IC_CON_SPD_MSK));
+
+	switch (i2c_spd) {
+	case IC_SPEED_MODE_MAX:
+		cntl |= IC_CON_SPD_HS;
+		high = MIN_HS_SCL_HIGHTIME;
+		low = MIN_HS_SCL_LOWTIME;
+		break;
+
+	case IC_SPEED_MODE_STANDARD:
+		cntl |= IC_CON_SPD_SS;
+		high = MIN_SS_SCL_HIGHTIME;
+		low = MIN_SS_SCL_LOWTIME;
+		break;
+
+	case IC_SPEED_MODE_FAST:
+	default:
+		cntl |= IC_CON_SPD_FS;
+		high = MIN_FS_SCL_HIGHTIME;
+		low = MIN_FS_SCL_LOWTIME;
+		break;
+	}
+
+	writel(cntl, &i2c_regs_p->ic_con);
+
+	hcnt = (IC_CLK * high) / NANO_TO_MICRO;
+	writel(hcnt, &i2c_regs_p->ic_fs_scl_hcnt);
+
+	lcnt = (IC_CLK * low) / NANO_TO_MICRO;
+	writel(lcnt, &i2c_regs_p->ic_fs_scl_lcnt);
+
+	/* re-enable i2c ctrl back now that speed is set */
+	enbl |= IC_ENABLE_0B;
+	writel(enbl, &i2c_regs_p->ic_enable);
+}
+
+/*
+ * i2c_set_bus_speed - Set the i2c speed
+ * @speed:	required i2c speed
+ *
+ * Set the i2c speed.
+ */
+void i2c_set_bus_speed(int speed)
+{
+	if (speed >= I2C_MAX_SPEED)
+		set_speed(IC_SPEED_MODE_MAX);
+	else if (speed >= I2C_FAST_SPEED)
+		set_speed(IC_SPEED_MODE_FAST);
+	else
+		set_speed(IC_SPEED_MODE_STANDARD);
+}
+
+/*
+ * i2c_get_bus_speed - Gets the i2c speed
+ *
+ * Gets the i2c speed.
+ */
+int i2c_get_bus_speed(void)
+{
+	u32 cntl;
+
+	cntl = (readl(&i2c_regs_p->ic_con) & IC_CON_SPD_MSK);
+
+	if (cntl == IC_CON_SPD_HS)
+		return I2C_MAX_SPEED;
+	else if (cntl == IC_CON_SPD_FS)
+		return I2C_FAST_SPEED;
+	else if (cntl == IC_CON_SPD_SS)
+		return I2C_STANDARD_SPEED;
+
+	return 0;
+}
+
+/*
+ * i2c_init - Init function
+ * @speed:	required i2c speed
+ * @slaveadd:	slave address for the device
+ *
+ * Initialization function.
+ */
+void i2c_init(int speed, int slaveadd)
+{
+	unsigned int enbl;
+
+	/* Disable i2c */
+	enbl = readl(&i2c_regs_p->ic_enable);
+	enbl &= ~IC_ENABLE_0B;
+	writel(enbl, &i2c_regs_p->ic_enable);
+
+	writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_regs_p->ic_con);
+	writel(IC_RX_TL, &i2c_regs_p->ic_rx_tl);
+	writel(IC_TX_TL, &i2c_regs_p->ic_tx_tl);
+	i2c_set_bus_speed(speed);
+	writel(IC_STOP_DET, &i2c_regs_p->ic_intr_mask);
+	writel(slaveadd, &i2c_regs_p->ic_sar);
+
+	/* Enable i2c */
+	enbl = readl(&i2c_regs_p->ic_enable);
+	enbl |= IC_ENABLE_0B;
+	writel(enbl, &i2c_regs_p->ic_enable);
+}
+
+/*
+ * i2c_setaddress - Sets the target slave address
+ * @i2c_addr:	target i2c address
+ *
+ * Sets the target slave address.
+ */
+static void i2c_setaddress(unsigned int i2c_addr)
+{
+	writel(i2c_addr, &i2c_regs_p->ic_tar);
+}
+
+/*
+ * i2c_flush_rxfifo - Flushes the i2c RX FIFO
+ *
+ * Flushes the i2c RX FIFO
+ */
+static void i2c_flush_rxfifo(void)
+{
+	while (readl(&i2c_regs_p->ic_status) & IC_STATUS_RFNE)
+		readl(&i2c_regs_p->ic_cmd_data);
+}
+
+/*
+ * i2c_wait_for_bb - Waits for bus busy
+ *
+ * Waits for bus busy
+ */
+static int i2c_wait_for_bb(void)
+{
+	unsigned long start_time_bb = get_timer(0);
+
+	while ((readl(&i2c_regs_p->ic_status) & IC_STATUS_MA) ||
+	       !(readl(&i2c_regs_p->ic_status) & IC_STATUS_TFE)) {
+
+		/* Evaluate timeout */
+		if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
+			return 1;
+	}
+
+	return 0;
+}
+
+/* check parameters for i2c_read and i2c_write */
+static int check_params(uint addr, int alen, uchar *buffer, int len)
+{
+	if (buffer == NULL) {
+		printf("Buffer is invalid\n");
+		return 1;
+	}
+
+	if (alen > 1) {
+		printf("addr len %d not supported\n", alen);
+		return 1;
+	}
+
+	if (addr + len > 256) {
+		printf("address out of range\n");
+		return 1;
+	}
+
+	return 0;
+}
+
+static int i2c_xfer_init(uchar chip, uint addr)
+{
+	if (i2c_wait_for_bb()) {
+		printf("Timed out waiting for bus\n");
+		return 1;
+	}
+
+	i2c_setaddress(chip);
+	writel(addr, &i2c_regs_p->ic_cmd_data);
+
+	return 0;
+}
+
+static int i2c_xfer_finish(void)
+{
+	ulong start_stop_det = get_timer(0);
+
+	while (1) {
+		if ((readl(&i2c_regs_p->ic_raw_intr_stat) & IC_STOP_DET)) {
+			readl(&i2c_regs_p->ic_clr_stop_det);
+			break;
+		} else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
+			break;
+		}
+	}
+
+	if (i2c_wait_for_bb()) {
+		printf("Timed out waiting for bus\n");
+		return 1;
+	}
+
+	i2c_flush_rxfifo();
+
+	/* Wait for read/write operation to complete on actual memory */
+	udelay(10000);
+
+	return 0;
+}
+
+/*
+ * i2c_read - Read from i2c memory
+ * @chip:	target i2c address
+ * @addr:	address to read from
+ * @alen:
+ * @buffer:	buffer for read data
+ * @len:	no of bytes to be read
+ *
+ * Read from i2c memory.
+ */
+int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
+{
+	unsigned long start_time_rx;
+
+	if (check_params(addr, alen, buffer, len))
+		return 1;
+
+	if (i2c_xfer_init(chip, addr))
+		return 1;
+
+	start_time_rx = get_timer(0);
+	while (len) {
+		writel(IC_CMD, &i2c_regs_p->ic_cmd_data);
+
+		if (readl(&i2c_regs_p->ic_status) & IC_STATUS_RFNE) {
+			*buffer++ = (uchar)readl(&i2c_regs_p->ic_cmd_data);
+			len--;
+			start_time_rx = get_timer(0);
+
+		} else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
+				printf("Timed out. i2c read Failed\n");
+				return 1;
+		}
+	}
+
+	return i2c_xfer_finish();
+}
+
+/*
+ * i2c_write - Write to i2c memory
+ * @chip:	target i2c address
+ * @addr:	address to read from
+ * @alen:
+ * @buffer:	buffer for read data
+ * @len:	no of bytes to be read
+ *
+ * Write to i2c memory.
+ */
+int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
+{
+	int nb = len;
+	unsigned long start_time_tx;
+
+	if (check_params(addr, alen, buffer, len))
+		return 1;
+
+	if (i2c_xfer_init(chip, addr))
+		return 1;
+
+	start_time_tx = get_timer(0);
+	while (len) {
+		if (readl(&i2c_regs_p->ic_status) & IC_STATUS_TFNF) {
+			writel(*buffer, &i2c_regs_p->ic_cmd_data);
+			buffer++;
+			len--;
+			start_time_tx = get_timer(0);
+
+		} else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
+				printf("Timed out. i2c write Failed\n");
+				return 1;
+		}
+	}
+
+	return i2c_xfer_finish();
+}
+
+/*
+ * i2c_probe - Probe the i2c chip
+ */
+int i2c_probe(uchar chip)
+{
+	u32 tmp;
+
+	/*
+	 * Try to read the first location of the chip.
+	 */
+	return i2c_read(chip, 0, 1, (uchar *)&tmp, 1);
+}
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __DW_I2C_H_
+#define __DW_I2C_H_
+
+struct i2c_regs {
+	u32 ic_con;
+	u32 ic_tar;
+	u32 ic_sar;
+	u32 ic_hs_maddr;
+	u32 ic_cmd_data;
+	u32 ic_ss_scl_hcnt;
+	u32 ic_ss_scl_lcnt;
+	u32 ic_fs_scl_hcnt;
+	u32 ic_fs_scl_lcnt;
+	u32 ic_hs_scl_hcnt;
+	u32 ic_hs_scl_lcnt;
+	u32 ic_intr_stat;
+	u32 ic_intr_mask;
+	u32 ic_raw_intr_stat;
+	u32 ic_rx_tl;
+	u32 ic_tx_tl;
+	u32 ic_clr_intr;
+	u32 ic_clr_rx_under;
+	u32 ic_clr_rx_over;
+	u32 ic_clr_tx_over;
+	u32 ic_clr_rd_req;
+	u32 ic_clr_tx_abrt;
+	u32 ic_clr_rx_done;
+	u32 ic_clr_activity;
+	u32 ic_clr_stop_det;
+	u32 ic_clr_start_det;
+	u32 ic_clr_gen_call;
+	u32 ic_enable;
+	u32 ic_status;
+	u32 ic_txflr;
+	u32 ix_rxflr;
+	u32 reserved_1;
+	u32 ic_tx_abrt_source;
+};
+
+#define IC_CLK			166
+#define NANO_TO_MICRO		1000
+
+/* High and low times in different speed modes (in ns) */
+#define MIN_SS_SCL_HIGHTIME	4000
+#define MIN_SS_SCL_LOWTIME	5000
+#define MIN_FS_SCL_HIGHTIME	800
+#define MIN_FS_SCL_LOWTIME	1700
+#define MIN_HS_SCL_HIGHTIME	60
+#define MIN_HS_SCL_LOWTIME	160
+
+/* Worst case timeout for 1 byte is kept as 2ms */
+#define I2C_BYTE_TO		(CONFIG_SYS_HZ/500)
+#define I2C_STOPDET_TO		(CONFIG_SYS_HZ/500)
+#define I2C_BYTE_TO_BB		(I2C_BYTE_TO * 16)
+
+/* i2c control register definitions */
+#define IC_CON_SD		0x0040
+#define IC_CON_RE		0x0020
+#define IC_CON_10BITADDRMASTER	0x0010
+#define IC_CON_10BITADDR_SLAVE	0x0008
+#define IC_CON_SPD_MSK		0x0006
+#define IC_CON_SPD_SS		0x0002
+#define IC_CON_SPD_FS		0x0004
+#define IC_CON_SPD_HS		0x0006
+#define IC_CON_MM		0x0001
+
+/* i2c target address register definitions */
+#define TAR_ADDR		0x0050
+
+/* i2c slave address register definitions */
+#define IC_SLAVE_ADDR		0x0002
+
+/* i2c data buffer and command register definitions */
+#define IC_CMD			0x0100
+
+/* i2c interrupt status register definitions */
+#define IC_GEN_CALL		0x0800
+#define IC_START_DET		0x0400
+#define IC_STOP_DET		0x0200
+#define IC_ACTIVITY		0x0100
+#define IC_RX_DONE		0x0080
+#define IC_TX_ABRT		0x0040
+#define IC_RD_REQ		0x0020
+#define IC_TX_EMPTY		0x0010
+#define IC_TX_OVER		0x0008
+#define IC_RX_FULL		0x0004
+#define IC_RX_OVER 		0x0002
+#define IC_RX_UNDER		0x0001
+
+/* fifo threshold register definitions */
+#define IC_TL0			0x00
+#define IC_TL1			0x01
+#define IC_TL2			0x02
+#define IC_TL3			0x03
+#define IC_TL4			0x04
+#define IC_TL5			0x05
+#define IC_TL6			0x06
+#define IC_TL7			0x07
+#define IC_RX_TL		IC_TL0
+#define IC_TX_TL		IC_TL0
+
+/* i2c enable register definitions */
+#define IC_ENABLE_0B		0x0001
+
+/* i2c status register  definitions */
+#define IC_STATUS_SA		0x0040
+#define IC_STATUS_MA		0x0020
+#define IC_STATUS_RFF		0x0010
+#define IC_STATUS_RFNE		0x0008
+#define IC_STATUS_TFE		0x0004
+#define IC_STATUS_TFNF		0x0002
+#define IC_STATUS_ACT		0x0001
+
+/* Speed Selection */
+#define IC_SPEED_MODE_STANDARD	1
+#define IC_SPEED_MODE_FAST	2
+#define IC_SPEED_MODE_MAX	3
+
+#define I2C_MAX_SPEED		3400000
+#define I2C_FAST_SPEED		400000
+#define I2C_STANDARD_SPEED	100000
+
+#endif /* __DW_I2C_H_ */
+/*
+ * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+
+struct sh_i2c {
+	u8 iccr1;
+	u8 iccr2;
+	u8 icmr;
+	u8 icier;
+	u8 icsr;
+	u8 sar;
+	u8 icdrt;
+	u8 icdrr;
+	u8 nf2cyc;
+	u8 __pad0;
+	u8 __pad1;
+};
+
+static struct sh_i2c *base;
+static u8 iccr1_cks, nf2cyc;
+
+/* ICCR1 */
+#define SH_I2C_ICCR1_ICE	(1 << 7)
+#define SH_I2C_ICCR1_RCVD	(1 << 6)
+#define SH_I2C_ICCR1_MST	(1 << 5)
+#define SH_I2C_ICCR1_TRS	(1 << 4)
+#define SH_I2C_ICCR1_MTRS	\
+	(SH_I2C_ICCR1_MST | SH_I2C_ICCR1_TRS)
+
+/* ICCR1 */
+#define SH_I2C_ICCR2_BBSY	(1 << 7)
+#define SH_I2C_ICCR2_SCP	(1 << 6)
+#define SH_I2C_ICCR2_SDAO	(1 << 5)
+#define SH_I2C_ICCR2_SDAOP	(1 << 4)
+#define SH_I2C_ICCR2_SCLO	(1 << 3)
+#define SH_I2C_ICCR2_IICRST	(1 << 1)
+
+#define SH_I2C_ICIER_TIE	(1 << 7)
+#define SH_I2C_ICIER_TEIE	(1 << 6)
+#define SH_I2C_ICIER_RIE	(1 << 5)
+#define SH_I2C_ICIER_NAKIE	(1 << 4)
+#define SH_I2C_ICIER_STIE	(1 << 3)
+#define SH_I2C_ICIER_ACKE	(1 << 2)
+#define SH_I2C_ICIER_ACKBR	(1 << 1)
+#define SH_I2C_ICIER_ACKBT	(1 << 0)
+
+#define SH_I2C_ICSR_TDRE	(1 << 7)
+#define SH_I2C_ICSR_TEND	(1 << 6)
+#define SH_I2C_ICSR_RDRF	(1 << 5)
+#define SH_I2C_ICSR_NACKF	(1 << 4)
+#define SH_I2C_ICSR_STOP	(1 << 3)
+#define SH_I2C_ICSR_ALOVE	(1 << 2)
+#define SH_I2C_ICSR_AAS		(1 << 1)
+#define SH_I2C_ICSR_ADZ		(1 << 0)
+
+#define IRQ_WAIT 1000
+
+static void sh_i2c_send_stop(struct sh_i2c *base)
+{
+	clrbits_8(&base->iccr2, SH_I2C_ICCR2_BBSY | SH_I2C_ICCR2_SCP);
+}
+
+static int check_icsr_bits(struct sh_i2c *base, u8 bits)
+{
+	int i;
+
+	for (i = 0; i < IRQ_WAIT; i++) {
+		if (bits & readb(&base->icsr))
+			return 0;
+		udelay(10);
+	}
+
+	return 1;
+}
+
+static int check_stop(struct sh_i2c *base)
+{
+	int ret = check_icsr_bits(base, SH_I2C_ICSR_STOP);
+	clrbits_8(&base->icsr, SH_I2C_ICSR_STOP);
+
+	return ret;
+}
+
+static int check_tend(struct sh_i2c *base, int stop)
+{
+	int ret = check_icsr_bits(base, SH_I2C_ICSR_TEND);
+
+	if (stop) {
+		clrbits_8(&base->icsr, SH_I2C_ICSR_STOP);
+		sh_i2c_send_stop(base);
+	}
+
+	clrbits_8(&base->icsr, SH_I2C_ICSR_TEND);
+	return ret;
+}
+
+static int check_tdre(struct sh_i2c *base)
+{
+	return check_icsr_bits(base, SH_I2C_ICSR_TDRE);
+}
+
+static int check_rdrf(struct sh_i2c *base)
+{
+	return check_icsr_bits(base, SH_I2C_ICSR_RDRF);
+}
+
+static int check_bbsy(struct sh_i2c *base)
+{
+	int i;
+
+	for (i = 0 ; i < IRQ_WAIT ; i++) {
+		if (!(SH_I2C_ICCR2_BBSY & readb(&base->iccr2)))
+			return 0;
+		udelay(10);
+	}
+	return 1;
+}
+
+static int check_ackbr(struct sh_i2c *base)
+{
+	int i;
+
+	for (i = 0 ; i < IRQ_WAIT ; i++) {
+		if (!(SH_I2C_ICIER_ACKBR & readb(&base->icier)))
+			return 0;
+		udelay(10);
+	}
+
+	return 1;
+}
+
+static void sh_i2c_reset(struct sh_i2c *base)
+{
+	setbits_8(&base->iccr2, SH_I2C_ICCR2_IICRST);
+
+	udelay(100);
+
+	clrbits_8(&base->iccr2, SH_I2C_ICCR2_IICRST);
+}
+
+static int i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg)
+{
+	if (check_bbsy(base)) {
+		puts("i2c bus busy\n");
+		goto fail;
+	}
+
+	setbits_8(&base->iccr1, SH_I2C_ICCR1_MTRS);
+	clrsetbits_8(&base->iccr2, SH_I2C_ICCR2_SCP, SH_I2C_ICCR2_BBSY);
+
+	writeb((id << 1), &base->icdrt);
+
+	if (check_tend(base, 0)) {
+		puts("TEND check fail...\n");
+		goto fail;
+	}
+
+	if (check_ackbr(base)) {
+		check_tend(base, 0);
+		sh_i2c_send_stop(base);
+		goto fail;
+	}
+
+	writeb(reg, &base->icdrt);
+
+	if (check_tdre(base)) {
+		puts("TDRE check fail...\n");
+		goto fail;
+	}
+
+	if (check_tend(base, 0)) {
+		puts("TEND check fail...\n");
+		goto fail;
+	}
+
+	return 0;
+fail:
+
+	return 1;
+}
+
+static int
+i2c_raw_write(struct sh_i2c *base, u8 id, u8 reg, u8 *val, int size)
+{
+	int i;
+
+	if (i2c_set_addr(base, id, reg)) {
+		puts("Fail set slave address\n");
+		return 1;
+	}
+
+	for (i = 0; i < size; i++) {
+		writeb(val[i], &base->icdrt);
+		check_tdre(base);
+	}
+
+	check_tend(base, 1);
+	check_stop(base);
+
+	udelay(100);
+
+	clrbits_8(&base->iccr1, SH_I2C_ICCR1_MTRS);
+	clrbits_8(&base->icsr, SH_I2C_ICSR_TDRE);
+	sh_i2c_reset(base);
+
+	return 0;
+}
+
+static u8 i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg)
+{
+	u8 ret = 0;
+
+	if (i2c_set_addr(base, id, reg)) {
+		puts("Fail set slave address\n");
+		goto fail;
+	}
+
+	clrsetbits_8(&base->iccr2, SH_I2C_ICCR2_SCP, SH_I2C_ICCR2_BBSY);
+	writeb((id << 1) | 1, &base->icdrt);
+
+	if (check_tend(base, 0))
+		puts("TDRE check fail...\n");
+
+	clrsetbits_8(&base->iccr1, SH_I2C_ICCR1_TRS, SH_I2C_ICCR1_MST);
+	clrbits_8(&base->icsr, SH_I2C_ICSR_TDRE);
+	setbits_8(&base->icier, SH_I2C_ICIER_ACKBT);
+	setbits_8(&base->iccr1, SH_I2C_ICCR1_RCVD);
+
+	/* read data (dummy) */
+	ret = readb(&base->icdrr);
+
+	if (check_rdrf(base)) {
+		puts("check RDRF error\n");
+		goto fail;
+	}
+
+	clrbits_8(&base->icsr, SH_I2C_ICSR_STOP);
+	udelay(1000);
+
+	sh_i2c_send_stop(base);
+
+	if (check_stop(base)) {
+		puts("check STOP error\n");
+		goto fail;
+	}
+
+	clrbits_8(&base->iccr1, SH_I2C_ICCR1_MTRS);
+	clrbits_8(&base->icsr, SH_I2C_ICSR_TDRE);
+
+	/* data read */
+	ret = readb(&base->icdrr);
+
+fail:
+	clrbits_8(&base->iccr1, SH_I2C_ICCR1_RCVD);
+
+	return ret;
+}
+
+#ifdef CONFIG_I2C_MULTI_BUS
+static unsigned int current_bus;
+
+/**
+ * i2c_set_bus_num - change active I2C bus
+ *	@bus: bus index, zero based
+ *	@returns: 0 on success, non-0 on failure
+ */
+int i2c_set_bus_num(unsigned int bus)
+{
+	switch (bus) {
+	case 0:
+		base = (void *)CONFIG_SH_I2C_BASE0;
+		break;
+	case 1:
+		base = (void *)CONFIG_SH_I2C_BASE1;
+		break;
+	default:
+		printf("Bad bus: %d\n", bus);
+		return -1;
+	}
+
+	current_bus = bus;
+
+	return 0;
+}
+
+/**
+ * i2c_get_bus_num - returns index of active I2C bus
+ */
+unsigned int i2c_get_bus_num(void)
+{
+	return current_bus;
+}
+#endif
+
+void i2c_init(int speed, int slaveaddr)
+{
+#ifdef CONFIG_I2C_MULTI_BUS
+	current_bus = 0;
+#endif
+	base = (struct sh_i2c *)CONFIG_SH_I2C_BASE0;
+
+	if (speed == 400000)
+		iccr1_cks = 0x07;
+	else
+		iccr1_cks = 0x0F;
+
+	nf2cyc = 1;
+
+	/* Reset */
+	sh_i2c_reset(base);
+
+	/* ICE enable and set clock */
+	writeb(SH_I2C_ICCR1_ICE | iccr1_cks, &base->iccr1);
+	writeb(nf2cyc, &base->nf2cyc);
+}
+
+/*
+ * i2c_read: - Read multiple bytes from an i2c device
+ *
+ * The higher level routines take into account that this function is only
+ * called with len < page length of the device (see configuration file)
+ *
+ * @chip:   address of the chip which is to be read
+ * @addr:   i2c data address within the chip
+ * @alen:   length of the i2c data address (1..2 bytes)
+ * @buffer: where to write the data
+ * @len:    how much byte do we want to read
+ * @return: 0 in case of success
+ */
+int i2c_read(u8 chip, u32 addr, int alen, u8 *buffer, int len)
+{
+	int i = 0;
+	for (i = 0; i < len; i++)
+		buffer[i] = i2c_raw_read(base, chip, addr + i);
+
+	return 0;
+}
+
+/*
+ * i2c_write: -  Write multiple bytes to an i2c device
+ *
+ * The higher level routines take into account that this function is only
+ * called with len < page length of the device (see configuration file)
+ *
+ * @chip:   address of the chip which is to be written
+ * @addr:   i2c data address within the chip
+ * @alen:   length of the i2c data address (1..2 bytes)
+ * @buffer: where to find the data to be written
+ * @len:    how much byte do we want to read
+ * @return: 0 in case of success
+ */
+int i2c_write(u8 chip, u32 addr, int alen, u8 *buffer, int len)
+{
+	return i2c_raw_write(base, chip, addr, buffer, len);
+}
+
+/*
+ * i2c_probe: - Test if a chip answers for a given i2c address
+ *
+ * @chip:   address of the chip which is searched for
+ * @return: 0 if a chip was found, -1 otherwhise
+ */
+int i2c_probe(u8 chip)
+{
+	u8 byte;
+	return i2c_read(chip, 0, 0, &byte, 1);
+}
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spr_i2c.h>
-
-static struct i2c_regs *const i2c_regs_p =
-    (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
-
-/*
- * set_speed - Set the i2c speed mode (standard, high, fast)
- * @i2c_spd:	required i2c speed mode
- *
- * Set the i2c speed mode (standard, high, fast)
- */
-static void set_speed(int i2c_spd)
-{
-	unsigned int cntl;
-	unsigned int hcnt, lcnt;
-	unsigned int high, low;
-
-	cntl = (readl(&i2c_regs_p->ic_con) & (~IC_CON_SPD_MSK));
-
-	switch (i2c_spd) {
-	case IC_SPEED_MODE_MAX:
-		cntl |= IC_CON_SPD_HS;
-		high = MIN_HS_SCL_HIGHTIME;
-		low = MIN_HS_SCL_LOWTIME;
-		break;
-
-	case IC_SPEED_MODE_STANDARD:
-		cntl |= IC_CON_SPD_SS;
-		high = MIN_SS_SCL_HIGHTIME;
-		low = MIN_SS_SCL_LOWTIME;
-		break;
-
-	case IC_SPEED_MODE_FAST:
-	default:
-		cntl |= IC_CON_SPD_FS;
-		high = MIN_FS_SCL_HIGHTIME;
-		low = MIN_FS_SCL_LOWTIME;
-		break;
-	}
-
-	writel(cntl, &i2c_regs_p->ic_con);
-
-	hcnt = (IC_CLK * high) / NANO_TO_MICRO;
-	writel(hcnt, &i2c_regs_p->ic_fs_scl_hcnt);
-
-	lcnt = (IC_CLK * low) / NANO_TO_MICRO;
-	writel(lcnt, &i2c_regs_p->ic_fs_scl_lcnt);
-}
-
-/*
- * i2c_set_bus_speed - Set the i2c speed
- * @speed:	required i2c speed
- *
- * Set the i2c speed.
- */
-void i2c_set_bus_speed(int speed)
-{
-	if (speed >= I2C_MAX_SPEED)
-		set_speed(IC_SPEED_MODE_MAX);
-	else if (speed >= I2C_FAST_SPEED)
-		set_speed(IC_SPEED_MODE_FAST);
-	else
-		set_speed(IC_SPEED_MODE_STANDARD);
-}
-
-/*
- * i2c_get_bus_speed - Gets the i2c speed
- *
- * Gets the i2c speed.
- */
-int i2c_get_bus_speed(void)
-{
-	u32 cntl;
-
-	cntl = (readl(&i2c_regs_p->ic_con) & IC_CON_SPD_MSK);
-
-	if (cntl == IC_CON_SPD_HS)
-		return I2C_MAX_SPEED;
-	else if (cntl == IC_CON_SPD_FS)
-		return I2C_FAST_SPEED;
-	else if (cntl == IC_CON_SPD_SS)
-		return I2C_STANDARD_SPEED;
-
-	return 0;
-}
-
-/*
- * i2c_init - Init function
- * @speed:	required i2c speed
- * @slaveadd:	slave address for the spear device
- *
- * Initialization function.
- */
-void i2c_init(int speed, int slaveadd)
-{
-	unsigned int enbl;
-
-	/* Disable i2c */
-	enbl = readl(&i2c_regs_p->ic_enable);
-	enbl &= ~IC_ENABLE_0B;
-	writel(enbl, &i2c_regs_p->ic_enable);
-
-	writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_regs_p->ic_con);
-	writel(IC_RX_TL, &i2c_regs_p->ic_rx_tl);
-	writel(IC_TX_TL, &i2c_regs_p->ic_tx_tl);
-	i2c_set_bus_speed(speed);
-	writel(IC_STOP_DET, &i2c_regs_p->ic_intr_mask);
-	writel(slaveadd, &i2c_regs_p->ic_sar);
-
-	/* Enable i2c */
-	enbl = readl(&i2c_regs_p->ic_enable);
-	enbl |= IC_ENABLE_0B;
-	writel(enbl, &i2c_regs_p->ic_enable);
-}
-
-/*
- * i2c_setaddress - Sets the target slave address
- * @i2c_addr:	target i2c address
- *
- * Sets the target slave address.
- */
-static void i2c_setaddress(unsigned int i2c_addr)
-{
-	writel(i2c_addr, &i2c_regs_p->ic_tar);
-}
-
-/*
- * i2c_flush_rxfifo - Flushes the i2c RX FIFO
- *
- * Flushes the i2c RX FIFO
- */
-static void i2c_flush_rxfifo(void)
-{
-	while (readl(&i2c_regs_p->ic_status) & IC_STATUS_RFNE)
-		readl(&i2c_regs_p->ic_cmd_data);
-}
-
-/*
- * i2c_wait_for_bb - Waits for bus busy
- *
- * Waits for bus busy
- */
-static int i2c_wait_for_bb(void)
-{
-	unsigned long start_time_bb = get_timer(0);
-
-	while ((readl(&i2c_regs_p->ic_status) & IC_STATUS_MA) ||
-	       !(readl(&i2c_regs_p->ic_status) & IC_STATUS_TFE)) {
-
-		/* Evaluate timeout */
-		if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
-			return 1;
-	}
-
-	return 0;
-}
-
-/* check parameters for i2c_read and i2c_write */
-static int check_params(uint addr, int alen, uchar *buffer, int len)
-{
-	if (buffer == NULL) {
-		printf("Buffer is invalid\n");
-		return 1;
-	}
-
-	if (alen > 1) {
-		printf("addr len %d not supported\n", alen);
-		return 1;
-	}
-
-	if (addr + len > 256) {
-		printf("address out of range\n");
-		return 1;
-	}
-
-	return 0;
-}
-
-static int i2c_xfer_init(uchar chip, uint addr)
-{
-	if (i2c_wait_for_bb()) {
-		printf("Timed out waiting for bus\n");
-		return 1;
-	}
-
-	i2c_setaddress(chip);
-	writel(addr, &i2c_regs_p->ic_cmd_data);
-
-	return 0;
-}
-
-static int i2c_xfer_finish(void)
-{
-	ulong start_stop_det = get_timer(0);
-
-	while (1) {
-		if ((readl(&i2c_regs_p->ic_raw_intr_stat) & IC_STOP_DET)) {
-			readl(&i2c_regs_p->ic_clr_stop_det);
-			break;
-		} else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
-			break;
-		}
-	}
-
-	if (i2c_wait_for_bb()) {
-		printf("Timed out waiting for bus\n");
-		return 1;
-	}
-
-	i2c_flush_rxfifo();
-
-	/* Wait for read/write operation to complete on actual memory */
-	udelay(10000);
-
-	return 0;
-}
-
-/*
- * i2c_read - Read from i2c memory
- * @chip:	target i2c address
- * @addr:	address to read from
- * @alen:
- * @buffer:	buffer for read data
- * @len:	no of bytes to be read
- *
- * Read from i2c memory.
- */
-int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
-{
-	unsigned long start_time_rx;
-
-	if (check_params(addr, alen, buffer, len))
-		return 1;
-
-	if (i2c_xfer_init(chip, addr))
-		return 1;
-
-	start_time_rx = get_timer(0);
-	while (len) {
-		writel(IC_CMD, &i2c_regs_p->ic_cmd_data);
-
-		if (readl(&i2c_regs_p->ic_status) & IC_STATUS_RFNE) {
-			*buffer++ = (uchar)readl(&i2c_regs_p->ic_cmd_data);
-			len--;
-			start_time_rx = get_timer(0);
-
-		} else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
-				printf("Timed out. i2c read Failed\n");
-				return 1;
-		}
-	}
-
-	return i2c_xfer_finish();
-}
-
-/*
- * i2c_write - Write to i2c memory
- * @chip:	target i2c address
- * @addr:	address to read from
- * @alen:
- * @buffer:	buffer for read data
- * @len:	no of bytes to be read
- *
- * Write to i2c memory.
- */
-int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
-{
-	int nb = len;
-	unsigned long start_time_tx;
-
-	if (check_params(addr, alen, buffer, len))
-		return 1;
-
-	if (i2c_xfer_init(chip, addr))
-		return 1;
-
-	start_time_tx = get_timer(0);
-	while (len) {
-		if (readl(&i2c_regs_p->ic_status) & IC_STATUS_TFNF) {
-			writel(*buffer, &i2c_regs_p->ic_cmd_data);
-			buffer++;
-			len--;
-			start_time_tx = get_timer(0);
-
-		} else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
-				printf("Timed out. i2c write Failed\n");
-				return 1;
-		}
-	}
-
-	return i2c_xfer_finish();
-}
-
-/*
- * i2c_probe - Probe the i2c chip
- */
-int i2c_probe(uchar chip)
-{
-	u32 tmp;
-
-	/*
-	 * Try to read the first location of the chip.
-	 */
-	return i2c_read(chip, 0, 1, (uchar *)&tmp, 1);
-}
@@ -41,7 +41,7 @@
  
 /* I2C driver configuration */
 #define CONFIG_HARD_I2C
-#define CONFIG_SPEAR_I2C
+#define CONFIG_DW_I2C
 #define CONFIG_SYS_I2C_SPEED			400000
 #define CONFIG_SYS_I2C_SLAVE			0x02
1		-/*
2		- * (C) Copyright 2009
3		- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
4		- *
5		- * See file CREDITS for list of people who contributed to this
6		- * project.
7		- *
8		- * This program is free software; you can redistribute it and/or
9		- * modify it under the terms of the GNU General Public License as
10		- * published by the Free Software Foundation; either version 2 of
11		- * the License, or (at your option) any later version.
12		- *
13		- * This program is distributed in the hope that it will be useful,
14		- * but WITHOUT ANY WARRANTY; without even the implied warranty of
15		- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16		- * GNU General Public License for more details.
17		- *
18		- * You should have received a copy of the GNU General Public License
19		- * along with this program; if not, write to the Free Software
20		- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21		- * MA 02111-1307 USA
22		- */
23		-
24		-#ifndef __SPR_I2C_H_
25		-#define __SPR_I2C_H_
26		-
27		-struct i2c_regs {
28		- u32 ic_con;
29		- u32 ic_tar;
30		- u32 ic_sar;
31		- u32 ic_hs_maddr;
32		- u32 ic_cmd_data;
33		- u32 ic_ss_scl_hcnt;
34		- u32 ic_ss_scl_lcnt;
35		- u32 ic_fs_scl_hcnt;
36		- u32 ic_fs_scl_lcnt;
37		- u32 ic_hs_scl_hcnt;
38		- u32 ic_hs_scl_lcnt;
39		- u32 ic_intr_stat;
40		- u32 ic_intr_mask;
41		- u32 ic_raw_intr_stat;
42		- u32 ic_rx_tl;
43		- u32 ic_tx_tl;
44		- u32 ic_clr_intr;
45		- u32 ic_clr_rx_under;
46		- u32 ic_clr_rx_over;
47		- u32 ic_clr_tx_over;
48		- u32 ic_clr_rd_req;
49		- u32 ic_clr_tx_abrt;
50		- u32 ic_clr_rx_done;
51		- u32 ic_clr_activity;
52		- u32 ic_clr_stop_det;
53		- u32 ic_clr_start_det;
54		- u32 ic_clr_gen_call;
55		- u32 ic_enable;
56		- u32 ic_status;
57		- u32 ic_txflr;
58		- u32 ix_rxflr;
59		- u32 reserved_1;
60		- u32 ic_tx_abrt_source;
61		-};
62		-
63		-#define IC_CLK 166
64		-#define NANO_TO_MICRO 1000
65		-
66		-/* High and low times in different speed modes (in ns) */
67		-#define MIN_SS_SCL_HIGHTIME 4000
68		-#define MIN_SS_SCL_LOWTIME 5000
69		-#define MIN_FS_SCL_HIGHTIME 800
70		-#define MIN_FS_SCL_LOWTIME 1700
71		-#define MIN_HS_SCL_HIGHTIME 60
72		-#define MIN_HS_SCL_LOWTIME 160
73		-
74		-/* Worst case timeout for 1 byte is kept as 2ms */
75		-#define I2C_BYTE_TO (CONFIG_SYS_HZ/500)
76		-#define I2C_STOPDET_TO (CONFIG_SYS_HZ/500)
77		-#define I2C_BYTE_TO_BB (I2C_BYTE_TO * 16)
78		-
79		-/* i2c control register definitions */
80		-#define IC_CON_SD 0x0040
81		-#define IC_CON_RE 0x0020
82		-#define IC_CON_10BITADDRMASTER 0x0010
83		-#define IC_CON_10BITADDR_SLAVE 0x0008
84		-#define IC_CON_SPD_MSK 0x0006
85		-#define IC_CON_SPD_SS 0x0002
86		-#define IC_CON_SPD_FS 0x0004
87		-#define IC_CON_SPD_HS 0x0006
88		-#define IC_CON_MM 0x0001
89		-
90		-/* i2c target address register definitions */
91		-#define TAR_ADDR 0x0050
92		-
93		-/* i2c slave address register definitions */
94		-#define IC_SLAVE_ADDR 0x0002
95		-
96		-/* i2c data buffer and command register definitions */
97		-#define IC_CMD 0x0100
98		-
99		-/* i2c interrupt status register definitions */
100		-#define IC_GEN_CALL 0x0800
101		-#define IC_START_DET 0x0400
102		-#define IC_STOP_DET 0x0200
103		-#define IC_ACTIVITY 0x0100
104		-#define IC_RX_DONE 0x0080
105		-#define IC_TX_ABRT 0x0040
106		-#define IC_RD_REQ 0x0020
107		-#define IC_TX_EMPTY 0x0010
108		-#define IC_TX_OVER 0x0008
109		-#define IC_RX_FULL 0x0004
110		-#define IC_RX_OVER 0x0002
111		-#define IC_RX_UNDER 0x0001
112		-
113		-/* fifo threshold register definitions */
114		-#define IC_TL0 0x00
115		-#define IC_TL1 0x01
116		-#define IC_TL2 0x02
117		-#define IC_TL3 0x03
118		-#define IC_TL4 0x04
119		-#define IC_TL5 0x05
120		-#define IC_TL6 0x06
121		-#define IC_TL7 0x07
122		-#define IC_RX_TL IC_TL0
123		-#define IC_TX_TL IC_TL0
124		-
125		-/* i2c enable register definitions */
126		-#define IC_ENABLE_0B 0x0001
127		-
128		-/* i2c status register definitions */
129		-#define IC_STATUS_SA 0x0040
130		-#define IC_STATUS_MA 0x0020
131		-#define IC_STATUS_RFF 0x0010
132		-#define IC_STATUS_RFNE 0x0008
133		-#define IC_STATUS_TFE 0x0004
134		-#define IC_STATUS_TFNF 0x0002
135		-#define IC_STATUS_ACT 0x0001
136		-
137		-/* Speed Selection */
138		-#define IC_SPEED_MODE_STANDARD 1
139		-#define IC_SPEED_MODE_FAST 2
140		-#define IC_SPEED_MODE_MAX 3
141		-
142		-#define I2C_MAX_SPEED 3400000
143		-#define I2C_FAST_SPEED 400000
144		-#define I2C_STANDARD_SPEED 100000
145		-
146		-#endif /* __SPR_I2C_H_ */
...	...	@@ -27,6 +27,7 @@
27	27
28	28	COBJS-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o
29	29	COBJS-$(CONFIG_DRIVER_DAVINCI_I2C) += davinci_i2c.o
	30	+COBJS-$(CONFIG_DW_I2C) += designware_i2c.o
30	31	COBJS-$(CONFIG_FSL_I2C) += fsl_i2c.o
31	32	COBJS-$(CONFIG_I2C_MVTWSI) += mvtwsi.o
32	33	COBJS-$(CONFIG_I2C_MV) += mv_i2c.o
33	34
...	...	@@ -40,11 +41,11 @@
40	41	COBJS-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o
41	42	COBJS-$(CONFIG_S3C44B0_I2C) += s3c44b0_i2c.o
42	43	COBJS-$(CONFIG_SOFT_I2C) += soft_i2c.o
43		-COBJS-$(CONFIG_SPEAR_I2C) += spr_i2c.o
44	44	COBJS-$(CONFIG_TEGRA_I2C) += tegra_i2c.o
45	45	COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
46	46	COBJS-$(CONFIG_U8500_I2C) += u8500_i2c.o
47	47	COBJS-$(CONFIG_SH_I2C) += sh_i2c.o
	48	+COBJS-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
48	49
49	50	COBJS := $(COBJS-y)
50	51	SRCS := $(COBJS:.o=.c)
	1	+/*
	2	+ * (C) Copyright 2009
	3	+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
	4	+ *
	5	+ * See file CREDITS for list of people who contributed to this
	6	+ * project.
	7	+ *
	8	+ * This program is free software; you can redistribute it and/or
	9	+ * modify it under the terms of the GNU General Public License as
	10	+ * published by the Free Software Foundation; either version 2 of
	11	+ * the License, or (at your option) any later version.
	12	+ *
	13	+ * This program is distributed in the hope that it will be useful,
	14	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+ * GNU General Public License for more details.
	17	+ *
	18	+ * You should have received a copy of the GNU General Public License
	19	+ * along with this program; if not, write to the Free Software
	20	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+ * MA 02111-1307 USA
	22	+ */
	23	+
	24	+#include <common.h>
	25	+#include <asm/io.h>
	26	+#include <asm/arch/hardware.h>
	27	+#include "designware_i2c.h"
	28	+
	29	+static struct i2c_regs *const i2c_regs_p =
	30	+ (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
	31	+
	32	+/*
	33	+ * set_speed - Set the i2c speed mode (standard, high, fast)
	34	+ * @i2c_spd: required i2c speed mode
	35	+ *
	36	+ * Set the i2c speed mode (standard, high, fast)
	37	+ */
	38	+static void set_speed(int i2c_spd)
	39	+{
	40	+ unsigned int cntl;
	41	+ unsigned int hcnt, lcnt;
	42	+ unsigned int high, low;
	43	+ unsigned int enbl;
	44	+
	45	+ /* to set speed cltr must be disabled */
	46	+ enbl = readl(&i2c_regs_p->ic_enable);
	47	+ enbl &= ~IC_ENABLE_0B;
	48	+ writel(enbl, &i2c_regs_p->ic_enable);
	49	+
	50	+
	51	+ cntl = (readl(&i2c_regs_p->ic_con) & (~IC_CON_SPD_MSK));
	52	+
	53	+ switch (i2c_spd) {
	54	+ case IC_SPEED_MODE_MAX:
	55	+ cntl \|= IC_CON_SPD_HS;
	56	+ high = MIN_HS_SCL_HIGHTIME;
	57	+ low = MIN_HS_SCL_LOWTIME;
	58	+ break;
	59	+
	60	+ case IC_SPEED_MODE_STANDARD:
	61	+ cntl \|= IC_CON_SPD_SS;
	62	+ high = MIN_SS_SCL_HIGHTIME;
	63	+ low = MIN_SS_SCL_LOWTIME;
	64	+ break;
	65	+
	66	+ case IC_SPEED_MODE_FAST:
	67	+ default:
	68	+ cntl \|= IC_CON_SPD_FS;
	69	+ high = MIN_FS_SCL_HIGHTIME;
	70	+ low = MIN_FS_SCL_LOWTIME;
	71	+ break;
	72	+ }
	73	+
	74	+ writel(cntl, &i2c_regs_p->ic_con);
	75	+
	76	+ hcnt = (IC_CLK * high) / NANO_TO_MICRO;
	77	+ writel(hcnt, &i2c_regs_p->ic_fs_scl_hcnt);
	78	+
	79	+ lcnt = (IC_CLK * low) / NANO_TO_MICRO;
	80	+ writel(lcnt, &i2c_regs_p->ic_fs_scl_lcnt);
	81	+
	82	+ /* re-enable i2c ctrl back now that speed is set */
	83	+ enbl \|= IC_ENABLE_0B;
	84	+ writel(enbl, &i2c_regs_p->ic_enable);
	85	+}
	86	+
	87	+/*
	88	+ * i2c_set_bus_speed - Set the i2c speed
	89	+ * @speed: required i2c speed
	90	+ *
	91	+ * Set the i2c speed.
	92	+ */
	93	+void i2c_set_bus_speed(int speed)
	94	+{
	95	+ if (speed >= I2C_MAX_SPEED)
	96	+ set_speed(IC_SPEED_MODE_MAX);
	97	+ else if (speed >= I2C_FAST_SPEED)
	98	+ set_speed(IC_SPEED_MODE_FAST);
	99	+ else
	100	+ set_speed(IC_SPEED_MODE_STANDARD);
	101	+}
	102	+
	103	+/*
	104	+ * i2c_get_bus_speed - Gets the i2c speed
	105	+ *
	106	+ * Gets the i2c speed.
	107	+ */
	108	+int i2c_get_bus_speed(void)
	109	+{
	110	+ u32 cntl;
	111	+
	112	+ cntl = (readl(&i2c_regs_p->ic_con) & IC_CON_SPD_MSK);
	113	+
	114	+ if (cntl == IC_CON_SPD_HS)
	115	+ return I2C_MAX_SPEED;
	116	+ else if (cntl == IC_CON_SPD_FS)
	117	+ return I2C_FAST_SPEED;
	118	+ else if (cntl == IC_CON_SPD_SS)
	119	+ return I2C_STANDARD_SPEED;
	120	+
	121	+ return 0;
	122	+}
	123	+
	124	+/*
	125	+ * i2c_init - Init function
	126	+ * @speed: required i2c speed
	127	+ * @slaveadd: slave address for the device
	128	+ *
	129	+ * Initialization function.
	130	+ */
	131	+void i2c_init(int speed, int slaveadd)
	132	+{
	133	+ unsigned int enbl;
	134	+
	135	+ /* Disable i2c */
	136	+ enbl = readl(&i2c_regs_p->ic_enable);
	137	+ enbl &= ~IC_ENABLE_0B;
	138	+ writel(enbl, &i2c_regs_p->ic_enable);
	139	+
	140	+ writel((IC_CON_SD \| IC_CON_SPD_FS \| IC_CON_MM), &i2c_regs_p->ic_con);
	141	+ writel(IC_RX_TL, &i2c_regs_p->ic_rx_tl);
	142	+ writel(IC_TX_TL, &i2c_regs_p->ic_tx_tl);
	143	+ i2c_set_bus_speed(speed);
	144	+ writel(IC_STOP_DET, &i2c_regs_p->ic_intr_mask);
	145	+ writel(slaveadd, &i2c_regs_p->ic_sar);
	146	+
	147	+ /* Enable i2c */
	148	+ enbl = readl(&i2c_regs_p->ic_enable);
	149	+ enbl \|= IC_ENABLE_0B;
	150	+ writel(enbl, &i2c_regs_p->ic_enable);
	151	+}
	152	+
	153	+/*
	154	+ * i2c_setaddress - Sets the target slave address
	155	+ * @i2c_addr: target i2c address
	156	+ *
	157	+ * Sets the target slave address.
	158	+ */
	159	+static void i2c_setaddress(unsigned int i2c_addr)
	160	+{
	161	+ writel(i2c_addr, &i2c_regs_p->ic_tar);
	162	+}
	163	+
	164	+/*
	165	+ * i2c_flush_rxfifo - Flushes the i2c RX FIFO
	166	+ *
	167	+ * Flushes the i2c RX FIFO
	168	+ */
	169	+static void i2c_flush_rxfifo(void)
	170	+{
	171	+ while (readl(&i2c_regs_p->ic_status) & IC_STATUS_RFNE)
	172	+ readl(&i2c_regs_p->ic_cmd_data);
	173	+}
	174	+
	175	+/*
	176	+ * i2c_wait_for_bb - Waits for bus busy
	177	+ *
	178	+ * Waits for bus busy
	179	+ */
	180	+static int i2c_wait_for_bb(void)
	181	+{
	182	+ unsigned long start_time_bb = get_timer(0);
	183	+
	184	+ while ((readl(&i2c_regs_p->ic_status) & IC_STATUS_MA) \|\|
	185	+ !(readl(&i2c_regs_p->ic_status) & IC_STATUS_TFE)) {
	186	+
	187	+ /* Evaluate timeout */
	188	+ if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
	189	+ return 1;
	190	+ }
	191	+
	192	+ return 0;
	193	+}
	194	+
	195	+/* check parameters for i2c_read and i2c_write */
	196	+static int check_params(uint addr, int alen, uchar *buffer, int len)
	197	+{
	198	+ if (buffer == NULL) {
	199	+ printf("Buffer is invalid\n");
	200	+ return 1;
	201	+ }
	202	+
	203	+ if (alen > 1) {
	204	+ printf("addr len %d not supported\n", alen);
	205	+ return 1;
	206	+ }
	207	+
	208	+ if (addr + len > 256) {
	209	+ printf("address out of range\n");
	210	+ return 1;
	211	+ }
	212	+
	213	+ return 0;
	214	+}
	215	+
	216	+static int i2c_xfer_init(uchar chip, uint addr)
	217	+{
	218	+ if (i2c_wait_for_bb()) {
	219	+ printf("Timed out waiting for bus\n");
	220	+ return 1;
	221	+ }
	222	+
	223	+ i2c_setaddress(chip);
	224	+ writel(addr, &i2c_regs_p->ic_cmd_data);
	225	+
	226	+ return 0;
	227	+}
	228	+
	229	+static int i2c_xfer_finish(void)
	230	+{
	231	+ ulong start_stop_det = get_timer(0);
	232	+
	233	+ while (1) {
	234	+ if ((readl(&i2c_regs_p->ic_raw_intr_stat) & IC_STOP_DET)) {
	235	+ readl(&i2c_regs_p->ic_clr_stop_det);
	236	+ break;
	237	+ } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
	238	+ break;
	239	+ }
	240	+ }
	241	+
	242	+ if (i2c_wait_for_bb()) {
	243	+ printf("Timed out waiting for bus\n");
	244	+ return 1;
	245	+ }
	246	+
	247	+ i2c_flush_rxfifo();
	248	+
	249	+ /* Wait for read/write operation to complete on actual memory */
	250	+ udelay(10000);
	251	+
	252	+ return 0;
	253	+}
	254	+
	255	+/*
	256	+ * i2c_read - Read from i2c memory
	257	+ * @chip: target i2c address
	258	+ * @addr: address to read from
	259	+ * @alen:
	260	+ * @buffer: buffer for read data
	261	+ * @len: no of bytes to be read
	262	+ *
	263	+ * Read from i2c memory.
	264	+ */
	265	+int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
	266	+{
	267	+ unsigned long start_time_rx;
	268	+
	269	+ if (check_params(addr, alen, buffer, len))
	270	+ return 1;
	271	+
	272	+ if (i2c_xfer_init(chip, addr))
	273	+ return 1;
	274	+
	275	+ start_time_rx = get_timer(0);
	276	+ while (len) {
	277	+ writel(IC_CMD, &i2c_regs_p->ic_cmd_data);
	278	+
	279	+ if (readl(&i2c_regs_p->ic_status) & IC_STATUS_RFNE) {
	280	+ *buffer++ = (uchar)readl(&i2c_regs_p->ic_cmd_data);
	281	+ len--;
	282	+ start_time_rx = get_timer(0);
	283	+
	284	+ } else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
	285	+ printf("Timed out. i2c read Failed\n");
	286	+ return 1;
	287	+ }
	288	+ }
	289	+
	290	+ return i2c_xfer_finish();
	291	+}
	292	+
	293	+/*
	294	+ * i2c_write - Write to i2c memory
	295	+ * @chip: target i2c address
	296	+ * @addr: address to read from
	297	+ * @alen:
	298	+ * @buffer: buffer for read data
	299	+ * @len: no of bytes to be read
	300	+ *
	301	+ * Write to i2c memory.
	302	+ */
	303	+int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
	304	+{
	305	+ int nb = len;
	306	+ unsigned long start_time_tx;
	307	+
	308	+ if (check_params(addr, alen, buffer, len))
	309	+ return 1;
	310	+
	311	+ if (i2c_xfer_init(chip, addr))
	312	+ return 1;
	313	+
	314	+ start_time_tx = get_timer(0);
	315	+ while (len) {
	316	+ if (readl(&i2c_regs_p->ic_status) & IC_STATUS_TFNF) {
	317	+ writel(*buffer, &i2c_regs_p->ic_cmd_data);
	318	+ buffer++;
	319	+ len--;
	320	+ start_time_tx = get_timer(0);
	321	+
	322	+ } else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
	323	+ printf("Timed out. i2c write Failed\n");
	324	+ return 1;
	325	+ }
	326	+ }
	327	+
	328	+ return i2c_xfer_finish();
	329	+}
	330	+
	331	+/*
	332	+ * i2c_probe - Probe the i2c chip
	333	+ */
	334	+int i2c_probe(uchar chip)
	335	+{
	336	+ u32 tmp;
	337	+
	338	+ /*
	339	+ * Try to read the first location of the chip.
	340	+ */
	341	+ return i2c_read(chip, 0, 1, (uchar *)&tmp, 1);
	342	+}
	1	+/*
	2	+ * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
	3	+ * Copyright (C) 2012 Renesas Solutions Corp.
	4	+ *
	5	+ * This program is free software; you can redistribute it and/or
	6	+ * modify it under the terms of the GNU General Public License as
	7	+ * published by the Free Software Foundation; either version 2 of
	8	+ * the License, or (at your option) any later version.
	9	+ *
	10	+ * This program is distributed in the hope that it will be useful,
	11	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	+ * GNU General Public License for more details.
	14	+ *
	15	+ * You should have received a copy of the GNU General Public License
	16	+ * along with this program; if not, write to the Free Software
	17	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	18	+ * MA 02111-1307 USA
	19	+ */
	20	+
	21	+#include <common.h>
	22	+#include <i2c.h>
	23	+#include <asm/io.h>
	24	+
	25	+struct sh_i2c {
	26	+ u8 iccr1;
	27	+ u8 iccr2;
	28	+ u8 icmr;
	29	+ u8 icier;
	30	+ u8 icsr;
	31	+ u8 sar;
	32	+ u8 icdrt;
	33	+ u8 icdrr;
	34	+ u8 nf2cyc;
	35	+ u8 __pad0;
	36	+ u8 __pad1;
	37	+};
	38	+
	39	+static struct sh_i2c *base;
	40	+static u8 iccr1_cks, nf2cyc;
	41	+
	42	+/* ICCR1 */
	43	+#define SH_I2C_ICCR1_ICE (1 << 7)
	44	+#define SH_I2C_ICCR1_RCVD (1 << 6)
	45	+#define SH_I2C_ICCR1_MST (1 << 5)
	46	+#define SH_I2C_ICCR1_TRS (1 << 4)
	47	+#define SH_I2C_ICCR1_MTRS \
	48	+ (SH_I2C_ICCR1_MST \| SH_I2C_ICCR1_TRS)
	49	+
	50	+/* ICCR1 */
	51	+#define SH_I2C_ICCR2_BBSY (1 << 7)
	52	+#define SH_I2C_ICCR2_SCP (1 << 6)
	53	+#define SH_I2C_ICCR2_SDAO (1 << 5)
	54	+#define SH_I2C_ICCR2_SDAOP (1 << 4)
	55	+#define SH_I2C_ICCR2_SCLO (1 << 3)
	56	+#define SH_I2C_ICCR2_IICRST (1 << 1)
	57	+
	58	+#define SH_I2C_ICIER_TIE (1 << 7)
	59	+#define SH_I2C_ICIER_TEIE (1 << 6)
	60	+#define SH_I2C_ICIER_RIE (1 << 5)
	61	+#define SH_I2C_ICIER_NAKIE (1 << 4)
	62	+#define SH_I2C_ICIER_STIE (1 << 3)
	63	+#define SH_I2C_ICIER_ACKE (1 << 2)
	64	+#define SH_I2C_ICIER_ACKBR (1 << 1)
	65	+#define SH_I2C_ICIER_ACKBT (1 << 0)
	66	+
	67	+#define SH_I2C_ICSR_TDRE (1 << 7)
	68	+#define SH_I2C_ICSR_TEND (1 << 6)
	69	+#define SH_I2C_ICSR_RDRF (1 << 5)
	70	+#define SH_I2C_ICSR_NACKF (1 << 4)
	71	+#define SH_I2C_ICSR_STOP (1 << 3)
	72	+#define SH_I2C_ICSR_ALOVE (1 << 2)
	73	+#define SH_I2C_ICSR_AAS (1 << 1)
	74	+#define SH_I2C_ICSR_ADZ (1 << 0)
	75	+
	76	+#define IRQ_WAIT 1000
	77	+
	78	+static void sh_i2c_send_stop(struct sh_i2c *base)
	79	+{
	80	+ clrbits_8(&base->iccr2, SH_I2C_ICCR2_BBSY \| SH_I2C_ICCR2_SCP);
	81	+}
	82	+
	83	+static int check_icsr_bits(struct sh_i2c *base, u8 bits)
	84	+{
	85	+ int i;
	86	+
	87	+ for (i = 0; i < IRQ_WAIT; i++) {
	88	+ if (bits & readb(&base->icsr))
	89	+ return 0;
	90	+ udelay(10);
	91	+ }
	92	+
	93	+ return 1;
	94	+}
	95	+
	96	+static int check_stop(struct sh_i2c *base)
	97	+{
	98	+ int ret = check_icsr_bits(base, SH_I2C_ICSR_STOP);
	99	+ clrbits_8(&base->icsr, SH_I2C_ICSR_STOP);
	100	+
	101	+ return ret;
	102	+}
	103	+
	104	+static int check_tend(struct sh_i2c *base, int stop)
	105	+{
	106	+ int ret = check_icsr_bits(base, SH_I2C_ICSR_TEND);
	107	+
	108	+ if (stop) {
	109	+ clrbits_8(&base->icsr, SH_I2C_ICSR_STOP);
	110	+ sh_i2c_send_stop(base);
	111	+ }
	112	+
	113	+ clrbits_8(&base->icsr, SH_I2C_ICSR_TEND);
	114	+ return ret;
	115	+}
	116	+
	117	+static int check_tdre(struct sh_i2c *base)
	118	+{
	119	+ return check_icsr_bits(base, SH_I2C_ICSR_TDRE);
	120	+}
	121	+
	122	+static int check_rdrf(struct sh_i2c *base)
	123	+{
	124	+ return check_icsr_bits(base, SH_I2C_ICSR_RDRF);
	125	+}
	126	+
	127	+static int check_bbsy(struct sh_i2c *base)
	128	+{
	129	+ int i;
	130	+
	131	+ for (i = 0 ; i < IRQ_WAIT ; i++) {
	132	+ if (!(SH_I2C_ICCR2_BBSY & readb(&base->iccr2)))
	133	+ return 0;
	134	+ udelay(10);
	135	+ }
	136	+ return 1;
	137	+}
	138	+
	139	+static int check_ackbr(struct sh_i2c *base)
	140	+{
	141	+ int i;
	142	+
	143	+ for (i = 0 ; i < IRQ_WAIT ; i++) {
	144	+ if (!(SH_I2C_ICIER_ACKBR & readb(&base->icier)))
	145	+ return 0;
	146	+ udelay(10);
	147	+ }
	148	+
	149	+ return 1;
	150	+}
	151	+
	152	+static void sh_i2c_reset(struct sh_i2c *base)
	153	+{
	154	+ setbits_8(&base->iccr2, SH_I2C_ICCR2_IICRST);
	155	+
	156	+ udelay(100);
	157	+
	158	+ clrbits_8(&base->iccr2, SH_I2C_ICCR2_IICRST);
	159	+}
	160	+
	161	+static int i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg)
	162	+{
	163	+ if (check_bbsy(base)) {
	164	+ puts("i2c bus busy\n");
	165	+ goto fail;
	166	+ }
	167	+
	168	+ setbits_8(&base->iccr1, SH_I2C_ICCR1_MTRS);
	169	+ clrsetbits_8(&base->iccr2, SH_I2C_ICCR2_SCP, SH_I2C_ICCR2_BBSY);
	170	+
	171	+ writeb((id << 1), &base->icdrt);
	172	+
	173	+ if (check_tend(base, 0)) {
	174	+ puts("TEND check fail...\n");
	175	+ goto fail;
	176	+ }
	177	+
	178	+ if (check_ackbr(base)) {
	179	+ check_tend(base, 0);
	180	+ sh_i2c_send_stop(base);
	181	+ goto fail;
	182	+ }
	183	+
	184	+ writeb(reg, &base->icdrt);
	185	+
	186	+ if (check_tdre(base)) {
	187	+ puts("TDRE check fail...\n");
	188	+ goto fail;
	189	+ }
	190	+
	191	+ if (check_tend(base, 0)) {
	192	+ puts("TEND check fail...\n");
	193	+ goto fail;
	194	+ }
	195	+
	196	+ return 0;
	197	+fail:
	198	+
	199	+ return 1;
	200	+}
	201	+
	202	+static int
	203	+i2c_raw_write(struct sh_i2c base, u8 id, u8 reg, u8 val, int size)
	204	+{
	205	+ int i;
	206	+
	207	+ if (i2c_set_addr(base, id, reg)) {
	208	+ puts("Fail set slave address\n");
	209	+ return 1;
	210	+ }
	211	+
	212	+ for (i = 0; i < size; i++) {
	213	+ writeb(val[i], &base->icdrt);
	214	+ check_tdre(base);
	215	+ }
	216	+
	217	+ check_tend(base, 1);
	218	+ check_stop(base);
	219	+
	220	+ udelay(100);
	221	+
	222	+ clrbits_8(&base->iccr1, SH_I2C_ICCR1_MTRS);
	223	+ clrbits_8(&base->icsr, SH_I2C_ICSR_TDRE);
	224	+ sh_i2c_reset(base);
	225	+
	226	+ return 0;
	227	+}
	228	+
	229	+static u8 i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg)
	230	+{
	231	+ u8 ret = 0;
	232	+
	233	+ if (i2c_set_addr(base, id, reg)) {
	234	+ puts("Fail set slave address\n");
	235	+ goto fail;
	236	+ }
	237	+
	238	+ clrsetbits_8(&base->iccr2, SH_I2C_ICCR2_SCP, SH_I2C_ICCR2_BBSY);
	239	+ writeb((id << 1) \| 1, &base->icdrt);
	240	+
	241	+ if (check_tend(base, 0))
	242	+ puts("TDRE check fail...\n");
	243	+
	244	+ clrsetbits_8(&base->iccr1, SH_I2C_ICCR1_TRS, SH_I2C_ICCR1_MST);
	245	+ clrbits_8(&base->icsr, SH_I2C_ICSR_TDRE);
	246	+ setbits_8(&base->icier, SH_I2C_ICIER_ACKBT);
	247	+ setbits_8(&base->iccr1, SH_I2C_ICCR1_RCVD);
	248	+
	249	+ /* read data (dummy) */
	250	+ ret = readb(&base->icdrr);
	251	+
	252	+ if (check_rdrf(base)) {
	253	+ puts("check RDRF error\n");
	254	+ goto fail;
	255	+ }
	256	+
	257	+ clrbits_8(&base->icsr, SH_I2C_ICSR_STOP);
	258	+ udelay(1000);
	259	+
	260	+ sh_i2c_send_stop(base);
	261	+
	262	+ if (check_stop(base)) {
	263	+ puts("check STOP error\n");
	264	+ goto fail;
	265	+ }
	266	+
	267	+ clrbits_8(&base->iccr1, SH_I2C_ICCR1_MTRS);
	268	+ clrbits_8(&base->icsr, SH_I2C_ICSR_TDRE);
	269	+
	270	+ /* data read */
	271	+ ret = readb(&base->icdrr);
	272	+
	273	+fail:
	274	+ clrbits_8(&base->iccr1, SH_I2C_ICCR1_RCVD);
	275	+
	276	+ return ret;
	277	+}
	278	+
	279	+#ifdef CONFIG_I2C_MULTI_BUS
	280	+static unsigned int current_bus;
	281	+
	282	+/**
	283	+ * i2c_set_bus_num - change active I2C bus
	284	+ * @bus: bus index, zero based
	285	+ * @returns: 0 on success, non-0 on failure
	286	+ */
	287	+int i2c_set_bus_num(unsigned int bus)
	288	+{
	289	+ switch (bus) {
	290	+ case 0:
	291	+ base = (void *)CONFIG_SH_I2C_BASE0;
	292	+ break;
	293	+ case 1:
	294	+ base = (void *)CONFIG_SH_I2C_BASE1;
	295	+ break;
	296	+ default:
	297	+ printf("Bad bus: %d\n", bus);
	298	+ return -1;
	299	+ }
	300	+
	301	+ current_bus = bus;
	302	+
	303	+ return 0;
	304	+}
	305	+
	306	+/**
	307	+ * i2c_get_bus_num - returns index of active I2C bus
	308	+ */
	309	+unsigned int i2c_get_bus_num(void)
	310	+{
	311	+ return current_bus;
	312	+}
	313	+#endif
	314	+
	315	+void i2c_init(int speed, int slaveaddr)
	316	+{
	317	+#ifdef CONFIG_I2C_MULTI_BUS
	318	+ current_bus = 0;
	319	+#endif
	320	+ base = (struct sh_i2c *)CONFIG_SH_I2C_BASE0;
	321	+
	322	+ if (speed == 400000)
	323	+ iccr1_cks = 0x07;
	324	+ else
	325	+ iccr1_cks = 0x0F;
	326	+
	327	+ nf2cyc = 1;
	328	+
	329	+ /* Reset */
	330	+ sh_i2c_reset(base);
	331	+
	332	+ /* ICE enable and set clock */
	333	+ writeb(SH_I2C_ICCR1_ICE \| iccr1_cks, &base->iccr1);
	334	+ writeb(nf2cyc, &base->nf2cyc);
	335	+}
	336	+
	337	+/*
	338	+ * i2c_read: - Read multiple bytes from an i2c device
	339	+ *
	340	+ * The higher level routines take into account that this function is only
	341	+ * called with len < page length of the device (see configuration file)
	342	+ *
	343	+ * @chip: address of the chip which is to be read
	344	+ * @addr: i2c data address within the chip
	345	+ * @alen: length of the i2c data address (1..2 bytes)
	346	+ * @buffer: where to write the data
	347	+ * @len: how much byte do we want to read
	348	+ * @return: 0 in case of success
	349	+ */
	350	+int i2c_read(u8 chip, u32 addr, int alen, u8 *buffer, int len)
	351	+{
	352	+ int i = 0;
	353	+ for (i = 0; i < len; i++)
	354	+ buffer[i] = i2c_raw_read(base, chip, addr + i);
	355	+
	356	+ return 0;
	357	+}
	358	+
	359	+/*
	360	+ * i2c_write: - Write multiple bytes to an i2c device
	361	+ *
	362	+ * The higher level routines take into account that this function is only
	363	+ * called with len < page length of the device (see configuration file)
	364	+ *
	365	+ * @chip: address of the chip which is to be written
	366	+ * @addr: i2c data address within the chip
	367	+ * @alen: length of the i2c data address (1..2 bytes)
	368	+ * @buffer: where to find the data to be written
	369	+ * @len: how much byte do we want to read
	370	+ * @return: 0 in case of success
	371	+ */
	372	+int i2c_write(u8 chip, u32 addr, int alen, u8 *buffer, int len)
	373	+{
	374	+ return i2c_raw_write(base, chip, addr, buffer, len);
	375	+}
	376	+
	377	+/*
	378	+ * i2c_probe: - Test if a chip answers for a given i2c address
	379	+ *
	380	+ * @chip: address of the chip which is searched for
	381	+ * @return: 0 if a chip was found, -1 otherwhise
	382	+ */
	383	+int i2c_probe(u8 chip)
	384	+{
	385	+ u8 byte;
	386	+ return i2c_read(chip, 0, 0, &byte, 1);
	387	+}
...	...	@@ -41,7 +41,7 @@
41	41
42	42	/* I2C driver configuration */
43	43	#define CONFIG_HARD_I2C
44		-#define CONFIG_SPEAR_I2C
	44	+#define CONFIG_DW_I2C
45	45	#define CONFIG_SYS_I2C_SPEED 400000
46	46	#define CONFIG_SYS_I2C_SLAVE 0x02
47	47